28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)
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Volt Synchronous Intel StrataFlash® Memory
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)
Performance
110/115/120 Initial Access Speed 64/128/256 Mbit Densities Asynchronous Page-Mode Reads, Words Wide Synchronous Burst-Mode Reads, Words Wide 32-Word Write Buffer Buffered Enhanced Factory Programming
Architecture
Multi-Level Cell Technology: High Density Cost Symmetrical K-Word Blocks Mbit (256 Blocks) Mbit (128 Blocks) Mbit Blocks) Ideal "CODE DATA" applications
Security
2-Kbit Protection Register Unique 64-bit Device Identifier Absolute Data Protection with VPEN Individual Instantaneous Block Locking, Unlocking Lock-Down Capability
Software
(typ.) Program Erase Suspend Latency Time Flash Data Integrator (FDI), Common Flash Interface (CFI) Compatible Programmable WAIT Signal Polarity
Quality Reliability
Operating Temperature: 100K Minimum Erase Cycles Block 0.18 ETOXVII Process
Packaging Voltage
64-Ball Intel® Easy Package 56-and 79-Ball Intel® Package 2.70 3.60 VCCQ 1.65 1.95 2.375- 3.60
Volt Synchronous Intel StrataFlash® Memory product line adds high performance burstmode interface other additional features Intel's StrataFlash® family products. Just like counterpart, K3/K18 utilizes reliable proven two-bit-per-cell technology deliver memory space, offering high density flash cost. This Intel's third generation technology, manufactured 0.18 lithography, making most widely used proven product family market. Synchronous Intel StrataFlash Memory Volt device (VCC), versions based around Volt (K3) Volt (K18)VCCQ. These devices ideal mainstream applications requiring large storage space both code data storage. Advanced system designs will benefit from high performance page burst modes direct execution from flash memory. Available densities from Mbit Mbit Mbyte), Synchronous Intel StrataFlash Memory highest density NOR-based flash component available today, just when Intel introduced original device 1997.
Notice: This document contains information products production. specifications subject change without notice. Verify with your local Intel sales office that have latest datasheet before finalizing design. Order Number: 290737-005 June 2002
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Volt Synchronous Intel StrataFlash® Memory contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2002. *Other names brands claimed property others.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Contents
Introduction
Document Purpose.7 Nomenclature Conventions Product Overview 2.1.1 High Performance Page/Burst Modes.9 2.1.2 Single Chip Solution 2.1.3 Packaging Options 2.1.4 Product Highlights Package Diagram.11 Signal Descriptions.14 Block Diagram Memory
Device Description
Device Operations
Operations.17 3.1.1 Read Mode 3.1.2 Write/Program 3.1.3 Output Disable.18 3.1.4 Standby 3.1.5 Reset/Deep Power-Down Device Commands Asynchronous Page-Mode Read Synchronous Burst-Mode Read Read Configuration Register 4.3.1 Read Mode 4.3.2 Latency Count 4.3.3 WAIT Polarity 4.3.4 Data Hold 4.3.5 WAIT Delay 4.3.6 Burst Sequence.26 4.3.7 Clock Edge 4.3.8 Burst Length Word Programming Write-Buffer Programming.27 Program Suspend Program Resume Buffered Enhanced Factory Programming (BEFP) 5.5.1 BEFP Requirements Considerations.29 5.5.2 BEFP Setup Phase 5.5.3 BEFP Program Verify Phase
Read Modes
Program Modes
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
5.5.4
BEFP Exit Phase.
Erase Mode
Block Erase Erase Suspend. Erase Resume Block Locking Operations 7.1.1 Block Lock 7.1.2 Block Unlock 7.1.3 Block Lock-Down 7.1.4 Block Lock During Erase Suspend. 7.1.5 Lock-Down Control Protection Registers 7.2.1 Reading Protection Registers 7.2.2 Programming Protection Registers 7.2.3 Locking Protection Registers Array Protection Read Status Register 8.1.1 Clear Status Register Read Device Identifier Read Query/CFI Configuration (Easy package ONLY) Power-Up/Down Characteristics Power Supply Decoupling Reset Characteristics Absolute Maximum Ratings Operating Conditions Current Characteristics Read Operations Write Operation Block Erase Program Operation Performance Reset Operation Test Conditions Capacitance
Security Modes
Special Modes
Power Reset
10.0
Electrical Specifications.
10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9
Appendix Appendix Appendix Appendix Appendix Appendix
Write State Machine (WSM) Common Flash Interface Flowcharts Mechanical Package Information Additional Information.73 Order Information
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Revision History
Date Revision 08/22/01 09/24/01 09/27/01 02/22/02 06/17/02 Revision -001 -002 -003 -004 -005 Original Version Corrected Typographical Errors 11.0 Characteristics section. Change VFBGA Package from ball package. ordering info Appendix Changes ballouts engineering review editing/formatting updates. Changes Iccr, elimination Speed expansion Vccq range. Description
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Introduction
Document Purpose
This document contains information pertaining Volt Synchronous Intel StrataFlash® Memory devices, K18. purpose this document describe features, operations specifications these devices.
Nomenclature
Volt core: Volt I/O: Volt I/O: AMIN: AMAX: range VCCQ range 2.375 VCCQ range 1.65 1.95 Easy packages: AMIN packages: AMIN Easy packages: Mbit AMAX Mbit AMAX Mbit AMAX packages: Mbit AMAX Mbit AMAX Mbit AMAX group flash cells that share common erase circuitry erase simultaneously write data flash array Refers signal package connection name Refers timing voltage levels Command User Interface Time Programmable Protection Register Protection Lock Register Reserved Future Status Register Read Configuration Register Write State Machine Multi-Level Cell Indicates logic Indicates logic zero
Block: Program: VPEN: VPEN: CUI: OTP: PLR: RFU: RCR: WSM: MLC: Set: Clear:
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Conventions
(noun): (noun): Byte: Word: Kword: Brackets: Hexadecimal prefix Binary prefix 1,000 1,000,000 bits bits 1,024 words 1,024 bits 1,024 bytes 1,048,576 bits 1,048,576 bytes Square brackets ([]) will used designate group membership define group signals with similar function (i.e. A[21:1], SR[4,1] D[15:0]).
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Device Description
This section provides overview Volt Synchronous Intel StrataFlash® Memory features, packaging information, signal names device architecture.
Product Overview
Volt Synchronous Intel StrataFlash Memory product line adds high performance burstmode interface other additional features Intel's StrataFlash family products. Just like counterpart, K3/K18 utilizes reliable proven two-bit-per-cell technology deliver memory space, offering high density flash cost. This third generation Intel's multi-level cell (MLC) technology, manufactured 0.18 lithography, making most widely used proven product family market. Synchronous Intel StrataFlash Memory Volt device (VCC), versions based around Volt VCCQ (K3) Volt VCCQ (K18). These devices ideal mainstream applications requiring large storage space both code data storage. Advanced system designs will benefit from high performance page burst modes direct execution from flash memory. Available densities from Mbit Mbyte), Synchronous Intel StrataFlash Memory highest density NOR-based flash component available today, just when Intel introduced original device 1997.
2.1.1
High Performance Page/Burst Modes
NOR-based flash generally preferred over other architectures reliability fast read speeds. Fast reads allow application execute code directly flash, rather than downloading execution, saving costs redundant system memory board space. Synchronous Intel StrataFlash Memory sets standard fast read speeds adding burst mode utilizing word page mode. Burst mode increases throughput 76MB/s, effectively five times faster than asynchronous reads standard flash memory, supports performance with zero wait states. Both page burst modes also provide high performance glueless interface Intel® StrongARM* SA-1110 (and future Intel® XScale processors) many other microprocessors.
2.1.2
Single Chip Solution
addition code execution, many applications also have data storage needs. K3/K18 memory provides single-chip solution combined code execution data storage. single-chip solution easy implement utilizing unique hardware software combination: Synchronous Intel StrataFlash Memory Intel® Persistent Storage Manager (PSM). PSM, royalty free when used with Intel® Flash, installable file system block device driver Microsoft Windows* version later. Intel software appropriate application using Microsoft Windows operating system, including Companions, Set-Top Boxes, other connected appliances hand-held devices. Other operating system ports also available. Intel optimized Intel StrataFlash Memory product line.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
wireless applications, Intel® Flash Data Integrator (FDI) Version software provides ability manage data files Intel StrataFlash Memory open architecture, including support downloaded Java* applets, Bluetooth* file transfers, voice recognition tags.
2.1.3
Packaging Options
Synchronous Intel StrataFlash Memory available multiple packages: Easy BGA, Intel® Stacked-CSP (stacking with SRAM flash flash). 64-ball Easy package provides reliability long-term footprint compatibility cost chip scale package size. Intel Stacked-CSP packages offer small footprints wireless applications. Manufactured Intel's 0.18-micron process technology, Intel StrataFlash Memory offers unprecedented value, performance reliability, still lowest cost-per-bit flash memory industry.
2.1.4
Product Highlights
High performance read modes: 16-word synchronous burst, 8-word page:
64Mb: 110/25/13ns (async/page/burst) 128Mb: 115/25/13ns 256Mb:120/25/13ns operation 64-ball Easy packages Intel Stacked-CSP VCCQ: 2.375 (K3); 1.65 1.95 (K18) One-time-programmable protection registers (2Kbits) Program Erase suspend capability Cost-effective multi-level cell architecture Royalty-free software support most applications with Intel PSM, Version Full extended operating temperature: -40° +85° Proven reliability: 100,000 cycles, years data retention
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Package Diagram
Volt Synchronous Intel StrataFlash Memory device available 64-ball Easy package 64-, 128-, Mbit densities. (See Figure This device also available 56-ball package Mbit densities 79-ball package Mbit density. (See Figure page 13.)
Figure 64-Ball Easy Package, Ball Pitch
VPEN
VPEN
RST# Vccq Vccq
Vccq Vccq RST#
ADV# WAIT
WAIT ADV#
128M
Vccq
Vccq
128M
Vssq Vssq View Ball Side Down Version -Easy
256M
256M
Vssq Vssq Bottom View Ball SideUp Version Easy
NOTES: Address valid only 128-Mbit densities above; otherwise, connect (NC). Address valid only 256-Mbit density; otherwise, connect (NC).
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Figure Ball Package 0.75 Ball Pitch (64- 128Mb Densities ONLY)
VCCQ
VPEN
VPEN
RST#
RST#
ADV#
ADV#
WAIT
WAIT
VCCQ
VSSQ
VCCQ
VSSQ
VSSQ
VCCQ
VSSQ
VFBGA View Ball Side Down
VFBGA Bottom View Ball Side
NOTE: Address only valid 128-Mbit density; otherwise, connect (NC).
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Figure 79-ball Package (256-Mbit Density)
VCCQ VSSQ VCCQ VSSQ WAIT ADV# RST# VPEN
VFBGA View Ball Side Down
VPEN RST# ADV# WAIT VCCQ VSSQ VCCQ VSSQ
VFBGA Bottom View Ball Side
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Signal Descriptions
Table lists active signals used provides brief description each.
Table
Signal Descriptions
A[AMAX:AMIN] D[15:0] RST# Type INPUT INPUT/ OUTPUT INPUT INPUT INPUT INPUT Name Function ADDRESS: Device address. Address internally latched during read/write operations. nomenclature Section AMAX AMIN values. DATA I/O: Inputs data commands during write operations, outputs data during read operations. Float when de-asserted. Data internally latched during write operations. CHIP ENABLE: Active-low; CE#-low selects device. CE#-high deselects device, places standby mode, places data WAIT outputs High-Z state. OUTPUT ENABLE: Active-low; OE#-low enables device's output data buffers during read cycles. OE#-high places data outputs High-Z state. WRITE ENABLE: Active-low; controls writes flash device. Address data latched rising edge WE#. RESET: Active-low; resets internal circuitry inhibits write operations. This provides data protection during power transitions. RST#-high enables normal operation. Exit from reset places device asynchronous read-array mode. WRITE PROTECT: Active-low; WP#-low enables lock-down mechanism. Blocks locked down cannot unlocked with unlock command. WP#-high overrides lock-down function enabling blocks erased programmed through software. ADDRESS VALID: Active-low; during synchronous read operations, addresses latched rising edge ADV# rising falling) edge CLK, whichever occurs first. ERASE/PROGRAM/BLOCK LOCK ENABLE: Controls device protection. When VPEN VPENLK, flash contents protected against Program Erase. CLOCK: Synchronizes device system's frequency synchronous-read mode, increments internal address generator. During synchronous read operations, addresses latched ADV#'s rising edge CLK's rising falling) edge, whichever occurs first. STATUS: Indicates status internal state machine. When configured level mode (default mode), acts RY/BY# pin. When configured pulse modes, indicate program and/or erase completion. alternate configurations STATUS pin, configuration commands. tied VCCQ with pull-up resistor. WAIT: Indicates invalid data synchronous-read (burst) modes. WAIT High-Z whenever de-asserted. WAIT gated OE#. CORE POWER SUPPLY: Core (logic) source voltage. Writes flash array inhibited when VLKO. Operations invalid voltages should attempted. Device operations invalid voltages should attempted. POWER SUPPLY: Output-driver source voltage. GROUND: Ground reference device core power supply. Connect system ground. GROUND: Ground reference device power supply. Connect system ground. DON'T USE: this ball. This ball should connected power supplies, signals other balls must left floating. CONNECT: internal connection; driven floated. RESERVED FUTURE USE: Balls designated reserved Intel future device functionality enhancement.
ADV# VPEN
INPUT INPUT INPUT INPUT OPEN DRAIN OUTPUT OUTPUT POWER POWER POWER POWER
WAIT VCCQ VSSQ
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Block Diagram
Figure Volt Synchronous Intel StrataFlash® Memory Block Diagram
DQ15
VCCQ
VCCQ
Output Buffer
Input Buffer
Query Output Multiplexer Write Buffer Identifier Register Status Register Data Comparator Y-Decoder Y-Gating 64-Mbit: Sixty-four 128-Mbit: One-hundred twenty-eight 256-Mbit Two-hundred fifty-six 64Kword Blocks
Write State Machine
Logic Data Register
VCCQ RST#
WAIT
Command User Interface
Read State Machine
Input Multiplexer
AMAX AMIN ADV#
Input Buffer Address Latch Address Counter
Program/Erase Voltage Switch
VPEN
X-Decoder
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Memory
Volt Synchronous Intel StrataFlash array divided into equally-sized symmetrical blocks that 64-Kword size. Mbit device contains blocks, Mbit device contains blocks Mbit device contains blocks. Flash cells within block organized rows columns. block contains rows words. words divided into eight-word groups. (Refer Figure
Figure Volt Synchronous Intel StrataFlash® Memory
0xFFFFFF 0xFF0000 Block 0x7FFFFF Block 0x7F0000 256-Mbit Device 128-Mbit Device 0x3FFFFF 0x3F0000 64-Mbit Device Block 0x3FFFF 0x2FFFF 0x1FFFF 0xFFFF Block Block Block Block
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Device Operations
This section provides overview device operations. on-chip Write State Machine (WSM) manages block-erase word-program algorithms. system provides control insystem read, write, erase operations device system bus. Device commands written Command User Interface (CUI) control flash memory device's operations. does occupy addressable memory location; it's mechanism through which flash device controlled.
Operations
cycles from device conform standard microprocessor operations. Table summarizes operations voltage levels that must applied device control signals when operating within each device mode. Whenever asserted, device active state; selected internal circuits active. determine whether D[15:0] outputs inputs, respectively.
Table
Mode
Operations
RST# Enabled OE#(1) WE#(1) ADV# WAIT Valid VPEN Data DOUT DOUT High-Z High-Z High-Z (default mode) High-Z Notes
Synch Array Read Asynch. Reads Synch. Status, Query Identifier Reads Output Disable Standby Reset Command Write Array Writes
Enabled
Driven
High-Z
Enabled Disabled Enabled Enabled
Driven High-Z High-Z Driven Driven
VPENH
High-Z High-Z High-Z High-Z
NOTES: should never asserted simultaneously, done, overrides WE#. Refer Characteristics. When VPEN VPENLK, memory contents read altered. should control pins VPENLK VPENH VPEN. outputs, should VOH. Array writes either program erase operations.
3.1.1
Read Mode
perform read operation, must asserted. device-select control; when active, enables flash memory device. data-output control; when active, addressed flash memory data driven onto bus. read states, RST# must de-asserted. Section 10.4, "Read Operations" page Refer Section 4.0, "Read Modes" page details reading from flash array, refer Section 8.0, "Special Modes" page details regarding other available read states.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
3.1.2
Write/Program
perform write operation, both asserted, de-asserted. device write operations asynchronous, with being ignored. During write operation, address data latched rising edge CE#, whichever occurs first. Table "Command Definitions" page cycle commands. Section 10.5, "Write Operation" page Write operations with invalid and/or VPEN voltages produce spurious results should attempted.
3.1.3
Output Disable
Whenever de-asserted, device outputs, D[15:0], disabled placed highimpedance state.
3.1.4
Standby
Anytime de-asserted, device deselected placed standby, substantially reducing power consumption. standby, data outputs placed high-impedance state independent level placed OE#. device de-selected (CE# de-asserted) during program erase operation, will continue consume active power until program erase operation completed. There additional latency subsequent read operations.
3.1.5
Reset/Deep Power-Down
After initial power-up reset, device defaults Read Array mode device status register 0x80. already Read Array mode, asserting RST# de-energizes internal circuits, places output drivers high-impedance state. After returning from reset (RST# de-asserted) minimum amount time required before initial read access outputs valid data. Also, minimum delay required after reset before write cycle initiated. After this wake-up interval passed, normal operation restored. Section 10.4, "Read Operations" page reset timing details. Note: RST# asserted during program erase operation, operation will aborted memory contents aborted location (for program) block (for erase) longer valid, since data have been only partially written erased. Once RST# asserted, device shuts down operation progress, process which takes minimum amount time complete. When RST# been de-asserted, device will reset read array mode. RST# remains asserted specified time, device will enter deep power-down. system returning from aborted program erase operation, minimum amount time must satisfied before read write operation initiated. with automated device, important assert RST# when system reset. When system comes reset, system processor will attempt read from flash memory system boot device. Automated flash memories provide status information when read during program block erase operations. reset occurs with flash memory reset, improper initialization occur because flash memory providing status information rather
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
than array data. Intel® Flash memories allow proper initialization following system reset through RST# input. RST# should controlled same low-true reset signal that resets system CPU.
Device Commands
Device operations initiated writing specific device commands Command User Interface (CUI). (See Table commands used modify array data, Word Program Block Erase. Writing either these commands initiates sequence internally-timed functions that culminate completion requested task. However, operation aborted either asserting RST# issuing appropriate Suspend command.
Table
Command Definitions (Sheet
Command Cycles First Cycle Type Write Write Write Write Write Addr Address Address Address Address within Block Address Address memory location programed Address within Block Address memory location programed Address within Block Address Address Data 0xFF 0x90 0x98 0x70 0x50 0x40 0x10 0xE8 Address memory programed Address within Block Address within Block Address within Block Data programed Number words written buffer 0xD0 0xD0 Type Read Read Read Read Second Cycle Addr Address memory read Identifier Code Address Query Code Address Address with Block Data Array Data Identifier Code Data Query Code Data Status Register Data
Read Array Read Identifier Read Read Query (CFI) Read Status Register Clear Status Register Program
Number buffer words
Write
Write
Program
Write Buffer4
Write
Write
Buffered Erase Suspend Resume Block Erase Erase/Program Suspend Erase/Program Resume
Write Write Write Write
0x80 0x20 0xB0 0xD0
Write Write
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Table
Command Definitions (Sheet
Command Cycles First Cycle Type Write Write Write Write Write Addr Address within Block Address within Block Address within Block Address Data 0x60 0x60 0x60 0x60 0xB8 Type Write Write Write Write Write Second Cycle Addr Address within Block Address within Block Address within Block Address Data 0x03 0x01 0xD0 0x2F Data programmed Protection Register 0xFFFD
Read Configuration Register Register Configuration (Burst, Lock, Protection) Lock Block Unlock Block Lock-Down Block Protection Program
Write
0xC0
Write
Lock Protection Program Lock Protection
Write
Lock Protection Address 128bit Lock Protection Address 2K-bit
0xC0
Write
Lock Protection Address 128-bit LPA1
Write
0xC0
Write
LPD3
NOTES: Configuration register data presented device addresses A[AMIN+15:AMIN]. A[AMAX:AMIN+16] address bits must cleared. Table "Read Configuration Register" page descriptions. Configuration code D[7:0]. Lock Protection Register1 Data. Valid values between 0xFFFE 0x0000. second cycle Write-to-Buffer command count words load into buffer, followed data streaming count value. Then Confirm command (0xD0) issued execute program operation. Refer Figure "Write Buffer Flowchart" page Valid Protection Register Address.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Read Modes
device supports four types read modes: read array, read identifier, read status read query. Upon power-up return from reset, device defaults read array mode. change device's read mode, appropriate Read command must written device. (See Section 3.2, "Device Commands" page 19.) Section 8.0, "Special Modes" page details regarding read status, read query modes. device supports types array read modes: asynchronous page mode synchronous burst mode. Asynchronous page mode default read mode after powered-up, after reset. must configured enable Synchronous Burst reads flash memory array. (See Section 4.3, "Read Configuration Register" page 22.) Read Array command functions independent VPEN. following sections describes readarray mode operations detail.
Asynchronous Page-Mode Read
Asynchronous page mode default read mode upon power-up return from reset. However, perform array reads after other device operation (e.g., write operation), Read Array command must issued order read from flash memory. Asynchronous page-mode reads permitted blocks, used access device register information. Note: Asynchronous page mode reads only performed when set. (See Section 4.3, "Read Configuration Register" page 22.) perform asynchronous page-mode read, address driven onto A[AMAX:AMIN], asserted. RST# must de-asserted. ADV# must held throughout read cycle. used asynchronous page-mode reads, ignored. only asynchronous reads performed, recommended that tied valid level. Array data driven D[15:0] after minimum delay. (See Section 10.4, "Read Operations" page 45.) asynchronous page mode, eight-word groups "sensed" simultaneously from flash memory loaded into internal page buffer. After initial access delay, first word data buffer corresponds initial address, A[AMAX:AMIN]. Address bits A[AMAX:AMIN latched device. However, lower address bits, A[AMIN +2:AMIN], latched. Address bits A[AMIN+2:AMIN] determine which word eight-word group output from data buffer given time. Subsequent reads from device come from page buffer, output D[15:0] after minimum delay, long address bits A[AMIN+2:AMIN] only address bits that change. Data read from page buffer multiple times, order. address bits A[AMAX:AMIN+3] change time, toggled, device will sense load eight-word group from flash memory into page buffer. controlling certain signals, such and/or OE#, device made output less than eight-words data. Asynchronous page-mode read used access register information, only word loaded into page buffer.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Synchronous Burst-Mode Read
Since asynchronous page mode default read mode following device power-up reset, appropriate bits must before synchronous burst mode reads flash memory occur. Section 4.3, "Read Configuration Register" page details. Immediately after configuring RCR, necessary issue Read Array command (0xFF) before performing synchronous burst-mode read. However, perform synchronous burst-mode read after executing other device operation (e.g., write operation), necessary issue Read Array command before performing synchronous burst-mode read flash memory. perform synchronous burst-mode read, address driven onto A[AMAX:AMIN], asserted. RST# must de-asserted. ADV# asserted, then de-asserted latch address. Alternatively, ADV# remain asserted throughout burst access, which case, address latched next valid edge. synchronous burst mode, eight-word groups "sensed" simultaneously from flash memory loaded into internal page buffer. After initial access delay, first word output from data buffer next valid edge. Subsequent buffer data output valid edges. Synchronous burst-mode reads only step through data buffer once, only sequential manner; starting from address latched beginning burst cycle (see Section 10.4, "Read Operations" page 45). device supports word bursts. However, controlling certain control signals, such and/or OE#, device output less than 8/16-words synchronous data. burst-mode read used access register information. When burst-mode read performed register, only word loaded into data buffer. burst mode, address latched either rising edge ADV# next valid edge with ADV# low, whichever occurs first.
Read Configuration Register
Read Configuration Register (RCR) used select read mode (synchronous asynchronous), defines synchronous burst characteristics device. modify settings, write command device (see Section 3.0, "Device Operations" page 17). contents examined writing Read Identifier command device. Section 8.2, "Read Device Identifier" page 39). Register shown Table following sections describe each detail.
Table
Read Configuration Register (Sheet Read Configuration Register (RCR)
Read Mode WAIT Polarity Data Hold WAIT Delay Burst Edge
Default Value 0xFFFF
Burst Length
Latency Count
LC[3:0] Name Read Mode (RM)
BL[2:0]
Description Synchronous burst-mode read Asynchronous page-mode read (default)
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Table
Read Configuration Register (Sheet
14:11 Latency Count (LC[3:0]) 0000 Code 0001 Code 0010 =Code 0011 =Code 0100 =Code 0101 =Code 0110 Code 0111 Code 1000 Code 1001 Code 1010 Code 1011 1111 Code Code these codes =WAIT signal active =WAIT signal active high (Default) =Hold data clock =Hold data clocks (default) =WAIT de-asserted with valid data =WAIT de-asserted clock before valid data (default) =Reserved =Linear (default) falling edge rising edge (default) Reserved bits should cleared =8-word burst =16-word burst =RFU
Wait Polarity (WP) Data Hold (DH) Wait Delay (WD) Burst Sequence (BS) Clock Edge (CE) Reserved Burst Length (BL0-2)
4.3.1
Read Mode
read mode (RM) selects synchronous burst mode asynchronous page mode operation device. When set, asynchronous page mode selected (default). When cleared, synchronous burst mode selected. Synchronous burst mode used array reads, whereas asynchronous page mode used reading array data, Status Register information, Device information, information. Note that when operating synchronous burst mode, Status, information will driven onto next valid clock edge following initial synchronous access delay, will remain duration access cycle.
4.3.2
Latency Count
Latency Count bits, LC[3:0], tell device many clock cycles must elapse from rising edge ADV# from first valid clock edge after ADV# asserted) until first data word driven onto D[15:0]. input clock frequency used determine this value. Table page latency values. these equations calculate first access latency count: (1): (2): Frequency} Period n(CLK Period) tAVQV tADD tDATA
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
formula tAVQV (ns) tADD(ns) tDATA (ns) known initial system access time. (3): First Access Latency Count (LC)
clock periods (rounded next integer) Parameters defined CPU: tADD Clock CE#, ADV#, Address Valid whichever occurs last. tDATA Data clock (CPU specific) Parameters defined flash: tAVQV Address Output Delay Example: Clock Speed tADD (typical speed from CPU) (max) tDATA (typical speed from CPU) (min) tAVQV (from Characteristic Read Operations Table) From (1): {1/66 (MHz)}1000 From n(15 n(15 120/15 (Integer) From n-2=8-2=6 First Access Latency Count setting Code Figure shows data available valid after latencies from ADV# going low. Figure Data Output with Setting Code
tCHQV
tADD
tDATA
Address
Valid Address
ADV#
Code
Data [D/Q]
High Valid Output0 Valid Output
R103
Dataoplc.wmf
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
4.3.3
WAIT Polarity
WAIT Polarity (WP) selects asserted, true, state WAIT. When set, WAIT active-high signal (default). When cleared, WAIT active-low signal.
4.3.4
Data Hold
burst read operations, Data Hold (DH) determines whether data output remains valid D[15:0] clock cycles. When set, output data held clocks (default). When cleared, output data held clock cycle. (See Figure processor's data setup time flash memory's clock-to-data output delay should considered determining whether hold output data clocks.
Figure Data Hold Timing
Data Hold Data Hold
DQ15-0 [D/Q] DQ15-0 [D/Q]
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
4.3.5
WAIT Delay
WAIT Delay (WD) controls WAIT signal's delay behavior during synchronous burst reads. WAIT asserted either during, clock cycle before, valid data output D[15:0].When set, WAIT de-asserted clock before valid data (default). When cleared, WAIT de-asserted with valid data. setting dependent system data sampling requirements.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
4.3.6
Burst Sequence
Burst Sequence (BR) selects linear-burst sequence (default). Only linear-burst sequence supported. Table shows synchronous burst sequence burst lengths, well effect Burst Wrap (BW) setting.
Table
Burst Sequence Word Ordering
Burst Addressing Sequence (DEC) Start Addr. (DEC)
8-Word Burst (BL[2:0] 010) 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
16-Word Burst (BL[2:0] 011) 0-1-2-3-4.14-15 1-2-3-4-5.15-0 2-3-4-5-6.0-1 3-4-5-6-7.1-2 4-5-6-7-8.2-3 5-6-7-8-9.3-4 6-7-8-9-10.4-5 7-8-9-10-11.5-6
14-15-0-1-2.12-13 15-0-1-2-3.13-14
4.3.7
Clock Edge
Clock Edge (CE) selects either rising (default) falling clock edge CLK. This clock edge that used start burst cycle output synchronous data assert/deassert WAIT.
4.3.8
Burst Length
BL[2:0] selects linear burst length synchronous burst reads flash memory. burst length configured 8-word 16-word burst. Once burst cycle begins, device will output synchronous burst data until reaches burstable address space.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Program Modes
device supports three different programming methods: word programming, write-buffer programming, Buffered Enhanced Factory Programming Buffered-EFP. Successful programming requires addressed block unlocked. block locked down, must de-asserted block unlocked before attempting program array. attempt program locked block will result operation aborting, SR[1] SR[4] being set, indicating programming error. following sections describe device programming detail.
Word Programming
Word programming performed executing Word Program command. Word programming non-buffered operation programs word flash array based initial program address A[AMAX:AMIN]. determine status word-program operation, poll status register analyze bits. flash device standby mode during program operation, device will continue program word until operation complete; then device will enter standby mode. Refer Figure "Word Programming Flowchart" page detailed flow implement word program operation. During programming, Write State Machine executes sequence internally-timed events that program desired data bits verifies that bits sufficiently programmed. Programming flash memory array changes "ones" "zeros." Memory array bits that zeros changed ones only erasing block. When programming finished, Status Register indicates programming failure. set, this indicates that Write State Machine could perform word programming operation because VPEN outside acceptable limits. set, word programming operation attempted program locked block, causing operation abort. After examining status register, should cleared using Clear Status Register command before issuing command. valid command follow, once word programming completed.
Write-Buffer Programming
device features 32-word Write Buffer allow optimum programming performance. write-buffer programming, data first written on-chip write buffer, then programmed into flash memory array buffer-size increments. Optimal performance realized when programming buffer-size aligned 32-word write-buffer boundary. write-buffer directly mapped flash array through A[AMIN+4:AMIN]. Unaligned buffered writes will decrease program performance. Buffered writes improve system programming performance more than over non-write buffer programming. perform write-buffer programming, Write-to-Buffer Setup command, 0xE8, issued along with block address (see Section 3.2, "Device Commands" page 19). Status Register information updated, read from block address will return Status Register data showing write buffer's availability. indicates availability write buffer loading data. set, write buffer available; set, write buffer available. retry, issue Write-to-Buffer Setup command again, re-check SR7. When set, write buffer available. Figure "Write Buffer Flowchart" page
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Next, word count written device buffer address. This tells device many data words will written write buffer, maximum size write buffer. next write, device start address given along with first data written flash memory array. Subsequent writes provide additional device addresses data. data addresses must within start address plus word count. Maximum programming performance lower power obtained aligning starting address beginning word boundary. misaligned starting address will result doubling total program time. After last data written write buffer, Write-to-Buffer Confirm command issued. Write State Machine begins copy Write Buffer contents flash memory array. command other than Write-to-Buffer Confirm command written device, command sequence error will occur Status Register bits SR4, will set. error occurs while writing array, device will stop programming, Status Register will set, indicating programming failure. Additional buffer writes initiated issuing another Write-to-Buffer Setup command repeating write-to-buffer sequence. Anytime set, device will accept Write-to-Buffer commands. attempt made program past block boundary using Write-to-Buffer command, device will abort operation. This will generate command sequence error, Status Register bits will set. Write-to-Buffer programming attempted while VPEN below VPENLK, Status Register bits will set. errors detected that have Status Register bits, Status Register should cleared using Clear Status Register command.
Program Suspend
execute program suspend, execute Program Suspend command. suspend operation halts in-progress programming operation. Suspend command written device address. Suspend command allows data accessed from memory location other than those suspended. program operation suspended perform device read. program operation nested within erase suspend operation suspended read flash device. Once program process starts, suspend operation only occur certain points program algorithm. Erase suspend operations cannot resume until program operations initiated during erase suspend complete. device read functions permitted during suspend operation. During suspend, VPEN must remain valid program level must change. Also, minimum amount time required between issuing Program Erase command then issuing Suspend command.
Program Resume
resume (i.e., continue) program suspend operation, execute Program Resume command. Resume command written device address. When program operation nested within erase suspend operation Program Suspend command issued, device will suspend program operation. When Resume command issued, device will resume complete program operation. Once nested program operation completed, additional
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Resume command required complete block erase operation. device supports maximum suspend/resume nested routines. Figure "Program Suspend/Resume Flowchart" page
Buffered Enhanced Factory Programming (BEFP)
BEFP speeds flash programming today's beat-rate-sensitive manufacturing environments. This enhanced algorithm eliminates traditional elements that drive overhead off-board on-board, off-line in-line, manual automated programmer systems. BEFP different than non-buffered mode; incorporates write buffer spread program performance across data words. Additionally, verification occurs same phase programming, inherent requirement two-bit-per-cell technology accurately program correct state. single two-cycle command sequence programs entire block data. This enhancement eliminates three write cycles buffer page, commands word count each data words. Host programmer cycles fill device write buffer, followed status check SR.0 determine when data from that page completed programming into sequential flash memory locations. Following buffer-to-flash programming sequence, increments internal addressing automatically select next 32-word array boundary. This aspect BEFP saves programming equipment address-bus setup overhead. combination, these enhancements allow programming equipment stream data device. With proper continuity testing, programming equipment rely internal verification assure device programmed properly. This capability eliminates external post-program verification associated overhead. BEFP consists three phases: setup, program/verify, exit. Refer Figure "Buffered Enhanced Factory Programming Procedure Flowchart" page graphical representation BEFP.
5.5.1
BEFP Requirements Considerations
BEFP requirements:
Ambient temperature: within specified operating range VPEN driven VPENH Target block unlocked before issuing Setup Confirm commands (first word address block programmed) must held constant from setup phase through data streaming target block, until transition exit phase desired
must align with start array buffer boundary1
BEFP considerations:
optimum performance, limit cycling below erase cycles block2 BEFP programs block time, buffer data must fall within single block3 BEFP cannot suspended Programming flash only occur when buffer full4
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Buffer boundary array determined A[AMIN+4:AMIN] (00h through 1Fh). Alignment start point A[AMIN+4:AMIN]=0.
Some degradation performance occur this limit exceeded, internal algorithm will continue work properly. internal address counter increments beyond block's maximum address, addressing will wrap around beginning block. number words less than case last page program sequence block, remaining locations must filled with FFFFh. responsibility manage this falls within programming equipment, customer data file.
Figure "Buffered Enhanced Factory Programming Procedure Flowchart" page detailed flowchart Buffered BEFP operation.
5.5.2
BEFP Setup Phase
After receiving BEFP Setup (80h) Confirm (D0h) command sequence, device SR.7 transitions from `0,' indicating that busy with BEFP algorithm startup. delay before checking SR.7 required allow time perform setups checks (block lock status VPEN level). error detected, SR.4 BEFP operation terminates. block found locked, SR.1 also set. SR.3 error occurred VPEN level being incorrect.
5.5.3
BEFP Program Verify Phase
After setup completion, host programming system must check SR.0 determine "data-stream ready" status. SR.0=0 indicates that BEFP program/verify phase activated write buffer available. basic sequences repeat this phase: loading write buffer, followed buffer data programming array. BEFP, count value buffer loading always maximum buffer size words. During page loading sequence, data received stored sequential buffer locations starting address 00h. Programming that page flash array starts immediately when buffer full.
Warning:
buffer must completely full programming occur. Supplying address outside current block's range during buffer fill sequence will cause operation lockup. number words less than case last page program sequence block, remaining locations must filled with FFFFh. responsibility manage this falls within programming equipment, customer data file. Data words from write buffer directed sequential memory locations array, programming takes where last page sequence left off. host programming system must poll SR.0 determine when page program sequence completes. SR.0=0 indicates that buffer data been transferred flash array, SR.0=1 indicates that still busy. host system check full status errors time, only necessary block basis, after BEFP exit.
Note:
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
host programming system continues BEFP algorithm providing next data words buffer. Alternatively, terminate this phase changing block address.The program/verify phase concludes when interfacing programmer writes different block address; data supplied must FFFFh. Upon program/verify phase completion, device enters BEFP exit phase.
5.5.4
BEFP Exit Phase
SR.7=1 indicates that device returned normal operating conditions. full status check should performed this time ensure entire block programmed successfully. After BEFP exit, valid command issued. BEFP SR.7 SR.0 Truth table shown Table
Table
BEFP SR.7 SR.0 Truth table
SR.7 SR.0 Condition Buffer available, device ready. Buffer available, device busy. Buffer available, device busy. Invalid state.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Erase Mode
Flash erasing performed block basis; therefore, only block erased time. Once block erased, bits within that block will read logic level one. determine status block erase, poll status register analyze bits. This following section describes block erase operations detail.
Block Erase
Block Erase operations initiated writing Block Erase command address block erased (refer Section 3.2, "Device Commands" page 19). This followed Block Erase Confirm command written address block erased. device placed standby (CE# de-asserted) reset (RST# de-asserted) during erase operation, device will continue erase block until erase operation completed before entering standby reset.VPEN must above VPENLK block must unlocked (see Figure "Block Erase Flowchart" page 66). Also, VPEN must remain valid level, must remain unchanged while erase suspend. During block erase, Write State Machine executes sequence internally-timed events that conditions, erases, verifies bits within block erased. Erasing flash memory changes array data from "zeros" "ones." Status Register indicates block erase status while sequence executes. When erasing finished, Status Register set, this indicates erase failure. set, this indicates that Write State Machine could perform erase operation because VPEN outside acceptable limits. set, erase operation attempted erase locked block, causing operation abort. must toggled update Status Register contents. After examining status register, should cleared using Clear Status Register command before issuing command. valid command follow, once block erase operation completed.
Erase Suspend
Issuing Erase Suspend command while erasing suspends block erase operation. This allows data accessed from memory locations other than being erased. Erase Suspend command issued device address within block. block erase operation suspended perform either word program read operation within block, except block that erase suspend state (see Figure "Erase Suspend/Resume Flowchart" page 67). When block erase operation executing, issuing Erase Suspend command requests Write State Machine suspend erase algorithm predetermined points. erase operation cannot nested within another erase suspend operation. Block erase suspended when Status Register bits SR[7,6] set. Suspend latency specified Section 10.6, "Block Erase Program Operation Performance" page
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Block erase cannot resume until program operations initiated during erase suspend complete. Read Array, Read Status Register, Read Identifier, Query, Program Resume valid commands during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Erase Resume, Block Lock, Block Unlock, Block Lock-Down valid commands during Erase Suspend.
Erase Resume
resume (i.e., continue) erase suspend operation, execute Erase Resume command. Resume command written device address. When program operation nested within erase suspend operation Program Suspend command issued, device will suspend program operation. When Resume command issued, device will resume program operations first. Once nested program operation completed, additional Resume command required complete block erase operation. device supports maximum suspend/resume nested routines. Figure "Block Erase Flowchart" page
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Security Modes
This device offers both hardware software security features. Block lock operations, Protection Registers, VPEN enable user implement various levels data protection. following section describes security features detail.
Block Locking Operations
Individual instant block locking used protect user code and/or data within flash memory array. blocks power locked protect array data from being altered during power transitions. block locked unlocked without latency. Locked blocks cannot programmed erased; they only read. Software-controlled security implemented with Block Lock Block Unlock commands. Hardware-controlled security implemented with Block Lock-Down command WP#. Refer Figure state diagram flash security features. Also Figure "Block Lock Operations Flowchart" page
Figure Block Locking State Diagram
Power-Up/Reset
Locked [X01]
LockedDown4,5 [011]
Hardware Locked5 [011]
Hardware Control
Unlocked [X00]
Software Locked [111]
Unlocked [110]
Software Block Lock (0x60/0x01) Software Block Unlock (0x60/0xD0) Software Block Lock-Down (0x60/0x2F) hardware control
Notes:
[a,b,c] represents [WP#, D0]. Don't Care. indicates block Lock-down status. `0', Lock-down been issued this block. `1', Lock-down been issued this block. indicates block lock status. `0', block unlocked. `1', block locked. Locked-down Hardware Software locked. [011] states should tracked system software determine difference between Hardware Locked Locked-Down states.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
7.1.1
Block Lock
blocks default locked state after initial power-up reset. unlocked block locked issuing Block Lock command sequence. This sets block lock status fully protects block from program erase. Attempted program erase operations locked block will return error SR1.
7.1.2
Block Unlock
locked block unlocked issuing Block Unlock command. unlocked blocks return locked state when device reset powered-down. Unlocked blocks programmed erased.
7.1.3
Block Lock-Down
Lock-Down Block command adds additional level security device. Issuing Lock-Down Block command sets lock-down status locks block. Lock-Down Block command used block's current state either locked unlocked. Once this set, enabled hardware lock control that particular block. block lockeddown de-asserted, user issue Unlock Block command allow program erase operations that block. Note: Only device reset power-down clear lock-down status bit.
7.1.4
Block Lock During Erase Suspend
Blocks locked, unlocked, locked down during erase suspend operation. this, first write Erase Suspend command device. After checking determine that erase operation suspended, write desired lock command sequence block. lock status bit(s) will change immediately. block being locked locked-down same block that suspended, lock status bit(s) will still change immediately, erase operation will complete when resumed. After completing lock, unlock, read, program operations, resume erase operation with Erase Resume command. Note: Block Lock Setup command followed command other than Block Lock, Block Unlock, Block Lock-Down will produce command sequence error Status Register bits SR5. this error occurs while erase suspended, will remain after erase operation resumed unless Status Register cleared first using Clear Status Register command. Otherwise, possible erase errors become masked command sequence error. Locking operations cannot occur during program suspend. Appendix "Write State Machine (WSM)" page shows valid commands during erase suspend.
7.1.5
Lock-Down Control
lock-down status particular block, signal then enabled master lock/unlock override that particular block. When asserted, blocks that have lockdown status automatically into lock-down state cannot unlocked with Unlock Block command. Once de-asserted, block reverts back locked state; only then unlocked software.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Protection Registers
Product Name includes 128-bit Protection Registers, PR16 through PR0, which used increase system security provide identification capabilities. PR0[63:0] permanently programmed Intel with unique number each flash device. PR0[127:64] through PR16 one-time programmable (OTP) available customer program. Once programmed, user-programmable registers locked prevent further programming. Note: User-programmable bits programed individually. However, once protection register locked, entire user segment locked more user bits programmed.
Figure Protection Register Memory
0x109 PR16
(User-Programmable)
0x102 0x91
(User-Programmable)
0x8A Lock Register 0x89
0x88 User-Programmable 0x85 0x84 Intel Factory-Programmed 0x81 Lock Register 0x80
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
7.2.1
Reading Protection Registers
read Protection Register data, issue Read Identifier command along with address corresponding desired word register data. (See Figure page 36.) Protection Register data read bits time.
7.2.2
Programming Protection Registers
program Protection Register, issue Protection Program command, plus desired Protection Register offset. Figure page appropriate address offsets Protection Register. Only word programmed user segment time. Issuing Protection Program command outside register's address space results status register error (SR4=1).
7.2.3
Locking Protection Registers
lock Protection Register, program corresponding Lock Register issuing Program Lock Register command followed desired Lock Register data. Lock Register already programmed Intel factory locks PR0[63:0]. Lock Register programmed user lock user-programmable portion Protection Register namely PR0[128:64]. rest bits Lock Register used. Lock Register controls locking remaining 128-bit Protection Registers. Each bits Lock Register corresponds 128-bit Protection Registers. example, lock PR6, program Lock Register After Lock Register programmed (locked), user segment Protection Register cannot changed. Protection Program commands written locked section result status register error (SR[5:4]=0b11).
Array Protection
VPEN signal hardware mechanism prohibit array alteration. When VPEN voltage below VPENLK voltage, array contents cannot altered. ensure proper erase program operation, VPEN must valid voltage level. determine status erase program operation, poll status register analyze bits.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Special Modes
This section describes details read status, registers. This sections also details configure signal.
Read Status Register
status device determined reading Status Register. read Status Register, issue Read Status Register command. Status Register data automatically made available following Word Program, Block Erase, Block Lock command sequence. Subsequent reads from device after these command sequences will output that device's status until another valid command written device (e.g. Read Array). Status Register read using single asynchronous- single synchronous-reads only; page- burst-mode reads cannot used read Status Register. Status Register data output D[7:0], while 0x00 output D[15:8]. falling edge (which ever occurs first) updates latches Status Register contents. Ready (SR7) provides overall status device. Status register bits SR[6:1] present status error information about Program, Erase, Suspend, VPEN, Block-Locked operation. Care should taken avoid Status Register ambiguity when issuing valid 2-cycle commands during Erase Suspend. command sequence error occurs during erase-suspend state, Status Register will contain command sequence error status (SR[7,5:4] set). When erase operation resumes finishes, possible errors during erase operation cannot detected Status Register because will contain previous error status. avoid this situation, always clear Status Register prior resuming erase operations.
Table
Status Register Description (Sheet Status Register (SR)
Ready
Default Value =0x80 Erase Error Program Error VPEN Program Suspend Description
Device busy; program erase cycle progress; SR[0] valid. Device ready; SR[6:1] valid. Erase suspend effect. Erase suspend effect. Erase successful. Erase fail Program Sequence Error when with SR[7,4]. Program successful. Program fail Program Sequence Error when with SR[7,5] VPEN within acceptable limits during program erase operation. VPEN VPENLK during program erase operation.
Erase Suspend
BlockLocked Error
BEFP Status
Name
Ready (RDY) Erase Suspend (ES) Erase Error (EE) Program Error (PE) VPEN Error (VE)
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Table
Status Register Description (Sheet Status Register (SR)
Program Suspend Block-Locked Error (LE) Program suspend effect. Program suspend effect. Block locked during program erase. Block locked during program erase; operation aborted. After BEFP data loaded into buffer: Buffered complete. Buffered progress. Default Value =0x80
BEFP Status (PS)
8.1.1
Clear Status Register
Clear Status Register command clears status register functions independent VPEN. Write State Machine sets clears status bits (SR[7:6,2,0]), only sets error bits (SR[5:4,3,1]). Status Register should cleared before starting command sequence avoid ambiguity. device reset also clears Status Register.
Read Device Identifier
Read Device Identifier command instructs device output Manufacturer/ Device Identifier codes, block-lock status, Protection Register data, Configuration Register data when read. (See Section 3.2, "Device Commands" page details issuing Read Device Identifier command.)
Table
Device Identifier Codes
Item Manufacturer Code Device Code Device Code Device Code Device Code Device Code Device Code Block Unlocked Block Locked Block Address Block Locked-Down Block Locked-Down Configuration Register Protection Register Lock 2K-OTP Lock Protection Register Space 0x80 0x89 0x81 0x88 0x8A 0x109 Address Data(1) 0x89 0x8801 0x8802 0x8803 0x8805 0x8806 0x8807 Configuration Register Content Protection Register Lock Lock Protection Register Content Content
NOTE: Data always available D[7:0]. D[15:8] 0x00.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Read Query/CFI
query register contains assortment flash product information such block size, density, allowable command sets, electrical specifications other product information. data contained this register conforms Common Flash Interface (CFI) protocol. obtain information from query register, execute Read Query Register command. Section 3.2, "Device Commands" page details issuing Query command. Refer Appendix "Common Flash Interface" page detailed explanation register. Information contained this register only accessed executing single-word read.
Configuration (Easy package ONLY)
configure signal, execute Configuration command. signal configured level pulse mode. Once configured particular mode, remains that mode until device powered down, reset another Configuration command issued change mode. After power-up reset, default configuration level mode. Level mode works similar Ready/Busy signal (RY/BY#), indicating status Write State Machine (WSM) during program erase operation. Configuration command only given when device busy suspended. possible configurations usage described Table
Table
Configuration Coding Definitions
Pulse Program Complete Notes
Used control HOLD memory controller prevent accessing flash memory subsystem while flash device's busy. Used generate system interrupt pulse when flash device array completed block erase. Helpful reformatting blocks after file system free space reclamation "cleanup." Used generate system interrupt pulse when flash device array completed program operation. Provides highest performance servicing continuous buffer write operations. Used generate system interrupts trigger servicing flash arrays when either erase program operations completed, when common interrupt service routine desired.
Pulse Erase Complete
Reserved
DQ1-DQ0 Configuration Codes
default, level mode; device ready indication pulse Erase Complete
pulse Program Complete pulse Erase Program Complete
NOTES: When configured pulse modes, pulses with typical pulse width invalid configuration code will result both status register bits SR.4 SR.5 being set.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Power Reset
This section provides overview some system level considerations regards flash device. This section provides brief description power-up, power-down, decoupling reset design considerations.
Power-Up/Down Characteristics
order prevent condition that result spurious write erase operation, recommended power-up power-down VCCQ together. also recommended power-up VPEN with slightly after VCC. Conversely, VPEN must power down with slightly before VCC.
Power Supply Decoupling
When device enabled, many internal conditions change. Circuits energized, charge pumps switched internal voltage nodes ramped. this internal activities produce transient signals. magnitude transient signals depends device system loading. minimize effect these transient signals, ceramic capacitor required across each VCC/VSS VCCQ/VSSQ signal. Capacitors should placed close possible device connections. Additionally, every eight flash devices, electrolytic capacitor should placed between power supply connection. This capacitor should help overcome voltage slumps caused (print circuit board) trace inductance.
Reset Characteristics
holding flash device reset during power-up power-down transitions, invalid conditions masked. flash device enters reset mode when RST# driven low. reset, internal flash circuitry disabled outputs placed high-impedance state. After return from reset, certain amount time required before flash device able perform normal operations. After return from reset, flash device defaults asynchronous page mode. RST# driven during program erase operation, program erase operation will aborted memory contents aborted block address longer valid. Figure "Reset Operation Waveforms" page detailed information regarding reset timings.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
10.0
10.1
Electrical Specifications
Absolute Maximum Ratings
absolute maximum ratings shown Table
Warning:
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability.
Table Absolute Maximum Ratings
Parameter Temperature under bias Storage temperature Voltage signal (except VCCQ) VCC1 (K3) voltage VCC2 (K18) voltage VCCQ1 (K3) voltage VCCQ2 (K18) voltage Output short circuit current Maximum Rating +125 -0.5 VCCQ +0.5 -0.2 +4.1 -0.2 +3.8 -0.2 +4.1 -0.2 +2.45 Notes
NOTES: Specified voltages with respect VSS. Minimum voltage -0.5 input/output signals -0.2 VCCQ. During transitions, this level undershoot -2.0 periods Maximum voltage +0.5 which, during transitions, overshoot +2.0 periods Maximum voltage input/output signals VCCQ VCCQ +0.5 which, during transitions, overshoot VCCQ +2.0 periods Program/erase voltage normally V-3.6 Output shorted more than second. more than output shorted time.
10.2
Operating Conditions
Symbol VCC1 VCC2 VCCQ1 VCCQ2 Block Erase Cycles Parameter Operating Temperature Core Voltage (K3) Core Voltage (K18) Vccq Supply voltage (K3) Vccq Supply voltage (K18) Blocks, 2.70 2.70 2.375 1.65 100,000 3.60 3.30 3.60 1.95 Units Cycles
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
10.3
Current Characteristics
Table Current Characteristics
VCCQ Parameter Input Load Current Notes 1.65 1.95 2.375 Unit Test Condition VCCMAX, VCCQ VCCQMAX, VCCQ VCCMAX, VCCQ VCCQMAX, VCCQ CMOS Inputs, VCCMAX, VCCQ VCCQMAX, Device Disabled RST# VCCQ±0.2V/GND±0.2V VCCMAX, tACC tAVQV Word Read Burst length Burst length tACC tAVQV, tAPA VCCMAX MHz(K3), MHz(K18) VCCMAX VIL, VIH, Inputs
Output Leakage Current Mbit, Mbit Mbit Single Word Read Asynchronous Page Mode
ICCS
Standby
ICCR
Average Read Current Synchronous Burst
ICCW ICCE ICCWS, ICCES
Program Current Block Erase Current Program Suspend Block Erase Suspend Current
CMOS Inputs, VPEN CMOS Inputs, VPEN Device enabled
NOTES: currents unless noted. Typical values +25°C, best-case address pattern. Maximum values worst-case address pattern. Includes STS. CMOS inputs/outputs either Current values specified over specific temperature range (-40°C +85°C). Sampled, 100% tested. ICCES, ICCWS specified with device deselected. device read while erase suspend/program suspend, current ICCES plus ICCR ICCWS plus ICCR. VPEN VPENLK inhibits block erase, program lock-bit operations. Don't VPEN outside valid ranges.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Table Voltage Characteristics
VCCQ Parameter(1) Input Voltage Input High Voltage Output Voltage Output High Voltage CMOS CMOS Note 1.65 1.95 VCCQ -0.4 VCCQ 2.375 VCCQ Unit VCCMIN, VCCQ VCCQMIN, VCCMIN, VCCQ VCCQMIN, -100 Test Condition
CMOS
VPENLK VPENH VLKO VCCQLKO
CMOS
VCCQ -0.2 1.65 1.95
VCCQ -0.2
VPEN Lock-Out during normal operations VPEN during Block Erase, Program LockBit operations Lockout Voltage VCCQ Lockout Voltage
NOTES: currents unless noted. Typical values typical VCC, +25°C. Includes STS. Sampled, 100% tested. ICCES, ICCWS specified with device deselected. device read while erase suspend/program suspend, current ICCES plus ICCR ICCWS plus ICCR. VPEN VPENLK inhibits block erase, program lock-bit operations. Don't VPEN outside valid ranges. Block erases, programming lock-bit configurations inhibited when VCC<VLKO, guaranteed range between VLKOMIN VCCMIN, above VCCMAX. undershoot -0.4V overshoot VCCQ +0.4V durations less.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
10.4
Read Operations
Table Read Characteristics (Sheet
VCCQ Parameter(3) Density Note 1.65 1.95V 2.375 Unit
Asynchronous Specifications Mbit tAVAV Read cycle time Mbit Mbit Mbit tAVQV Address output delay Mbit Mbit Mbit tELQV output delay Mbit Mbit tGLQV output delay Mbit tPHQV RST# high output delay Mbit Mbit tELQX tGLQX tEHQZ tGHQZ tEHEL tELTL/H tEHTZ output Low-Z output Low-Z high output High-Z high output High-Z Output hold from first occurring address, change high WAIT high WAIT High-Z
Latching Specifications R101 R102 tAVVH tELVH Address setup ADV# high ADV# high Mbit R103 tVLQV ADV# output delay Mbit Mbit R104 R105 R106 tVLVH tVHVL tVHAX ADV# pulse width ADV# pulse width high Address hold from ADV# high
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Table Read Characteristics (Sheet
VCCQ R108 tAPA Parameter(3) Page address access Density Note 1.65 1.95V 2.375 Unit
Clock Specifications R200 R201 R202 R203 fCLK tCLK tCH/L tCHCL frequency period high/low time fall/rise time
Synchronous Specifications R301 R302 R303 R304 R305 R306 R307 R312 tAVCH tVLCH tELCH tCHQV tCHQX tCHAX tCHTL/H tCHVL Address valid setup ADV# setup setup output delay Output hold from Address hold from WAIT delay ADV#
NOTES: high between synchronous reads Data read voltage VCCQ1. Figure Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate. delayed tELQV-tGLQV after without impact tELQV. Address hold synchronous burst-mode tCHAX tVHAX, whichever timing specification satisfied first. Sampled, 100% tested. devices configured standard word read mode, R108(tAPA) will equal R2(tAVQV). clock duty cycle should (app.). Applies only subsequent synchronous reads.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Figure Single Word Asynchronous Read Waveform
Address ADV# WAIT Data RST#
Figure Single Word Latched Asynchronous Read Waveform
Address A[1:0][A] R106 R101 R105 ADV# CE#[E} OE#[G] WAIT Data [D/Q]
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Figure Page Mode Read Waveform
R106 A[Max:3] R101 A[2:0] R105 ADV# WAIT Data [D/Q] R108 R108
Figure Single Word Burst Read Waveform
Latency Count R301 R306 Address R101 R105 R104 ADV# R303 R102 WAIT R304 Data [D/Q]
NOTE: WAIT (shown active low) configured assert either during, clock before, valid data.
R106
R307
R305
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Figure Word Synchronous Burst Read Waveform
Latency R304 R305 Address R106 R101 R105 ADV# WAIT DATA [D/Q] R304 R304 Note R305 R305
NOTES: Section 4.9.13, "First Access Latency Count (CR.11-13)" page describes insert clock cycles during initial access. WAIT (shown active high) configured assert either during clock before valid data.
Figure Clock Input Waveform
R201
R202 R203
CLKINPUT.WMF
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
10.5
Write Operation
Table Write Characteristics
VCCQ Parameter Density Notes 1.65 1.95 2.375 Unit
Mbit tPHWL RST# high recovery setup write pulse width Data setup high Address setup high hold from high Data hold from high Address hold from high pulse width high VPEN Setup (CE#) Going High VPEN Hold from Valid SRD, Going High hold from Status read setup high Write recovery before read high data valid Mbit Mbit tELWL tWLWH tDVWH tAVWH tWHEH tWHDX tWHAX tWHWL tVPWH (tVPEH) tQVVL tQVBL tBHWH tWHGL tWHQV
tAVQV
tAVQV
NOTES: Read timing characteristics during block erase, program lock-bit operations same during read-only operations. Refer Characteristics Read-Only Operations. write operation initiated terminated with either WE#. Sampled, 100% tested. Write pulse width (tWLWH) defined from going (whichever goes last) going high (whichever goes high first). Hence, tWLWH tELEH tWLEH tELWH. Write pulse width high (tWHWL) defined from going high (whichever goes high first) going (whichever goes last). Hence, tWHWL tEHEL tWHEL tEHWL. array access, tAVQV required addition tWHGL accesses after write. timings based configured RY/BY# default mode.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Figure Write Write Waveform
Address Data [D/Q] RST#/
Figure Asynchronous Read Write Waveform
Address Data [D/Q] RST#
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Figure Asynchronous Write Read Waveform
Address
Data [D/Q]
10.6
Block Erase Program Operation Performance
Table Block Erase Program Operation Performance
tWHQV1, tEHQV1 tWHQV2, tEHQV2 tWHQV3, tEHQV3 tBBWB tBWB tBEFP-SETUP tWHQV4, tEHQV4 tWHRH1, tEHRH1 tWHRH, tEHRH tSTS
Parameter
Write Buffer Program Time (Time program bytes/32 words) Word Program Time (Using Word Program Command) Block Program Time (Using Write-to- Buffer Command) Buffered Buffer Write Time Buffered Block Write Time Buffered Set-up Time Block Erase Time Program Suspend Latency Time Read Erase Suspend Latency Time Read Pulse Width Time
Notes
0.58
Unit
NOTES:
Typical values measured +25°C nominal voltages. Assumes corresponding lock-bits set. Subject change based device characterization. These performance numbers valid speed versions. Sampled 100% tested. Excludes system level overhead. These values valid when buffer full, start address aligned 32-bit boundary. Effective word program time (tWHQV1, tEHQV1) 10.0 µs/word (typ).
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
10.7
Reset Operation
Figure Reset Operation Waveforms
Reset during read mode
RST#
Reset during program block erase
Abort Complete
RST#
Reset during program block erase
Abort Complete
RST#
Power-up RST# high
RESET.WMF
Table Reset Specifications
Symbo Parameter Notes Unit
tPLPH tPLRH tVCCPH
RST# pulse width RST# device reset during erase RST# device reset during program Power Valid RST# de-assertion (high)
1,2,3,4 1,3,4,7 1,3,4,7 1,4,5,6
NOTES: These specifications valid product versions (packages speeds). device reset tPLPH <tPLPH MIN, this guaranteed. applicable RST# tied Vcc. Sampled, 100% tested. RST# tied supply, device will ready until tVCCPH after min. RST# tied supply/signal with VCCQ voltage levels, RST# input voltage must exceed until VCC(min). Reset completes within tPLPH RST# asserted while erase program operation executing.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
10.8
Test Conditions
Figure Input/Output Reference Waveform
VCCQ
Input VCCQ/2
Test Points
VCCQ/2 Output
IO_REF.WMF
NOTE: test inputs driven VCCQ Logic Logic "0." Input/output timing begins ends VCCQ/2. Input rise fall times (10% 90%) Worst case speed occurs VCCMIN.
Figure Transient Equivalent Testing Load Circuit
VCCQ Device Under Test
LOAD_CKT.WMF
NOTE: included capacitance.
Table Test Configuration Component Value Worst Case Speed Conditions
Test Configuration VCCQMIN Standard Test NOTE: includes capacitance. (pF)
10.9
Capacitance
Parameter(1) Input Capacitance Output Capacitance
Table Capacitance
COUT Unit Condition VOUT
NOTES: +25°C, MHz. Sampled, 100% tested.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Appendix Write State Machine (WSM)
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Appendix Common Flash Interface
Query Structure Overview
Query command causes flash component display Common Flash Interface (CFI) Query structure "database." structure sub-sections address locations summarized below. further details AP-646 Common Flash Interface (CFI) Command Sets (Order 292204) full description CFI.
Table Query Structure(1)
Offset 00000h 00001h (BA+2)h(2) 000(04 -0F)h 00010h 0001Bh 00027h P(3) Block Status Register Reserved Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table 0089 Sub-Section Name Description Manufacturer Code Device Code Block-specific information Reserved vendor-specific information Command vendor data offset Device timing voltage information Flash device layout Vendor-defined additional information specific Primary Vendor Algorithm
NOTES: Refer Query Structure Output section offset detailed definition offset address function device width mode. beginning location Block Address (e.g., 010000h beginning location block when block size Kword). Offset defines which points Primary Intel-specific Extended Query Table.
Query Identification String
Identification String provides verification that component supports Common Flash Interface specification. also indicates specification version supported vendor-specified command set(s).
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Table Identification
Offset Length Description Query-unique ASCII string "QRY" Addr. Primary vendor command control interface code. 16-bit code vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command control interface code 0000h means second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists Code Value
System Interface Information
following tables give information power supplies program erase time details output device when system software requests System Interface Information. values stored available from offset address 1Bh.
Table System Interface Information
Offset Length Description logic supply minimum program/erase voltage bits bits volts logic supply maximum program/erase voltage bits bits volts [programming] supply minimum program/erase voltage bits bits volts [programming] supply maximum program/erase voltage bits bits volts such that typical single word program time-out such that typical buffer write time-out such that typical block erase time-out such that typical full chip erase time-out such that maximum word program time-out times typical such that maximum buffer write time-out times typical such that maximum block erase time-out times typical such that maximum chip erase time-out times typical
Addr.
Code
Value
1024
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Device Geometry Definition
following tables give critical details provided when software requests flash device geometry information such size device, types read interfaces, program buffer size etc.,
Table Device Geometry Definition
Offset Length Description such that device size number bytes Flash Device Interface Code assignments: Address Value Meaning
Table Below
such that maximum number bytes write buffer=2n Number Erase Blocks Within Device: means erase blocking; device erases "bulk" specifies number device partition regions with more contiguous samesize erase blocks Array size (total blocks) (individual blocks size) Erase Block Region Information bits 0-15=y, number identical-size erase blocks bits 16-31=z, region erase block(s) size bytes
Table Below
Table 46a. Erase blocks Erase block region information
Address Mbit Mbit Mbit)
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Primary Vendor Specific Extended Query Table
Certain flash features commands optional. Primary Vendor Specific Extended Query Table specifies this other similar information.
Table Primary Vendor Specific Extended Query Table
Offset(1) P=31h (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h Major version number, ASCII Minor version number, ASCII Primary Extended Query Table Unique ASCII String "PRI" Length Description (Optional Flash Features Commands) Optional feature command support(1=yes, 0=no) bits 11-31 reserved; undefined bits "0". then another field optional features follows 30-bit field. Chip Erase Supported Suspend Erase Supported -Suspend Program Supported Legacy lock/unlock Supported Queued Erase Supported Instant Individual Block Locking Supported Protection Bits Supported Page-mode read supported Synchronous Read Supported Simultaneous Operations Supported Feature space Supported Code Value
bit3
(P+5)h (P+6)h (P+7)h (P+8)h
Supported Functions After Suspend: Read Array, Status, Query (P+9)h Other Supported Operations are: bits reserved; undefined bits Program supported after erase suspend
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Table Primary Vendor Specific Extended Query Table
Offset(1) P=31h Length Description (Optional Flash Features Commands) Block Status Register Mask (P+A)h (P+B)h bits reserved; undefined bits Block Lock-bit status register active Block Lock down status active Unlock down logic supply highest performance program/ erase voltage (P+C)h bits value 100mV bits value Volts optimum program/erase supply voltage bits value 100mV bits value Volts Code Value
(P+D)h
-0.0V
Table Protection Register Information
Offset(1) P=31h
(P+E)h
Length
Description(Optional Flash Features Commands)
Number Protection register fields JEDEC space. "00h", indicates that protection fields available Protection field Protection description This field describes user-available Time Programmable(OTP) protection register bytes. Some preprogrammed with device-unique serial numbers. Others user-programmable. Bits 0-15 point protection register lock byte, section's first byte. following bytes factory pre-programmed user-programmable bits Lock/bytes JEDEC-plane physical address bits 8-15 =Lock/bytes JEDEC-plane physical high address bits 16-23 such that factory pre-programmed bytes bits 24-31 such that user-programmable bytes Protection field Protection description Bits 0-31 point protection register physical Lockword address Jedec-plane. Following bytes factory user-programmable Bits 32-39 ="n"-factory pgm'd groups(low byte) Bits 40-47="n"-factory pgm'd groups(high byte) bits 48-55 ="n" such that 2n=factory programmable bytes group bits 56-63="n"-user pgm'd groups(low byte) bits 64-71="n"-user pgm'd groups(high byte) bits 72-79="n" such that user programmable bytes/ group
Code
Value
(P+F)h, (P+10)h, (P+11)h, (P+12)h
bytes bytes
(P+13)h, (P+14)h, (P+15)h, (P+16)h, (P+17)h, (P+18)h, (P+19)h, (P+1A)h, (P+1B)h, (P+1C)h
NOTE:
variable pointer which defines offset 15h.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Table Burst/Page Read Information
Offset(1) P=31h Length Description(Optional Flash Features Commands) Page Mode Read Capability (P+1D)h bits 0-7="n" such that value represents number read page bytes. offset device word width determine page mode data output width. indicates read page buffer. Number synchronous mode read configuration fields that follow. indicates burst capability Synchronous Mode Read Capability Configuration Bits Reserved bits such that 2n+1 value represents maximum number continuous synchronous burst reads when device configured maximum word width. value indicates that device capable continuous linear bursts until that will output data until internal burst counter reaches device's burstable address space. This field's 3-bit value written directly Read Configuration Register Bits device configured maximum word width. offset word width determine burst data output width. Synchronous Mode Read Capability Configuration bytes Code Value
(P+1E)h
(P+1F)h
(P+20)h
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Appendix Flowcharts
Figure Write Buffer Flowchart
Operation Write
Start
Command Write Buffer
Comments Data 0xE8 Addr Block Address XSR.7 Valid Addr Block Address Check XSR.7 Write Buffer available Write Buffer available Data Count corresponds count Addr Block Address Data Write Buffer Data Addr Start Address Data Write Buffer Data Addr Block Address
Device Supports Buffer Writes? Time-out Loop Counter Next Target Address Issue Write Buffer Command 0xE8 Block Address Read Extended Status Register Block Address)
Single Word Programming
Read
Standby
Write (Notes Write (Notes Write (Notes Write Write Confirm
Data 0xD0 Addr Block Address Status register Data Transition either updates Addr Block Address Check SR.7 Ready Busy
Read
Buffer Available? XSR.7 Write Word Count, Block Address Write Buffer Data, Start Address X=X+1 Write Buffer Data, Block Address Write Confirm 0xD0 Block Address Abort Write Buffer? Write another Block Address Write Buffer Aborted Time-out Count Expired?
Standby
Word count values 7-DQ0 loaded into Count register. Count ranges this device 0x00 0x1F. device outputs status register when read (XSR longer available). Write Buffer contents will programmed device start address destination flash address. Align start address Write Buffer boundary maximum programming performance (i.e., 5-A1 start address device aborts Write Buffer command current address outside original block address. Status register indicates "improper command sequence" Write Buffer command aborted. Follow this with Clear Status Register command. Full status check done after erase write sequences complete. Write 0xFF after last operation reset device read array mode.
Another Write Buffer? Read Status Register
Issue Read Status Register Command
SR.7 Full Status Check Desired Programming Complete
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Figure Word Programming Flowchart
WORD PROGRAM PROCEDURE
Start
Operation
Command Program Setup
Comments Data 0x40 Addr Location Program Data Data Program Addr Location Program Status Register Data. Toggle Update Status Register Data Check SR.7 Ready Busy
Write 0x40, Address Write Data Address
Write
Write
Data
Read
Read Status Register SR.7 Full Status Check Desired Suspend Program
Suspend Program Loop
Standby
Repeat subsequent programming operations. full status check done after each program after sequence program operations. Write 0xFF after last program operation read array mode.
Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above)
Operation Standby Command Comments Check SR.3 VPEN Error Detect Check SR.4 Data Program Error Check SR.1 Attempted Program Locked Block Program aborted
SR.3 SR.4 SR.1 Program Successful
VPEN Range Error
Standby
Standby
Program Error
SR.3 MUST cleared before further attempts allowed rite State Machine during program attempt
Device Protect Error
SR.4, SR.3 SR.1 only cleared Clear Staus Register command cases where multiple locations programmed before full status checked. error detected, clear status register before attempting retry other error recovery.
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Figure Program Suspend/Resume Flowchart
Operation Write
Start
Command Program Suspend
Comments Data 0xB0 Addr Status Register Data; Toggle Update Status Register Data Addr Check SR.7 Ready Busy Check SR.2 Program Suspended Program Completed
Write 0xB0
Read
Read Status Register
Standby
SR.7 SR.2 Write 0xFF
Standby
Program Completed
Write
Read Array
Data 0xFF Addr Read array data from block other than being programmed.
Read Program Resume
Write
Data 0xD0 Addr
Read Array Data
Done Reading Write 0xD0
Write 0xFF
Program Resumed
Read Array Data
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Figure Buffered Enhanced Factory Programming Procedure Flowchart
BEFP Setup
Start
BEFP Program Verify
Read Status Register
BEFP Exit
Read Status Register
Unlock Block
SR.0=1=N
Data Stream Ready? SR.0=0=Y
SR.7=0=N
BEFP Exited? SR.7=1=Y Full Status Check Procedure
Write Address
Initialize count
Write Address
Write Data Address
Program Complete
BEFP Setup time
Increment count
Read Status Register
Check
BEFP Setup Done?
SR.7=0=Y
Check VPEN Lock errors (SR.3, SR.1)
SR.0=1=N
SR.7=1=N
Read Status Register
Program Done? SR.0=0=Y
Exit Last Data? Write FFFFh Address other block BEFP Setup State Write Write (note Write Read (note Standby BEFP Setup Done? Unlock Block BEFP Setup BEFP Confirm Comments Unlock block Data Address Data Address Status Register Address Check SR.7 BEFP ready BEFP ready State Read BEFP Program Verify Comments Status Register Address Check SR.0 Ready data ready data State Read BEFP Exit Comments Status Register Address Check SR.7 Exit Completed Exit Completed
Data Standby Stream Ready? Initialize Standby Count Write (note Standby Standby Read Inc. Count Buffer Full? Buffer Full?
Standby
Repeat subsequent blocks. After BEFP exit, Full Status Check determine program error occurred. Full Status Check procedure Word Program flowchart. Write enter read array mode.
Data word program Address yes, read SR.0 load next data word
SR.7 Error Check SR.3, SR.1 Standby Condition SR.3 VPEN error Check SR.1 locked block NOTES: first word address programmed within target block. must align write buffer boundary. status register updated when system read toggles low-high-low. Write buffer contents programmed sequentially flash array starting WA0. internally increments addressing.
Status Register Address Check SR.0 Program Program done Standby Done? Program progress Standby Last Data? Fill Buffer again Exit Program Verify phase
Write
Exit Program yes, read SR.0 Verify load next data word Phase
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Figure Block Erase Flowchart
Start
Operation
Command
Comments Data 0x20 Addr Within Block Erased Data 0xD0 Addr Within Block Erased Status Register Data Toggle Update Status Register Data Check SR.7 Ready Busy
Write 0x20 Block Address Write 0xD0 Block Address Read Status Register SR.7 Full Status Check Desired Suspend Erase Suspend Erase Loop
Write
Erase Setup
Write
Erase Confirm
Read
Standby Repeat subsequent block erasures.
Full Status Check done after each block erase after sequence block erasures. rite after last write operation reset device read array mode.
Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above)
Operation Standby Command Comments Check SR.3 VPEN Detect Check SR.4,5 Both Command Sequence Error Check SR.5 Block Erase Error Check SR.1 Attempted Erase Locked Block Erase Aborted
SR.3 SR.4,5 SR.5 SR.1 Block Erase Successful
VPEN Range Error
Standby
Command Sequence Error
Standby
Standby
Block Erase Error
MUST cleared, during erase attempt, before further attempts allowed Write State Machine. SR.1, only cleared Clear Staus Register Command, cases where multiple blocks erased before full status checked. error detected, clear status register before attempting retry other error recovery.
Attempted Erase Locked Block Aborted
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Figure Erase Suspend/Resume Flowchart
ERASE SUSPEND/RESUME PROCEDURE
Start
Operation Write
Command Erase Suspend
Comments Data 0xB0 Addr =Block Suspend (BA) Status Register Data Toggle Update Status Register Data Addr Suspended Block (BA) Check SR.7 Ready Busy Check SR.6 Erase Suspended Erase Completed
Write 0xB0
Read
Write 0x70
Standby
Read Status Register
Standby
SR.7 SR.6 Read Read Array Data Read Write? Done? Write 0xD0
Write Read Write
Read Array Program
Data Read Write Addr Write Read Address Read array program data from/to block other than being erased.
Erase Completed
Write Erase Resume
Data 0xD0 Addr Suspended Block (BA)
Program Program Loop
Write 0xFF
Erase Resumed
Read Array Data
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Figure Protection Register Programming Flowchart
Start
Operation
Command Protection Program Setup Protection Program
Comments
Write 0xC0 (Protection Reg. Program Setup) Write Protect. Register Address/Data
rite rite
Data 0xC0 Data Data Program Addr Location Program Status Register Data Toggle Update Status Register Data Check SR.7 Ready Busy
Read
Standby
Read Status Register
SR.7 Full Status Check Desired Program Complete
Protection Program operations only addressed within protection register address space. Addresses outside defined space will return error. Repeat subsequent programming operations. Full Status Check done after each program after sequence program operations. rite after last program operation reset device read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above)
Operation Standby Command Comments SR.1 SR.3 SR.4 VPEN Prot. Reg. Prog. Error Register Locked: Aborted
SR.3, SR.4
VPEN Range Error
Standby
SR.1, SR.4
Protection Register Programming Error Locked-Register Program Attempt Aborted
Standby
SR.3 MUST cleared, during program attempt, before further attempts allowed Write State Machine. SR.1, SR.3 SR.4 only cleared Clear Staus Register Command, cases multiple protection register program operations before full status checked. error detected, clear status register before attempting retry other error recovery.
SR.1, SR.4
Program Successful
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Figure Block Lock Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Start
Lock Setup
Command Operation Write Lock Setup
Comments Data Addr Block lock/unlock/lock-down (BA)
Write Block Address
Lock Confirm
Write 01,D0,2Fh Block Address
Read Plane
Write
Lock, Data (Lock block) Unlock, (Unlock block) Lockdown (Lockdown block) Confirm Addr Block lock/unlock/lock-down (BA) Read Plane Data Addr Block address offset (BA+2)
Write Optional
Write (Optional)
Read Block Lock Status
Read Block Lock Block Lock status data (Optional) Status Addr Block address offset (BA+2) Standby (Optional) Read Array Confirm locking change (See Block Locking State Transitions Table valid combinations.) Data Addr Block address (BA)
Locking Change?
Read Array
Write
Write Partition Address Lock Change Complete
LOCK_OP.WMF
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Appendix Mechanical Package Information
Figure Easy Package Drawing
Ball Corner Ball Corner
View Ball side down
Bottom View Ball Side
Seating Plane
Note: Drawing scale
Table Easy Package Dimensions Table
Millimeters
Symbol Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Package Body Length (256 Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along (64/128/256 Corner Ball Distance Along (64/128 Corner Ball Distance Along (256 1.400 2.900 3.900 1.500 3.000 4.000 0.330 9.900 12.900 14.900 0.250 0.780 0.430 10.000 13.000 15.000 1.000 0.100 1.600 3.100 4.100 0.0551 0.1142 0.1535 0.0591 0.1181 0.1575 0.530 10.100 13.100 15.100 0.0130 0.3898 0.5079 0.5866 1.200 0.0098 0.0307 0.0169 0.3937 0.5118 0.5906 0.0394 0.0039 0.0630 0.1220 0.1614 0.0209 0.3976 0.5157 0.5945 Notes
Inches
0.472
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Figure Package Drawing
Ball Corner Ball Corner
View Bump Side Down
Seating Plane
Bottom View Ball Side
Note: Drawing scale
Table Package Dimensions Table
Millimeters Symbol Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Width (128 Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along Corner Ball Distance Along (128 Corner Ball Distance Along 1.125 2.775 2.150 1.225 2.875 2.250 0.325 7.600 10.900 8.900 0.150 0.665 0.375 7.700 11.000 9.000 0.750 0.100 1.325 2.975 2.350 0.0443 0.1093 0.0846 0.0482 0.1132 0.0886 0.425 7.800 11.100 9.100 0.0128 0.2992 0.4291 0.3504 1.000 0.0059 0.0262 0.0148 0.3031 0.4331 0.3543 0.0295 0.0039 0.0522 0.1171 0.0925 0.0167 0.3071 0.4370 0.3583 Notes Inches 0.0394
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Figure Package Drawing
Indicator
Corner
View Bump side down
Bottom View Bump side
Side View Note: Drawing scale Seating Plan
Table (256 Dimensions Table
Millimeters Symbol Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along Corner Ball Distance Along 2.650 2.150 2.750 2.250 0.325 14.900 8.900 0.150 0.665 0.375 14.500 9.000 0.750 0.100 2.850 2.350 0.1043 0.0846 0.1083 0.0886 0.425 14.600 9.100 0.0128 0.5669 0.3504 1.000 0.0059 0.0262 0.0148 0.5709 0.3543 0.0295 0.0039 0.1122 0.0925 0.0167 0.5748 0.3583 Notes Inches 0.0394
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Appendix Additional Information
Order Number 298636 298136 292237 297859 292222 292221 292204 292202 298161
Document Tool Volt Intel Synchronous StrataFlash Memory 256-, 128-, 64-Mbit Specification Update Intel® Persistent Storage Manager User's Guide AP-689 Using Intel Persistent Storage Manager AP-677 Intel StrataFlash Memory Technology AP-644 Designing Intel StrataFlash® Memory into Intel® Architecture AP-663 Using Intel StrataFlash Memory Write Buffer AP-646 Common Flash Interface (CFI) Command Sets AP-644 Migration Guide Volt Intel StrataFlash® Memory Intel Flash Memory Chip Scale Package User's Guide
NOTES: Please call Intel Literature Center (800) 548-4725 request Intel documentation. International customers should contact their local Intel distribution sales office. Visit Intel's World Wide home page http://www.intel.com technical documentation tools. most current information Intel StrataFlash memory, visit website http://
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Appendix Order Information
Package Designator, Extended Temperature (-40C +85C) 0.75 Easy Product line designator Intel® Flash products Density Mbit (8-MB x16) Mbit (16-MB x16) Mbit (32-MB x16) Access Speed (ns) Mbit 110,120, Mbit 115, 125, Mbit 120, 130, Process Identifier 0.18um Voltage Identifer (VCC VCCQ) 3.6V 3.6V 3.6V 1.65-1.95V Product Family Synchronous Intel StrataFlash® Memory
Table Valid Combinations
Density GE28F640K3C110 GE28F640K3C120 GE28F640K18C110 GE28F640K18C130 GE28F128K3C115 GE28F128K3C125 GE28F128K18C115 GE28F128K18C135 GE28F256K3C120 GE28F256K3C130 GE28F256K18C120 GE28F256K18C140 Easy RC28F640K3C110 RC28F640K3C120 RC28F640K18C110 RC28F640K18C130 RC28F128K3C115 RC28F128K3C125 RC28F128K18C115 RC28F128K18C135 RC28F256K3C120 RC28F256K3C130 RC28F256K18C120 RC28F256K18C140
Mbit
Mbit
Mbit
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