4401035 VHDL Based Design Methodology Kirk email: access-sup

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4401035 VHDL Based Design Methodology Kirk email: access-sup

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VHDL Based Design Methodology
4401035
VHDL Based Design Methodology
Kirk email: access-support@cadr.amis.com
Some customers also interested prospect being able explore design space, although currently taking advantage this capability. believe that HDLs managing design complexity. While there always much talk about design teams, believe that most ASIC devices designed just person. question many gates single designer deal with before design becomes unmanageable? Traditional schematic capture methods seem place limit somewhere around gates. With HDLs, limit single engineer taken giant step, perhaps 100k gates higher. With good library reusable modules, it's quite possible that this number could even jump gate range. Thus, HDLs incredible amount power into hands individual designer. trend towards larger gate counts important ASIC vendor. only does this trend mean more silicon will sold, also think will more silicon that specializes building. HDLs will make easier design large ASICs with specialized functionality. Hence will significant growth medium volume complex ASICs. volumes will below what largest ASIC vendors support, high cost effective FPGA solutions.
Introduction
Hardware description languages (HDLs) have revolutionized digital systems designed. This revolution been quietly building steam, exploded last several years. ASIC vendor, provided base line support those customers adopted this methodology early However, time come adopt this methodology own. This section describes reasons behind AMI's transition HDLs, well steps that taking this transition.
Industry Trends
Over past four years have seen Verilog VHDL from being used less than designs nearly 100% large designs (over gates) many smaller designs well. customers report cycle time reductions times versus traditional schematic capture methodology. reductions both expressive power HDLs synthesis technology. customers expect achieve even greater cycle time reductions they gain more experience methodology they expand their libraries reusable code modules.
Language Selection
Clearly, HDLs important AMI's future. question then, which support. designs fabricate which HDLs, about currently being
VHDL Based Design Methodology
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designed with VHDL remaining with Verilog. Q3'94, software industry reported that VHDL sales exceeded Verilog sales first time, even though Verilog clearly larger installed base. Universities training engineering students VHDL every student learning Verilog. Another important consideration that VHDL been widely adopted FPGA vendors. VHDL IEEE Standard recently completed second round standardization with VHDL-1993 Standard also being adopted ANSI. Verilog just recently achieved IEEE Standard status. VHDL bigger more complex language, also seems more general purpose perhaps little less associated with particular vendor. With VHDL-1993 Standard came number very important features which enable language also support AMI's NETRANS FPGA migration business. With understanding these issues, made internal decision 1994 completely overhaul internal system VHDL'93 based. team composed Field Applications Engineers, Design Engineers, Library Developers Software Engineers assembled facilitate this transition. Part this team's responsibility develop infrastructure within such that sales, marketing, engineering, test management personnel educated relevant issues pertaining VHDL based designs.
VHDL Structural Netlists
Since 1978, used internal netlist format, called Bolt, backplane. design kits included tool which wrote Bolt. variety translators existed which supported interfaces wide array systems. This capability became essential component AMI's popular NETRANS FPGA migration business. Bolt backplane process being replaced VHDL backplane. first phase introduction equivalent capability centered around VHDL Structural (Gate Level) Netlist representation. Follow-up phases will support Behavioral capability. With introduction VHDL Structural Netlist backplane, accepts VHDL netlists directly. translations performed, there syntax limitations data exchanges with customer VHDL level. Historically, offered extensive design conversion enhancement services customers. These include capabilities such FPGA migration, ASIC second sourcing, automatic scan test insertion, boundary scan insertion, clock synthesis logic optimization. major problem with these services difficulty regenerating aesthetically pleasing schematic diagrams designer work with. With VHDL, have noticed that designers will accept modified VHDL netlist. Since real design coded textual description anyway modified netlist retains original design names, there issue.
VHDL Based Design Methodology
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long passes their regression tests they satisfied. addition internal conversion VHDL, added additional support VHDL design kit. These tools give customer more control over final structural netlist. additional tools available this time design checker, delay calculator, static timing analyzer test bench generator.
compatible with AMI's gate level models running industry standard VHDL simulators. addition, VHDL Delay Calculator computes delays five simulation corners which part AMI's standard design methodology. 5-corners represent best, typical worst case well important corners CMOS: best case rising with worst case falling, worst case rising with best case falling. These five sets delay numbers compactly written files. VHDL Delay Calculator essential element AMI's strategy provide VHDL Signoff Simulation capability.
Design Checker
VHDL Design Checker (based original Design Analyzer) checks wide variety design problems. These checks based many years experience with thousands ASIC designs. list checks includes both generic design problems well issues particular AMI's technology. clean bill health from Design Checker good indication that design will proceed smoothly through AMI. also greatly increases probability first time silicon success.
Static Timing Analyzer
companion tool VHDL Delay Calculator AMI's Static Timing Analyzer. This tool also included VHDL Design Kit. uses same precise delay information verify design's timing. VHDL Static Timing Analyzer reports longest paths, maximum clock frequency, checks setup hold time violations. With larger larger designs become essential able separate functional timing verification.
Delay Calculator
developed proprietary approach modeling non-linear delay propagation effects sub-micron technology. Equation Based Modeling approach provides Spice-like accuracy, typically within Spice. VHDL Delay Calculator software implementation this approach which takes VHDL netlist interconnect parasitics compute delays Standard Delay Format (SDF). This file
Test Bench Generator
VHDL Test Bench Generator helps with importing test benches into manufacturing test programs. also simplifies process setting running 5-corner simulations. analyzes netlist vectors create test bench entity that performs on-the-fly comparison 5corner data writes tester compati-
VHDL Based Design Methodology
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vectors. VHDL Test Bench Generator also included VHDL Design Kit.
Third Party Tool Support
supported leading third party VHDL tools with synthesis simulation libraries number years. These libraries continually being updated stay current with industry standard simulators synthesizers.
only significant difference between Verilog VHDL, that internally, will continue translate Verilog gate level netlists. However, instead translating Bolt, will translate VHDL. addition supporting Verilog synthesis libraries, process bringing Verilog sign-off simulation status Cadence Verilog Intergraph VeriBest products. Verilog Design includes Delay Calculator Test Bench Generator. will also accept Verilog gate level netlists.
VHDL Signoff Simulation
currently process bringing VHDL with VITAL models sign-off status. VITAL models currently very accurate. working with VITAL committee obtain sign-off quality models. currently supports VITAL modeling standard, anticipates that VITAL will further serve reduce modeling support load. Models using both IEEE 1164 VITAL should give same results compliant simulator. noted previously, provides delay calculator which generates delay information format. expect this industry standard back annotation format some time.
Products Services
offers complete line Digital Mixed-Signal ASIC Foundry solutions from CMOS fabrication line located USA. unusual fabrication capability extensive modular fabrication process which makes possible build advanced feature size devices along with older technologies. This enables support customer product deliveries many years, eliminating need lifetime buys. also industry leader FPGA migrations ASICs well ASIC second sourcing with NETRANS products services. views move accepting VHDL netlists FPGAs logical extension NETRANS business. AMI's NETRANS methodology faster than synthesis retargeting better able deal with asynchronous designs.
Verilog Support
this time, Verilog clearly largest installed base users. important that continue support them, even expand level support provide. Fortunately, support requirements Verilog very similar those VHDL.

4401035 VHDL Based Design Methodology Kirk email: access-sup

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