TDA9855 I2C-bus controlled BTSC stereo/SAP decoder audio processor

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TDA9855 I2C-bus controlled BTSC stereo/SAP decoder audio processor

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TDA9855 I2C-bus controlled BTSC stereo/SAP decoder audio processor
Product specification Supersedes data July 1994 File under Integrated Circuits, IC02 1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
FEATURES Quasi alignment-free BTSC stereo decoder automatic adjustment channel separation I2C-bus High integration level with automatically tuned integrated filters Input level adjustment I2C-bus controlled Alignment-free processing noise reduction circuit I2C-bus transceiver. GENERAL DESCRIPTION
TDA9855
TDA9855 bipolar-integrated BTSC stereo/SAP decoder with hi-fi audio processor (I2C-bus controlled) application sets.
Audio processor Selector internal external signals (line Automatic volume level control Subwoofer surround output with separate volume control Volume control Special loudness characteristic automatically controlled combination with volume setting Bass treble control Audio signal zero-crossing detection between volume step switching Mute control audio signal zero-crossing. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA9855 TDA9855WP SDIP52 PLCC68 DESCRIPTION plastic shrink dual in-line package; leads (600 mil) plastic leaded chip carrier; leads VERSION SOT247-1 SOT188-2
LICENSE INFORMATION license required this product. further information, please contact COMPANY THAT Corporation BRANCH Licensing Operations ADDRESS Forest Marlborough, 01752 Tel.: (508) 229-2500 Fax: (508) 229-2590 Palm House, 1-20-2 Honmachi Shibuya-ku, Tokyo Japan Tel.: (03) 3378-0915 Fax: (03) 3374-5191
Tokyo Office
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
QUICK REFERENCE DATA SYMBOL VCOMP(rms) VoR,L(rms) THDL,R O(rms) Gbass Gtreble PARAMETER supply voltage supply current input signal voltage (RMS value) 100% modulation CONDITIONS MIN. line (mono); (RMS) CCIR noise weighting filter (peak value) noise weighting filter (RMS value) audio section; (RMS); gain CCIR noise weighting filter (peak value) noise weighting filter (RMS value) TYP. -3.5
TDA9855
MAX. +16.5
UNIT
output signal voltage (RMS value) 100% modulation input level adjustment control stereo channel separation total harmonic distortion signal handling (RMS value) control range volume control range maximum loudness boost bass control range treble control range subwoofer control range signal-to-noise ratio maximum gain maximum attenuation 0.5%
1997
1997
handbook, full pagewidth
External Input Right (EIR) (57) (58) (59) (67) (66) (68) (48) (49) (50) (54) (51) (52) (14) (55) (56) VOLUME RIGHT LOUDNESS CONTROL BASS RIGHT CONTROL TREBLE RIGHT CONTROL (63) OUTR (65)
BLOCK DIAGRAM
Philips Semiconductors
CERAMIC RESONATOR MURATA CSB503F58
(40)
(41)
(43)
(46)
(47)
STEREO DECODER
I2C-bus controlled BTSC stereo/SAP decoder audio processor
INPUT SELECT EFFECTS AUTOMATIC VOLUME LEVEL CONTROL
COMP
(38)
INPUT LEVEL ADJUST
STEREO /SAP SWITCH
DEMATRIX LINEOUT SELECT
TDA9855
OUTS
ZERO CROSSING
STEREO ADJUST SUPPLY LOGIC, I2CTRANCEIVER VOLUME LEFT LOUDNESS CONTROL (27) (24) (23) (22) (21) (20) External Input Left (EIL) (16) (19) (18) (37) (33, (39) (15) (35) (36) (13) (12) (11)
SUBWOOFER MATRIX, VOLUME SURROUND
DEMODULATOR
BASS LEFT CONTROL
TREBLE LEFT CONTROL
OUTL
(31)
(30)
(29) (25)
MHA837
numbers given parenthesis refer TDA9855WP version.
Product specification
TDA9855
Fig.1 Block diagram.
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
TDA9855
Component list Electrolytic capacitors ±20%; foil ceramic capacitors ±10%; resistors ±5%; unless otherwise specified; Fig.1. COMPONENTS 1997 VALUE TYPE electrolytic foil electrolytic foil electrolytic electrolytic electrolytic foil foil electrolytic foil ceramic foil foil foil ceramic electrolytic electrolytic electrolytic foil electrolytic electrolytic foil electrolytic electrolytic electrolytic electrolytic electrolytic electrolytic electrolytic electrolytic foil ceramic foil foil foil ceramic electrolytic foil electrolytic electrolytic electrolytic electrolytic ±10% ±10% ±10% 2220/1206 2220/1206 REMARK Ileak 2220/1206 2220/1206
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
COMPONENTS VALUE TYPE electrolytic electrolytic foil ceramic CSB503F58 CSB503JF958 PINNING PINS SYMBOL PLCC68 n.c. OUTS OUTL n.c. Vref n.c. 1997 SDIP52 treble control capacitor, left channel connected bass control capacitor, left channel bass control capacitor, left channel DESCRIPTION
TDA9855
REMARK 1206 general purpose diode radial leads alternative
output subwoofer output surround sound programmable address (module address) output, left channel connected input loudness, left channel input volume control, left channel output effects, left channel automatic volume control capacitor reference voltage 0.5VCC input line, left channel connected input automatic volume control, left channel output selector, left channel output line control, left channel capacitor timing wideband capacitor timing spectral capacitor wideband capacitor spectral variable emphasis output
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
PINS SYMBOL PLCC68 n.c. n.c. CDEC n.c. AGND DGND COMP VCAP n.c. n.c. CADJ n.c. CPS2 CPS1 n.c. OUTR n.c. SDIP52 connected variable emphasis input connected capacitor noise reduction capacitor mute capacitor DC-decoupling connected analog ground digital ground ground serial data input/output (I2C-bus) serial clock input (I2C-bus) supply voltage composite input signal capacitor electronic filtering supply capacitor pilot detector capacitor pilot detector connected capacitor phase detector connected capacitor filter adjustment ceramic resonator capacitor DC-decoupling mono capacitor DC-decoupling stereo/SAP output line control, right channel output selector, right channel DESCRIPTION
TDA9855
input automatic volume control, right channel connected input line control, right channel capacitor pseudo function capacitor pseudo function output effects, right channel input volume control, right channel input loudness, right channel connected output, right channel connected filter capacitor subwoofer
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
PINS SYMBOL PLCC68 SDIP52 bass control capacitor, right channel bass control capacitor, right channel treble control capacitor DESCRIPTION
TDA9855
handbook, full pagewidth
OUTR
OUTS
OUTL
n.c.
n.c.
n.c.
n.c.
n.c.
n.c. Vref n.c. n.c.
n.c.
n.c. CPS1 CPS2 n.c.
TDA9855H
CADJ n.c. n.c.
n.c.
CDEC
n.c.
AGND
DGND
COMP
VCAP
n.c.
MHA836
Fig.2 configuration (PLCC version).
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
FUNCTIONAL DESCRIPTION Decoder INPUT LEVEL ADJUSTMENT
TDA9855
handbook, halfpage
OUTS OUTL
n.c. OUTR CPS1 CPS2
composite input signal input level adjustment stage. order compensate tolerances demodulator which supplied composite input signal, TDA9855 provides input level adjustment stage. control range from -3.5 +4.0 steps subaddress control Tables level adjust setting Table allows optimum signal adjustment during alignment production line. This value stored non-volatile memory. maximum input signal voltage (RMS). STEREO DECODER output signal level adjustment stage coupled low-pass filter which suppresses baseband noise above kHz. composite signal then into pilot detector/pilot cancellation circuit into demodulator. main signal passes fixed de-emphasis filter into dematrix circuit. decoded sub-signal sent stereo/SAP switch. generate pilot signal stereo demodulator uses circuit including ceramic resonator. stereo channel separation adjusted automatic procedure manually. detailed description Section "Adjustment procedure". stereo identification read I2C-bus (see Table different pilot thresholds selected I2C-bus (see Table 24). DEMODULATOR composite signal from output input level adjustment stage demodulator circuit through horizontal frequency) band-pass filter. demodulator level automatically controlled. demodulator includes internal noise field strength detectors that mute output event insufficient signal conditions. identification signal read I2C-bus (see Table SWITCH stereo/SAP switch feeds either signal demodulator output signal internal noise reduction circuit dematrix/line select circuit. Table shows different switch modes provided output pins LOL.
Vref
TDA9855
CDEC
MHA835
CADJ VCAP COMP
Fig.3 configuration (SDIP version).
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
DECODER circuit includes blocks required noise reduction system accordance with BTSC system specification. output signal through fixed de-emphasis circuit dematrix block. INTEGRATED FILTERS filter functions necessary stereo demodulation part filter circuits provided on-chip using transconductor circuits. required filter accuracy attained automatic filter alignment circuit. Audio processor SELECTOR selector allows selecting either internal line signals (dematrix output) external line signals combines left right signals several modes (see Table 12). input signal capability line inputs (LIR/LIL) (RMS). output selector AC-coupled automatic volume level control circuit pins SOR/SOL AVR/AVL avoid offset voltages. AUTOMATIC VOLUME LEVEL CONTROL automatic volume level stage controls output voltage constant level typically (RMS) from input voltage range (RMS). circuit adjusts variations modulation during broadcasting changes programme material. function switched off. avoid audible `plops' during permanent operation circuit soft blending scheme been applied between different gain stages. capacitor (4.7 determines attack decay time constants. addition ratio attack decay time changed I2C-bus (see notes Chapter "Characteristics"). EFFECTS audio processor section offers following mode selections: linear stereo, pseudo stereo, spatial stereo forced mono.The spatial mode provides antiphase crosstalk (switchable I2C-bus; Table 18). VOLUME/LOUDNESS volume control range from steps ends with mute step (see Table Balance control achieved independent volume 1997 TREBLE CONTROL
TDA9855
control each channel. volume control blocks operate combination with loudness control. filter linear when maximum gain volume control selected. filter characteristic changes automatically over range down setting volume control maximum loudness boost obtained. filter characteristic determined external components. proposed application provides maximum boost bass treble. loudness switched I2C-bus control (see Table 14). left right volume control stages include independent zero-crossing detectors. zero-crossing mode change volume automatically activated executed. execution enabled next zero-crossing signal. volume step activated before previous been processed, previous value will executed first, then value will activated. zero-crossing occurs next volume transmission will enforce last activated volume setting. zero-crossing mode realized between adjoining steps between steps, from step mute. this case required use. case only channel muted, steps necessary. first step transmission step second step step mute mode. step mute mode zero-crossing this relevant. This procedure provided software. BASS CONTROL single external capacitor each channel combination with linear operational amplifier internal resistors provides bass control range +16.5 steps frequencies Hz). Internally basic step width with intermediate steps obtained toggle function that provides additional boost attenuation (see Table should noted that both loudness bass control together result maximum bass boost 34.5 volume steps.
adjustable range treble control stage from steps filter characteristic determined external capacitor each channel. logic circuitry arranged that same data words (06H 16H) used both tone controls bass control range from treble control range from with steps used (see Tables 10).
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
SUBWOOFER; SURROUND SOUND CONTROL subwoofer surround mode activated with control (see Table provides output signal 1/2(L subwoofer mode, high selects surround mode provides output signal signal through volume control stage with range from steps main channel control output OUTS. last setting mute position (see Table 11). capacitor provides low-pass filter subwoofer mode. surround mode this capacitor should disconnected. balance position selected left right output levels will combined. MUTE mute function activated independently with last step volume subwoofer/surround control left, right centre output. setting general mute I2C-bus audio part outputs muted. channels include independent zero-crossing detector. zero-crossing mute feature selected TZCM: TZCM forced mute with direct execution TZCM execution time with signal zero-crossing. zero-crossing mode change activated executed. execution enabled next zero-crossing signal. avoid large delay mute switching, when very frequencies processed, output signal amplitude lower than offset voltage, following I2C-bus transmissions needed: first transmission mute execution second transmission approximately later, which must switch zero-crossing mode forced mute (TZCM third transmission reactivate zero-crossing mode (TZCM This transmission take place immediately, must follow before next mute execution. Adjustment procedure COMPOSITE INPUT LEVEL ADJUSTMENT Apply composite signal (from demodulator) with 100% modulation deviation) input level control I2C-bus monitoring line output (500 mV). Store setting non-volatile memory. Adjustment spectral
TDA9855
wideband expander performed stereo channel separation adjust. AUTOMATIC ADJUSTMENT PROCEDURE Capacitors external inputs must grounded Composite input signal kHz, modulation each channel; volume gain I2C-bus; avoid annoying sound level logic during adjustment procedure Effects, AVL, loudness Selector setting SC0, (see Table Line setting bits: STEREO (see Table Start adjustment transmission register ALI3; decoder will align itself After second, stop alignment transmitting register ALI3 read alignment data I2C-bus read operation from ALR1 ALR2 (see Chapter "I2C-bus protocol") store non-volatile memory; alignment procedure overwrites previous data stored ALI1 ALI2 Disconnect capacitors external inputs from ground. MANUAL ADJUSTMENT Manual adjustment necessary when dual tone generator available (e.g. service). Spectral wideband data have 10000 (middle position adjustment range) Composite input modulation Adjust channel separation varying wideband data Composite input kHz; modulation Adjust channel separation varying spectral data Iterative spectral/wideband operation optimum adjustment Store data non-volatile memory. After every power-on, alignment data input level adjustment data must loaded from non-volatile memory. TIMING CURRENT RELEASE RATE possible internal external spreading, timing current adjusted I2C-bus (see Table recommended dbx.
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
Requirements composite input signal ensure correct system performance SYMBOL PARAMETER CONDITIONS measured COMP MIN. TYP.
TDA9855
MAX.
UNIT
COMPL+R(rms) composite input level 100% modulation deviation; value COMP composite input level spreading under operating conditions output impedance frequency roll-off high frequency roll-off total harmonic distortion
Tamb aging; power supply influence note deviation deviation kHz; deviation kHz; deviation; note
-0.5
+0.5
THDL,R
low-ohmic
signal-to-noise ratio R/noise
CCIR 468-2 weighted quasi peak; deviation; kHz; de-emphasis critical picture modulation with sync only
side band suppression mono into unmodulated carrier; carrier/side band spectral spurious attenuation R/spurious
mono signal: deviation, kHz; side band: carrier frequency kHz; mainly de-emphasis; deviation, reference
Notes Low-ohmic preferred, otherwise signal loss spreading COMP, caused composite input impedance (see Chapter "Characteristics", Section INPUT LEVEL ADJUSTMENT CONTROL) must taken into account. order prevent clipping over-modulation (maximum deviation BTSC system 100% modulation kHz).
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
LIMITING VALUES accordance with Absolute Maximum Rating System (IEC 134). SYMBOL Tamb Tstg Vesd supply voltage voltage other pins with respect operating ambient temperature storage temperature electrostatic handling note note Notes Human body model: Charge device model: THERMAL CHARACTERISTICS SYMBOL Rth(j-a) SOT247-1 SOT188-2 PARAMETER thermal resistance from junction ambient CONDITIONS free VALUE PARAMETER CONDITIONS -2000 -300 MIN.
TDA9855
MAX. +150 +2000 +300
UNIT
UNIT
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
TDA9855
CHARACTERISTICS voltages measured relative GND; source resistance output load AC-coupled; kHz; Tamb volume gain control bass linear; treble linear; loudness off; off; effects linear; composite input signal accordance with BTSC standard; Fig.1; unless otherwise specified. SYMBOL General supply voltage supply current voltage signal handling pins
2VCC
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Decoder section INPUT LEVEL ADJUSTMENT CONTROL Gstep Vi(rms) input level adjustment control step resolution maximum input voltage level (RMS value) input impedance maximum gain maximum attenuation 29.5 input level adjusted I2C-bus Hz); monitoring line -3.5 40.5
STEREO DECODER MPXL+R(rms) input voltage level 100% modulation deviation (RMS value) MPXL-R input voltage level 100% modulation deviation (peak value) maximum headroom fmod kHz; equivalent input modulation
MPX(max)
MPXpilot(rms) nominal stereo pilot voltage level (RMS value) STon(rms) SToff(rms) OUTL+R pilot threshold voltage stereo (RMS value) pilot threshold voltage stereo (RMS value) hysteresis output voltage level 100% modulation LINE Hz); monitoring LINE input level adjusted I2C-bus data data data data
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
SYMBOL PARAMETER stereo channel separation LINE CONDITIONS aligned with dual tone modulation; Section "Adjustment procedure" Chapter "Functional description" frequency response modulation; fref THDL,R total harmonic distortion LINE signal-to-noise ratio modulation 100%; mono mode; CCIR 468-2 weighted; quasi peak; output signal MIN. TYP.
TDA9855
MAX.
UNIT
STEREO DECODER, OSCILLATOR (VCXO); note nominal VCXO output frequency (32fH) spread free-running frequency capture range frequency (nominal pilot) with nominal ceramic resonator with nominal ceramic resonator 500.0 ±190 503.5 ±265 507.0
DEMODULATOR; note SAPi(rms) SAPon(rms) SAPoff(rms) SAPhys SAPLEV nominal carrier input voltage level (RMS value) pilot threshold voltage (RMS value) pilot threshold voltage (RMS value) hysteresis output voltage level LINE LINE (LOL, LOR) position SAP/SAP; fmod 100% modulation modulation; kHz; fref frequency deviation intercarrier
fres
frequency response total harmonic distortion
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
SYMBOL PARAMETER CONDITIONS 100% modulation; kHz; line switched SAP/SAP 100% modulation; kHz; SAP; line switched stereo MIN. TYP.
TDA9855
MAX.
UNIT
LINE PINS Vo(rms) HEADo nominal output voltage (RMS value) output headroom output impedance output voltage output load resistance output load capacitance idle crosstalk into 100% modulation
0.45VCC 0.5VCC
0.55VCC
idle crosstalk into
VST-SAP
output voltage difference switched from
NOISE REDUCTION CIRCUIT tadj stereo adjustment time Section "Adjustment procedure" Chapter "Functional description" measured (pin current meter connected 1/2VCC steps I2C-bus
nominal timing current nominal release rate spectral detector spread timing current timing current adjustment range timing current release rate wideband detector nominal detector release rate
Is(range) Relrate
nominal timing current external capacitor values wideband spectral
dB/s dB/s
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
SYMBOL Audio part CIRCUIT SECTION FROM PINS PINS OUTL, OUTR OUTS; note roll-off frequencies C10, C26, Zi(min) frequency high frequency (-0.5 total harmonic distortion (RMS); (RMS); (RMS); (RMS); PSRR power supply ripple rejection crosstalk between inputs signal outputs noise output voltage Vr(rms) notes CCIR 468-2 weighted; quasi peak measured channel separation 12.5 SELECTOR (FROM PINS LOL, LOR, PINS SOR) Vi(rms) Voffset input impedance input isolation selected source other input maximum input voltage (RMS value) offset voltage selector output selection inputs output impedance output load resistance (AC) output load capacitance voltage gain, selector kHz; 12.5 kHz; 0.5% 0.05 0.02 PARAMETER CONDITIONS MIN. TYP.
TDA9855
MAX.
UNIT
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA9855
MAX.
UNIT
AUTOMATIC VOLUME LEVEL CONTROL (AVL) Vi(rms) Gstep input impedance maximum input voltage (RMS value) gain, maximum boost maximum attenuation equivalent step width between input stages (soft switching system) input level maximum boost (RMS value) input level maximum attenuation (RMS value) Vo(rms) VDC(OFF) output level operation (RMS value) offset between different gain steps Fig.4 Fig.4 Fig.4 voltage 6.50 6.33 6.33 6.11 6.11 5.33 5.33 2.60 note note note note note Idec spat1 spat2 Vi(rms) charge current decay time EFFECT CONTROLS anti-phase crosstalk spatial effect phase shift pseudo-stereo Fig.5 0.5% CCIR 468-2 weighted; quasi peak mute position 10.0 2.15 12.0 0.2% 11.0 13.2
Vi(rms)
1.125
Ratt
discharge resistors attack time constant
0.96
normal mode; note
VOLUME TONE CONTROL PART (INPUT PINS PINS OUTX OUTS) volume input impedance output impedance output load resistance (AC) output load capacitance maximum input voltage (RMS value) noise output voltage
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
SYMBOL Gstep PARAMETER total continuous control range step resolution step error between adjoining step VDC(OFF) attenuator error gain tracking error mute attenuation step offset between adjacent step step offset between step mute LOUDNESS CONTROL PART maximum loudness boost loudness referred loudness off; boost determined external components; Fig.6 BASS CONTROL (see Fig.7) Gbass Gstep bass control maximum boost maximum attenuation step resolution step error between adjoining step VDC(OFF) step offset between adjacent step 15.5 16.5 CONDITIONS maximum boost maximum attenuation MIN. TYP.
TDA9855
MAX. 10.0
UNIT
17.5
TREBLE CONTROL (see Fig.8) Gtreble treble control maximum boost maximum attenuation maximum boost Gstep step resolution step error between adjoining step VDC(OFF) step offset between adjacent step
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA9855
MAX.
UNIT
SUBWOOFER SURROUND CONTROL subwoofer control maximum boost; maximum attenuation; Gstep VDC(OFF) step resolution mute attenuation step offset between adjacent step step offset between step mute
without input offset (pin connected Vref) inclusive offset from OUTR, OUTL
internal resistor low-pass filter with external capacitor common mode rejection surround sound OUTS mono signal VIL/VIR; kHz; balance
RREJ
MUTING POWER SUPPLY DROP OUTL, OUTR OUTS VCC-DROP VRESET(STA) supply drop mute active increasing supply voltage decreasing supply voltage VRESET(END) reset voltage Digital part (I2C-bus pins); note HIGH-level input voltage LOW-level input voltage HIGH-level input current LOW-level input current LOW-level output voltage -0.3 +1.5 increasing supply voltage VCAP
POWER-ON RESET; note start reset voltage
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
Notes characteristics
TDA9855
oscillator designed operate together with MURATA resonator CSB503F58 TDA9855. Change resonator supplier possible, resonator specification must close CSB503F58 TDA9855. internal carrier level determined composite input level level adjustment gain. Select input line control. bus(p-p) Crosstalk: o(rms) transmission contains: Total initialization with volume DATA words, also definition characteristics Clock frequency Repetition burst rate Maximum signal amplitude (p-p). listed voltage corresponds with typical gain steps Attack time constant Ratt.
-Gv1 0.76 Decay time
Example: Idec decay time results 4.14 When reset active GMU-bit (general mute) LMU-bit (LINE mute) I2C-bus receiver reset position. characteristics accordance with I2C-bus specification. maximum clock frequency kHz. Information about I2C-bus found brochure "The I2C-bus (order number 9398 40011).
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
I2C-BUS PROTOCOL I2C-bus format read (slave transmits data) Table SLAVE ADDRESS DATA
TDA9855
DATA
Explanation I2C-bus format read (slave transmits data) NAME DESCRIPTION START condition; generated master connected connected ground logic (read); generated master acknowledge; generated slave slave transmits 8-bit data word acknowledge; generated master STOP condition; generated master Definition transmitted bytes after read condition FUNCTION BYTE SAPP SAPP ALR1 ALR2
Standard SLAVE ADDRESS programmable SLAVE ADDRESS DATA Table
Alignment read Alignment read Table
Function bits Table BITS FUNCTION stereo pilot identification (stereo received pilot identification (SAP received stereo alignment read data wideband expander spectral expander indefinite
SAPP
master generates acknowledge when received first data word ALR1, then slave transmits next data word ALR2. Afterwards master generates acknowledge, then slave begins transmitting first data word ALR1 etc. until master generates acknowledge transmits STOP condition.
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
I2C-bus format write (slave receives data) Table SLAVE ADDRESS SUBADDRESS DATA
TDA9855
Explanation I2C-bus format write (slave receives data) NAME DESCRIPTION START condition connected connected ground logic (write) acknowledge; generated slave Table Table STOP condition
Standard SLAVE ADDRESS programmable SLAVE ADDRESS SUBADDRESS (SAD) DATA
more than byte DATA transmitted, then auto-increment performed, starting from transmitted subaddress auto-increment subaddress accordance with order Table performed. Table Subaddress second byte after slave address FUNCTION Volume right Volume left Bass Treble Subwoofer Control Control Control Alignment Alignment Alignment REGISTER CON1 CON2 CON3 ALI1 ALI2 ALI3
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
Table Definition third byte after slave address FUNCTION Volume right Volume left Bass Treble Subwoofer Control Control Control Alignment Alignment Alignment Table REGISTER CON1 CON2 CON3 ALI1 ALI2 ALI3 AVLON STEREO LOFF TZCM VZCM
TDA9855
Function bits Table BITS FUNCTION volume control right volume control left bass control treble control subwoofer, surround control mute control outputs OUTL, OUTR OUTS (generate mute) on/off switch loudness on/off don't care surround/subwoofer 1/2(L 1/2(L selection between line line mode selection line zero-crossing mode mute operation (treble subwoofer/surround output stage) zero-crossing mode volume operation mute control dematrix line select selection between mono, stereo linear, spatial stereo pseudo mode input level adjustment stereo adjustment on/off stereo alignment data wideband expander stereo alignment data spectral expander attack time timing current alignment data stereo level switch
AVLON LOFF STEREO, TZCM VZCM
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
Table (dB) 1997 Volume setting registers DATA
TDA9855
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
DATA (dB) 1997
TDA9855
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
DATA (dB) Mute Table
TDA9855
Bass setting register DATA
Gbass (dB) 16.5 15.0 13.5 12.0 10.5 -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
Table Treble setting register DATA Gtreble (dB) FUNCTION(1) Inputs Inputs Inputs Inputs Inputs Inputs Inputs Inputs Note
TDA9855
Table Selector setting register CON1 DATA
Table Subwoofer/surround setting register DATA (dB) Mute
Input connected outputs SOL. Table setting register CON1 FUNCTION Surround sound Subwoofer Table LOFF setting register CON1 CHARACTERISTIC With loudness Linear DATA DATA
Table AVLON setting register CON1 FUNCTION Automatic volume control Automatic volume control DATA
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
Table Mute setting register CON1 FUNCTION Forced mute OUTR, OUTL OUTS Audio processor controlled outputs Table Mute setting register CON2 FUNCTION Forced mute Stereo processor controlled outputs Table Effects setting register CON2 DATA FUNCTION Stereo linear Pseudo Spatial stereo; anti-phase crosstalk Spatial stereo; anti-phase crosstalk Forced mono
TDA9855
DATA
DATA
Table Zero-crossing detection setting register CON2 FUNCTION Direct mute control Mute control delayed until next zero-crossing Table Zero-crossing detection setting register CON2 FUNCTION Direct volume control Volume control delayed until next zero-crossing DATA VZCM DATA TZCM
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
Table Switch setting line LINE SIGNALS Mute Left Mono Mono Mono Mono mute right mono mute mono DATA TRANSMISSION STATUS INTERNAL SWITCH, READABLE BITS REGISTER ALR1, ALR2: (SAPP), (STP) received received STEREO received STEREO received received received independent
TDA9855
SETTING BITS REGISTER CON2 STEREO
Table Input level adjust setting register CON3 DATA (dB) -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
TDA9855
Table Alignment data expander read register ALR1 ALR2 write register ALI1 ALI2 DATA FUNCTION Gain increase Nominal gain Gain decrease
Table setting register ALI2 (pilot threshold stereo FUNCTION STon(rms) STon(rms) DATA
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
Table Timing current setting register ALI3 DATA RANGE +30% +20% +10% Nominal -10% -20% -30% Table setting register ALI3 FUNCTION Stereo decoder operation mode Auto adjustment channel separation
TDA9855
DATA
Table attack time setting register ALI3 DATA Ratt 1200 2100
MHA312
handbook, full pagewidth
Vo(rms) (mV)
VCAV
10-2 VCAV max(rms) min(rms)
VI(rms) measured EOL/EOR. axis output level operation with typically axis VCAV voltage corresponds with typical gain steps range
10-1
Fig.4 Automatic volume level control diagram.
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
TDA9855
MHA311
handbook, full pagewidth
phase (degree) -100
-200
-300
-400
(Hz)
Table Table Table
Fig.5 Pseudo (phase degrees) function frequency (left output).
Table Explanation curves Fig.5 CURVE CAPACITANCE CPS1 (nF) CAPACITANCE CPS2 (nF) EFFECT normal intensified more intensified
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
TDA9855
handbook, full pagewidth
MHA844
(Hz)
Fig.6 Volume control with loudness (including roll-off frequency).
handbook, full pagewidth
MHA843
Gbass (dB)
(Hz)
Fig.7 Bass control.
1997
parameter: volume gain setting (dB)
(dB)
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
TDA9855
handbook, full pagewidth
MHA845
Gtreble (dB)
(Hz)
Fig.8 Treble control.
handbook, halfpage
MHA842
noise (µV)
gain (dBA)
Fig.9 Noise function gain (RMS value).
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
TDA9855
handbook, full pagewidth
gain volume (Gv(max))
TDA9855
POWER STAGE P(max)
1250
1.26 P(max) margin power peaks
MHA841
values given value.
Fig.10 Level diagram.
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
APPLICATION HINTS Selection input signals using zero-crossing mute mode (see Fig.11)
TDA9855
selection between internal signal path external input LIL/LIR produces modulation click depending difference signal values time switching. maximum possible difference between signals (p-p) gives large click. Using zero-crossing detector modulation click audible. example: selection enabled microcontroller sets zero-crossing (TZCM then mute (GMU I2C-bus. output signal follows input signal, until next zero-crossing occurs then activates mute. After fixed delay time before microcontroller send forced mute mode (TZCM return zero-crossing mode (TZCM sure that mute enabled. output signal remains muted until next signal zero-crossing input occurs, then follows that signal. delay time e.g. zero-crossing function working lowest frequency
handbook, full pagewidth
MED436
Input (internal signal). Output. Input (external input signal).
Fig.11 Zero-crossing function; only channel shown.
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
Loudness filter calculation example Figure shows basic loudness circuit with external low-pass filter application. allows attenuation range while boost determined gain stage Both result loudness control range Defining fref frequency where level does change while switching loudness on/off. external resistor fref calculated With generated. low-pass filter characteristic value external capacitor determined setting specific boost defined frequency referring gain fref indicated above. example: boost Gv(ref) loudness characteristic with additional high frequency boost desired, additional high-pass section included external filter circuit indicated block diagram. filter configuration that provides coupling avoids offset voltage problems. Figure shows example loudness circuit with bass treble boost.
handbook, halfpage
TDA9855
handbook, halfpage
MHA838
Fig.12 Basic loudness circuit.
MHA839
Fig.13 Loudness circuit with bass treble boost.
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
TDA9855
handbook, full pagewidth
+8.5 oscilloscope
inputs outputs oscilloscope
MHA840
TDA9855
Fig.14 Turn-on/off power supply circuit diagram.
handbook, full pagewidth
MED433
VCC.
Fig.15 Turn-on/off behaviour.
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
INTERNAL CONFIGURATIONS numbers refer SDIP-version.
TDA9855
handbook, halfpage handbook, halfpage 4.25
3.64
4.25
7.79
4.25
MHA846 MHA847
Fig.16 treble control capacitor, left; treble control capacitor, right.
Fig.17 bass control capacitor input, left; bass control capacitor input, right.
handbook, halfpage
4.25
handbook, halfpage
4.25
MHA848
MHA849
Fig.18 bass control capacitor output, left; bass control capacitor output, right.
Fig.19 output subwoofer; output, left channel; output selector, left channel; output selector, right channel; output, right channel.
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
TDA9855
handbook, halfpage
MHA850
Fig.20 (I2C-bus address switch).
handbook, halfpage
4.25 1.33
MHA851
Fig.21 input loudness, left; input loudness, right.
handbook, halfpage
4.25 10.58
MHA852
Fig.22 input volume, left; input volume, right.
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
TDA9855
handbook, halfpage
4.25
handbook, halfpage
MHA854
MHA853
Fig.23 output effects, left; output effects, right.
Fig.24 automatic volume control capacitor.
handbook, halfpage
handbook, halfpage
4.25
MHA855
MHA856
Fig.25 reference voltage 0.5VCC.
Fig.26 line input, left; line input, right.
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
TDA9855
handbook, halfpage
4.25
handbook, halfpage
4.25
1.75
MHA858
MHA857
Fig.27 input automatic volume control, left; input automatic volume control, right.
Fig.28 line output, left; line output, right.
handbook, halfpage
handbook, halfpage
4.25
MHA859
MHA860
Fig.29 timing capacitor wideband dbx; timing capacitor spectral dbx.
Fig.30 capacitor wideband dbx; capacitor spectral dbx.
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
TDA9855
handbook, halfpage
handbook, halfpage
MHA861 MHA862
Fig.31 variable emphasis dbx.
Fig.32 variable emphasis dbx.
handbook, halfpage handbook, halfpage
4.25
MHA863 MHA864
Fig.33 capacitor noise reduction dbx.
Fig.34 capacitor mute SAP.
handbook, halfpage
4.25
handbook, halfpage
MHA865
MHA866
Fig.35 capacitor decoupling SAP.
Fig.36 (I2C-bus data input/output).
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
TDA9855
handbook, halfpage
handbook, halfpage
apply this
MHA867
MHA868
Fig.37 (I2C-bus clock).
Fig.38 supply voltage.
handbook, halfpage
4.25
handbook, halfpage
MHA869 MHA870
Fig.39 input composite signal.
Fig.40 smoothing capacitor supply.
handbook, halfpage
handbook, halfpage
4.25
4.25
MHA871
MHA872
Fig.41 capacitor pilot detector.
Fig.42 capacitor pilot detector.
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
TDA9855
handbook, halfpage
4.25
handbook, halfpage
MHA873 MHA874
Fig.43 capacitor phase detector.
Fig.44 capacitor filter adjust.
handbook, halfpage
handbook, halfpage
4.25
MHA875
MHA876
Fig.45 ceramic resonator.
Fig.46 capacitor decoupling mono; capacitor decoupling stereo/SAP.
handbook, halfpage
4.25
handbook, halfpage
4.25
MHA877
Fig.47 capacitor pseudo function; capacitor pseudo function.
MHA878
Fig.48 capacitor subwoofer.
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
PACKAGE OUTLINES SDIP52: plastic shrink dual in-line package; leads (600 mil)
TDA9855
SOT247-1
seating plane
index
scale
DIMENSIONS original dimensions) UNIT max. 5.08 min. 0.51 max. 0.53 0.40 0.32 0.23 47.9 47.1 14.0 13.7 1.778 15.24 15.80 15.24 17.15 15.90 0.18 max. 1.73
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT247-1 REFERENCES JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 90-01-22 95-03-11
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
TDA9855
PLCC68: plastic leaded chip carrier; leads
SOT188-2
index
detail
scale
DIMENSIONS (millimetre dimensions derived from original inch dimensions) UNIT
inches
4.57 4.19
min.
0.51
0.25
max.
3.30 0.13
0.53 0.33
0.81 0.66
max.
0.51
1.44 1.02
0.18
0.18
0.10
D(1) max. max.
2.16 2.16
24.33 24.33 23.62 23.62 25.27 25.27 1.22 1.27 24.13 24.13 22.61 22.61 25.02 25.02 1.07
0.180 0.020 0.01 0.165
0.930 0.930 0.995 0.995 0.048 0.057 0.021 0.032 0.958 0.958 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.890 0.890 0.985 0.985 0.042 0.040 0.013 0.026 0.950 0.950
Note Plastic metal protrusions 0.01 inches maximum side included. OUTLINE VERSION SOT188-2 REFERENCES 112E10 JEDEC MO-047AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-03-11
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
SOLDERING Introduction There soldering method that ideal packages. Wave soldering often preferred when through-hole surface mounted components mixed printed-circuit board. However, wave soldering always suitable surface mounted ICs, printed-circuits with high population densities. these situations reflow soldering often used. This text gives very brief insight complex technology. more in-depth account soldering found Package Databook" (order code 9398 90011). SDIP SOLDERING DIPPING WAVE maximum permissible temperature solder solder this temperature must contact with joint more than seconds. total contact time successive solder waves must exceed seconds. device mounted seating plane, temperature plastic body must exceed specified maximum storage temperature (Tstg max). printed-circuit board been pre-heated, forced cooling necessary immediately after soldering keep temperature within permissible limit. REPAIRING SOLDERED JOINTS Apply voltage soldering iron (less than lead(s) package, below seating plane more than above temperature soldering iron less than remain contact seconds. temperature between contact seconds. PLCC REFLOW SOLDERING Reflow soldering techniques suitable PLCC packages. choice heating method influenced larger PLCC packages leads, more). infrared vapour phase heating used large packages absolutely (less than 0.1% moisture content weight), vaporization small amount moisture them cause cracking plastic body. more information, refer Drypack chapter "Quality Reference Handbook" (order code 9398 63011). 1997
TDA9855
Reflow soldering requires solder paste suspension fine solder particles, flux binding agent) applied printed-circuit board screen printing, stencilling pressure-syringe dispensing before package placement. Several techniques exist reflowing; example, thermal conduction heated belt. Dwell times vary between seconds depending heating method. Typical reflow temperatures range from Preheating necessary paste evaporate binding agent. Preheating duration: minutes WAVE SOLDERING Wave soldering techniques used PLCC packages following conditions observed: double-wave turbulent wave with high upward pressure followed smooth laminar wave) soldering technique should used. longitudinal axis package footprint must parallel solder flow. package footprint must incorporate solder thieves downstream corners. During placement before soldering, package must fixed with droplet adhesive. adhesive applied screen printing, transfer syringe dispensing. package soldered after adhesive cured. Maximum permissible solder temperature maximum duration package immersion solder seconds, cooled less than within seconds. Typical dwell time seconds mildly-activated flux will eliminate need removal corrosive residues most applications. REPAIRING SOLDERED JOINTS component first soldering diagonallyopposite leads. only voltage soldering iron (less than applied flat part lead. Contact time must limited seconds When using dedicated tool, other leads soldered operation within seconds between
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA9855
This data sheet contains target goal specifications product development. This data sheet contains preliminary data; supplementary data published later. This data sheet contains final product specifications.
Limiting values given accordance with Absolute Maximum Rating System (IEC 134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Where application information given, advisory does form part specification. LIFE SUPPORT APPLICATIONS These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. Philips customers using selling these products such applications their risk agree fully indemnify Philips damages resulting from such improper sale. PURCHASE PHILIPS COMPONENTS
Purchase Philips components conveys license under Philips' patent components system provided system conforms specification defined Philips. This specification ordered using code 9398 40011.
1997
Philips Semiconductors
Product specification
I2C-bus controlled BTSC stereo/SAP decoder audio processor
NOTES
TDA9855
1997
Philips Semiconductors worldwide company
Argentina: South America Australia: Waterloo Road, NORTH RYDE, 2113, Tel. 9805 4455, Fax. 9805 4466 Austria: Computerstr. A-1101 WIEN, P.O. 213, Tel. 1010, Fax. 1210 Belarus: Hotel Minsk Business Center, Bld. 1211, Volodarski Str. 220050 MINSK, Tel. +375 733, Fax. +375 Belgium: Netherlands Brazil: South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, James Bourchier Blvd., 1407 SOFIA, Tel. +359 211, Fax. +359 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. 7381 China/Hong Kong: Hong Kong Industrial Technology Centre, Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: South America Czech Republic: Austria Denmark: Prags Boulevard 1919, DK-2300 COPENHAGEN Tel. 2636, Fax. 0044 Finland: Sinikalliontie FIN-02630 ESPOO, Tel. +358 615800, Fax. +358 61580920 France: Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. 6161, Fax. 6427 Germany: D-20097 HAMBURG, Tel. Fax. Greece: 25th March Street, 17778 TAVROS/ATHENS, Tel. 4894 339/239, Fax. 4814 Hungary: Austria India: Philips INDIA Ltd, Band Building, floor, 254-D, Annie Besant Road, Worli, MUMBAI 025, Tel. 8541, Fax. 0966 Indonesia: Singapore Ireland: Newstead, Clonskeagh, DUBLIN Tel. +353 7640 000, Fax. +353 7640 Israel: RAPAC Electronics, Kehilat Saloniki 18053, AVIV 61180, Tel. +972 0444, Fax. +972 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza Novembre 20124 MILANO, Tel. 6752 2531, Fax. 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. 3740 5130, Fax. 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. 1412, Fax. 1415 Malaysia: Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. 5214, Fax. 4880 Mexico: 5900 Gateway East, Suite 200, PASO, TEXAS 79905, Tel. +9-5 7381 Middle East: Italy Netherlands: Postbus 90050, 5600 EINDHOVEN, Bldg. Tel. 82785, Fax. 88399 Zealand: Wagener Place, C.P.O. 1041, AUCKLAND, Tel. 4160, Fax. 7811 Norway: Manglerud 0612, OSLO, Tel. 8000, Fax. 8341 Philippines: Philips Semiconductors Philippines Inc., Valero Salcedo Village, P.O. 2108 MCC, MAKATI, Metro MANILA, Tel. 6380, Fax. 3474 Poland: Lukiska 04-123 WARSZAWA, Tel. 2831, Fax. 2327 Portugal: Spain Romania: Italy Russia: Philips Russia, Usatcheva 35A, 119048 MOSCOW, Tel. 6918, Fax. 6919 Singapore: Lorong Payoh, SINGAPORE 1231, Tel. 2538, Fax. 6500 Slovakia: Austria Slovenia: Italy South Africa: S.A. PHILIPS Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. 7430 Johannesburg 2000, Tel. 5911, Fax. 5494 South America: Rocio 220, floor, Suite 04552-903 Paulo, PAULO Brazil, Tel. 2333, Fax. 1849 Spain: Balmes 08007 BARCELONA, Tel. 6312, Fax. 4107 Sweden: Kottbygatan Akalla, S-16485 STOCKHOLM, Tel. 2000, Fax. 2745 Switzerland: Allmendstrasse 140, CH-8027 Tel. 2686, Fax. 7730 Taiwan: Philips Semiconductors, Chien Rd., Sec. TAIPEI, Taiwan Tel. +886 2134 2865, Fax. +886 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. 4090, Fax. 0793 Turkey: Talatpasa Cad. 80640 Tel. 2770, Fax. 6707 Ukraine: PHILIPS UKRAINE, Patrice Lumumba str., Building Floor 252042 KIEV, Tel. +380 2776, Fax. +380 0461 United Kingdom: Philips Semiconductors Ltd., Bath Road, Hayes, MIDDLESEX 5BX, Tel. 5000, Fax. 8421 United States: East Arques Avenue, SUNNYVALE, 94088-3409, Tel. 7381 Uruguay: South America Vietnam: Singapore Yugoslavia: PHILIPS, Pasica 5/v, 11000 BEOGRAD, Tel. +381 344, Fax.+381
other countries apply Philips Semiconductors, Marketing Sales Communications, Building BE-p, P.O. 218, 5600 EINDHOVEN, Netherlands, Fax. 24825 Philips Electronics N.V. 1997
Internet:
SCA55
rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent- other industrial intellectual property rights.
Printed Netherlands
547047/1200/03/pp52
Date release: 1997
Document order number:
9397 02446

TDA9855 I2C-bus controlled BTSC stereo/SAP decoder audio processor

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