General Architecture Overview ispPAC10 device from Lattice Semico

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General Architecture Overview ispPAC10 device from Lattice Semico

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Frequently Asked Questions About ispPAC Device
General Architecture Overview
ispPAC10 device from Lattice Semiconductor represents level integration flexibility general-purpose analog signal processing (Figure ispPAC10 consists four identical signal-processing blocks (called PACblocks), analog signal routing pool, band-gap reference, autocalibration circuitry non-volatile, in-system programmable configuration memory. Once applied circuit card, ispPAC10 completely reconfigurable through digital I/O, immediately accommodating design changes. ispPAC10 architecture fully differential from input output, effectively doubling dynamic range, eliminating effects power supply variations improving distortion signal-to-noise performance. This architecture allows circuit designer implement operational amplifier circuits such noninverting difference amplifiers without worrying about common mode feedthrough issues. detailed discussion about ispPAC10 architecture included ispPAC10 Data Sheet. Figure ispPAC10 Functional Block Diagram
Figure Simplified Model Single PACblock
PACblock Differential Inputs Feedback Enable Summation 2.10 2.5V CommonMode Voltage Input 62pF Differential Output
simplified equivalent circuit single PACblock shown Figure Each PACblock contains independently-programmable, instrumentation-grade input amplifiers, differential output amplifier, resistive feedback element (which open circuited) user-programmable feedback capacitor. input PACblock differential pairs, polarity which user-programmable. impedance each input (typ) regardless circuit topology. input amplifiers modeled programmable gain block summing resistor. current provided input amplifiers summed inverting input operational amplifier. feedback network output amplifier modeled fixed resistive element that disabled parallel with programmable capacitance with over unique values between 61.6pF. output operational amplifier differential voltage, also applied singleended applications. differential output centered 2.5V (the internal reference voltage) user externally. PACblocks cascaded form more complex circuit functions such second order biquad filter Analog Routing Pool. PAC-DesignerTM, easy-touse Windows®-based design tool, used generate configuration data necessary programming device. With this design tool, user create summing, difference, inverting, noninverting integrating amplifiers well more complex circuits without having pick soldering iron. configuration data stored non-volatile E2CMOS®, eliminating need reprogramming after power-up. following sections discuss questions frequently asked novice user.
OUT2+ OUT2IN2+ IN2TDI TRST
OUT1+ OUT126 IN1+ IN124 TEST TEST
Configuration Memory Analog Routing Pool Reference Auto-Calibration
VREFout CMVin IN317 IN3+ OUT3-
IN411
IN4+ OUT413
OUT4+
OUT3+
an6001_02
November 1999
Frequently Asked Questions About ispPAC10 Device
Basic Operation
values gain this component?
Designers configure ispPAC10 verify performance using PAC-Designer design tool (Figure circuit designer simply selects circuit element programmed clicking that element. pop-up window allows easy adjustment. PAC-Designer will also simulate circuit performance, allowing optimization design prior configuration. nects parallel port programming port ispPAC10. previous configuration erased ispPAC10 programmed match circuit. Programming performed through 4-wire IEEE 1149.1 compliant serial port.
What made mistake?
Simply return PAC-Designer schematic entry screen make necessary adjustments. When satisfied, download circuit configuration ispPAC10. non-volatile E2CMOS cells qualified least 10,000 reprogramming cycles.
looks good computer. design into device?
When satisfied with simulated circuit response, simply click download button configuration loaded into ispPAC10 through parallel port. download cable (provided PAC-Designer kit) con-
have reprogram device after power
configuration parameters ispPAC10 saved non-volatile memory on-chip. ispPAC10 will assume last circuit configuration stored memory after power-on autocal sequence complete.
Figure PAC-Designer Schematic Entry Design Screen
Frequently Asked Questions About ispPAC10 Device
cascade multiple PACblocks?
PAC-Designer schematic entry screen. Note that output each PACblock connected Analog Routing Pool (shown traces from output amplifiers). Place cursor over open input node PACblock cascaded click mouse. While holding mouse button, draw line adjacent PACblock output trace. Note that only output PACblock PACblock capable connecting other PACblock input nodes. This will have considered when cascading more than PACblocks. using internal 2.5V reference then AC-coupling input signal will accomplish this. single-ended input applied, other input input pair must biased value within common mode range well. same bias voltage used both inputs. Detailed circuits applying single-ended inputs included ispPAC10 Data Sheet application note AN6009, Single-Ended Applications.
Does input range include both supply rails?
input range operating supply. Voltages applied ispPAC10 that exceed these limits will saturate input amplifiers. There margin this input range specification.
initiate autocal sequence?
ispPAC10 performs full-chip autocalibration offset errors upon power-up. This cycle forces offsets output PACblock 200µV typ, independent gain. This cycle takes 250ms power-up during this time outputs ispPAC10 forced inputs unaffected maintain their high impedance characteristics. ispPAC10 commanded perform autocalibration time toggling pin. autocalibration cycle performed after powerup takes 100ms initiated rising edge signal. This will guarantee offset outputs less than 1mV, independent gain. autocalibration also initiated through software selecting JTAG Properties under Tools menu. During this time, during power-up, analog outputs forced
What with unused input pins?
There conditions where input categorized being unused. first occurs when applying single-ended input signal differential input pair (see Question Input Considerations section this document). second condition exists when both inputs input amplifier connected signal all. this case, input pins associated with that PACblock connected ground. Unlike traditional analog inputs, acceptable float these pins. This feature could used ease addition inputs after ispPAC10 been applied circuit card jumper connection later date. When input amplifier PACblock connected signal PAC-Designer, amplifier's inputs automatically connected internal 2.5V reference. physical pins associated with that input amplifier maintain their high impedance characteristics.
assign polarity input pins?
inputs PACblock differential. Input polarity user-selectable through PAC-Designer software simply changing input output connections. change polarity input pair through software, click input amplifier schematic symbol. selection integer gain steps from available. invert polarity input pins, select gain Note that also possible invert amplify input signal using same input amplifier.
Output Considerations
What load current this device drive?
output will source 10mA differentially single ended. re-referencing nature PACblock, input will result differential output, centered around VREFOUT CMVIN, selected user. VREFOUT normally 2.5V, internal band-gap reference value. load referenced ground then amount current available differential voltage swing reduced. determine amount load current available, subtract amount required drive common-mode output voltage, given load, from 10mA. remainder what available voltage swing.
Input Considerations
ispPAC10 device accept singleended input signal?
Yes, ispPAC10 accept single-ended signals number ways. single-ended signal common mode voltage that falls within common mode input range, signal applied directly. such bias does exist, must added. Ideally this bias will Vs/2 2.5V. Dividing down supply voltage
Frequently Asked Questions About ispPAC10 Device
What differential output swing?
ispPAC10 output swing guaranteed 6Vpp (differentially) into load. Unloaded outputs will swing within millivolts supply rails. This assumes output common mode voltage 2.5V. Other values output common mode voltage will shift this range down need considered.
don't filter macros included PAC-Designer allow program exact cutoff frequency want?
PAC-Designer includes software macros speed implementation more complex designs, such filters. adjustable capacitor feedback loop output amplifier consists capacitor array switch matrix. this switch matrix that configures capacitor array into unique values capacitance. Because total number capacitor values discrete, pole location when connected filter also discrete. value capacitors been chosen allow pole locations between 10kHz 100kHz. filter generator macro will find nearest frequency entered user.
ispPAC10 provide single-ended output?
Yes. Leaving PACblock output pins open using other drive load, effectively creates single-ended output. total available load current (10mA) sourced from this single output pin. Note that single-ended output will swing symmetrically around VREFOUT CMVIN, selected user, larger dynamic range differential operation cannot realized.
Static Performance
What gain range single PACblock achieve?
single instrumentation amplifier input PACblock programmed voltage gain ±10V/V (±20dB) integer steps. Applying fraction input signal second input PACblock will allow noninteger gains realized. Application note AN6007, In-System Programmable Gain with Fractional Gain Adjustments details this topic. both inputs PACblock connected parallel same input signal, maximum voltage gain that signal ±20V/V ±26dB).
What with unused outputs?
with most unused analog output pins, they should left open.
Dynamic Performance
What bandwidth ispPAC10?
full power analog bandwidth (Vin 6Vdiff, Vout -3dB) single PACblock typically 330kHz. Since PACblock contains both transconductance amplifiers voltage mode amplifiers (see ispPAC10 Data Sheet detailed architecture discussion), small-signal bandwidth independent gain. unity gain, small-signal bandwidth 650kHz while gain 330kHz translating into gain-bandwidth product 650kHz 3.3MHz respectively.
What voltage offset PACblock?
When ispPAC10 performs autocalibration sequence, output-referred offset voltage less than 1mV, independent gain setting. Typical input referred offset drift 50µV/°C gain 81µV/°C gain user perform autocal sequence time guarantee output referred offset voltage less than 1mV(200µV typ).
What range filter cutoffs?
popular application ispPAC10 device programmable anti-alias filter front ADC. PACDesigner fully supports filter designs, allowing choices topologies, number poles cutoff frequencies. number programmable pole frequencies PACblock 128. pole locations spaced linearly with respect frequency have been optimized that there locations between 10kHz 100kHz.
Frequently Asked Questions About ispPAC10 Device
Package Descriptions
ispPAC10 device packaged 28-pin SOIC package (Figure functions grouped Input pins: Input Considerations section above. Output pins: Output Considerations section above. Digital I/O: JTAG programming pins pin. Power pins: power supply range rated performance (±5%). recommended bypass supply ground with 10µF tantalum ceramic capacitor best performance. CMVIN pin: Consideration must given values other than internal 2.5V reference applied this pin. ispPAC10 Data Sheet more information. Factory test pins: Connect these pins ground rated performance. Figure ispPAC10 Diagram
OUT2+ OUT2- IN2+ IN2- TRST (5V) IN4- IN4+ OUT4- OUT4+ OUT1+ OUT1- IN1+ IN1- TEST (tie GND) TEST (tie GND) VREFOUT (0V) CMVIN IN3- IN3+ OUT3- OUT3+
28-Pin PDIP
ispPAC10
Technical Support Assistance
Toll Free Hotline: International: E-mail: Internet: 1-800-LATTICE (Domestic) 1-408-826-6002 ispPACs@latticesemi.com http://www.latticesemi.com

General Architecture Overview ispPAC10 device from Lattice Semico

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