with PLL, based 64Mx4 SDRAM with LVTTL, banks Refresh HYM72V64C73

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with PLL, based 64Mx4 SDRAM with LVTTL, banks Refresh HYM72V64C73

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64Mx72 bits PC133 SDRAM Registered DIMM
with PLL, based 64Mx4 SDRAM with LVTTL, banks Refresh
HYM72V64C736B(L)T4 Series
HYM72V64C736B(L)T4 Series 64Mx72bits Synchronous DRAM Modules. modules composed eighteen 64Mx4bits CMOS Synchronous DRAMs 400mil 54pin TSOP-II package, 2Kbit EEPROM 8pin TSSOP package 168pin glass-epoxy printed circuit board. 0.22uF 0.0022uF decoupling capacitors each SDRAM mounted 512Mbytes memory. HYM72V64C736B(L)T4 Series fully synchronous operation referenced positive edge clock inputs outputs synchronized with rising edge clock input. data paths internally pipelined achieve very high bandwidth.
FEATURES
PC133/PC100MHz support 168pin SDRAM Unbuffered DIMM Serial Presence Detect with EEPROM 1.7" (43.18mm) Height with double sided components Single 3.3±0.3V power supply
SDRAM internal banks four banks Module bank physical bank Auto refresh self refresh 8192 refresh cycles 64ms Programmable Burst Length Burst Type Full page Sequential Burst
device pins compatible with LVTTL interface Interleave Burst Data mask function Programmable Latency Clocks
ORDERING INFORMATION
Part
HYM72V64C736BT4-K HYM72V64C736BT4-H HYM72V64C736BLT4-K HYM72V64C736BLT4-H 133MHz Banks Power
Clock Frequency
Internal Bank
Ref.
Power
Normal
SDRAM Package
Plating
TSOP-II
Gold
This document general product description subject change without notice. Hynix Semiconductor does assume responsibility circuits described. patent licenses implied. Rev. 0.3/Jan.
PC133 SDRAM Registered DIMM
HYM72V64C736B(L)T4 Series
CK0~CK3 CKE0 /S0, BA0, /RAS, /CAS, REGE DQM0~DQM7 DQ63 SA0~2 NAME Clock Inputs Clock Enable Chip Select SDRAM Bank Address Address Address Strobe, Column Address Strobe, Write Enable Register Enable Data Input/Output Mask Data Input/Output Check Input/Output Power Supply (3.3V) Ground Clock Input Data Input/Output Address Input Write Protect Connection DESCRIPTION system clock input. other inputs registered SDRAM rising edge Controls internal clock signal when deactivated, SDRAM will states among power down, suspend self refresh Enables disables inputs except Selects bank activated during /RAS activity Selects bank read/written during /CAS activity Address RA12, Column Address CA9, CA12 Auto-precharge flag /RAS, /CAS define operation Refer function truth table details Register Enable which permits DIMM operateion Buffered Mode when REGE input Low, Registered Mode when REGE input High Controls output buffers read mode masks input data write mode Multiplexed data input output Check bits Power supply internal circuits input buffers Ground Serial Presence Detect Clock input Serial Presence Detect Data input/output Serial Presence Detect Address Input Write Protect Serial Presence Detect DIMM connection
Rev. 0.3/Jan.
PC133 SDRAM Registered DIMM
HYM72V64C736B(L)T4 Series
ASSIGNMENTS
FRONT SIDE
BACK SIDE
FRONT SIDE
BACK SIDE
NAME
NAME
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
NAME
DQM2 DQM3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
NAME
*CK1 CKE0 DQM6 DQM7 DQ48 DQ49 DQ50 DQ51 DQ52 REGE DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 *CK3
Architecture
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM0 DQM1 A10/AP DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 /CAS DQM4 DQM5 /RAS
Voltage
Note connected with termination (Rsfer block diagram)
Rev. 0.3/Jan.
PC133 SDRAM Registered DIMM
HYM72V64C736B(L)T4 Series
BLOCK DIAGRAM
Note serial resistor values 10ohms padding capacitance termination CK1~CK3 12pF
Rev. 0.3/Jan.
PC133 SDRAM Registered DIMM
HYM72V64C736B(L)T4 Series
SERIAL PRESENCE DETECT
BYTE NUMBER BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 BYTE8 BYTE9 BYTE10 BYTE11 BYTE12 BYTE13 BYTE14 BYTE15 BYTE16 BYTE17 BYTE18 BYTE19 BYTE20 BYTE21 BYTE22 BYTE23 BYTE24 BYTE25 BYTE26 BYTE27 BYTE28 BYTE29 BYTE30 BYTE31 BYTE32 BYTE33 BYTE34 BYTE35 BYTE36 BYTE62 BYTE63 BYTE64 BYTE65 FUNCTION DESCRIPTION Bytes Written into Serial Memory Module Manufacturer Total Bytes Memory Device Fundamental Memory Type Addresses This Assembly Column Addresses This Assembly Module Banks This Assembly Data Width This Assembly Data Width This Assembly (Continued) Voltage Interface Standard This Assembly SDRAM Cycle Time @/CAS Latency=3 Access Time from Clock @/CAS Latency=3 DIMM Configuration Type Refresh Rate/Type Primary SDRAM Width Error Checking SDRAM Width Minimum Clock Delay Back Back Random Column Address Burst Lenth Supported Banks Each SDRAM Device SDRAM Device Attributes, /CAS Lataency SDRAM Device Attributes, Lataency SDRAM Device Attributes, Lataency SDRAM Module Attributes SDRAM Device Attributes, General SDRAM Cycle Time @/CAS Latency=2 Access Time from Clock @/CAS Latency=2 SDRAM Cycle Time @/CAS Latency=1 Access Time from Clock @/CAS Latency=1 Minimum Precharge Time (tRP) Minimum Active Active Delay (tRRD) Minimum /RAS /CAS Delay (tRCD) Minimum /RAS Pulse Width (tRAS) Module Bank Density Command Address Signal Input Setup Time Command Address Signal Input Hold Time Data Signal Input Setup Time Data Signal Input Hold Time Superset Information (may used future) Revision Checksum Byte 0~62 Manufacturer JEDEC Code .Manufacturer JEDEC Code 1.5ns 0.8ns 1.5ns 0.8ns Intel 1.2B Hynix JEDED Unused Hynix (Korea Area) (United States Area) (Europe Area) (Japan Area) HSS(Singapore) ASIA Area 7.5ns 5.4ns 7.8125us Self Refresh Supported tCCD 1,2,4,8,Full Page Banks /CAS Latency=2,3 Latency=0 Latency=0 Registered/Buffered inputs, with voltage tolerence, Burst Read Single Write, Precharge All, Auto Precharge, Early Precharge 7.5ns 5.7ns 15ns 15ns 15ns 45ns 512MB 1.5ns 0.8ns 1.5ns 0.8ns FUNCTION Bytes Bytes SDRAM Bank Bits LVTTL 7.5ns 5.4ns VALUE
NOTE
10ns 20ns 15ns 20ns 45ns
BYTE72
Manufacturing Location
Rev. 0.3/Jan.
PC133 SDRAM Registered DIMM
HYM72V64C736B(L)T4 Series
Continued
BYTE NUMBER
BYTE73 BYTE74 BYTE75 BYTE76 BYTE77 BYTE78 BYTE79 BYTE80 BYTE81 BYTE82 BYTE83 BYTE84 BYTE85 BYTE86 BYTE87~91 BYTE92 BYTE93 BYTE94 BYTE95 BYTE99 ~125 BYTE126 BYTE127 BYTE128 ~256
FUNCTION Manufacturer's Part Number (Component) Manufacturer's Part Number (256Mb based) Manufacturer's Part Number (Voltage Interface) Manufacturer's Part Number (Memory Width) .Manufacturer's Part Number (Memory Width) Manufacturer's Part Number (Module Type) Manufacturer's Part Number (Data Width) .Manufacturer's Part Number (Data Width) Manufacturer's Part Number (Refresh, SDRAM Bank) Manufacturer's Part Number(Manufacturing Site) Manufacturer's Part Number (Package Type) Manufacturer's Part Number (Component Configuration) Manufacturer's Part Number (Hyphen) Manufacturer's Part Number (Min. Cycle Time) Revision Code (for Component) .Revision Code (for PCB) Manufacturing Date .Manufacturing Date Assembly Serial Number Manufacturer Specific Data (may used future) Intel Sepcification frequency Intel Specification Details 100MHz Support Unused Storage Locations
FUNCTION
(SDRAM) (3.3V, LVTTL) Refresh, 4Banks) based) (Hyphen) Blanks Process Code Process Code Year Work Week Serial Number 100MHz Refer Note7
VALUE
NOTE
Note bank address excluded Interleave Burst Type adopted ASCII adopted Basically Hynix writes Part except `HYM' Byte 73~90 limited bytes from byte byte fixed dependent connected DIMM, junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge suport Refer Intel Specification 1.2B Refer Hynix site
Byte L-Part
BYTE NUMBER
BYTE82 BYTE83 BYTE84 BYTE85 BYTE86 BYTE87
FUNCTION Manufacturer's Part Number(Manufacturing Site) Manufacturer's Part Number (Power) Manufacturer's Part Number (Package Type) Manufacturer's Part Number (Component Configuration) Manufacturer's Part Number (Hyphent) Manufacturer's Part Number (Min. Cycle Time)
FUNCTION based) (Hyphen)
VALUE
NOTE
Rev. 0.3/Jan.
PC133 SDRAM Registered DIMM
HYM72V64C736B(L)T4 Series
ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature Storage Temperature Voltage relative Voltage relative Short Circuit Output Current Power Dissipation Soldering Temperature Time TSTG VIN, VOUT VDD, VDDQ TSOLDER Symbol -1.0 -1.0 Rating Unit
Note Operation above absolute maximum rating adversely affect device reliability.
OPERATING CONDITION (TA=0 70°C)
Parameter Power Supply Voltage Input High voltage Input voltage Symbol VDD, VDDQ -0.3 VDDQ Unit Note
Note 1.All voltages referenced 2.VIH(max) acceptable 5.6V pulse width with <=3ns duration. 3.VIL(min) acceptable -2.0V pulse width with <=3ns duration.
OPERATING TEST CONDITION (TA=0 70°C, VDD=3.3±0.3V, VSS=0V)
Parameter Input High Level Voltage Input Timing Measurement Reference Level Voltage Input Rise Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance Access Time Measurement Symbol Vtrip Voutref Value 2.4/0.4 Unit Note
Note 1.Output load measure access times equivalent gates capacitor (50pF). details, refer AC/DC output load circuit
Rev. 0.3/Jan.
PC133 SDRAM Registered DIMM
HYM72V64C736B(L)T4 Series
CAPACITANCE (TA=25°C, f=1MHz)
-K/H Parameter CKE0 Input Capacitance /S0, A0~12, BA0, /RAS, /CAS, DQM0~DQM7 Data Input Output Capacitance DQ63 Symbol CI/O Unit
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250
Output
Output 50pF
50pF
Output Load Circuit
Output Load Circuit
Rev. 0.3/Jan.
PC133 SDRAM Registered DIMM
HYM72V64C736B(L)T4 Series
CHARACTERISTICS (TA=0 70°C, VDD=3.3±0.3V)
Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Voltage Symbol Min. Unit Note -4mA +4mA
Note 1.VIN 3.6V, other pins tested under 2.DOUT disabled, VOUT=0
CHARACTERISTICS
Parameter Symbol Test Condition Burst length=1, bank active tRC(min), IOL=0mA VIL(max), VIL(max), VIH(min), VIH(min), Input signals changed time during 2clks. other pins VDD-0.2V 0.2V VIH(min), Input signals stable. VIL(max), VIL(max), VIH(min), VIH(min), Input signals changed time during 2clks. other pins VDD-0.2V 0.2V VIH(min), Input signals stable. tCK(min), IOL=0mA banks active CL=3 Speed 2400
Unit
Note
Operating Current
IDD1
IDD2P Precharge Standby Current Power Down Mode IDD2PS IDD2N Precharge Standby Current Power Down Mode IDD2NS Active Standby Current Power Down Mode IDD3P IDD3PS IDD3N Active Standby Current Power Down Mode IDD3NS Burst Mode Operating Current Auto Refresh Current Self Refresh Current IDD4 IDD5 IDD6
1120
3000 4900
tRRC tRRC(min), banks active 0.2V Normal power
Note IDD1 IDD4 depend output loading cycle rates. Specified values measured with output open Min. tRRC (Refresh cycle time) shown CHARACTERISTICS values measured with Registered HYM72V64C736BT4-K/H HYM72V64C736BLT4-K/H
Rev. 0.3/Jan.
PC133 SDRAM Registered DIMM
CHARACTERISTICS operating conditions unless otherwise noted)
Parameter Symbol System Clock Cycle Time Latency Latency tCK3 tCK2 tCHW tCLW tAC3 tAC2 tCKS tCKH tOLZ tOHZ3 tOHZ2 1000 1000 Latency Unit Note
HYM72V64C736B(L)T4 Series
Clock High Pulse Width Clock Pulse Width Access Time From Clock Latency
Data-Out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time Setup Time Hold Time Command Setup Time Command Hold Time Data Output Low-Z Time Data Output High-Z Time Latency Latency
Note Registered DIMM, data delayed additional clock cycle register (this Device DIMM Assume (input rise fall time 1ns, 1ns, then [(tR+tF)/2-1]ns should added parameter Access times measured with input signals 1v/ns edge rate, from 0.8v 2.0v 1ns, then (tR/2-0.5)ns should added parameter
Rev. 0.3/Jan.
PC133 SDRAM Registered DIMM
HYM72V64C736B(L)T4 Series
CHARACTERISTICS
Parameter Symbol Operation Cycle Time Auto Refresh Delay Active Time Precharge Time Bank Active Delay Delay Write Command Data-In Delay Data-In Precharge Command Data-In Active Command Data-Out Hi-Z Data-In Mask Command Precharge Data Output Hi-Z Latency Latency tRRC tRCD tRAS tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tPDE tSRE tREF 100K 100K Unit Note
Power Down Exit Time Self Refresh Exit Time Refresh Time
Note Timing delay register considered registered DIMM command given tRRC after self refresh exit
Rev. 0.3/Jan.
PC133 SDRAM Registered DIMM
HYM72V64C736B(L)T4 Series
DEVICE OPERATING OPTION TABLE
HYM72V64C736B(L)T4-K
Latency 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) 2CLKs 2CLKs 2CLKs tRCD 2CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 5CLKs 8CLKs 9CLKs 7CLKs 2CLKs 3CLKs 2CLKs 5.4ns 2.7ns
HYM72V64C736B(L)T4-H
Latency 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) 3CLKs 3CLKs 3CLKs tRCD 3CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 5CLKs 9CLKs 9CLKs 7CLKs 3CLKs 3CLKs 2CLKs 5.4ns 2.7ns
Note DIMM/CAS Latency Device (Registered Mode)
Rev. 0.3/Jan.
PC133 SDRAM Registered DIMM
HYM72V64C736B(L)T4 Series
COMMAND TRUTH TABLE
Command Mode Register Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge Banks Precharge selected Bank Burst Stop Auto Refresh Burst-Read-SingleWRITE Entry Self Refresh1 Exit CKEn-1 CKEn High (Other Pins code)
ADDR
A10/ code
Note
Entry Precharge power down Exit
Clock Suspend
Entry Exit
Note Exiting Self Refresh occurs asynchronously bringing from high Dont care, Logic High, Logic Low. =Bank Address, Address, Column Address, Opcode Operand Code, Operation
Rev. 0.3/Jan.
PC133 SDRAM Registered DIMM
HYM72V64C736B(L)T4 Series
PACKAGE DEMENSION
Rev. 0.3/Jan.

with PLL, based 64Mx4 SDRAM with LVTTL, banks Refresh HYM72V64C73

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