HYMP564R72A(L)8 Preliminary Hynix HYMP564R72(L)8 series regi
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DDR2 SDRAM Registered DIMM
HYMP564R72A(L)8
Preliminary
Hynix HYMP564R72(L)8 series registered 240-pin double data rate Synchronous DRAM Dual In-Line Memory Modules(DIMMs) which organized 64Mx72 high-speed memory arrays. Hynix HYMP564R72(L)8 series consists nine 64Mx8 DDR2 SDRAMs 60-Lead FBGA chipsize packages. Hynix HYMP564R72(L)8 series provide high performance 8-byte interface 133.35mm width form factor industry stanard. suitable easy interchange addition. Hynix HYMP564R72(L)8 series designed high speed 333MHz offers fully synchronous operations referenced both rising falling edges differential clock inputs. While addresses control inputs latched rising edges clock, Data, Data strobes Write data masks inputs sampled both rising falling edges data paths internally pipelined 4-bit prefetched achieve very high bandwidth. input output voltage levels compatible with SSTL_1.8. High speed frequencies, programmable latencies burst lengths allow variety device operation high performance memory system. Hynix HYMP564R72(L)8 series incorporates SPD(serial presence detect). Serial presence detect function implemented serial 2,048-bit EEPROM. first bytes serial data programmed Hynix identify DIMM type, capacity other information DIMM last bytes available customer.
FEATURES
512MB (64M Registered DDR2 DIMM based 64Mx8 DDR2 SDRAM JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V 0.1V Power Supply JEDEC Standard 240-pin dual in-line memory module (DIMM) Error Check Correction (ECC) Capability inputs outputs compatible with SSTL_1.8 interface (Off-Chip Driver Impedance Adjustment) (On-Die Termination) Fully differential clock operations /CK) with 200MHz 233MHz 333Hz Programmable Latency supported Programmable Burst Length with both sequential interleave mode inputs outputs SSTL_1.8 compatible Auto refresh self refresh supported 7.8us refresh period Lower than TCASE 3.9us( TCASE Serial Presence Detect(SPD) with EEPROM DDR2 SDRAM Package: 60ball FBGA
ORDERING INFORMATION
Type
PC2-3200 (DDR2-400) HYMP564R72(L)8-E3 HYMP564R72(L)8-C5 PC2-4300 (DDR2-533) HYMP564R72(L)8-C4 HYMP564R72(L)8-Y6 PC2-5300 (DDR2-667) HYMP564R72(L)8-Y5 5-5-5 rank 512MB Reg. DIMM 3-3-3 5-5-5 4-4-4 6-6-6 240pin Registered DIMM 133.35 30,00 (MO-237)
Part
HYMP564R72(L)8-E4
Description
CL-tRCD-tRP
4-4-4
Form Factor
This document general product description subject change without notice. Hynix Semiconductor does assume responsibility circuits described. patent licenses implied. Rev. Jan. 2004
HYMP564R72A(L)8
Input/Output Functional Description
Symbol CK0~CK1 Type Polarity Positive Edge Negative Edge Active High Description Positive line differential pair system clock inputs that drives input on-DIMM PLL.
CK0~CK1
Negative line differential pair system clock inputs that drives input on-DIMM PLL.
CKE0~CKE1
Activates DDR2 SDRAM signal when high deactivates signal when low. deactivating clocks, initiates Power Down mode Self Refresh mode. Enables associated DDR2 SDRAM command decoder when disables command decoder when high. When command decoder disabled, commands ignored previous operations continue. Rank selected Rank selected On-Die Termination signals. When sampled positive rising edge clock. RAS,CAS WE(ALONG WITH define command being entered. Reference voltage SSTL18 inputs Power supplies DDR2 SDRAM output buffers provide improved noise immunity. current DDR2 unbuffered DIMM designs, VDDQ shares same power plane pins.
S0~S1
Active
ODT0~ODT1 RAS, CAS, Vref VDDQ BA0~BA1
Supply Supply
Active High Active
Selects which DDR2 SDRAM internal bank four activated. During Bank Activate command cycle, Address input difines address(RA0~RA13) During Read Write command cycle, Address input defines column address when sampled cross point rising edge falling edge addition column address, used invoke autoprecharge operation burst read write cycle. high., autoprecharge selected BA0-BAn defines bank precharged. low, autoprecharge disabled. During Precharge command cycle., used conjunction with BA0-BAn control which bank(s) precharge. high, banks will precharged regardless state BA0-BAn inputs. low, then BA0-BAn used define which bank precharge. Data Check Input/Output pins.
A0~A9,A10/AP A11~A13
DQ0~DQ63, CB0~CB7
DM0~DM8
Active High
input mask signal write data. Input data masked when sampled High coincident with that input data during write access. sampled both edges DQS. Although pins input only, loading matches loading. Power ground DDR2 SDRAM input buffers, core logic. VDDQ pins tied VDD/VDDQ planes these modules.
VDD,VSS
Supply Positive Edge Negative Edge
DQS0~DQS17
Positive line differential data strobe input output data
DQS0~DQS17
Negative line differential data strobe input output data
SA0~SA1
These signals tied system planar either VDDSPD configure serial EEPROM address range. This bidirectional used transfer data into EEPROM. resister connected from line VDDSPD system planar pull This signal used clock data into EEPROM. resistor connected from VDDSPD pull system board. Power supply EEPROM. This supply separate from VDD/VDDQ power plane. EEPROM supply operable from 1.7V 3.6V. RESET connected register PLL. When low, register outputs will driven clocks DRAMs register(s) will level (the will remain synchronized with input clock) Parity Address Control bus("1". Odd, "0".Even) Parity error found Address Control Used memory analysis tools(unused memory DIMMs)
VDDSPD
Supply
RESET
Par_In Err_Out TEST
Rev. Jan. 2004
HYMP564R72A(L)8
CKE0~CKE1 A0~A9,A11~A13 A10/AP BA0, SA0~SA2 Par_In Err_Out RESET CB0~CB7 Description Clock Input,positive line Clock input,negative line Clock Enable Input Address Strobe Column Address Strobe Write Enable Chip Select Input Address input Address input/Autoprecharge SDRAM Bank Address Serial Presence Detect(SPD) Clock Input Data Input/Output PROM Address Inputs Parity Address Control Parity error found Addre Reset Enable Data Strobe Inputs/Outputs
ODT[1:0] VDDQ DQ0~DQ63 CB0~CB7 DQS(0~8) DQS(0~8) DM(0~8),DQS(9~17) DQS(9~17) TEST VDDQ VREF VDDSPD
Description Termination Inputs Power Supply Data Input/Output Data check bits Input/Output Data strobes Data strobes,negative line Data Maskes/Data strobes Data strobes,negative line Reserved Future Connect Memory test tool(Not Connected Useable DIMMs) Core Power Power Supply Ground Reference Power Supply Power Supply
Location
Front Side
Back Side
Rev. Jan. 2004
HYMP564R72A(L)8
ASSIGNMENT
Name VREF DQS0 DQS0 DQS1 DQS1 DQ10 DQ11 DQ16 DQ17 DQS2 DQS2 DQ18 DQ19 DQ24 DQ25 DQS3 DQS3 DQ26 DQ27 A10/AP VDDQ VDDQ NC/S1 ODT1 VDDQ DQ32 Name DQS8 DQS8 VDDQ CKE0 RESET VDDQ VDDQ Name DQ33 DQS4 DQS4 DQ34 DQ35 DQ40 DQ41 DQS5 DQS5 DQ42 VDQ43 DQ48 DQ49 NC(TEST) DQS6 DQS6 DQ50 DQ51 DQ56 DQ57 DQS7 DQS7 DQ58 DQ59 Name DM0,DQS9 DQS9 DQ12 DQ13 DM1,DQS10 DQS10 DQ14 DQ15 DQ20 DQ21 DM2,DQS11 DQS11 DQ22 DQ23 DQ28 DQ29 DM3,DQS12 DQS12 DQ30 DQ31 /CK0 VDDQ /RAS /CS0 VDDQ ODT0 DQ36 DQ37 Name DM8,DQS17 DQS17 VDDQ NC,CKE1 VDDQ VDDQ Name DM4/DQS13 DQS13 DQ38 DQ39 DQ44 DQ45 DM5/DQS14 DQS14 DQ46 DQ47 DQS2 DQ53 DM6/DQS15 DQS15 DQ54 DQ55 DQ60 DQ61 DM7/DQS16 DQS16 DQ62 DQ63 VDDSPD
Connect, RFU= Reserved Future Use.
Note:
RESET(Pin connected both Reset register. NC/Err_out (Pin NC/Par_In(Pin68) optional function check address command parity. Test pin(Pin 102) reserved analysis probes connected normal memory modules(DIMMs)
Rev. Jan. 2004
HYMP564R72A(L)8
FUNCTIONAL BLOCK DIAGRAM
/RS0
DQS0 /DQS0 DM0,DQS9 /DQS9
RDQS
DQS4 /DQS4 DM4,DQS13 /DQS13
/RDQS
/DQS
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
RDQS
/RDQS
/DQS
DQS1 /DQS1 DM1,DQS10 /DQS10
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
RDQS
DQS5 /DQS5 DM5,DQS14 /DQS14
/RDQS
/DQS
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
RDQS
/RDQS
/DQS
DQS2 /DQS2 DM2,DQS11 /DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
RDQS
DQS6 /DQS6 DM6,DQS15 /DQS15
/RDQS
/DQS
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
RDQS
/RDQS
/DQS
DQS0 /DQS0 DM0,DQS9 /DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
RDQS
DQS7 /DQS7 DM7,DQS16 /DQS16
/RDQS
/DQS
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
RDQS
/RDQS
/DQS
DQS8 /DQS8 DM8DQS17 /DQS17
RDQS
Serial
VDDQ
Serial DOD8 DOD8 DOD8
/RDQS
/DQS
/CS0* /RAS /CAS
CKE0 ODT0
/RS0 /CS: SDRAMs RBA0 RBA1 BA1: SDRAMs
/CK0
PCK0 PCK6, PCK8,PCK9 SDRAMs toD8 /PCK0 /PCK6, /PCK8, /PCK9 /CK: SDRAMs toD8
/RA0 RA13 A13: SDRAMs /RRAS ==>/RAS: SDRAMs /RCAS ==>/CAS: SDRAMs RCKE0 CKE: SDRAMs /RWE /WE: SDRAMs RODT0 ODT0: SDRAMs
/RESET
PCK7 Register
/PCK7 /CK: Register
Notes wiring changed within byte.
/RESET PCK7
/RST
/PCK7
Unless otherwise noted, register valutes Ohms.
connects D/CS connects /CSR register.
Rev. Jan. 2004
HYMP564R72A(L)8
ABSOLUTE MAXIMUM RATINGS
Parameter Operating temperature(ambient) DRAM Component Case Temperature Range Operating Humidity(relative) Storage Temperature Storage Humidity(without condensation) Barometric Pressure(operating storage) Symbol TOPR TCASE HOPR TSTG HSTG PBAR Value ~+95 +100
Unit
Note
Pascal
Note Stresses greater than those listed cause permanent damage device. This stress rating only, device functional operation above conditions indicated implied. Expousure absolute maximum rating conditions extended periods affect reliablility. DRAM case temperature Above 85oC, Auto-Refresh command interval reduced tREFI=3.9. Measurement conditions TCASE, please refer JEDEC document JESD51-2. 9850
Operating Condtions(AC&DC)
OPERATING CONDITIONS (SSTL_1.8)
Parameter Symbol Power Supply Voltage VDDQ Input Reference Voltage EEPROM Supply Voltage Termination Voltage VREF VDDSPD 0.49 VDDQ VREF-0.04 0.51 VDDQ VREF+0.04 Unit Note
Note
1.VDDQ must less than equal VDD. Peak peak noise VREF exeed +/-2% VREF(dc) transmitting device must track VREF receiving device.
Input Logic Level
Parameter Input High Voltage Input Voltage Symbol VIH(DC) VIL(DC) VREF 0.125 -0.30 VDDQ VREF 0.125 Unit Note
Rev. Jan. 2004
HYMP564R72A(L)8
Input Logic Level
Parameter Input logic High Input logic Symbol VIH(AC) VIL(AC) VREF 0.250 VREF 0.250 Unit Note
Input Test Conditions
Symbol VREF VSWING(MAX) SLEW Notes: Input waveform timing referenced input signal crossing through VREF level applied device under test. input signal minimum slew rate maintained over range from VIL(dc) VIH(ac) rising edges range from VIH(dc) VIL(ac) falling edges shown below figure. timings referenced with input waveforms switching from VIL(ac) VIH(ac) positive transitions VIH(ac) VIL(ac) negative transitions. Condition Input reference voltage Input signal maximum peak peak swing Input signal minimum slew rate Value VDDQ V/ns Units Notes
Start Falling Edge Input Timing
Start Rising Edge Input Timing
VSWING(MAX)
VDDQ VIH(ac) VIH(dc) VREF VIL(dc) VIL(ac)
delta Falling Slew VIH(dc) VIL(ac) delta
delta Rising Slew VIH(ac) VIL(dc) delta
Figure Input Test Signal Waveform
Rev. Jan. 2004
HYMP564R72A(L)8
Differential Input logic Level
Symbol (ac) (ac) Parameter differential input voltage differential cross point voltage Min. VDDQ 0.175 Max. VDDQ VDDQ 0.175 Units Notes
VIN(DC) specifies allowable execution each input differential pair such DQS, DQS, LDQS, LDQS, UDQS UDQS. VID(DC) specifies input differential voltage |VTR -VCP required switching, where true input (such DQS, LDQS UDQS) level complementary input (such DQS, LDQS UDQS) level. minimum value equal VIH(DC) IL(DC).
VDDQ VSSQ
Differential signal levels
Notes: VID(AC) specifies input differential voltage |VTR -VCP required switching, where true input signal (such DQS, LDQS UDQS) complementary input signal (such DQS, LDQS UDQS). minimum value equal IH(AC) IL(AC). typical value VIX(AC) expected about VDDQ transmitting device VIX(AC) expected track variations VDDQ VIX(AC) indicates voltage whitch differential input signals must cross. Crossing point
Differential output parameters
Symbol (ac) Parameter differential cross point voltage Min. VDDQ 0.125 Max. VDDQ 0.125 Units Notes
Notes: typical value VOX(AC) expected about transmitting device VOX(AC) expected track variations VDDQ VOX(AC) indicates voltage whitch differential output signals must cross.
Rev. Jan. 2004
HYMP564R72A(L)8
Output Buffer Levels
Output Test Conditions
Symbol VOTR Parameter Minimum Required Output Pull-up under Test Load Maximum Required Output Pull-down under Test Load Output Timing Measurement Reference Level SSTL_18 Class 0.603 0.603 VDDQ Units Notes
VDDQ device under test referenced.
Output Current Drive
Symbol IOH(dc) IOL(dc) Parameter Output Minimum Source Current Output Minimum Sink Current SSTl_18 Class 13.4 13.4 Units Notes
VDDQ VOUT 1420 (VOUT VDDQ)/IOH must less than values VOUT between VDDQ VDDQ VDDQ VOUT VOUT/IOL must less than values VOUT between value VREF applied receiving device values IOH(dc) IOL(dc) based conditions given Notes They used test device drive current capability ensure plus noise margin minus noise margin delivered SSTL_18 receiver. actual current values derived shifting desired driver operating point (see Section 3.3) along load line define convenient driver current measurement.
defalut characteristics
Description
Output impedance Pull-up pull-down mismatch Output slew rate Sout
Parameter
12.6
23.4
Unit
ohms ohms V/ns
Notes
1,2,3 1,4,5,6
Note: Absolute Specifications (0°C TCASE +tbd°C; +1.8V ±0.1V, VDDQ +1.8V ±0.1V) Impedance measurement condition output source current: VDDQ 1.7V; VOUT 1420mV; (VOUT-VDDQ)/Ioh must less than 23.4 ohms values VOUT between VDDQ VDDQ-280mV. Impedance measurement condition output sink current: VDDQ 1.7V; VOUT 280mV; VOUT/Iol must less than 23.4 ohms values VOUT between 280mV. Mismatch absolute value between pull-up pull-dn, both measured same temperature voltage. Slew rate measured from vil(ac) vih(ac). absolute value slew rate measured from equal greater than slew rate measured from DRAM output slew rate specification applies 400MT/s 533MT/s speed bins.
Rev. Jan. 2004
HYMP564R72A(L)8
CAPACITANCE (VDD=1.8V,VDDQ=1.8V, TA=25. f=1MHz
Parameter Input Capacitance Input Capacitance Input Capacitance Input Capacitance CK0, /CK0 CKE0, Address, /RAS, /CAS, DQ,DM,DQS, /DQS Symbol Unit
Note Pins under test tied GND. These value guaranteed design tested sample basis only.
Specifications(tbd)
HYMP564R72(L)8 Parameter
Operating bank active-precharge current Operating bank active-read-precharge current Precharge power-down current Precharge quiet standby current Precharge standby current Active power-down current IDD3P(S) Active Standby Current Operating burst read current Operating Current Burst auto refresh current Self Refresh Current IDD6(L) Operating bank interleave read current IDD7
3200 Symbol
IDD0
4300 max.
5300 max. Unit
max.
Note
IDD1 IDD2P IDD2Q IDD2N IDD3P(F)
IDD3N IDD4R IDD4W IDD5B IDD6
Rev. Jan. 2004
HYMP564R72A(L)8
Meauarement Conditions
Symbol IDD0 Conditions
Operating bank active-precharge current; tCK(IDD), tRC(IDD), tRAS tRASmin(IDD);CKE HIGH, HIGH between valid commands;Address inputs SWITCHING;Data inputs SWITCHING Operating bank active-read-precharge curren IOUT 0mA;BL CL(IDD), tCK(IDD), (IDD), tRAS tRASmin(IDD), tRCD tRCD(IDD) HIGH, HIGH between valid commands Address inputs SWITCHING Data pattern same IDD4W Precharge power-down current banks idle tCK(IDD) Other control address inputs STABLE; Data inputs FLOATING Precharge quiet standby current;All banks idle; tCK(IDD);CKE HIGH, HIGH; Other control address inputs STABLE; Data inputs FLOATING Precharge standby current; banks idle; tCK(IDD); HIGH, HIGH; Other control address inputs SWITCHING; Data inputs SWITCHING Active power-down current; banks open; tCK(IDD); LOW; Other control address inputs STABLE; Data inputs FLOATING Fast Exit MRS(12) Slow Exit MRS(12)
Units
IDD1
IDD2P IDD2Q IDD2N
IDD3P
IDD3N
Active standby current; banks open; tCK(IDD), tRAS tRASmax(IDD), =tRP(IDD); HIGH, HIGH between valid commands; Other control address inputs SWITCHING; Data inputs SWITCHING Operating burst write current; banks open, Continuous burst writes; CL(IDD), tCK(IDD), tRAS tRASmax(IDD), tRP(IDD); HIGH, HIGH between valid commands; Address inputs SWITCHING; Data inputs SWITCHING Operating burst read current; banks open, Continuous burst reads, IOUT 0mA; CL(IDD), tCK(IDD), tRAS tRASmax(IDD), tRP(IDD); HIGH, HIGH between valid commands; Address inputs SWITCHING;; Data pattern same IDD4W Burst refresh current; tCK(IDD); Refresh command every tRFC(IDD) interval; HIGH, HIGH between valid commands; Other control address inputs SWITCHING; Data inputs SWITCHING Self refresh current; 0.2V; Other control address inputs FLOATING; Data inputs FLOATING Operating bank interleave read current; bank interleaving reads, IOUT 0mA; CL(IDD), tRCD(IDD)-1*tCK(IDD); tCK(IDD), tRC(IDD), tRRD tRRD(IDD), tRCD 1*tCK(IDD); HIGH, HIGH between valid commands; Address inputs STABLE during DESELECTs; Data pattern same IDD4R; Refer following page detailed timing conditions
IDD4W
IDD4R
IDD5B
IDD6
IDD7
Note: specifications tested after device properly initialized Input slew rate specified Parametric Test Condition parameters specified with disabled. Data consists DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, UDQS. values must with combinations EMRS bits Definitions defined VILAC(max) HIGH defined VIHAC(min) STABLE defined inputs stable HIGH level FLOATING defined inputs VREF VDDQ/2 SWITCHING defined inputs changing between HIGH every other clock cycle (once clocks) address control signals, inputs changing between HIGH every other data transfer (once clock) signals including masks strobes. Rev. Jan. 2004
HYMP564R72A(L)8
Electrical Characteristics Timings
Speed Bins CL,tRCD,tRP,tRC tRAS Corresponding
Speed Bin(CL-tRCD-tRP) Parameter Latency tRCD tRAS DDR2-667(Y5) 5-5-5 DDR2-667(Y6) 6-6-6 DDR2-533(C4) 4-4-4 DDR2-533(C5) 5-5-5 18.75 18.75 63.75 DDR2-400(C3) 3-3-3 DDR2-400(C4) 4-4-4 Unit
Timing Parameters Speed Grade
DDR2-400 Parameter Symbol Data-Out edge Clock edge Skew DQS-Out edge Clock edge Skew Clock High Level Width Clock Level Width Clock Half Period System Clock Cycle Time input hold time input setup time Control Address input Pulse Width each input input pulse witdth each input pulse width each input Data-out high-impedance window from low-impedance time from CK/CK low-impedance time from CK/CK DQS-DQ skew associated signals hold skew factor DQ/DQS output hold time from Write command first latching transition input high pulse width input pulse width falling edge setup time falling edge hold time from Mode register command cycle time Write postamble tDQSCK tIPW tDIPW tLZ(DQS) tLZ(DQ) tDQSQ tQHS tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPST -600 -500 0.45 0.45 (tCL,tCH) 5000 0.35 0.55 0.55 8000 -500 -500 0.45 0.45 (tCL,tCH) 3750 0.35 0.55 0.55 8000 -450 -400 0.45 0.45 (tCL,tCH) 3000 0.35 0.55 0.55 8000 DDR2-533 DDR2-667 Unit Note
2*tAC tQHS 0.25 0.35 0.35 0.25
2*tAC tQHS 0.25 0.35 0.35 0.25
2*tAC tQHS 0.25 0.35 0.35 0.25
Rev. Jan. 2004
HYMP564R72A(L)8
continued DDR2 Parameter Symbol Write preamble Address control input hold time Address control input setup time Read preamble Read postamble Auto-Refresh Active/Auto-Refresh command period Active Active Delay command delay Write recovery time Auto Precharge Write Recovery Precharge Time Write Read Command Delay Internal read precharge command delay Exit self refresh non-read command Exit self refresh read command Exit precharge power down non-read command Exit active power down read command Exit active power down read command (Slow exit, Lower power) minimum pulse width (high pulse width) turn-on delay turn-on turn-on(Power-Down mode) turn-off delay turn-off
DDR2 0.25
DDR2 Unit Note
tWPRE tRPRE tRPST
0.25
tRFC
tRRD tCCD tDAL
(tWR/tCK) (tRP/tCK) tRFC tAC(min)
(tWR/tCK) (tRP/tCK) tRFC
(tWR/tCK) (tRP/tCK) tRFC
tWTR tRTP tXSNR tXSRD tXARD tXARDS
AOND
tAON
tAC(max)
tAC(min)
tAC(max)
tAC(min)
tAC(max) +0.7
tAONPD tAOFD tAOF
tAC(min)+2 2tCK+tAC tAC(min)+2 2tCK+tAC tAC(min)+2 2tCK+tAC (max)+1 (max)+1 (max)+1 tAC(min) tAC(max) tAC(min) tAC(max) tAC(min) tAC(max)
turn-off (Power-Down mode)
power down entry latency
AOFPD tAC(min)+ 2.5tCK+t tAC(min)+ 2.5tCK+t tAC(min)+ 2.5tCK+t AC(max) AC(max) AC(max) tANPD tAXPD tOIT tDelay tREFI tIS+tCK+tI tIS+tCK+tI tIS+tCK+tI
power down exit latency drive mode output delay Minimum time clocks remains after asynchronously drops Average periodic Refresh Interval
tREFI
Note details notes, please refer relevant HYNIX component datasheet(HY5PS12821(L)F). TCASE 85°C 85°C TCASE 95°C Rev. Jan. 2004
HYMP564R72A(L)8
PACKAGE OUTLINE
Frontside View
133.35
Side
4.0±0.1
(Front)
30.0
Detail-A
5.175
Detail-B
1.27 0.10
63.0
55.0
5.175
Backside View
17.80 10.0
Detail Contacts
0.20
0.20
Detail Contacts
2.50
2.50
0.05
1.50± 0.10 5.00
Note) dimensions typical millimeter scale unless otherwise stated.
Rev. Jan. 2004
3.80
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