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PREPARED Thierry CORBIERE
THIS DRAWING AVAILABLE DEPARTMENTS AGENCIES DEPARTMENT DEFENSE
CHECKED
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216
APPROVED
MICROCIRCUIT, DIGITAL,
DRAWING APPROVAL DATE
MONOLITHIC SILICON
AMSC
REVISION LEVEL DRAFT
SIZE SHEET
CAGE CODE
F7400
5962-00540
DSCC FORM 2233 DISTRIBUTION STATEMENT Approved public release; distribution unlimited.
5962-EXXX
SCOPE Scope. This drawing documents product assurance class levels consisting high reliability (device classes space application (device class choice case outlines lead finishes available reflected Part Identifying Number (PIN). When available, choice Radiation Hardness Assurance (RHA) levels reflected PIN. PIN. shown following example: 5962
00540
Federal stock class designator
designator (see 1.2.1) Drawing number
Device type (see 1.2.2)
Device class designator (see 1.2.3)
Case outline (see 1.2.4)
Lead finish (see 1.2.5)
1.2.1 designator. Device classes marked devices meet MIL-PRF-38535 specified levels marked with appropriate designator. Device class marked devices meet MIL-PRF-38535, appendix specified levels marked with appropriate designator. dash indicates non-RHA device. 1.2.2 Device type(s). device type(s) identify circuit function follows: Device type Generic number 695E Circuit function Monolithic 32-bit SPARC processor Frequency 25MHz
1.2.3 Device class designator. device class designator single letter identifying product assurance level follows: Device class Device requirements documentation Vendor self-certification requirements MIL-STD-883 compliant, non-JAN class level microcircuits accordance with MIL-PRF-38535, appendix Certification qualification MIL-PRF-38535
1.2.4 Case outline(s). case outline(s) designated MIL-STD-1835 follows: Outline letter Descriptive designator Figure Terminals Package style Ceramic quad flat package
1.2.5 Lead finish. lead finish specified MIL-PRF-38535 device classes MIL-PRF-38535, appendix device class
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Absolute maximum ratings. Supply Voltage range (VDD) Input Voltage range (VIN) Output current (IOUT) Lead temperature (soldering, seconds) Storage Temperature (TSTG) Maximum power dissipation (continuous) (PD) Thermal resistance junction-to-case (JC) Junction temperature (TJ) -0.5 7.0V -0.5 +265°C +150 1.5W 3°C/W +165°C
Recommended operating conditions. Operating supply voltage range (VDD) Input Voltage range (VIN) +4.5 -55°C +125°C
Digital logic testing device classes Fault coverage measurement manufacturing logic tests (MIL-STD-883, test method 5012). percent APPLICABLE DOCUMENTS Government specification, standards, handbooks. following specification, standards, handbooks form part this drawing extent specified herein. Unless otherwise specified, issues these documents those listed issue Department Defense Index Specifications Standards (DoDISS) supplement thereto, cited solicitation. SPECIFICATION DEPARTMENT DEFENSE MIL-PRF-38535 Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT DEFENSE MIL-STD-883 MIL-STD-973 MIL-STD-1835 Test Method Standard Microcircuits. Configuration Management. Interface Standard Microcircuit Case Outlines.
Stresses above absolute maximum rating cause permanent damage device. Extended operation maximum levels degrade performance affect reliability. Values will added when they become available. (VDD 0.5V) should exceed +7.0 maximum current single output Duration seconds maximum distance less than from device body, same lead shall resoldered until minutes have elapsed. Values will added when they become available.
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HANDBOOKS DEPARTMENT DEFENSE MIL-HDBK-103 MIL-HDBK-780 List Standard Microcircuit Drawings (SMD's). Standard Microcircuit Drawings.
(Unless otherwise indicated, copies specification, standards, handbooks available from Standardization Document Order Desk, Robbins Avenue, Building Philadelphia, 19111-5094.) Non-Government publications. following document(s) form part this document extent specified herein. Unless otherwise specified, issues documents which adopted those listed issue DODISS cites solicitation. Unless otherwise specified, issues documents listed DODISS issues documents cited solicitation. INSTITUTE ELECTRICAL ELECTRONICS ENGINEERS (IEEE) IEEE Standard 1149.1 IEEE Standard test Access port Boundary Scan Architecture. (Application copies should addressed Institute Electrical Electronics Engineers, Hoes Lane, Piscataway, 08854-4150.) (Non-Government standards other publications normally available from organizations that prepare distribute documents. These documents also available through libraries other information services.)
Order precedence. event conflict between text this drawing references cited herein, text this drawing takes precedence. Nothing this document, however, supersedes applicable laws regulations unless specific exemption been obtained. REQUIREMENTS Item requirements. individual item requirements device classes shall accordance with MIL-PRF-38535 specified herein modified device manufacturer's Quality Management (QM) plan. modification plan shall affect form, fit, function described herein. individual item requirements device class shall accordance with MIL-PRF-38535, appendix non-JAN class level devices specified herein. Design, construction, physical dimensions. design, construction, physical dimensions shall specified MIL-PRF-38535 herein device classes MIL-PRF-38535, appendix herein device class 3.2.1 Case outline(s). case outline(s) shall accordance with 1.2.4 herein figure herein 3.2.2 Terminal connections. terminal connections shall specified figure 3.2.3 Block diagram(s). block diagram shall specified figure 3.2.4 Test circuit timing waveforms. test circuit timing waveforms shall described figure 3.2.5 Boundary scan instruction codes. boundary scan instruction codes shall specified figure 3.2.6 Radiation exposure circuit. radiation exposure circuit shall specified when available. Electrical performance characteristics postirradiation parameter limits. Unless otherwise specified herein, electrical performance characteristics postirradiation parameter limits specified table shall apply over full case operating temperature range. Electrical test requirements. electrical test requirements shall subgroups specified table electrical tests each subgroup defined table Marking. part shall marked with listed herein. addition, manufacturer's also marked listed MIL-HDBK-103. packages where marking entire number feasible space limitations, manufacturer option marking "5962-" device. product using this option, designator
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000
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shall still marked. Marking device classes shall accordance with MIL-PRF-38535. Marking device class shall accordance with MIL-PRF-38535, appendix 3.5.1 Certification/compliance mark. certification mark device classes shall "QML" required MIL-PRF-38535. compliance mark device class shall required MIL-PRF-38535, appendix Certificate compliance. device classes certificate compliance shall required from QML-38535 listed manufacturer order supply requirements this drawing (see 6.6.1 herein). device class certificate compliance shall required from manufacturer order listed approved source supply MIL-HDBK-103 (see 6.6.2 herein). certificate compliance submitted DSCC-VA prior listing approved source supply this drawing shall affirm that manufacturer's product meets, device classes requirements MIL-PRF-38535 herein device class requirements MIL-PRF-38535, appendix herein. Certificate conformance. certificate conformance required device classes MIL-PRF-38535 device class MIL-PRF-38535, appendix shall provided with each microcircuits delivered this drawing. Notification change device class device class notification DSCC-VA change product (see herein) involving devices acquired this drawing required change defined MIL-STD-973. Verification review device class device class DSCC, DSCC's agent, acquiring activity retain option review manufacturer's facility applicable required documentation. Offshore documentation shall made available onshore option reviewer. 3.10 Microcircuit group assignment device class Device class devices covered this drawing shall microcircuit group number (see MIL-PRF-38535, appendix 3.11 IEEE 1149.1 compliance. These devices shall compliant IEEE 1149.1.
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000
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TABLE Electrical performance characteristics. Test conditions -55°C +125°C
Test
Symbol
+4.5 +5.5 unless otherwise specified
Group subgroups
Device type
Limits
Unit
High level input voltage
VIHCR
5.5V 5.5V 4.5V
level input voltage High level output voltage
4.5V =-6mA
Minimum Maximum values recorded
VOHB
4.5V =-16mA
Minimum Maximum values recorded
level output voltage
4.5V
Minimum Maximum values recorded
VOLB
4.5V 12mA
Minimum Maximum values recorded
High level input current level input current
IILT
5.5V 5.5V 5.5V 5.5V 5.5V 5.5V F=25MHz 5.5V F=25MHz
Three-state leakage current Three-state leakage current Supply current (internal) IVDD pins Supply current (idle) IVDD pins Input capacitance
IOZH IOZL IDDDIN IDDIDLE
Functional test
2.5V 25°C 4.4.1c 1.45 1.55 4.4.1b
footnotes table.
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Test
Symbol
Test conditions -55°C +125°C
+4.5 +5.5 unless otherwise specified 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure
Group subgroups
Device type
Limits
Unit
CLK2 Period
SYSCLK Period
CLK2 High pulse width RA(31:0) RAPAR RSIZE output delay MEMCS*(9:0) ROMCS* EXMCS* output delay DDIR DDIR* output delay
9.75
10.25
12.5
MEMWR* output delay
24.5
output delay
20.5
Data setup time during load
Data hold time during load
Data output delay
Data output valid
output delay
ALE* output delay
BUFFEN* output delay
MDS* DRDY* output delay
MEXC* output delay
RASI(3:0) RSIZE(1:0) RASPAR setup time
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RASI(3:0) RSIZE(1:0) RASPAR hold time BOOT PROM address output delay BUSRDY* setup time
4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure
BUSRDY* hold time
IOSEL output delay
DMAAS setup time
DMAAS hold time
DMAREQ* setup time
DMAGNT* output delay
RA(31:0) RAPAR CPAR setup time
RA(31:0) RAPAR CPAR hold time
period
setup time
hold time
setup time
hold time
output delay
INULL output delay
RESET* CPUHALT* output delay SYSERR* SYSAV output delay IUERR* output delay
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EXTINT(4:0) setup time
4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure 4.5V figure
EXTINT(4:0) hold time
EXTINTACK output delay
output delay mode) BUFFEN* output delay
INST output delay
Data output delay low-Z
recorded Tested go/nogo during functional test Applies RA31-0, RAPAR, RASI3-0, RSIZE1-0, RASPAR, CPAR, D31-0, CB6-0, DPAR, RLDSTO, DXFER, LOCK, WE*, WRT, PROM8*, ROMWRT*, BUSRDY*, BUSERR*, DMAREQ*, DMAAS, SYSHALT*, NOPAR*, IWDE, WDCLK, CLK2, TMODE1-0, DEBUG, TCK, TRST*, TMS, TDI. Applies RxA, RxB, GPI7-0, EXTINT4-0, EWDINT, SYSRESET*. Applies RAPAR, RASI3-0, RSIZE1-0, RASPAR, CPAR, D31-0, CB6-0, DPAR, RLDSTO, ALE*, DXFER, LOCK, WE*, WRT, MHOLD*, MDS*, MEXC*, BA1-0, ROMCS*, MEMCS9-0*, BUFFEN*, DDIR, DDIR*, IOSEL3-0*, IOWR*, EXMCS*, DMAGNT*, DRDY*, IUERR*, CPUHALT*, SYSERR*, SYSAV, INULL, INST, FLUSH, DIA, RTC, TxA, TxB, GPIINT, EXTINTACK, SYSCLK, RESET*, TDO. Applies RA31-0, MEMWR*, OE*. Applies PROM8*, ROMWRT*, BUSRDY*, BUSERR*, DMAREQ*, DMAAS, SYSHALT*, NOPAR*, RxA, RxB, EXTINT4-0, IWDE, EWDINT, WDCLK, CLK2, SYSRESET*, TMODE1-0, DEBUG, TCK, TRST*, TMS, TDI. Applies PROM8*, ROMWRT*, BUSRDY*, BUSERR*, DMAREQ*, DMAAS, SYSHALT*, NOPAR*, RxA, RxB, EXTINT4-0, IWDE, EWDINT, WDCLK, CLK2, SYSRESET, TMODE1-0, DEBUG TCK, TRST*. Applies TMS, TDI. Applies RA31-0, RAPAR, RASI3-0, RSIZE1-0, RASPAR, CPAR, D31-0, CB6-0, DPAR, RLDSTO, DXFER, LOCK, WE*, WRT, GPI7-0. Tested during tests recorded.
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FIGURE Case outline.
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000
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MQFP_F LOCATION
NAME GPIINT GPI[7] VCCO VSSO GPI[6] GPI[5] GPI[4] GPI[3] VCCO VSSO GPI[2] GPI[1] GPI[0] D[31] D[30] VCCO VSSO D[29] D[28] VCCI VSSI D[27] D[26] VCCO VSSO D[25] D[24] D[23] D[22] VCCO VSSO D[21] D[20] D[19] D[18] VCCO VSSO D[17] D[16] VCCI VSSI D[15] D[14] VCCO VSSO D[13] D[12] D[11] D[10] VCCO VSSO D[9] D[8] D[7] D[6] VCCO VSSO D[5] D[4] D[3] D[2] VCCO VSSO D[1]
MQFP_F LOCATION
NAME D[0] RSIZE[1] RSIZE[0] RASI[3] VCCO VSSO RASI[2] RASI[1] RASI[0] RA[31] RA[30] VCCO VSSO RA[29] RA[28] RA[27] VCCO VSSO RA[26] RA[25] RA[24] VCCI VSSI VCCO VSSO RA[23] RA[22] RA[21] VCCO VSSO RA[20] RA[19] RA[18] VCCO VSSO RA[17] RA[16] RA[15] VCCO VSSO RA[14] VCCI VSSI RA[13] RA[12] VCCO VSSO RA[11] RA[10] RA[9] VCCO VSSO RA[8] RA[7] RA[6] VCCO VSSO RA[5] RA[4] RA[3] VCCO VSSO RA[2] RA[1]
MQFP_F LOCATION
NAME RA[0] VCCO VSSO RAPAR RASPAR DPAR VCCO VSSO SYSCLK TRST* CLK2 DRDY* DMAAS VCCO VSSO DMAGNT* EXMCS* VCCI VSSI DMAREQ* BUSERR* BUSRDY* ROMWRT* NOPAR* SYSHALT* CPUHALT* VCCO VSSO SYSERR* SYSAV EXTINT[4] EXTINT[3] EXTINT[2] EXTINT[1] EXTINT[0] VCCI VSSI EXTINTACK IUERR* VCCO VSSO CPAR IOWR* IOSEL[3]* VCCO VSSO IOSEL[2]* IOSEL[1]* IOSEL[0]* VCCO VSSO RLDSTO LOCK
MQFP_F LOCATION
NAME DXFER MEXC* VCCO VSSO RESET* SYSRESET* BA[1] BA[0] CB[6] CB[5] VCCO VSSO CB[4] CB[3] CB[2] CB[1] VCCO VSSO CB[0] ALE* VCCI VSSI PROM8* ROMCS* MEMCS[9]* VCCO VSSO MEMCS[8]* MEMCS[7]* MEMCS[6]* MEMCS[5]* MEMCS[4]* MEMCS[3]* VCCO VSSO MEMCS[2]* MEMCS[1]* MEMCS[0]* VCCI VSSI VCCO VSSO MEMWR* BUFFEN* DDIR VCCO VSSO DDIR* MHOLD* MDS* WDCLK IWDE EWDINT TMODE[1] TMODE[0] DEBUG INULL VCCO VSSO FLUSH INST
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FIGURE Terminal connections.
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Clock Reset Management
32-Bit Integer Unit
32/64-Bit Floating Point Unit
Arbitrer
Ctrl
Access Controller
Ctrl
Error Management General Purpose Interface Bits
General Purpose Timer UART UART
Real Time Clock Timer
Watch
Wait State Controller Address Interface
Ready/Busy size Data Check bits Parities
Interrupt Controller
EDAC
RxD,
Interrupts
Parity Generator Checker
FIGURE Block diagram.
Device type Instruction name Instruction code BYPASS 11.1111 EXTEST 00.0000 SAMPLE PRELOAD 00.0001 INTEST 00.0011 Code 10.0000 Reserved emulation 01.1000 Reserved emulation 01.1001 Reserved emulation 01.1010 Reserved emulation 01.1100 Reserved emulation 01.1101 Reserved emulation 01.1110 FIGURE Boundary scan instruction
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FIGURE Timing waveforms.
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QUALITY ASSURANCE PROVISIONS Sampling inspection. device classes sampling inspection procedures shall accordance with MILPRF-38535 modified device manufacturer's Quality Management (QM) plan. modification plan shall affect form, fit, function described herein. device class sampling inspection procedures shall accordance with MIL-PRF-38535, appendix Screening. device classes screening shall accordance with MIL-PRF-38535, shall conducted devices prior qualification technology conformance inspection. device class screening shall accordance with method 5004 MIL-STD-883, shall conducted devices prior quality conformance inspection. 4.2.1 Additional criteria device class Burn-in test, method 1015 MIL-STD-883. Test condition test circuit shall maintained manufacturer under document revision level control shall made available preparing acquiring activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified test method 1015. +125°C, minimum. Interim final electrical test parameters shall specified table herein.
4.2.2 Additional criteria device classes burn-in test duration, test condition test temperature, approved alternatives shall specified device manufacturer's plan accordance with MIL-PRF-38535. burn-in test circuit shall maintained under document revision level control device manufacturer's Technology Review Board (TRB) accordance with MIL-PRF-38535 shall made available acquiring preparing activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified test method 1015 MIL-STD-883. Interim final electrical test parameters shall specified table herein. Additional screening device class beyond requirements device class shall specified MIL-PRF-38535, appendix
Qualification inspection device classes Qualification inspection device classes shall accordance with MIL-PRF-38535. Inspections performed shall those specified MIL-PRF-38535 herein groups inspections (see 4.4.1 through 4.4.4). Conformance inspection. Technology conformance inspection classes shall accordance with MIL-PRF-38535 including groups inspections specified herein except where option MIL-PRF-38535 permits alternate in-line control testing. Quality conformance inspection device class shall accordance with MIL-PRF-38535, appendix specified herein. Inspections performed device class shall those specified method 5005 MIL-STD-883 herein groups inspections (see 4.4.1 through 4.4.4).
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4.4.1 Group inspection. Tests shall specified table herein. device class subgroups tests shall sufficient verify truth table. device classes subgroups shall include verifying functionality device; these tests shall have been fault graded accordance with MIL-STD-883, test method 5012 (see herein). Subgroup measurement) shall measured only initial test after process design changes which affect input capacitance. minimum devices with zero rejects shall required.
4.4.2 Group inspection. group inspection end-point electrical parameters shall specified table herein. 4.4.2.1 Additional criteria device class Steady-state life test conditions, method 1005 MIL-STD-883: Test condition test circuit shall maintained manufacturer under document revision level control shall made available preparing acquiring activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified test method 1005 MIL-STD-883. +125°C, minimum. Test duration: 1,000 hours, except permitted method 1005 MIL-STD-883.
4.4.2.2 Additional criteria device classes steady-state life test duration, test condition test temperature, approved alternatives shall specified device manufacturer's plan accordance with MIL-PRF-38535. test circuit shall maintained under document revision level control device manufacturer's accordance with MIL-PRF-38535 shall made available acquiring preparing activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified test method 1005 MILSTD-883.
TABLE Electrical test requirements. Test requirements Subgroups accordance with MIL-STD-883, method 5005, table Device class Interim electrical parameters (see 4.2) Final electrical parameters (see 4.2) Group test requirements (see 4.4) Group end-point electrical parameters (see 4.4) Group end-point electrical parameters (see 4.4) Group end-point electrical parameters (see 4.4) applies subgroup applies subgroups Subgroups accordance with MIL-PRF-38535, table III) Device class Device class 1,7,9
4.4.3 Group inspection. group inspection end-point electrical parameters shall specified table herein. 4.4.4 Group inspection. Group inspection required only parts intended marked radiation hardness assured
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(see herein). End-point electrical parameters shall specified table herein. device classes devices test vehicle shall subjected radiation hardness assured tests specified MIL-PRF-38535 level being tested. device class devices shall subjected radiation hardness assured tests specified MIL-PRF-38535, appendix level being tested. device classes must meet postirradiation end-point electrical parameter limits defined table +25°C ±5°C, after exposure, subgroups specified table herein. When specified purchase order contract, copy delta limits shall supplied.
PACKAGING Packaging requirements. requirements packaging shall accordance with MIL-PRF-38535 device classes MIL-PRF-38535, appendix device class NOTES Intended use. Microcircuits conforming this drawing intended Government microcircuit applications (original equipment), design applications, logistics purposes. 6.1.1 Replaceability. Microcircuits covered this drawing will replace same generic device covered contractor prepared specification drawing. 6.1.2 Substitutability. Device class devices will replace device class devices. Configuration control SMD's. proposed changes existing SMD's will coordinated with users record individual documents. This coordination will accomplished accordance with MIL-STD-973 using Form 1692, Engineering Change Proposal. Record users. Military industrial users should inform Defense Supply Center Columbus when system application requires configuration control which SMD's applicable that system. DSCC will maintain record users this list will used coordination distribution changes drawings. Users drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0525. Comments. Comments this drawing should directed DSCC-VA Columbus, Ohio 43216-5000, telephone (614) 692-0674. Abbreviations, symbols, definitions. abbreviations, symbols, definitions used herein defined MIL-PRF-38535 MIL-HDBK-1331, table herein.
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name
Type
Description
RA31-0 RAPAR RASI3-0 RSIZE1-0 RASPAR CPAR D31-0 CB6-0 DPAR RLDSTO DXFER LOCK MHOLD
Registered Address Bus. Registered address parity. 4-bit registered address space identifier. 2-bit registered transaction size. Registered SIZE parity. Control parity. 32-bit data bus. 7-bit check-bit bus. Data parity. Registered atomic load-store. Address latch enable. Data transfer. lock. Read access. Write enable. Advanced write. Memory hold. signal asserted when "Memory Hold" (MHOLD), "floating Point Hold" (FHOLD) "Floating Point Condition Codes Valid" (FCCV) Hold (BHOLD) internally generated. Memory data strobe. Memory exception Select 8-bit wide PROM Latched address used 8-bit wide boot PROM PROM chip select write enable Memory chip select Memory write strobe Memory output enable Data buffer enable Data buffer direction Data buffer direction chip select exchange memory write strobe Exchange memory chip select ready error request grant address strobe Data ready during access error Processor FPU) halt freeze System error System halt
SIZE
MEXC PROM8 BA[1:0] ROMCS ROMWRT MEMCS[9:0] MEMWR BUFFEN DDIR DDIR IOSEL[3:0] IOWR EXMCS BUSRDY BUSERR DMAREQ DMAGNT DMAAS DRDY IUERR CPUHALT SYSERR SYSHALT
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DRAFT
SYSAV NOPAR INULL INST FLUSH RxA/RxB TxA/TxB GPI[7:0] GPIINT EXTINT[4:0] EXTINTACK IWDE EWDINT WDCLK CLK2 SYSCLK RESET SYSRESET TMODE[1:0] DEBUG TRST VCCI/VSSI VCCO/VSSO
System availability parity Integer unit nullify cycle Instruction fetch instruction flush Delay instruction annulled Real Time Clock Counter output Receive data UART Transmit data UART input/output interrupt External interrupt External interrupt acknowledge Internal watch enable External watch input interrupt Watch clock Double frequency clock System clock Output reset System input reset Factory test mode Software debug mode Test (JTAG) clock Test (JTAG) reset Test (JTAG) mode select Test (JTAG) data input Test (JTAG) data output Main internal power Output driver power Table III. descriptions
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
SIZE
REVISION LEVEL
5962-00540
SHEET
DRAFT
Sources supply. 6.6.1 Sources supply device classes Sources supply device classes listed QML-38535. vendors listed QML-38535 have submitted certificate compliance (see herein) DSCC-VA have agreed this drawing. 6.6.2 Approved sources supply device class Approved sources supply class listed MIL-HDBK-103. vendors listed MIL-HDBK-103 have agreed this drawing certificate compliance (see herein) been submitted accepted DSCC-VA.
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
SIZE
REVISION LEVEL
5962-00540
SHEET
DRAFT
STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 2000-June Approved sources supply 5962-00540 listed below immediate acquisition information only shall added MIL-HDBK-103 during next revision. MIL-HDBK-103 will revised include addition deletion sources. vendors listed below have agreed this drawing certificate compliance been submitted accepted DSCC-VA. This bulletin superseded next dated revision MIL-HDBK-103.
Standard microcircuit drawing 5962-0054001QXC 5962-0054001VXC
Vendor CAGE number F7400 F7400
Vendor similar TSC695E-25MAMQ TSC695E-25SASV
lead finish shown each representing hermetic package most readily available from manufacturer listed that part. desired lead finish listed contact vendor determine availability. Caution. this number item acquisition. Items acquired this number satisfy performance requirements this drawing.
Vendor CAGE number F7400
Vendor name address CHANTERIE GACHET 70602 NANTES F-44000, France Voice Telephone: (0)240181818 Telephone: (0)240181920
information contained herein disseminated convenience only Government assumes liability whatsoever inaccuracies information bulletin.

PREPARED Thierry CORBIERE THIS DRAWING AVAILABLE DEPARTMENTS AGEN

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