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ADSP-21065L EZ-KIT Lite Evaluation System Manual
Part Number: 82-000490-01 Revision December 2000
Notice Analog Devices, Inc. reserves right make changes discontinue product service identified this publication without notice. Analog Devices assumes liability Analog Devices applications assistance, customer product design, customer software performance, infringement patents services described herein. addition, Analog Devices shall held liable special, collateral, incidental consequential damages connection with arising furnishing, performance, this product. Analog Devices products intended life-support applications, devices, systems. Analog Devices product such applications without written consent Analog Devices officer prohibited. Users restricted from copying, modifying, distributing, reverse engineering, reverse assembling reverse compiling ADSP-21065L EZ-KIT Lite operational software (one copy made back-up purposes only). part this document reproduced form without permission. Trademark Service Mark Notice Analog Devices logo, SHARC, SHARC logo, VisualDSP, VisualDSP logo, EZ-ICE registered trademarks; TigerSHARC, TigerSHARC logo, White Mountain DSP, VisualDSP++, VisualDSP++ logo, Apex-ICE, EZ-KIT Lite, Mountain-ICE, Summit-ICE, Trek-ICE, Collaborative trademarks Analog Devices, Inc. Microsoft Windows registered trademarks Windows trademark Microsoft Corporation. Adobe Acrobat trademarks Adobe Systems Incorporated. other brand product names trademarks service marks their respective owners. Limited Warranty ADSP-21065L EZ-KIT Lite hardware warranted against defects materials workmanship period year from date purchase from Analog Devices from authorized dealer. Copyright 2000, Analog Devices, Inc. rights reserved. Revision 1.0, December 2000
TABLE CONTENTS
LIST TABLES LIST FIGURES INTRODUCTION. MORE INFORMATION ABOUT ANALOG DEVICES, INC. PRODUCTS. TECHNICAL CUSTOMER SUPPORT. PURPOSE THIS MANUAL. INTENDED AUDIENCE. MANUAL CONTENTS DESCRIPTION DOCUMENTS RELATED PRODUCTS
GETTING STARTED OVERVIEW CONTENTS YOUR EZ-KIT LITE PACKAGE CONFIGURATION VISUALDSP++. INSTALLATION PROCEDURES 2.5.1 Installing EZ-KIT Lite Hardware 2.5.2 Installing VisualDSP++ 2.5.3 Installing VisualDSP++ EZ-KIT Lite License 2.5.4 Installing EZ-KIT Lite Software
USING EZ-KIT LITE SOFTWARE OVERVIEW STANDARD OPERATION. 3.2.1 Devices 3.2.2 POST Routines. 3.2.3 Monitor Program Operation. 3.2.4 AD1819 Transmissions. RUNNING YOUR PROGRAMS 3.3.1 ADSP-21065L Memory Map. 3.3.2 Using AD1819A SoundPort Codec Analog Front 3.3.3 Method Using Monitor's Codec Buffers Interrupt Handler 3.3.4 Programming AD1819 Indexed Control Registers 3.3.5 EMAFE Programming
DEMONSTRATION PROGRAMS OVERVIEW STARTING VISUALDSP++ DEBUGGER DEBUGGER OPERATION WITH ADSP-21065L EZ-KIT LITE 4.3.1 Loading Programs 4.3.2 Registers Memory 4.3.3 Setting Breakpoints Stepping 4.3.4 Resetting EZ-KIT Lite Board. BENCHMARKING UTILITIES DEMONSTRATION PROGRAMS 4.5.1 FFT.dxe. 4.5.2 BP.dxe. 4.5.3 Pluck.dxe. 4.5.4 Gunn.dxe.
4.5.5 Primes.dxe. 4.5.6 Tt.dxe 4.5.7 Blink.dxe. WORKING WITH EZ-KIT LITE HARDWARE. OVERVIEW SYSTEM ARCHITECTURE BOARD LAYOUT. 5.3.1 Boot EPROM. 5.3.2 User Push-Button Switches 5.3.3 User LED's POWER SUPPLIES 5.4.1 Power Connector. 5.4.2 European Power Supply Specifications. 5.4.3 AD1819 Connections 5.4.4 Expansion Port Connectors 5.4.5 EMAFE Interface Connector 5.4.6 JTAG Connector (Emulator Port) JUMPERS 5.5.1 Boot Mode Selection Jumper 5.5.2 EPROM Size Selection Jumpers 5.5.3 Processor Jumpers. EPROM OPERATION 5.6.1 Designers Note. UART. 5.7.1 Designers Note. EMAFE AD1819. 5.10 5.11 TIMING DIAGRAMS EXPANSION CONNECTORS OVERVIEW EMAFE EXPANSION 6.2.1 EMAFE Connector Interface Signal Descriptions REFERENCE. OVERVIEW SETTINGS MENU COMMANDS 7.2.1 Test Communications. 7.2.2 Baud Rate. 7.2.3 Comm Port 7.2.4 Codec DEMO MENU COMMANDS. APPENDIX RESTRICTIONS CPLD CODE LISTING APPENDIX BILL MATERIALS APPENDIX SCHEMATICS INDEX
LIST TABLES
TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE MINIMUM CONFIGURATION USER CONFIGURABLE EZ-KIT LITE SETTINGS FLAG SUMMARY INTERRUPTS USED MONITOR PROGRAM TABLE 3-3. POST ROUTINES. TABLE 3-4. POST ERROR CODES MEMORY AVAILABLE MEMORY LOCATIONS EZ-KIT LITE PROGRAMMING AD1819 INDEXED CONTROL REGISTERS POWER CONNECTOR EUROPEAN POWER SUPPLY SPECIFICATIONS BOOT MODE SELECTION EPROM SIZE SELECTION PROCESSOR SELECTION LINE SELECTION AD1819 CODEC SELECTION SDRAM CONNECTIONS EXPANSION CONNECTORS EVALUATION BOARD POWER CONNECTIONS EMAFE CONNECTOR EMAFE CONNECTOR INTERFACE SIGNAL DESCRIPTION EMAFE CONNECTOR INTERFACE SIGNAL DESCRIPTION EMAFE CONNECTOR INTERFACE SIGNAL DESCRIPTION DEMO DIALOG DESCRIPTION.
LIST FIGURES
FIGURE ADSP-21065L EZ-KIT LITE MONITOR KERNEL CODEC TRANSFER SCHEME FIGURE TARGET SELECTION DIALOG FIGURE TARGET MESSAGE FIGURE TARGET COMMUNICATIONS STATUS MESSAGE FIGURE EZ-KIT LITE SYSTEM BLOCK DIAGRAM FIGURE EZ-KIT LITE LAYOUT. FIGURE JTAG CONNECTOR WITH JUMPERS INSTALLED. FIGURE EPROM ADDRESS (256K EXAMPLE) FIGURE EMAFE WRITE CYCLE TIMING PARAMETER DEFINITIONS FIGURE EMAFE WRITE CYCLE TIMING DIAGRAM FIGURE EMAFE READ CYCLE TIMING PARAMETER DEFINITIONS FIGURE EMAFE READ CYCLE TIMING DIAGRAM FIGURE PHYSICAL LAYOUT ADSP-21065L EVALUATION BOARD EMAFE DAUGHTER BOARD FIGURE SETTINGS MENU COMMANDS FIGURE SAMPLE RATE DIALOG FIGURE SOURCE SETTING FIGURE DEMO DIALOG FIGURE BANDPASS DEMO CONTROLS DIALOG
INTRODUCTION
Thank purchasing ADSP-21065L EZ-KIT Lite evaluation kit. evaluation board designed used conjunction with VisualDSP++ development environment based ADSP-21065L SHARC® floating-point digital signal processor (DSP). shipped with evaluation board VisualDSP++ software. VisualDSP++ that comes with will only operate with evaluation board. complete version must purchased seperately. Using EZ-KIT Lite with VisualDSP++, observe ADSP-21065L execute programs from onchip RAM, interact with on-board devices, communicate with other peripherals. access ADSP-21065L SHARC processor using through serial port optional JTAG emulator. monitor program that runs EZ-KIT Lite, gives access ADSP21065L processor's internal memory space through serial port. contrast, JTAG emulator allows perform in-circuit emulation through processor's JTAG interface. board's features include: Analog Devices ADSP-21065L running 60MHz Analog Devices AD1819A 16-bit SoundPort® Codec RS-232 interface Socketed EPROM (128K board, 256K 512K selectable) SDRAM Four push buttons Flag inputs Three push buttons inputs user programmable LEDs Power supply regulation EMAFE (Enhanced Modular Analog Front End) connector expansion Expansion connectors
EZ-KIT Lite board equipped with hardware that facilitates interactive demonstrations. push button switches user programmable LEDs provide user control board status. Additionally, AD1819A SoundPort Codec provides access audio input (selectable line level microphone) audio output (line level). EZ-KIT Lite includes monitor program stored non-votilitile memory. monitor program allows user download, execute debug ADSP-21065L programs. removing socketed EPROM, replacing with EPROM containing user code, board stand-alone unit, without
user also connect JTAG emulator EZ-KIT Lite. Through JTAG emulator, load programs, start stop program execution, observe alter registers memory, perform other debugging operations. JTAG emulators purchased seperately through Analog Devices. Additionally, EZ-KIT Lite provides expansion connectors that user examine processor signals, well provide interface host control.
More Information About Analog Devices, Inc. Products
Analog Devices accessible Internet www.analog.com. page directly accessible www.analog.com/dsp. This page provides access specific technical information documentation, product overviews, product announcements.
Technical Customer Support
reach Customer Support group following ways: Email questions dsptools.support@analog.com Contact your local Analog Devices sales office authorized Analog Devices distributor
Purpose This Manual
ADSP-21065L EZ-KIT Lite evaluation system manual gives directions installing evaluation board software Also, manual provides guidelines running user code ADSP-21065L.
Intended Audience
This manual user's guide reference ADSP-21065L EZ-KIT Lite evaluation board. programmers familiar with Analog Devices SHARC architecture, operation, programming primary audience this manual. programmers unfamiliar with Analog Devices DSPs this manual, should supplement this manual with ADSP-21065L User's Manual, ADSP-21065L Technical Reference VisualDSP++ tools manuals.
Manual Contents Description
This manual contains following information: Chapter Introduction Provides manual information Analog Devices contact information. Chapter Getting Started Provides software hardware installation procedures, system requirements, basic board information. Chapter Using EZ-KIT Lite Software Provides information EZ-KIT Lite system from software perspective, details monitor program, EMAFE, codec. Chapter Demonstration Programs Provides information VisualDSP++ debugger operation with ADSP-21065L EZ-KIT Lite, benchmarking utilities, demonstration programs. Chapter Working With EZ-KIT Lite Hardware Provides information Hardware aspects evaluation system. Chapter Expansion Connectors Provides information EMAFE expansion descriptions connector interface signals. Chapter Reference Provides information settings menu commands demo menu commands. Appendix Restrictions CPLD Code Listing Provides information board restrictions encounter when using your EZ-KIT Lite, files used programmable device(s) EZ-KIT Lite board. Appendix Bill Materials Provides list components used manufacture EZ-KIT Lite board. Appendix Schematics Provides resource allow EZ-KIT Lite board level debugging reference design.
Documents Related Products
more information ADSP-21065L components EZ-KIT Lite system, following documents: ADSP-21065L SHARC User's Manual Technical Reference ADSP-21065L AC'97 SoundPort®
ADSP-2106x family processors supported complete evaluation tools. Software tools include compiler, assembler, runtime libraries librarian, linker, simulator, PROM splitter. following documents: VisualDSP++ Getting Started Guide VisualDSP++ User's Guide ADSP-21xxx Family DSPs Assembler Manual ADSP-21xxx Family DSPs C/C++ Compiler Library Manual ADSP-21xxx Family DSPs Linker Utilities ADSP-21xxx Family DSPs Product Bulletin VisualDSP++ ADSP-21xxx Family DSPs
These documents found Analog Devices Technical Documentation site
plan EZ-KIT Lite conjunction with JTAG emulator, refer documentation that accompanies emulator. Your software installation includes on-line help part Windows interface. These help files provide information about ADSP-21065L evaluation board accompanying tools.
GETTING STARTED
Overview
This chapter provides information install software ADSP-21065L evaluation board. important that installation software hardware order presented correct operation. This chapter also provides basic board information conatins following sections: Contents your EZ-KIT Lite package configuration Installation procedures
Contents Your EZ-KIT Lite Package
EZ-KIT Lite evaluation board contains (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate human body equipment discharge without detection. Permanent damage occur devices subjected high energy discharges. Proper precautions recommended avoid performance degradation loss functionality. Unused EZ-KIT Lites should stored protective shipping package.
ADSP-21065L EZ-KIT Lite evaluation board package should contain following items. item missing, contact vendor where purchased your EZ-KIT Lite Analog Devices. ADSP-21065L EZ-KIT Lite board Power cable with power supply (7.5 Volts) RS-232 serial port 9-pin cable EZ-KIT Lite containing examples, target .dll files, help files, utilities VisualDSP++ Registration card please fill return
Configuration
correct operation VisualDSP++ software EZ-KIT Lite demos, computers must have minimum configuration shown below.
Table Minimum Configuration Windows 2000 Windows OSR2, Windows Windows 2000 Pentium processor faster Monitor color video card 2-button mouse available space CD-ROM Windows Windows release 4.0, Service Pack later Pentium processor faster Monitor color video card 2-button mouse available space CD-ROM
VisualDSP++
ADSP-21065L EZ-KIT Lite system shipped with VisualDSP++ Integrated Development Environment (IDE), debugger code generation tools. VisualDSP++ limited functionality EZ-KIT Lite serial number that shipped with this product. EZ-KIT Lite serial number restricts VisualDSP++ debugger only connect ADSP-21065L EZKIT Lite evaluation board running debug monitor serial port emulator simulator support). Additionally, linker will restrict user only (2.5k words) ADSP21065L's on-chip program memory space. full VisualDSP++ software suite purchased, user will obtain serial number from Analog Devices that will lift restrictions mentioned above. basic components that shipped with VisualDSP++ are: Integrated Development Environment (IDE) graphical interface project management, allowing user project options, access code generation tools, launch debugger. Debugger allows user view insides perform debug operations such read/write memory, read/write registers, load programs, run, step, halt, more. SHARC Family Code Generation Tools compiler, assembler, runtime libraries librarian, linker, simulator, PROM splitter. Example Projects Both VisualDSP++ ADSP-21065L EZ-KIT Lite shipped with example projects Assembly source code that demonstrate various features tools ADSP-21065L DSP.
Installation Procedures
following procedures provided safe effective ADSP-21065L evaluation board. important that follow these instructions order presented ensure correct operation your software hardware.
2.5.1 Installing EZ-KIT Lite Hardware
ADSP-21065L EZ-KIT Lite board designed outside stand alone unit. There need remove chassis from your computer. following steps connect EZ-KIT Lite board: Remove EZ-KIT Lite board from package-be careful when handling these boards avoid discharge static electricity, which damage some components. Connect RS-232 cable available Comm Port ADSP-21065L evaluation board. Plug provided cord into 120-Volt receptacle plug connector other cable into (Power evaluation board. LEDs light briefly. FLAG9 power (red) remain LEDs light check power connections. configure your board take advantage audio capabilities demos, following procedure: Plug self-powered computer speakers into jack J7(Line Out) board. Turn speakers volume adequate level. Connect line electronic audio device jack (MIC/Line board. jumpers LINE. Jumper enable AD1819 codec. (This board default)
This completes hardware installation.
2.5.2 Installing VisualDSP++
This EZ-KIT Lite comes with latest evaluation version VisualDSP++ SHARC Family DSPs. must install this software prior installing EZ-KIT Lite software. Insert VisualDSP++ into CD-ROM drive. This will bring browser. Click "Install VisualDSP++" option. This will launch setup wizard. Follow this wizard with on-screen instructions.
2.5.3 Installing VisualDSP++ EZ-KIT Lite License
Before VisualDSP++ software used, license must installed. install EZ-KIT Lite license, follow these steps: Make sure VisualDSP++ been installed first. Insert VisualDSP++ into CD-ROM drive already drive. Once browser screen select "Install License" option. follow setup wizard instructions. (Note: Make sure that have proper serial number located back holder.)
2.5.4 Installing EZ-KIT Lite Software
EZ-KIT Lite software supplied separate CD-ROM. install EZ-KIT Lite software, follow these steps: Make sure VisualDSP++ been installed first. Close Windows applications. install will work correctly VisualDSP++ applications running. Insert EZ-KIT Lite into CD-ROM drive. setup will automatically start. Follow installation wizard choosing appropriate options. When setup completed reboot machine, necessary.
2.5.4.1 Default Settings
After have installed board utility software, your EZ-KIT Lite have default settings shown Table 2-2. change these settings through Settings menu debugger.
Table User Configurable EZ-KIT Lite Settings Selection Comm Port Baud Rate Codec Sample Rate Codec Source Codec Gain Default Setting Comm 115200 48000 Microphone
2.5.4.2 On-Line Help
VisualDSP++ Debugger comes with complete on-line help file Adobe .pdf files manuals. context help button Highlight command press help command icon
help commands dialogs click from toolbar Help Help Topics Debugger Help help file.
USING EZ-KIT LITE SOFTWARE
Overview
combination EZ-KIT Lite board monitor software operate target VisualDSP++ debugger. debugger allows viewing processor registers memory, perform several debugging activities, such setting breakpoints, stepping through code, plotting range memory. VisualDSP++ installed, please install from VisualDSP++ that came with this product. more information, refer Chapter section "VisualDSP++". This chapter provides monitor level software information EZ-KIT Lite board operates with installed software. This chapter also provides information that helps user his/her programs ADSP-21065L EZ-KIT Lite board. This information appears following sections: "Standard Operation" Describes operation EZ-KIT Lite board, from Power self Test (POST) routines AD1819 codec's operation. "Running Your Programs" Provides information about writing running your executables that link with monitor program EZ-KIT Lite board.
Standard Operation
This section covers standard operation EZ-KIT Lite board. describes capabilities on-board components, board power-up, on-board Monitor program.
3.2.1 Devices 3.2.1.1 Flags
ADSP-21065L asynchronous FLAG pins that interact with running program. flags configured inputs reset DSP. more information Flag pins, Chapter "System Design, Flag Pins" ADSP21065L SHARC User's Manual. flags their uses, follows: FLAG0-3 connected push buttons EZ-KIT Lite board user input. instance, user tell program poll flag when occurs, some other operation such jump another instruction. push button flags inputs through MODE2 register. Once configured, they read through ASTAT register.
FLAG4-9 connect LEDs supply feedback program execution. example user write code trigger flag (and corresponding LED) when routine complete will light. flags configured through IOCTL register set/read through IOSTAT register.
FLAG10 available EMAFE interface used signaling. EMAFE flag configured through IOCTL register set/read through IOSTAT register. FLAG11 reserved monitor determine AD1819 codec enabled. When using monitor program supplied with EZ-KIT Lite board, alter this flag pin.
Table Flag Summary Flag
Flag0-3
Push-button Input (SW3, SW5, SW7, SW8) Feedback EMAFE Flag Reserved monitor
Flag4-9 Flag10 Flag11
3.2.1.2 Interrupts
Each three external interrupts, IRQ0-2, ADSP-21065L directly accessible through push button switches SW2, SW4, EZ-KIT Lite board. IRQ0-1 "wire-Or'ed"; IRQ0 used implement interrupt driven serial routines with UART IRQ1 provided with EMAFE board read write registers. external interrupts controlled through MODE1, MODE2, IMASK registers configured ways: modifying vector table through instructions user code. MODE2 register also controls interrupt sensitivity between level edge. prevent interrupt from being masked, write particular interrupt IMASK register. monitor program running ADSP-21065L uses three interrupts; IRQ0, SPT1I SFT3, normal operation. These interrupt vectors provided "demorth.asm" file that comes with EZ-KIT Lite.
When writing code, these interrupts (and their corresponding vectors) should altered. these vectors overwritten, kernel work shown Table 3-1. more information registers that control interrupts, complete list interrupt vector addresses, Appendix ADSP-21065L SHARC Technical Reference.
Table Interrupts Used Monitor Program Interrupt IRQ0 Description Multiplexed from UART through open collector device SFT3 Lost Functionality Overwritten Debugger's ability interrupt running code
Used signal monitor send Ability send messages from data back Host user code debugger
SPT1
AD1819 Transmit Interrupt Monitor's ability control AD1819
SPR1
AD1819 Receive Interrupt
following rules restrictions should followed when using interrupts: cannot step into interrupt. Interrupts disabled when user program halted. board cannot communicate with host interrupt higher than IRQ0 used. board cannot communicate with host interrupt nesting disabled. user does require supplied monitor program, IRQ0 with configured user. initialization code user's program, interrupt vector IRQ0 must replaced. This removes monitor functionality. user does connect EMAFE EZ-KIT Lite, IRQ1 with configured other purposes. EMAFE card attached uses IRQ1, there disable EMAFE's control interrupt line. EMAFE attached, IRQ1 available other uses. Note: monitor program does interact with EMAFE board, does have response IRQ1 request.
3.2.1.3 Serial Ports
ADSP-21065L features synchronous Serial Ports (SPORT0 SPORT1). SPORTs operate clock frequency, providing each with maximum data rate Mbit/sec. Each SPORT primary secondary transmit receive channels. SPORT data automatically transferred from on-chip memory using DMA.
Each SPORTs supports three operation modes: SPORT mode, mode interface commonly used audio codecs) (Time Division Multiplex) multichannel mode. additional information serial ports please refer Chapter ADSP-21065L SHARC User's Manual. Both synchronous serial ports connected EMAFE interface. SPORT1 also connected on-board AD1819. Jumper used disable AD1819, doesn't interfere with EMAFE. normal operation AD1819, must connected GND. EMAFE using SPORT1, serial communication AD1819A should disabled connecting +3.3VCC.
3.2.2 POST Routines
POST (Power Self Test) routines series standard tests initializations that EZ-KIT Lite performs power-on reset. perform power-on reset, disconnect power board least three seconds then reconnect power. board automatically resets (note that LED's light briefly). user also reset board during operation through Debug Reset command from debugger menu bar. Both types reset cause reset known state followed message that displays message "Communications Success". this point user should reload programs he/she working Table shows types resets their functions.
Table Table 3-3. Post Routines
Routine EPROM Check Internal Memory Check External Memory Check UART Check AD1819 Check Initializations
Power-on Reset
Reset During Operation
Error codes transmitted displayed LEDs. remains after reset, then error been caused component shown Table
Table Table 3-4. POST Error Codes
Flag
Error EPROM UART AD1819 Memory
3.2.2.1 Memory Checks
monitor program performs some standard memory checks which follows: EPROM Internal memory External SDRAM
EPROM test consists verifying number memory. monitor code corrupted, monitor crash before reaching actual program code. These checks include: Write, then verify Write, then verify Write, then verify memory address Write, then verify compliment memory address
3.2.2.2 UART Check/Initialization
UART check done three stages. these stages implemented POST. third controlled host (PC), when attempts connect EZ-KIT Lite. These stages are: Register Write This test confirms that ADSP-21065L capable writing reading from register UART. Three patterns written then read from register UART, tested. three patterns must read back correctly pass this test. Internal Loop Back this test, bytes sent read from UART. This test checks functionality UART connections from ADSP-21065L, through UART chip. Transmitted Loop Back last UART test performed host after POST complete. this test, host sends UART test protocol. This protocol specifies number bytes that transmitted EZ-KIT Lite board, instructs board echo byte stream back host. This test determines whether EZ-KIT Lite board correct baud rate, verifies external connections between board host.
power EZ-KIT Lite board defaults baud rate 115200 baud with data bits, stop bit, parity. want change this rate change after POST complete Settings Baud Rate command from debugger menu bar. Note that setting baud rate lower number significantly slow boards response debug activities.
3.2.2.3 AD1819 Check/Initialization
reset, AD1819 begins transmitting clock used synchronize data transfers over SPORT1. Once this goes high, AD1819 ready standard communication over SPORT1. POST then writes verifies three patterns internal register AD1819. three writes verified, connection verified.
3.2.3 Monitor Program Operation
monitor program runs EZ-KIT Lite board part executable provides ability download, debug, user programs. VisualDSP++ debugger interface monitor using EZ-KIT Lite target with debugger lets operate board remotely. There three main components monitor program: Halt loop UART Command Processing Kernel
monitor program idles Halt loop when running user code. While there, read/write memory, read/write registers, download programs, breakpoints, change UART's baud rate, modify AD1819 configuration, single step through code. enter halt loop from your code, must halt user code-either with breakpoint halt instruction. this point, halt loop polls UART. With every character received from UART, command processing kernel verifies whether full command been received. command been received, kernel processes command; otherwise control returned halt loop wait more characters. only method executing your code once halt loop been entered send Single Step command debugger. UART entered when user code running, host still interacting with board. host sends bytes, UART takes data stream from UART, builds command. with halt loop, each character received passed command processing kernel. Unlike halt loop, monitor returns user code immediately after interrupt serviced.
following restrictions should followed ensure correct board operation. host loses contact with monitor while user program running user program disables UART interrupt changes UART interrupt vector. host loses contact with monitor while program running when nesting turned off. host loses contact with monitor while program running timer ISR, provided highest priority timer vector used. host cannot halt with debugger's Debug, Halt command global enable disabled (IRPTEN bit), however, breakpoints will work.
Command processing, initiated from either UART Halt Loop, done command processing kernel. This kernel parses commands executes instructions. instruction requires data sent back host, kernel initiates response.
3.2.3.1 Break Points
ability stop execution code examine processor registers memory extremely helpful when debugging code. Note that debugger automatically inserts breakpoints function Main(), when Settings Main command checked, _exit instruction.
3.2.4 AD1819 Transmissions
After reset, AD1819 generates clock used transfer data across SPORT1. ADSP-21065L initiates transmissions with AD1819 sending synchronization pulse. Even though AD1819 transmits data clock, ready normal operation. Until AD1819 ready, holds first (AD1819 Ready bit) SLOT low. When ready, this driven high. first transmission AD1819 done differently than subsequent transmissions. packets initially expected AD1819 have consistent size. This first transmission instructs AD1819 standardize packet size 16-bit. This command created shifting stuffing bits transmit buffer. Slot each transmission specifies which slots contain valid data. ADSP-21065L uses transfers automatically send receive data from AD1819. When transmit empties transmit buffer, interrupt occurs. Request interrupt loads data from User buffer into buffer. variable Request buffer loaded with After buffer loaded, initialized transmit data buffer. receive portion AD1819 interface designed similar way. SPORT1's receive register configured load buffer.
When buffer full, interrupt generated that checks request variable. variable then contents buffer written into User Buffer, request cleared. Afterwards, re-initialized fill buffer again.
Running Your Programs
This section provides user with basic information that needed their programs ADSP-21065L EZ-KIT Lite. Build these programs using SHARC tools. This information includes rules using processor memory, description AD1819 control registers (with respect programming), simple program generation procedure. Although there many ways about developing programs VisualDSP++ environment, program evaluation within environment should include following steps: Step1: Create Project File Step Target Processor Project Options Step Edit Project Source Files Step Customize Project Build Options Step Build Debug Version Project Step Debug Project Step Build Release Version Project
following these steps, projects build consistently accurately with minimal project management. ADSP-21065L SHARC Technical Reference ADSP-21065L SHARC User's Manual provides detailed information programming processor VisualDSP++ manuals provide information code evaluation with SHARC tools. more than ADSP-21065L EZ-KIT Lite Session debugger time. EZ-KIT Lite session simulator session same time open debugger interfaces more than EZ-KIT Lite session. Before making changes source code IDE, user needs clear breakpoints close source window. Then make changes, rebuild program reload into debugger.
3.3.1 ADSP-21065L Memory
ADSP-21065L EZ-KIT Lite board contains external SDRAM. This memory connected (Memory Select). ADSP-21065L Kbits internal SRAM that used either program data storage. configuration on-chip SRAM detailed ADSP-21065L SHARC User's Manual. Table shows memory ADSP-21065L EZ-KIT Lite. IMDW0 SYSCON register must keep communication with host. This determines data accesses made internal memory block 40-bit three column accesses (set 32-bit column accesses (cleared monitor program requires three column data accesses memory block
reset, restart, halt, debug monitor kernal forces IMDW0 IMDW1 user code should also these bits ensure that operates same both simulator EZ-KIT Lite board. These settings only affect data accesses, instruction fetches. Block resides Three Column memory. storing data Block must three column format. user DAG2 data bus) access SDRAM because SDRAM mapped into address that greater than bits. example, segment seg_pmda should mapped SDRAM. user using interrupt handlers his/her program, (i.e. interrupt()) then seg_dmda must located external SDRAM. this case seg_dmda MUST located internal memory. This caused problem with interrupt handlers libc.dlb. correction will posted Analog Devices site.
Table Memory
Start Address 0x0000 0000 0x0000 8000
Address 0x0000 02FF 0x0000 9FFF
Content Registers Block Normal Address (internal memory) Block Normal Address (internal memory) Block Short word Block Short word EPROM (through BMS)1 EMAFE Address (reserved EZ-KIT) EMAFE Data (reserved EZ-KIT) UART (reserved EZKIT) SDRAM (reserved EZKIT)
0x0000 C000
0x0000 DFFF
0x0001 0000 0x0001 8000 0x0002 0000 0x0100 0000
0x0001 3FFF 0x0001 BFFF 0x0002 FFFF 0x0100 0000
0x0100 0001
0x0100 0001
0x0100 0004
0x0100 0007
0x0300 0000
0x0310 0000
caution when accessing Boot EPROM. EPROM chip select, BMS, same limitations MS0. EPROMs larger than 128K have restricted access their data below address 0x020000 their data aliased other memory locations. user program access this data from these other locations.
Table shows currently used available memory locations EZ-KIT Lite board. user change these locations their programs.
Table Available Memory Locations EZ-KIT Lite Memory Range 0x00008000 0x0000801F 0x00008020 0x00008023 Availability Interrupt Vectors user (48-bit) IRQ0 vector (reserved monitor overwritten .dxe load) 0x00008024 0x00008033 0x00008034 0x00008037 0x00008038 0x0000807B 0x0000807C 0x0000807F 0x00008100 0x00008FFF Interrupt Vectors user (48-bit) SPORT Vector (reserved monitor) Interrupt Vectors user (48-bit) SWI3 Vector (reserved monitor) User Program Space (3840 48-bit locations, internal block 0x00009000 0x000097FF 0x0000C000 0x0000DFFF Kernel Code (48-bit, internal block User space (can configured 8192 0x01000000 0x01000001 0x01000008 0x0100000F 0x01000010 0x03000000 0x030FFEFF EMAFE address location (external block EMAFE data location (external block 16550 UART registers (external block AD1819 reset address (external block User space (external block 1048320 32-bit locations SDRAM) 0x030FFF00 0x030FFF05 0x030FFF06 0x030FFF07 0x030FFF0C 0x030FFF0D 0x030FFF0E 0x030FFF0F 0x030FFF10 0x030FFF11 0x030FFFFF User AD1819 transmit buffer User AD1819 transmit ready flag User AD1819 receive buffer User AD1819 receive ready flag User SWI3 data pointer User SWI3 number data items User SWI3 data type Reserved Kernel
3.3.2 Using AD1819A SoundPort Codec Analog Front
There ways AD1819 SoundPort codec 21065L EZ-KIT Lite with VisualDSP++ debugger. Method codec buffers codec interrupt handler within EPROM monitor that installed AD1819/SPORT1 initialization routine EPROM Monitor Program. This method useful want quickly test your algorithm. This method preferable early evaluation, user does need concerned with many details AD1819 theory operation. following section provides coding guidelines programmer link required codec SPORT buffers. audio demos provided with ADSP-21065L EZ-KIT Lite this method communicating with codec RS-232 host codec control. Method Disabling Overwriting SPORT1 codec buffers, downloading custom AD1819/SPORT1 initialization routine with RS-232 monitor. custom user routine includes instructions necessary reset codec, program SPORT1, activates serial port transmit receive transfers, programs AD1819a register desired configuration. This method preferable want test AD1819 code that downloaded SHARC JTAG, burnt into EPROM, test AD1819 functionality custom-based 21065L design. detailed AD1819 SHARC interface information example source that demonstrates this second method, contact Analog Devices hotline search site following document: Interfacing ADSP-21065L SHARC AD1819a 'AC97' SoundPort codec. Further information AC-97 serial protocol found AD1819A Datasheet.
3.3.3 Method Using Monitor's Codec Buffers Interrupt Handler
This section provides more detail Method from previous section. ADSP21065L uses transfers automatically send receive data from codec. After codec reset, codec begins transmitting clock used synchronously transfer data across SPORT1. ADSP-21065L, turn, initiates transmissions with codec sending frame synchronization pulse. Even though codec transmits data clock, ready normal operation. While codec ready holds first (codec Ready bit) SLOT low. When ready, this driven high. Once this goes high, codec ready standard communication with ADSP-21065L. AD1819 initially expects data transfers packets according AC'97 specification, where there 16-bit time slot slots audio frame. This packet scheme does work well transfer schemes, standard Multichannel Mode data transfers with ADSP-21065L, which expects slots same number bits. realign your data, SLOT16 AD1819's Serial Configuration register soon serial port enabled. this, program must perform single transfer using initial packing style.
After SLOT16 set, subsequent packets standardized bits. Once data aligned, EPROM's monitor POST routine then writes verifies three patterns internal register codec. three writes verified, codec connection verified. ADSP-21065L then continually transmits receives data from codec. Slot each transmission specifies which slots contain valid data (and called Phase time slot).
3.3.3.1
Linking Your Code RS-232 Monitor Codec Interrupt Handlers
EPROM monitor's interrupt handler AD1819, user needs following methods: C-code-link your code with file demorth.asm (this located .\demos\tt folder). This file contains replacement standard runtime header 060_hdr.asm. This file also includes jump EPROM codec interrupt handler SPORT1 interrupt vector location. Assembly-use demorth.asm file interrupt vector table create your interrupt vector table that includes jump address 0x9001at SPORT1 interrupt vector location.
3.3.3.2 Linking Your Code RS-232 Monitor Buffers
monitor constantly sends receives packets from codec. send data codec, user needs desired data into codec transmit buffer, transmit variable. Similarly, receive data from codec, receive variable should value variable then polled change back When this happens codec data been transferred into codec receive buffer, read. Figure shows software structure codec data transfer. transfer RS232 monitor program EPROM boot.
Figure ADSP-21065L EZ-KIT Lite Monitor Kernel Codec Transfer Scheme
3.3.3.2.1 DSP/Codec Transmit Sequence
SPORT1 transmit empties transmit buffer, SPORT1 transmit interrupt occurs. variable Request then interrupt loads data from User Buffer into Buffer; otherwise, Buffer loaded with After Buffer loaded, re-initialized transmit data Buffer. With this structure monitor, user needs only data User Buffer, then Request send data codec.
3.3.3.2.2 DSP/Codec Receive Sequence
receive portion codec interface designed similar transmit portion. SPORT1's receive register configured load Buffer. When Buffer full, interrupt forced that checks Request variable. variable then contents Buffer written into User Buffer, Request cleared. re-initialized fill Buffer again.
3.3.3.3 RS-232 Monitor Codec Memory
monitor's codec variables, examine buffers.asm .ldf files provided with demos. These files provide access necessary variables overlapping locations variables. RS-232 Monitor Program complied linked place following user variables buffers communicated codec following memory locations:
0x030FFF00 0x030FFF05
User CODEC transmit buffer DM(user_tx_buf)
0x030FFF06 0x030FFF07 0x030FFF0C
User CODEC transmit ready flag DM(user_tx_ready) User CODEC receive buffer DM(user_rx_buf)
0x030FFF0D
User CODEC receive ready flag DM(user_rx_ready)
When writing code, user needs define variables that they linked these exact locations defined monitor kernel that your code access kernel codec buffers. this scheme passing audio data user algorithm written include following file (found buffers.asm) your code: TITLE: BUFFERS.ASM BUFFERS.ASM Links variables into same locations kernel uses that demo talk kernel codec isr*/ .GLOBAL .GLOBAL .GLOBAL .GLOBAL .GLOBAL .GLOBAL .GLOBAL _user_tx_buf; _user_tx_ready; _user_rx_buf; _user_rx_ready; _user_data_out_ptr; _user_num_data; _user_data_type;
.SEGMENT/DM seg_bnk3; make buffers line same kernel
.var _user_tx_buf[6]; .var _user_tx_ready; .var _user_rx_buf[6]; .var _user_rx_ready; .ENDSEG; Note that these variables have leading underscore make them C-compatible. writing assembly code, include following segment within data variable declaration section same assembly codec file code: .SEGMENT/DM seg_bnk3; .VAR user_tx_buf[6]; .VAR user_tx_ready; Codec (set kernel) flags buffers .VAR user_rx_buf[6]; .VAR user_rx_ready; .ENDSEG; addition variable declaration, users needs tell linker place these variables specified monitor kernel program locations codec bank This done including following lines Linker Description File: MEMORY seg_bnk3 TYPE(DM RAM) START(0x030FFF00) END(0x030FFFFF) WIDTH(32) PROCESSOR SECTIONS seg_bnk3 INPUT_SECTIONS( $OBJECTS(seg_bnk3) $LIBRARIES(seg_bnk3)) >seg_bnk3 This ensures that linked variables reside follows: DM(user_tx_buf) placed addresses 0x030FFF00 0x030FFF05 DM(user_tx_ready) placed address 0x030FFF06 DM(user_rx_buf) placed addresses 0x030FFF07 0x030FFF0C DM(user_rx_ready) placed address 0x030FFF0D
examples these codec variables declared linked together with ADSP-
21065L EZ-KIT Lite assembly programs, user inspect source files EZ-KIT Lite audio demos.
3.3.4 Programming AD1819 Indexed Control Registers
monitor program provides setup routine AD1819. Table shows registers used their state after reset. user monitor buffers contained demo programs write their code AD1819 codec. code must initialize these registers when using AD1819. example programs further documentation AD1819 programming with ADSP-21065L, visit site www.analog.com/dsp.
Table Programming AD1819 Indexed Control Registers Address 0x06 0x0E 0x10 0x1C 0x20 0x78 0x7A Index Register Name Master Volume Mono Microphone Volume Line Volume Record Gain General Purpose Sample Rate Sample Rate #define Label 2106x program MASTER_VOLUME_MONO MIC_VOLUME LINE_IN_VOLUME RECORD_GAIN GENERAL_PURPOSE SAMPLE_RATE_GENERATE_0 SAMPLE_RATE_GENERATE_1 State 0x8000 0x8008 0x8808 0x0F0F 0x8000 0xBB80 0xBB80
3.3.5 EMAFE Programming
Communicating with EMAFE done through either SPORTs, through indexed addressing. read write memory EMAFE, memory should written address 0x0100 0000. After writing address, data read from written address 0x0100 0001. Multiple reads, writes, executed without rewriting address. Because timings ADSP-21065L, address hold cycle must added cycles communicate with EMAFE.
This done WAIT register ADSP-21065L guarantees that data remains valid when line goes high (invalid). this done, data address written EMAFE stored correctly.
stated previous section, must connected +3.3VCC SPORT1 used EMAFE AD1819 will contend with EMAFE's operation.
DEMONSTRATION PROGRAMS
Overview
This chapter describes loading running demonstration programs supplied with ADSP-21065L EZ-KIT Lite board. demos designed VisualDSP++ Debugger which supplied that shipped with this product. detailed information debugger features operation, VisualDSP++ Debugger Guide Reference Debugger Tutorial (for ADSP-2106x Family DSPs).
Starting VisualDSP++ Debugger
After VisualDSP++ software license have been installed, click Windows Start menu. Select Programs VisualDSP++ Debugger from Start menu. debugger interface appears. From Session menu, select Session. Target Selection dialog appears. Configure debug session shown Figure click
Figure Target Selection Dialog
Target Message dialogue will appears.
Figure Target Message
Press Reset button evaluation board. LEDs light after brief delay seconds) LEDs turn except FLAG9 power LEDs. Make sure that LEDs turn (except FLAG9 power LEDs) before click During this delay, POST tests which verify operation RAM, AD1819, UART, EPROM. After LEDs dark, message opens with message shown Figure 4-3.
Figure Target Communications Status Message
Click initialization completes disassembly window opens. code disassembly window EZ-KIT Lite monitor program.
Debugger Operation with ADSP-21065L EZ-KIT Lite
VisualDSP++ Debugger Guide Reference Debugger Tutorial (for ADSP-2106x Family DSPs) contains most information need operate VisualDSP++ Debugger with your EZ-KIT Lite evaluation board. Because manual written using simulator target, there some differences restrictions debugger operation that described this section.
4.3.1 Loading Programs
Because loading programs into hardware target, load process takes more time then loading simulator. Wait Load Complete message Output window before attempt debug activities.
load program, following procedure: From File menu, select Load. Open Processor Program dialog appears. Navigate folder where executable file resides. demos that supplied with EZ-KIT Lite located C:\Program Files\Analog folder. Select .dxe file click Open.
file loads message Load Complete appears Output window when load process completed.
4.3.2 Registers Memory
current values registers, Window, Refresh command. Values changed while user program running. current version VisualDSP++ Debugger does view hardware stack information.
4.3.3 Setting Breakpoints Stepping
Breakpoints last three instructions do-loop allowed, this causes improper debugger operation. Breakpoints after delayed branch instruction before branch occurs causes improper debugger operation. Using single stepping function steps through delayed branch instruction last three instructions do-loop. debugger automatically inserts breakpoints function Main(), when Settings, Main command checked, _exit instruction.
4.3.4 Resetting EZ-KIT Lite Board
EZ-KIT Lite board reset with push button switch board with Debug Reset command debugger menu bar. Both resets, clear reset chips memory debug information there will need reload programs that were running. Debug Restart command resets processor, however, processor retains debug information memory contents. following sequence must used when starting debugger: Start debugger from windows Start menu. Start Programs VisualDSP Debugger debugger starts Target message Reset Button appears Press Reset button board. Wait approximately three seconds LED's (except power FLAG9) turn off. Click message Communications Success appears.
reset button while debugger open unless debugger requests press While user load several programs into debugger during single debug session without resetting EZ-KIT Lite board, recommended reset board prior loading program.
Benchmarking Utilities
evaluation platform needs report accurate cycle count order develop efficient programs. Because monitor program running EZ-KIT Lite board intrusive, debugger's cycle counter (located status bar) does work. accurate cycle count, EZ-KIT Lite comes with benchmarking utilities. These utilities come both assembly code types. following procedures enable accurate cycle counting program. embed count_start count_end functions your code. count_start function that returns initial starting value current cycle counter. user then uses this value argument count_end function. count_end function returns total number elapsed cycles between count_start count_end. These functions completely self contained, user does need save restore processor registers. following example write these functions into your existing code.
User must program that uses this code from when function count_start(); starts, least function count_end returns without halting stepping obtain accurate cycle count.
#include "bmtools.h" clock_start, clock count; clock_start count_start(); <insert code here> clock_count count_end(clock_start);
complete code example that shows version benchmark utility, DFT_c_bm example that included Examples folder. assembly version count_start count_end functions also available. this version, insert pair function calls, start cycle count (count_start) another cycle count (count_end). elapsed number cycles stored within 48-bit wide memory location, ecount_save. These functions completely self contained, saving restoring registers necessary.
User must program that uses this code from when function count_start; starts, least function count_end returns without halting stepping obtain accurate cycle count.
Call count_start; <insert code here> Call count_end
complete code example that shows assembly version benchmark utility, DFT_assm_bm program that included Examples folder. Note, that both assembly utilities require that bmtools.dlb included Libraries statement project's (Linker Description File). more information files, refer Linker Utilities Manual ADSP-21xxx Family DSPs. Both assembly versions benchmarking utilities should operate SHARC processor. maximum number cycles that counted
Demonstration Programs
demos included with EZ-KIT Lite designed show user features capabilities VisualDSP++ Debugger ADSP-21065L DSP. demos listed executable file name described their output. demos located directory C:\Program Files\Analog EZ-KIT\Demos. more than ADSP-21065L EZ-KIT Lite Session debugger time. User EZ-KIT Lite session simulator session same time open debugger interfaces more than EZ-KIT Lite session.
4.5.1 FFT.dxe
demo performs frequency analysis analog signal presented board. Demo menu command debugger change performed. This demo maps seg_dmda into SDRAM. Therefore, added interrupts other then codec's interrupt handler, fail. more information, "ADSP-21065L Memory Map".
4.5.2 BP.dxe
demo modifies signal subjecting bandpass filter. previous demo, source signal changed through codec controls available through Settings, Codec command. demo specific control window also available change some parameters bandpass filter. Several AD1819 options also modified while demo program running. Settings Codec command, change sample rate, input gain, source (microphone input line input).
4.5.3 Pluck.dxe
pluck demo plays tune Line connector. hear output, connect powered speakers
4.5.4 Gunn.dxe
Peter Gunn demo also plays tune Line connector. hear output, connect powered speakers
4.5.5 Primes.dxe
primes demo program calculates first prime numbers staring with number sends them output window. printf function used this demo. This demo maps seg_dmda into SDRAM. Therefore, added interrupts other then codec's interrupt handler, fail. more information, "ADSP-21065L Memory Map".
4.5.6 Tt.dxe
Talk-through demo samples data from Line AD1819 board with appropriately) kHz, then sends data back Line AD1819 (J7). This demo maps seg_dmda into SDRAM. Therefore, added interrupts other then codec's interrupt handler, fail. more information, "ADSP-21065L Memory Map".
4.5.7 Blink.dxe
Blink demo program uses timer interrupt blink flag LEDs
WORKING WITH EZ-KIT LITE HARDWARE
Overview
This chapter discusses hardware design issues ADSP-21065L EZ-KIT Lite board. following topics covered: Power Supplies EPROM Operation UART EMAFE
EZ-KIT Lite board schematics available insert this manual.
System Architecture
Figure EZ-KIT Lite System Block Diagram
Enhanced Modular Analog Front (EMAFE) connector accessed through ADSP-21065L processor (16-bit parallel interface) through serial ports that connect directly processor. these serial ports shared with on-board AD1819A.
Board Layout
Figure shows layout EZ-KIT Lite board. This figure highlights locations major components connectors. Each these major components described following sections.
Figure EZ-KIT LITE Layout
5.3.1 Boot EPROM
boot EPROM provides bits program storage that loaded ADSP21065L when programmed boot from EPROM. Selection boot source controlled (Boot Memory Select) BSEL (EPROM Boot) pins. first instructions (1536 bytes) automatically loaded ADSP-21065L after reset. remaining program image must loaded program that installed those first instructions. Refer ADSP21065L SHARC User's Manual more information booting.
5.3.2 User Push-Button Switches
user input/control, there eight push-button switches EZ-KIT Lite board: RESET, FLAG RESET switch lets initiate power-on reset DSP. user loses contact between EZ-KIT Lite board while running programs, RESET button restore communication. FLAG switches toggle status four flag pins (FLAG DSP. switches send interrupts (IRQ DSP. This manually causes interrupts when executing program. IRQ0 shared with UART, IRQ1 shared with EMAFE connector.
"Flags" section Chapter more information interfacing push-button switches from programs.
5.3.3 User LED's
There flag LEDs EZ-KIT Lite board user output that available. FLAG LEDs controlled FLAG outputs labeled according flag output that controls them. "Flags" section Chapter more information interfacing user LEDs from programs.
5.3.3.1 Power
Power LED, when indicates that +3.3V used digital circuitry, present.
Power Supplies
ADP3310s generate 3.3V power required board. These parts linear regulators that also regulate current. resistor placed between pins limits amount current through device. resistance needed given maximum output current determined with equation below. 0.05/(1.5Io) Power regulation done through P-channel FET. help disperse heat from heatsink attached drain. Note that regulated voltage available heat-sink, since voltage regulated from drain FET.
minimum supply voltage ADSP-21065L 3.0V. ADM708T used monitor supply voltage holds processor reset power supply's voltage below 3.08V. board hardware also reset push button that connected this part. more information, "User Push-button Switches" section this Chapter.
5.4.1 Power Connector
power connector supplies voltages EZ-KIT Lite board. Table shows power connector pinout. user does power supply provided with EZ-KIT Lite board, replace with that connections shown Table 5-1.
Table Power Connector
Terminal
Center Outer Ring
Connection
+6.5-9.0 amps
5.4.2 European Power Supply Specifications
Table European Power Supply Specifications
VOLTAGE: CURRENT: RIPPLE: CONNECTOR: Type: Plug Size: Polarity:
7.5V (Full Load) Amps (Minimum Rating) (Max Full Load)
Switchcraft style, FEMALE (OD) (ID) (length) millimeters Center Postitive (inside terminal)
5.4.3 AD1819 Connections
When AD1819A enabled EZ-KIT Lite board, accessing audio input output jacks board possible. Each audio connectors stereo mini jacks accept standard commercially available stereo mini plugs. Microphone/Line_in Input jack connects LINE_IN_L (left) LINE_IN_R (right) pins MIC1 MIC2 AD1819A SoundPort Stereo Codec, depending setting jumpers JP2. Jumper settings explained Table 5-6. LINE Output jack connects left LINE_OUT right LINE_OUT pins codec.
5.4.4 Expansion Port Connectors
expansion port connectors provide access signals ADSP21065L. possibility these connectors, beyond debugging, host control. interrupts, signals, event signals available through this port. more information, "Expansion Connectors" section Chapter WARNING: External port loading effect external speed performance.
5.4.5 EMAFE Interface Connector
WARNING: Using EMAFE interface connector connect MAFE board damage ADSP-21065L EZ-KIT Lite, MAFE, both. Enhanced Modular Analog Front (EMAFE) connector provides standard interface connecting analog input/output daughter boards. connector female pins arranged three rows pins right angle connector. interface supports 16bit parallel data path, serial ports, interrupt output, flag input. Refer "EMAFE Expansion" section Chapter more information EMAFE interface.
5.4.6 JTAG Connector (Emulator Port)
JTAG header (Figure 5-3) connecting point JTAG in-circuit emulator probe. Note that missing (pin provide keying. socket mating connector should have plug inserted that location. EZ-KIT Lite board shipped with jumpers installed across pins These jumpers must removed before installing JTAG probe. When JTAG probe removed, care must taken replace these jumpers ensure that ADSP21065L processor initializes correctly power-up.
proper power sequence JTAG Emulator ADSP-21065L EZ-KIT Lite board remove power, reverse order.
Figure JTAG Connector With Jumpers Installed
Figure shows locations configuration jumpers EZ-KIT Lite board which jumpers pin. These jumpers should checked before using board ensure proper operation. Each jumper selection blocks described following sections.
Jumpers
5.5.1 Boot Mode Selection Jumper
jumper (JP6) controls behavior ADSP-21065L processor when system reset (from power when RESET button used). When jumper connected GND, removed, processor boots from EPROM. jumper connected GND, processor attempts boot from host interface (through expansion port).
Table Boot Mode Selection
Other
Description HOST boot EPROM boot (factory default)
5.5.2 EPROM Size Selection Jumpers
EZ-KIT Lite supports 128K 256K 512K EPROMs, each which selectable through jumpers JP5. EPROM socket originally populated with 256K EPROM. different EPROM used, should adjusted accommodate different size. Table shows pins that jumpers should connected
Table EPROM Size Selection
3.3Vcc 3.3Vcc
3.3Vcc 3.3Vcc
Description 128K 256K (factory default) 512K Used
5.5.3 Processor Jumpers
During typical operation EZ-KIT Lite board, there only single system. Jumpers should checked guarantee that board configured single processor system. case where second processor attached board through expansion connectors, these jumpers should changed configure EZ-KIT Lites' ADSP-21065L processor processor processor multiprocessor system. debug monitor will properly boot from EPROM configured single processor. System configuration options shown Table 5-5.
Table Processor Selection
Other Other
Other Other
Description Single Processor (factory default) Processor Processor INVALID
5.5.3.1 Line Selection Jumpers
EZ-KIT Lite uses single stereo phone jack line microphone. select between functions. valid settings these jumpers shown Table 5-6.
Table Line Selection
Line Line
Line Line
Description Microphone INVALID INVALID Line
5.5.3.2 AD1819 Codec Selection Jumper
SPORT1 shared between AD1819 EMAFE interface. Jumper disables drive capability AD1819 SPORT1 lines, thereby preventing contention between devices. When SPORT1 used EMAFE device EMAFE device installed, should connected ground, enabling AD1819.
Table AD1819 Codec Selection
3.3VCC
Description EMAFE selected (AD1819 disabled) AD1819 selected (factory default)
EPROM Operation
EPROM shipped with EZ-KIT Lite 256K EPROM. socket accommodate 128K 256K 512K EPROM. these other EPROMS used, jumpers should changed route correct signals EPROM. Settings these jumpers shown Table 5-4.
EPROM addressing differs, depending silicon revision ADSP-21065L your EZKIT Lite board. revision silicon, EPROM addressing begins address 0x020000. revision greater, addressing begins address 0x000000 (i.e. memory space, Figure 5-4).
5.6.1 Designers Note
When removed connected GND, ADSP-21065L initialized boot from EPROM. this board, line used control wait states.
Figure EPROM Address (256K example)
UART
UART used part; therefore, 74LVTH245 used translate data coming from UART required 3.3V logic needed processor.
5.7.1 Designers Note
access UART correctly, relationship between timing data, chip select, read/write lines needed changed. Most these changes were implemented through CPLD. additional 10ns delay needed control lines. Since this delay possible through CPLD, digital delay added circuit. important note that UART CPLD only decode subset available address lines. Because this partial decoding, UART aliased throughout address space.
EMAFE
indexed addressing required EMAFE interface implemented through CPLD. CPLD controls loading address, well data direction data bus. with UART, address only partially decoded. aliasing seen with UART also exists with EMAFE interface address space. ADSP-21065L, data valid when line goes high. address hold cycle enabled WAIT register), data stays valid through transition. parallel communication between ADSP-21065L processor evaluation board EMAFE consists some control logic control lines (MC, etc.), 8-bit latch that stores address information (MA[7:0]) transceiver buffer data lines (MD[15:0]). address lines latched data lines buffered reduce digital noise EMAFE board. serial ports from ADSP-21065L directly wired EMAFE connector interface pins. Level shifting serial port signals from ADSP-21065L required (non 3.3V compliant) peripherals EMAFE board, from peripherals EMAFE board 3.3v (non tolerant) ADSP-21065L. information EMAFE pins, "EMAFE Expansion" Chapter
AD1819
with UART, AD1819 device. prevent over driving SPORT lines ADSP-21065L, lines from AD1819 buffered through 74LVT125. This buffer additional purpose bypassing AD1819's control SPORT1, when SPORT1 required EMAFE. This done prevent contention between devices SPORT1 lines. power AD1819 reads SDATA_OUT signal line. high floating, AD1819 enters test mode. prevent AD1819 from entering this mode, pull down resistor been added line.
5.10 SDRAMS
processor's SDRAM interface enables transfer data from synchronous DRAM (SDRAM) 2xCLKIN. synchronous approach coupled with 2xCLKIN frequency supports data transfer high throughput-up Mbytes/sec. inputs sampled outputs valid rising edge clock SDCLK. Table lists describes processor's SDRAM pins their connections.
Table SDRAM connections
Type I/O/Z
Description SDRAM Column Address Select pin. Connect SDRAM's buffer pin. SDRAM Data Mask pin. Connect SDRAM's buffer pin. processor drives this high during reset, until SDRAM started.
Memory select lines external memory bank configured SDRAM. Connect SDRAM's (chip select) pin.
SDA10
I/O/Z
SDRAM Address Select pin. Connect SDRAM's pin. SDRAM pin. SDRAM interface uses this retain control SDRAM device during host requests. Connect SDRAM's pin.
SDCKE SDCLK0 SDCLK1 SDWE
I/O/Z O/S/Z O/S/Z I/O/Z
SDRAM Clock Enable pin. Connect SDRAM's pin. SDRAM SDCLK0 output pin. Connect SDRAM's pin. SDRAM SDCLK1 output pin. Connect SDRAM's pin. SDRAM Write Enable pin. Connect SDRAM's buffer pin.
Input; Output; Synchronous; Hi-Z
There SDRAM chips EZ-KIT Lite board connected MS3. They configured accessed parallel, providing bits external data memory, starting address 0x3000000. ADSP-21065L uses address line bank select. Additionally, ADSP21065L separate address line (line SDRAM, since this line used during refresh. This allows refresh occur while another data transfer runs data bus. Chapter "SDRAM Interface" ADSP-21065L SHARC User's Manual more information SDRAM controller.
5.11 Timing Diagrams
Figure EMAFE Write Cycle Timing Parameter Definitions
Figure EMAFE Write Cycle Timing Diagram
Figure EMAFE Read Cycle Timing Parameter Definitions
Figure EMAFE Read Cycle Timing Diagram
Expansion Connectors
Overview
expansion connectors provide access ADSP-21065L's interface pins. These pins user watch data transmissions. addition, host interface, interrupt, pwm_event pins also available this connector.
Table Expansion Connectors Connector (J2) Name DGND DGND DGND DGND Name Connector (J4) Name DGND DGND DGND DGND Name
DMAR2 DMAG2
PWM_EVENT0 PWM_EVENT1
IRQ0 IRQ2
IRQ1
EXT_CLK
Table 6-1. Expansion Connectors (Cont.)
Connector (J2) Name DGND Name
Connector (J4) Name DGND DGND DGND Name
DGND
REDY RESET DMAG1
SBTS DMAR1
EMAFE Expansion
WARNING: Using EMAFE interface connector connect MAFE board damage ADSP21065L EZ-KIT Lite, MAFE, both. This section describes Enhanced Modular Analog Front (EMAFE) Daughter Card interface ADSP-21065L digital signal processor evaluation board. EMAFE interface includes additional signal definitions capabilities ADSP-21065L processor. EMAFE allows upgrade path evaluating present future codec's ADC's (18xx, AD7xxx, multimedia codec, etc.) with ADSP21065L evaluation board. Only analog front will placed daughter board. Each EMAFE daughter board will have back plate allow different input connections (i.e. jack, speaker out, etc.). daughter board attached ADSP-21065L evaluation board single right angle mounted male connector mechanical standoffs give stability entire arrangement when daughter board evaluation board attached. evaluation board right angle mounted female connector. signal lines that need routed EMAFE daughter board from evaluation board should kept minimum reduce noise. Signals routed EMAFE daughter board from ADSP-21065L evaluation board defined below. Please note, Analog Devices does provide daughter board, user must design this board.
Figure Physical Layout ADSP-21065L evaluation board EMAFE daughter board
EMAFE Signal Description: EMAFE connector routes following signals from evaluation board EMAFE daughter board. Data lines. Address lines. Parallel Control lines. Synchronous Serial Port lines. Interrupt output. Flag input.
EMAFE connector also following power connections routed from ADSP-21065L evaluation board EMAFE daughter board.
Table Evaluation Board Power Connections VDD1 VDD2 Power Connection Digital power +5V, mA). Digital power +3.3V, mA).
EMAFE connector provides standard interface connecting analog input/output daughter boards. connector pins arranged three rows pins. pinout given Table description each pins listed alphabetically Tables through 6-6.
Table EMAFE Connector DGND VDD2 DGND MD10 VDD1 MD12 MD14 MFLAG DGND DGND VDD1 TXCLK0 TFS0 TXD0 DGND TXCLK1 TFS1 TXD1 DGND VDD1 VDD2 DGND VDD1 DGND VDD1 DGND DGND VDD2 CLK_OUT CHN_IN DGND DGND VDD1 DGND VDD2 DR0B DT0B DR1B DT1B VDD1 DGND DGND MD11 VDD1 MD13 MD15 MIRQ DGND DGND VDD1 RXCLK0 RFS0 RXD0 DGND RXCLK1 RFS1 RXD1
6.2.1 EMAFE Connector Interface Signal Descriptions
Table EMAFE Connector Interface Signal Description NAME DGND VDD2 DGND MD10 VDD1 MD12 MD14 MFLAG DGND DGND MRD* VDD1 TXCLK0 TFS0 TXD0 DGND TXCLK1 TFS1 TXD1 DESCRIPTION Digital Ground Used +3.3 Digital Power Used Used Parallel Data (BUFFERED ADSP-21065L D16) Parallel Data (BUFFERED ADSP-21065L D18) Parallel Data (BUFFERED ADSP-21065L D20) Digital Ground Parallel Data (BUFFERED ADSP-21065L D22) Parallel Data (BUFFERED ADSP-21065L D24) Parallel Data (BUFFERED ADSP-21065L D26) Digital Power (5v) Parallel Data (BUFFERED ADSP-21065L D28) Parallel Data (BUFFERED ADSP-21065L D30) Flag Input Digital Ground Used Parallel Address (LATCHED ADSP-21065L D17) Parallel Address (LATCHED ADSP-21065L D19) Digital Ground Parallel Address (LATCHED ADSP-21065L D21) Parallel Address (LATCHED ADSP-21065L D23) Module Read (Asserted Low) Digital Power (5v) Transmit Clock, Port Transmit Frame Sync, Port Transmit Data, Port Digital Ground Transmit Clock, Port Transmit Frame Sync, Port Transmit Data, Port
Table EMAFE Connector Interface Signal Description NAME DGND VDD1 VDD2 DGND VDD1 DGND VDD1 DGND DGND VDD2 CLK_OUT CHN_IN DGND DGND VDD1 DGND VDD2 DR0B DT0B DR1B DT1B DESCRIPTION Digital Ground Digital Power (5V) Digital Power (3.3V) Used Digital Ground Digital Power (5V) Used Used Digital Ground Used Used Used Digital Power (5v) Used Digital Ground Used Digital Ground Digital Power (3.3v) CODEC Chain Clock CODEC Chain Input Digital Ground CODEC Digital Ground CODEC Digital Power (5V) Digital Ground Used Digital Power (3.3V) ADSP-21065L I2S, SECONDARY DATA RECEIVE SIGNAL ADSP-21065L I2S, SECONDARY DATA TRANSMIT SIGNAL ADSP-21065L I2S, SECONDARY DATA TRANSMIT SIGNAL ADSP-21065L I2S, SECONDARY DATA RECEIVE SIGNAL
Table EMAFE Connector Interface Signal Description NAME VDD1 DGND DGND MD11 VDD1 MD13 MD15 MIRQ* DGND MCS* MWR* VDD1 RXCLK0 RFS0 RXD0 DGND RXCLK1 RFS1 RXD1 DESCRIPTION Digital Power (5V) Used Used Digital Ground Used Parallel Data (BUFFERED ADSP-21065L D17) Parallel Data (BUFFERED ADSP-21065L D19) Parallel Data (BUFFERED ADSP-21065L D21) Digital Ground Parallel Data (BUFFERED ADSP-21065L D23) Parallel Data (BUFFERED ADSP-21065L D25) Parallel Data (BUFFERED ADSP-21065L D27) Digital Power (5v) Parallel Data (BUFFERED ADSP-21065L D29) Parallel Data (BUFFERED ADSP-21065L D31) Interrupt Output (Asserted Low) Parallel Address (LATCHED ADSP-21065L D16) Parallel Address (LATCHED ADSP-21065L D18) Parallel Address (LATCHED ADSP-21065L D20) Digital Ground Parallel Address (LATCHED ADSP-21065L D22) Module Select (Asserted Low) Module Write (Asserted Low) Digital Power (5v) Receive Clock, Port Receive Frame Sync, Port Receive Data, Port Digital Ground Receive Clock, Port Receive Frame Sync, Port Receive Data, Port
Reference
Overview
This chapter reference VisualDSP++. Because debugger dynamic, menu selections, commands, dialogs change depending target being used. This chapter provides information menu selections, commands, dialogs when target ADSP21065L evaluation board. other debugger commands, VisualDSP++ Guide Reference. Note that grayed commands unavailable with this target.
Settings Menu Commands
commands that pertain EZ-KIT Lite board contained Settings Demo menus. Settings menu provides access following commands:
Figure Settings Menu Commands
7.2.1 Test Communications
Tests EZ-KIT Lite communications. Responses Communications Success various error messages sent Output window. most cases resetting EZ-KIT Lite reestablishes communication.
7.2.2 Baud Rate
Sets baud rate port. Choices 9600, 19200, 38400, 57600, 115200. default rate 115200. Once change made, resetting needed subsequent debug sessions. Using baud rate 9600 causes EZ-KIT Lite operate very slowly also cause hang.
7.2.3 Comm Port
Selects communications port EZ-KIT Lite board. Choices Comm(1-4).
7.2.4 Codec
Sets several options codec operation. These commands are: Update Updates refreshes menu changes selected. Sample Rate Opens Sample Rate dialog (Figure that lets select sample rate from 7000 48000
Figure Sample Rate Dialog
Source Choose Microphone Line
Figure Source Setting
Gain Select Select gain from 22.5 increments
Demo Menu Commands
Demo menu command-Demo Control. This command opens dialog that lets user change several operating functions demos. Figure shows dialog that accompanies demo. Select Demo Control command demo which dialogs, error message that says "This demo does require user input" will appear. Click continue with demo.
Figure Demo Dialog
Table Demo Dialog Description Dialog Field Source Domain Description Select source FFT; codec random number generator. Splits original using following methods: (Decimation Time) (Decimation Frequency) Window Scaling filter Fourier transform. Scaling refers much data captured while running. Dynamic Scaling snapshot current high (limits) (activity). Cumulative Scaling shows activity over time (limits) (activity).
Figure Bandpass Demo Controls Dialog
dialog fields Bandpass demo follows: Input Source Select input from AD1819, noise from DSP. Filter Range Change filter applied demo.
APPENDIX RESTRICTIONS CPLD CODE LISTING
following restrictions apply configuration level release 2.01 ADSP-21065L evaluation board. information ADSP-21065L silicon anomalies, anomaly sheet that accompanied this product. Breakpoints last three instructions do-loop allowed, cause your code incorrectly. Breakpoints after delayed branch instruction before branch occurs causes your code incorrectly. Using single stepping function three instructions do-loop. steps through delayed branch instruction last
host loses contact with monitor while user program running user program disables UART interrupt changes UART interrupt vector. host loses contact with monitor while program running when nesting turned off. host loses contact with monitor while program running timer ISR, provided highest priority timer vector used. current version EZ-KIT monitor does view hardware stack information. reset button while debugger open unless debugger requests to.This will cause debugger crash. IMDW0 SYSCON register must keep communication with host. IMDW0 determines data accesses made block 48-bit three column accesses 32-bit column accesses (0). monitor program requires three column data accesses memory block IMDW0 monitor accesses incorrect memory locations within block (See User's Manual further discussion IMDW0).
setting IMDW0 will have effect C-programming long RND32 floating point precision. more than ADSP-21065L EZ-KIT Lite session debugger time. EZ-KIT Lite session simulator session same time open debugger interfaces more than EZ-KIT Lite session.
product documented describes debugger's Settings, Codec Sample Rate menu command follows: "Opens Sample Rate dialog that lets select sample rate from 7000 48000 Hz." default sample rate 48000. change sample from this setting. need change sample rates your program, will need write your CODEC driver. Information doing this provided Chapter ADSP-21065L EZ-KIT Lite Evaluation System Manual.
CPLD File
Listing shows Cypress WARP file used program CPLD board. CPLD CY7371i-83AC, which 32-macrocell CPLD with in-circuit programmability. functions performed are: Extends EPROM read cycles (board silicon revision only). access cycles used ADSP-21065L when booting, short EPROM; therefore, CPLD deasserts line long enough extend cycle appropriate time EPROM. Translates read write cycles into cycles that appropriate UART. timing requirements between chip select, read/write lines, data accesses different between ADSP-21065L UART. CPLD corrects these differences. Additionally, there minimum time restraint between subsequent access UART. CPLD accounts this needed time delay. Translates ADSP-21065L read write cycles into cycles appropriate EMAFE.
Listing
CPLD File
Copyright(c) 1998 Analog Devices, Inc. Rights Reserved Revision History 05/26/98 Original 05/27/98 inverted output ack_bar Allows addition open collector buffer added 05/29/98 Changed address UART 08/15/98 Locked pins prevent changes next rev.s 09/22/98 Changed functionality (driven only when needed) Added Codec reset functionality 09/28/98 Changed functionality Codec Reset (1usec low) 21065L.VHD library ieee; ieee.std_logic_1164.all; work.std_arith.all; entity interface port reset addr std_logic; std_logic; asynchronous reset Clock input Note: line only driven when needed. When codec reset written, codec_rst line goes 1usec. Addresses: UART: EMAFE_Address: EMAFE_Data: CODEC_RESET: VHDL code CPLD ASPL-21065L evaluation board
std_logic_vector(3 down std_logic;
wr_bar, rd_bar, cs_bar
bms_bar
std_logic;
Wait (EPROM) input UART Outputs EMAFE Outputs CODEC Reset
u_en_bar, u_rd_bar, u_wr_bar e_cs_bar, e_rd_bar, e_wr_bar, e_addr codec_rst_bar avoiding programming contol pins
std_logic; std_logic; std_logic; std_logic);
attribute pin_avoid interface:entity 33"; Need lock numbers, prevent accidental changes attribute pin_numbers interface:entity "reset:26 clk:7 wr_bar:29 rd_bar:9 cs_bar:15 "addr(3):11 addr(2):12 addr(1):14 addr(0):27 "bms_bar:10 u_en_bar:30 u_rd_bar:32 u_wr_bar:22 "ack:18 e_cs_bar:36 e_rd_bar:23 e_wr_bar:24 e_addr:37 "codec_rst_bar:8 interface; architecture state_machine interface type StateType (IDLE, CS1, CS2, WR1, WR2, WR3, WR4, WR_D1, ENDW1, ENDW2, ENDW3, ENDW4, CS3, CS4, CS5, CS6, RD1, RD2, RD3, RD4, ENDR1); signal present_state, next_state StateType; signal u_ack std_logic; signal generated from UART signal u_ack_v std_logic; UART valid signal signal w_ack signal w_ack_v std_logic; signal generated from EPROM std_logic; EPROM valid signal signal uart_ctrl_d: std_logic_vector(2 downto (u_rd_bar_d, -u_en_bar_d, u_wr_bar_d) control signals WAIT6); signal present_wstate, next_wstate WAIT_STATE; begin next state uart type WAIT_STATE (WAIT0, WAIT1, WAIT2, WAIT3, WAIT4, WAIT5,
-UART Control logic cs_bar, rd_bar, wr_bar, addr) variable std_logic; variable std_logic;
variable std_logic; begin rd_bar; wr_bar; cs_bar; case present_state when IDLE u_ack '1'; u_ack_v '0'; ((cs '1') ((rd '1') (std_match(addr, "001-"))) then Proceed only next_state CS1; addressed rd/wr else next_state IDLE; when u_ack '1'; u_ack_v '0'; ((cs '1') ((rd '1') (std_match(addr, "001-"))) then Proceed only next_state CS2; -else next_state IDLE; when u_ack '0'; u_ack_v '1'; '1') then next_state WR1; else next_state CS3; when u_ack '0'; u_ack_v '1'; next_state WR2; when =>u_ack '0'; u_ack_v '1'; next_state WR3; when u_ack '0'; u_ack_v '1'; next_state WR4; when u_ack '0'; u_ack_v '1'; next_state WR_D1; when WR_D1 u_ack '0'; u_ack_v '1'; next_state ENDW1; Continue Write Cycle Continue Write Cycle Continue Write Cycle Continue Write Cycle Continue Write Cycle Read cycle Write cycle Signal extended cycle Improper cycle addressed rd/wr needed; clarity
when ENDW1 u_ack '0'; u_ack_v '1'; next_state ENDW2; when ENDW2 u_ack '0'; u_ack_v '1'; next_state ENDW3; when ENDW3 u_ack '0'; u_ack_v '1'; next_state ENDW4; when ENDW4 u_ack '1'; u_ack_v '1'; next_state IDLE; when u_ack '0'; u_ack_v '1'; next_state CS4; when u_ack '0'; u_ack_v '1'; next_state CS5; when u_ack '0'; u_ack_v '1'; next_state CS6; when u_ack '0'; u_ack_v '1'; next_state RD1; when u_ack '0'; u_ack_v '1'; next_state RD2; when u_ack '0'; u_ack_v '1'; next_state RD3; when u_ack '0'; u_ack_v '1'; next_state RD4; when u_ack '1'; u_ack_v '1'; next_state ENDR1; when ENDR1 u_ack '1'; u_ack_v '1'; next_state IDLE; case; process uart_state; with next_state select uart_ctrl_d "111" when IDLE, "101" when CS1, "101" when CS2, "100" when WR1, Read Cycle Continue Read Cycle Continue Read Cycle Continue Read Cycle Continue Read Cycle Continue Read Cycle Continue Read Cycle Continue Read Cycle Continue Read Cycle Write Cycle Continue Write Cycle Continue Write Cycle Continue Write Cycle
"100" when WR2, "100" when WR3, "100" when WR4, "101" when WR_D1, "111" when ENDW1, "111" when ENDW2, "111" when ENDW3, "111" when ENDW4, "101" when CS3, "101" when CS4, "101" when CS5, "101" when CS6, "001" when RD1, "001" when RD2, "001" when RD3, "001" when RD4, "101" when ENDR1, when others; -State/Reset Control state_clocked:process(reset, clk) begin (reset '1') then present_state IDLE; u_rd_bar '1'; u_en_bar '1'; u_wr_bar '1'; present_wstate WAIT0; elsif rising_edge(clk) then present_state next_state; u_rd_bar uart_ctrl_d(2); u_en_bar uart_ctrl_d(1); u_wr_bar uart_ctrl_d(0); present_wstate next_wstate; process state_clocked; when (reset '1') else (u_ack w_ack) when ((u_ack_v '1') (w_ack_v '1')) else 'Z'; -EMAFE Control logic Generate Control buffering data from EMAFE interface UART State UART State UART State UART State Wait State UART State UART State UART State UART State Wait State
e_rd_bar rd_bar; e_wr_bar wr_bar; e_cs_bar when ((addr "0001") (cs_bar '0')) else '1'; e_addr when ((addr "0000") (cs_bar '0')AND (wr_bar '0')) else '1';
-Wait Generator EPROM Delay accesses EPROM since will access MHz. wait_state: process(rd_bar, bms_bar, present_wstate)- State selection control variable std_logic; variable std_logic; begin rd_bar; bms_bar; case present_wstate when WAIT0 ((bms '1') '1')) then Check EPROM w_ack '0'; w_ack_v '1'; next_wstate WAIT1; else w_ack '1'; w_ack_v '0'; when WAIT1 w_ack '0'; w_ack_v '1'; next_wstate WAIT2; when WAIT2 w_ack '0'; w_ack_v '1'; next_wstate WAIT3; when WAIT3 w_ack '0'; w_ack_v '1'; next_wstate WAIT4; when WAIT4 w_ack '0'; w_ack_v '1'; next_wstate WAIT5; Continue Delay Continue Delay Continue Delay Continue Delay ignore Delay
when WAIT5 w_ack '0'; w_ack_v '1'; next_wstate WAIT6; when WAIT6 w_ack '1'; w_ack_v '1'; next_wstate WAIT0; case; process wait_state;
Continue Delay
Release Delay
-Codec Reset cdc_rst: process(clk, addr, cs_bar, reset) variable cdc_cnt: std_logic_vector(4 downto begin (reset '1') then cdc_cnt (others '0'); codec_rst_bar '0'; elsif (rising_edge(clk)) then (cdc_cnt "00000") then cdc_cnt cdc_cnt codec_rst_bar '0'; else codec_rst_bar '1'; else cdc_cnt cdc_cnt codec_rst_bar '0'; process cdc_rst; end; counter started increment counter Reset codec reset reset counter pass reset codec otherwise (key rising edge) counter hasn't started
((addr "0100") (cs_bar '0')) then check reset Start counter Reset codec reset hold reset high
CODEC controls, reference buffer.asm .ldf files provided with demos. These files provide access necessary variables overlapping locations variables.
APPENDIX BILL MATERIALS
Item
C60, C62, C74, C75, C91, C92, C95, C105, C119, C122, C124, C127, C129, C130, C134, C135
Part Desc
SMT0805
Specification Ceramic, 10%, T&R,
Manufacturer/Source:P/N AVX: 08055E103KATMA Panasonic: ECU-1H103KBG
C11, C13, C22, C24, C38, C42, 0.01uF
C109, C110 C114, C115 C139, C140, C141, C142 C15, C77, C79, C82, C85, C87, C89, C112, C113 C16, C17, C20, C47, C51, C57, C69, C97, C98, C99, C100, C111, C120, C126, C133, C138
100pF 10uF
SMT0805 SMT0805 SMT0805 SMT1812 EIA3216
Ceramic, Ceramic, Ceramic, Ceramic, 20%, Tantalum, 10%,
Digi-Key: PCC220CNCT-ND Panasonic: ECU-V1H220JCN Digi-Key: PCC271CGCT-ND Digi-Key: PCC101CGCT-ND Panasonic: ECU-V1H101JCG AVX: 18125C105MAT2A Kemet: T491A106K010AS
C39, C117 C44, C49, C50, C54, C81, C59, C64, C65, C66, C67, C68, C10, C12, C14, C18, C19, C21, C23, C25, C37, C40, C41, C43, C45, C46, C48, C52, C53, C58, C61, C63, C70, C71,
0.047uF
SMT1206 SMT0805 SMTX SMT0805 SMT0805 EIA3216 SMT0805
Z5U, 10%, Ceramic, NPO, Ceramic, Tantalum, T&R, Z5U, 20%,
Digikey: PCC473BCT-ND Panasonic: ECU-V1Hr73KBW Digi-Key: PCC221CGCT-ND
Tantalum, ESR, 20%, Kemit: T494X107K020AS Digikey: PCC270CGCT-ND Panasonic: ECU-V1H270JCG Digi-Key: PCC470CGCT-ND AVX: TAJA105K016R Digi-Key: PCT3105CT-ND Allied: 231-1294 Murata: GRM40Z5U104M050BL
C72, C73, C93, C94, C96, C101, C102, C103, C104, C106, C107, C108, C116, C118, C121, C123, C125, C128, C131, C132, C136, C137 C78, C80, C88, C83, FB3, FB13 FB4, FB5, FB6, FB7, FB8, FB9, FB10, FB11, FB12 HQ1, JP1, JP2, JP3, JP4, JP5, JP6, JP7, Heat Sink TO-263AB 2.5mm Jack CON7x2M CON30x2M DB9F CON5x2M CON32x3F CON7M CON3M .100 .100 .100 .100 .100 Conduction through Drain AAVID: 573300D00010 Male, Angle Male Male Fem. Angle PCB, grounding board locks Male Breakaway Female Right Angle 3.5mm, 500VDC, horizontal Male Male, Kycon: KLD-SMT-0202-B Samtec: TSW-17-07-T-D Samtec: TSW-130-07-T-D Keltron: DNR-09SCJB-SG Kycon: K22-E9S-NJ Molex: 10-89-1101 Samtec: SSW-132-T-02-T-T-RA Switchcraft: 35RAPC4BHN2 Samtec: TSW-17-07-T-S Samtec: TMM-103-01-S-S-SM 1000 0.33 LED-Green Rectifier SMT0805 SMT3216 SMT, Gull Wing SMT0805 D0-214AA Z5U, 10%, Tantalum, 20%, Current, Diffused, T&R, 2mA, Ultra Bright Red, 20mA, Max. fv=1.15V 1.0A, 2ADC, 2.0uSec, Common Mode Choke Coil Filter Filter SMT1206 0.06 Ohm-DC, 1.5A, 50Vdc (EIA 2020 pkg) 0.025 Ohm-DC, Bead Inductor, Murata: BLM31P500S Murata: BLM11A601SPB Murata: PLM250S40B1 Microsemi: Panasonic: LNJ208R8ARAF Digikey: PCC102BNCT-ND Digikey: PCS6334CT-ND Panasonic: ECS-T1VY334R HLMP-7040
STEREO JACK
R11, R13, R16, R18, R28, R30, R33, R19, R20, R21, R22, R23, R24, R34, R36, R42, R44, R35, R37, R43, R38, R39, R52, R27, R29, R31, R32, R47, R48, R49, R50, R51, R57, R64, R72, R75, R78, R79,
PMOS 5.1K 1.5K
TO-263AB SMT0805 SMT0805 SMT0805 SMT0805 SMT0805 SMT0805 SMT0805 SMT0805 SOP-16 SOP-16 SMT0805 SMT0805
P-channel MOSFET, 60W, 24A, -20V Thick Film, Thick Film, 1/10
Fairchild: NDB6020P Digi-Key: P39ACT-ND Panasonic: ERJ-6GEY/J390 Digi-Key: P100ACT-ND Panasonic: ERJ-6GEYJ101
Thick Film, 1/10 Bourns: CR0805-911-JVCA Thick Film, 1/10 Bourns: CR0805-102-JVCA Panasonic: ERJ-6GEYJ102 Thick Film, 1/10 Thick Film, 1/10 Thick Film, 1/10 Thick Film, 1/10 Isolated, Bussed, Digi-Key: P47KACT-ND Allied: 297-9552 Digi-Key: P20KACT-ND Digi-Key: P5.1KACT-ND Digi-Key: P1.0MACT-ND CTS: 767-163-R33 Digikey: 767-163-R33-ND CTS: 767-161-R10K Digikey: 767-161-R10K-ND Thick Film, 1/10 Bourns: CR0805-152-JVCA Thick Film, 1/10 Bourns: CR0805-103-JVCA Panasonic: ERJ-6GEYJ103
R10, R12, R14, R15, R17, R26,
SJP1, SJP2, SJP3, SJP4, SJP5, SJP6, SJP10, SJP11 SJP7, SJP8
0.025 0.05 SHUNT2 SHUNT2
SMT1206 SMT1206
SMT, SMT, Open Top, Gold Plating Open Handle Momentary SPST (washable)
Dale: WSL1206R025FB25 Dale: WSL1206R050FB25 Samtec: 2SN-BK-G AMP: 881545-1 C&K: KT11P2JM
SW1, SW2, SW3, SW4, SW5, SW6, SW7, SWITCH
HEADER .100 Voltage Regulator Silicon Delay Line 74LVCH162 TSSOP-48 16-pin SOIC SO-8
Male, single 10A, 3.3V Triple, 10-ns delay, 2ns, 5.0V
Samtec: TSW-101-07-L-S Analog Devices: ADP3310AR-3.3 Dallas Semi: DS1013S-10
16-Bit Xcvr, Hold, IDT: IDT74LVCH16245APA Tolerant, +/-24 1.5-4.1 Phillips: 74LVCH16245A
Audio OpAmp 74LCX574
8-Pin SOIC TSSOP-20
Dual Single Supply (+4V +36V)
Analog Devices: SSM2135S
Octal Edge Trigg Flip-Flops Fairchild: 74LCX574MTC 3-State puts, 5VTolerant, +/-24 1.5-8.5 Motorola: MC74LCX574DT
SoundPort Codec 74LCX125
48-pin TQFP TSSOP-14
Compliant, 5.0V Quad buffers 3-state outputs, Hold, 5VTolerant, +/-24 1.5-6.0
Analog Devices: AD1819A Fairchild: 74LCX125MTC Motorola: MC74LCX125DT
U19,
EPROM SHARC SDRAM Voltage Regulator
32-pin 208-pin PQFP 50-pin TSOP SO-8
EPROM (256Kx8), 200ns, 3.3V Processor, 60MHz, 3.3V SDRAM 16Mb (1Mx16), 83MHz, 3.3V 10A,
SGS: M27V201-200F6 Macronix: MX27L2000 DC-20 Analog Devices: ADSP-21065L KS240X Micron: MT48LC1M16A1TG S-10 NEC: uPD4516161AG5-A10 Analog Devices: ADP3310AR-5
Voltage Monitor 8-pin SOIC
uProcessor Supervisor, 200ms, Analog Devices: ADM708TAR 3.3V
U11,
74LCX14 ADM232A PC16550DV 74LPT245
TSSOP-14 Narrow SOIC-16 PLCC-44 SOP-20
Schmitt Trigger Inverter, 5VTolerant,
Fairchild: 74LCX14MTC Toshiba: 74LCX14FT
RS232 Driver/Receiver, Analog Devices: ADM232AARN UART, FIFOs, 1.5M baud, National Semi: PC16550D Octal Transceiver Digikey: PI74LPT245AS-ND Hold, 5V-Tolerant, +32/-64 1.0-4.0 Pericom: PI74LPT245AS Phillips: N74F06D
74F06 32-Macro cell CPLD 18.432 24.576 30.0
SOP-14 44-Pin TQFP 4-Pin DIP-8
Open collector inverter, 3.5ns,
In-Circuit Programmable, 5.0V, Cypress: CY7C371i-83AC 75mA, 12ns, 5.0V/3.3V Crystal, Parallel, ppm, 18.432MHz Crystal, Parallel, ppm, 24.576MHz Oscillator, ppm, 30.0 MHz, 3.3V Machine M-Tron: M3A14FAD30.0000 SaRonix: NCH089B-30.0000 Andon: 101-632-01S-P29 Augat: 832-AG12D-ES Allied: 217-4165 Russel: BUT-4165 Epson: MA-505-24.576M-C2 Epson: MA-505-18.432M-C2
Socket, DIP-32 DIP-32 Button Bumper Rubber
APPENDIX SCHEMATICS
DMAR2# DMAG2#
FLAG[4.9]
+3.3Vcc
CODEC_ON#
FLAG[0.3]
+3.3Vcc +3.3Vcc DR0A DR0B RXCLK0 RFS0 DT0A DT0B TXCLK0 TFS0 DR1A DR1B RXCLK1 RFS1 DT1A DT1B TXCLK1 TFS1 PROM_CS#
+3.3Vcc
+3.3Vcc
Host Boot EPROM Boot Shunt
+3.3Vcc
PWM_EVENT0 PWM_EVENT1
DMAR1# DMAG1#
FLAG0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG7 FLAG8 FLAG9 MFLAG
IRQ0# IRQ1# IRQ2#
SDA10 RAS# CAS# SDWE# SDCKE SDCLK0
SDCLK0 SDCKE SDWE# CAS# RAS# SDA10 +3.3Vcc
CPA#
Jumper3 SJP6
Initially
BTDI
SJP7 SJP8
SBTS#
TRST BTRST CLKIN EZ-ICE BTCK BTMS
Shunt Shunt
RESET#
When used jumper pins
TRST
FLAG0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG7 FLAG8 FLAG9 FLAG10 FLAG11
DMAR1 DMAG1
DMAR2 DMAG2
RESET
DT1A DT1B TCLK1 TFS1
DT0A DT0B TCLK0 TFS0
SBTS
PWM_EVENT0 PWM_EVENT1
SDA10 SDWE SDCKE SDCLK0 SDCLK1
DR1A DR1B RCLK1 RFS1
DR0A DR0B RCLK0 RFS0
BSEL
IRQ0 IRQ1 IRQ2
+3.3Vcc
+3.3Vcc
BMSTR
VDD32 VDD31 VDD30 VDD29 VDD28 VDD27 VDD26 VDD25 VDD24 VDD23 VDD22 VDD21 VDD20 VDD19 VDD18 VDD17 VDD16 VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 VDD0
10uF
ADSP-21065L
REDY
XTAL2
CLKIN
GND36 GND35 GND34 GND33 GND32 GND31 GND30 GND29 GND28 GND27 GND26 GND25 GND24 GND23 GND22 GND21 GND20 GND19 GND18 GND17 GND16 GND15 GND14 GND13 GND12 GND11 GND10 GND9 GND8 GND7 GND6 GND5 GND4 GND3 GND2 GND1 GND0
0.1uF
0.01uF
C118
C119 10uF
C120
+3.3Vcc
0.1uF
0.1uF
0.1uF
0.01uF
0.01uF
C121
C122
C123
C124
C125
0.01uF
C126
C127
DSP_CLK
Single Processor Processor Processor INVALID
A[0.23] +3.3Vcc D[0.31]
MS0# MS1# MS2# MS3# MS0# MS1# MS2# MS3# BR1# BR2# HBR# REDY# BR1# BR2#
Initially both should installed Shunt SJP11 Designed Paragon Innovations, email: info@paragon-t x.com Title Size ADSP-21065L Proc. Main Documen Number 65-000299- (1125-01-001-0201) Approved Sheet
SJP10
Devices, Inc. Tech nology Way. Norwood, 02062
HBR# HBG# REDY#
Shunt
Date nesday, November 1998 Drawn Kris Stafford Filename {Filename}
EMAFE_CS# +3.3Vcc Vcc1 Vcc2 Vcc3 Vcc4 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 1DIR 2DIR MD10 MD11 MD12 MD13 MD14 MD15
EMAFE_RD# D[0.15] +3.3Vcc
Bypass Caps
+3.3Vcc
0.1uF
0.01uF
EMAFE_ADDR +3.3Vcc
0.01uF
0.1uF
+3.3Vcc
Bypass Caps
0.01uF C105 0.1uF C106
MD[0.15]
74LVTH16245A
74LVT574
U11F CHAIN_CLK CHAIN_IN CODEC_CS0 CODEC_CS1 EMAFE_CS# EMAFE_RD# EMAFE_WR# TXCLK0 RXCLK0 TFS0 RFS0 DT0A DR0A DR0B DT0B TXCLK1 RXCLK1 TFS1 DR1B RFS1 DT1A DT1B DR1A MD15 MD13 MD14 MD12 MD11
IRQ1#
ADSP-21065L must programmed Hold Time Cycle proper operation this circuit
MA[0.7]
74LCX14
74F06
MD10
SPORT0
MFLAG
+5Vcc +5Vcc
+3.3Vcc
SPORT1
+5Vcc
+3.3Vcc
+5Vcc
RXD1 DT1B TXD1 RFS1 DR1B TFS1 RXCLK1 DT0B TXCLK1 DGND DR0B DGND RXD0 VDD2 TXD0 RFS0 TFS0 RXCLK0 DGND TXCLK0 VDD1 VDD1 VDD1 DGND DGND DGND DGND CHN_IN CLK_OUT VDD2 DGND DGND DGND MIRQ MFLAG MD15 DGND MD14 MD13 MD12 VDD1 VDD1 VDD1 MD11 MD10 DGND DGND DGND VDD1 DGND DGND VDD2 VDD2 VDD1 VDD1 DGND DGND
Devices, Inc. Tech nology Way. Norwood, 02062
Designed Paragon Innovations, email: info@paragon -tx.com Title EMAFE Size ADSP-21065L FE-CODEC Documen Number 65-000299- (1125-01-001-0201) Approved Sheet
nesday, November 1998 Date Drawn Kris Stafford Filename {Filename}
A[0.19] SDA10 MS3# +3.3Vcc DQMH DQML Vcc0 Vcc1 Vccq0 Vccq1 Vccq2 Vccq3 Vss0 Vss1 Vssq0 Vssq1 Vssq2 Vssq3 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
SDA10 MS3# RAS# CAS# SDWE# SDCKE SDCLK0
should adjusted depending size EPROM.
Non-schematic Component
Sock EPROM
128K 256K 512K Used
Rev.s ADSP-21065L begin accessing EPROM 0x020000. Later Rev.s begin 0x000000. ensure that EPROM will work with revisions place code both places.
PROM_CS# M27V201 +3.3Vcc C128 0.1uF +3.3Vcc
MT48 LC1M16A1
SJP4 SJP5
SDA10 MS3# +3.3Vcc DQMH DQML Vcc0 Vcc1 Vccq0 Vccq1 Vccq2 Vccq3 Vss0 Vss1 Vssq0 Vssq1 Vssq2 Vssq3 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
Shunt Shunt +3.3Vcc Jumper3 Jumper3
PROM_CS#
MT48 LC1M16A1
D[0.31] +3.3Vcc Devices, Inc. Tech nology Way. Norwood, 02062
0.01uF
0.01uF
C129
C130 0.1uF
C131 0.1uF
C132 10uF
C133
+3.3Vcc
Designed Paragon Innovations, email: info@paragon -tx.com Title Size ADSP-21065L Memory Documen Number 65-000299- (1125-01-001-0201) Approved Sheet
0.01uF
0.01uF
C134
C135 0.1uF
C136 0.1uF
C137 10uF
C138
Date nesday, November 1998 Drawn Kris Stafford Filename {Filename}
+3.3Vcc +3.3Vcc 10uF 0.1uF 0.1uF 0.1uF 10uF 0.01uF 0.01uF 0.1uF 0.1uF 0.01uF 0.01uF 0.1uF Ferrite Bead 0.047uF 0.01uF +5Vcc +3.3Vcc 74LCX14 U21B 74LCX14 +3.3Vcc +5VA 0.1uF +5Vcc 0.1uF PLD_CLK
U21A DSP_CLK
30.0000MHz
used minimize noise board where 5Vcc crosses +3.3Vcc plane.
U21C 74LCX14 EXT_CLK
U21D
U21E
U21F
Heat sink
3.3V, 1.0A
573300 center Jack VIN_1 VIN_2 PLM250S40 100uF 0.01uF 0.025 0.1uF 10uF NDB6020P
74LCX14 +3.3Vcc 0.01uF
74LCX14
74LCX14
+3.3Vcc
+3.3Vcc PUSHB UTTON1 ADM708T RESET RESET RESET#
Gate
Vout
ADP3310-3.3
Heat sink
5.0V, 0.5A
Locate Ferrite Bead across voltage split plane
+5VA +5Vcc 0.1uF 10uF 0.1uF 10uF Devices, Inc. Tech nology Way. Norwood, 02062
573300 0.05 NDB6020P
Ferrite Bead
Rubber Foot
Rubber Foot
Gate
Rubber Foot Rubber Foot
Vout
Designed Paragon Innovations, email: info@paragon -tx.com Title Size ADSP-21065L PWR/RST Documen Number 65-000299- (1125-01-001-0201) Approved Sheet
ADP3310-5.0
Date ursday, November 1998 Drawn Kris Stafford Filename {Filename}
EMAFE UART-CPLD A[0.5] D[0.7]
D[0.15] EMAFE_WR# EMAFE_RD# EMAFE_CS# EMAFE_ADDR EMAFE_WR# EMAFE_RD# EMAFE_CS# EMAFE_ADDR
CODEC_RST# PROM_CS* MS1# PLD_CLK PLD_CLK UART-CPLD IRQ1# MFLAG TFS0 DT0A DT0B TXCLK0 RFS0 DR0A DR0B RXCLK0 TFS1 DT1A DT1B TXCLK1 RFS1 DR1A DR1B RXCLK1 A[0.19] D[0.31] PROM_CS# MS3# SDA10 RAS# CAS# SDWE# SDCKE SDCLK0 Memory TFS0 DT0A DT0B TXCLK0 RFS0 DR0A DR0B RXCLK0 TFS1 DT1A DT1B TXCLK1 RFS1 DR1A DR1B RXCLK1 CODEC_ON# Proc. Main RESET# Devices, Inc. Tech nology Way. Norwood, 02062 EMAFE DT1A TXCLK1 RFS1 DR1A RXCLK1 CODEC_ON# Codec CODEC_RST# IRQ0#
A[0.23] D[0.31] MS0# MS1# MS2# MS3# FLAG[0.3] FLAG[4.9] PWM_EVENT0 PWM_EVENT1 HBR# HBG# REDY# SBTS# CPA# BR1# BR2# IRQ0# IRQ1# IRQ2# FLAG[0.3] FLAG[4.9] IRQ0# IRQ1# IRQ2# FLAG[0.3] FLAG[4.9] MFLAG PWM_EVENT0 PWM_EVENT1 HBR# HBG# REDY# SBTS# CPA# BR1# BR2# DMAR1# DMAG1# DMAR2# DMAG2# A[0.23] D[0.31] PROM_CS# MS0# MS1# MS2# MS3# SDA10 RAS# CAS# SDWE# SDCKE SDCLK0 A[0.23] D[0.31]
CHAIN_CLK CHAIN_IN CODEC_CS0 CODEC_CS1
CHAIN_CLK CHAIN_IN CODEC_CS0 CODEC_CS1
Codec
EXT_CLK RESET#
DMAR1# DMAG1# DMAR2# DMAG2#
PWR/RST EXT_CLK DSP_CLK PLD_CLK
DSP_CLK RESET# PLD_CLK
PWR/RST
Designed Paragon Innovations, email: info@paragon -tx.com Title Size ADSP-21065L {Page Title} Documen Number 65-000299- (1125-01-001-0201) Approved Sheet
Date nesday, November 1998 Drawn Kris Stafford Filename {Filename}
+5Vcc
0.1uF
0.1uF
A[0.5] 0.1uF
0.01uF
BAUDOUT RCLK OUT1 OUT2 SOUT UART_RD# UART_WR# +5Vcc 0.1uF +3.3Vcc UART_EN# 18.432MHz 1.5K XOUT PC16550 INTR TXRDY DDIS RXRDY +5Vcc 0.1uF C1C2+
Ferrite Bead 0.1uF Ferrite Bead Female
D[0.7] UART_RD# UART_EN# +3.3Vcc
+5Vcc
C2T1_IN T2_IN R1_OUT R2_OUT ADM232A T1_OUT T2_OUT R1_IN R2_IN
RTS# CTS#
Ferrite Bead Ferrite Bead
74LPT245A
added reduce emissions since 3.3V logic talking part. Place close signal lines
74F06
IRQ0#
Keep this trace away from connector
+3.3Vcc
27pF
47pF
74F06 +3.3Vcc +5Vcc PROM_CS* +5Vcc MS1# PLD_CLK +5Vcc SMODE ISRVPP SCLK 5.0Vcc HEADER +5Vcc +3.3Vcc Vccio CY7C371i Vccint RESET ISRen SMODE SCLK UART_WR UART_RD UART_EN EMAFE_WR EMAFE_RD EMAFE_CS EMAFE_ADDR CODEC_RST NC10 NC11 NC12 NC13 NC14 CODEC_RST# EMAFE_WR# EMAFE_RD# EMAFE_CS# EMAFE_ADDR OUT1 OUT2 OUT3 UART_WR# UART_RD# UART_EN# 0.01uF 0.1uF
A[0.5]
+5Vcc
DS1013S 0.01uF 0.1uF
Devices, Inc. Tech nology Way. Norwood, 02062
Designed Paragon Innovations, email: info@paragon -tx.com Title Size ADSP-21065L CPLD Documen Number 65-0000299- (1125-01-001-0201) Approved Sheet
Date nesday, November 1998 Drawn Kris Stafford Filename {Filename}
D[0.31]
+3.3Vcc
General purpose LEDs
0.1uF 10uF MS0# MS3# HBR# REDY# BR2# RESET# DMAG1# MS1# MS2# HBG# SBTS# BR1# CPA# DMAR1# FLAG[0.3] 74LCX14 FLAG0 Green Green Green Green Green Green
+3.3Vcc
+3.3Vcc
+3.3Vcc
+3.3Vcc
+3.3Vcc
+3.3Vcc
PUSHB UTTON1 +3.3Vcc
0.1uF 10uF PUSHB UTTON1
U11A FLAG1 FLAG[4.9] FLAG4 FLAG5 FLAG6 FLAG7 FLAG8 FLAG9
74LCX14 +3.3Vcc
Power
+3.3Vcc
U11C 74LCX14 +3.3Vcc +3.3Vcc U11E FLAG3 +3.3Vcc +3.3Vcc FLAG2 U11D 74LCX14
PUSHB UTTON1 +3.3Vcc
+3.3Vcc
HEADER 30X2
Expansion
A[0.23] PWM_EVENT0 IRQ0# IRQ2# DMAR2# DMAG2# PWM_EVENT1 IRQ1# EXT_CLK
PUSHB UTTON1
74LCX14
74LCX14 +3.3Vcc +3.3Vcc +3.3Vcc 74LCX14 +5Vcc 74F06 +3.3Vcc +5Vcc +3.3Vcc +3.3Vcc
74LCX14
74LCX14
0.01uF
IRQ0#
PUSHB UTTON1
+3.3Vcc
0.1uF
10uF
0.1uF
0.1uF
0.1uF
10uF 0.1uF
+3.3Vcc
IRQ1# +3.3Vcc
PUSHB UTTON1
74LCX14
74F06
HEADER 30X2
U11B
Devices, Inc. Tech nology Way. Norwood, 02062
Expansion
IRQ2#
PUSHB UTTON1
74LCX14
74F06 Title Size
Designed Paragon Innovations, email: info@paragon -tx.com ADSP-21065L MAFE Switches Documen Number 65-000299- (1125-01-001-0201) Approved Sheet
Date ursday, November 1998 Drawn Kris Stafford Filename {Filename}
0.01uF
0.01uF
+3.3Vcc
Bypass Caps
0.01uF
0.1uF +5Vcc +5Vcc 10uF C102 0.1uF 10uF C103 0.1uF 10uF C104 0.1uF PC_BEEP LINE_IN_R CODEC_RST# RESET SDATA_OUT MIC1 SDATA_IN MIC2 SYNC BIT_CLK LINE_IN_L 220pF 220pF U13A SSM2135 0.33uF U13B SSM2135 +5VA
Line Circuit
CODEC_ON#
+5VA C100
EMAFE Interface uses SPORT1 (AD1819 used)
SJP3 +3.3Vcc +3.3Vcc Shunt
10uF C101 0.1uF
Place C82, C85, R39, close possible
DVSS2
DVSS1
AVSS1
DVDD1
AVSS2
AVDD2
DVDD2
AVDD1
+5VA 5.1K Vref 5.1K
SJP2
SJP1
Shunt
Shunt
DR1A RXCLK1 TXCLK1
Microphone/Line
FB12 Ferrite Bead FB11 Ferrite Bead 100pF C139 ONEJACK STEREO C140 100pF
AD1819A
CD_R CD_L CD_GND VIDEO_R VIDEO_L AUX_R
0.33uF
74LCX125
DT1A RFS1 CODEC_CS0
Microphone Circuit
VREFOUT
Digital Analog ground planes connect through single point, through FB13, which should placed close AD1819A.
FB13 Ferrite Bead
AUX_L PHONE
Place FB9, FB10, close possible
FB10 Ferrite Bead Ferrite Bead C141 100pF C142 100pF
CODEC_CS1 CHAIN_IN CHAIN_CLK
Line
CHAIN_IN MONO_OUT CHAIN_CLK LINE_OUT_R XTL_IN LINE_OUT_L AFILT2 FILT_R FILT_L AFILT1 RX3D CX3D XTL_OUT
PHONEJACK STEREO
24.576MHz C109 22pF 22pF +3.3Vcc 0.1uF C107 +5Vcc
VREF
C108 270pF 270pF C110 10uF Vref 0.1uF C116 47nF C111 0.1uF C117 C112 C113 C114 C115
Devices, Inc. Tech nology Way. Norwood, 02062
added reduce emissions since 3.3V logic talking part. Place close signal lines
Designed Paragon Innovations, email: info@paragon -tx.com Title Size ADSP-21065L CODEC Documen Number 65-000299- (1125-01-001-0201) Approved Sheet
ursday, November 1998 Date Drawn Kris Stafford Filename {Filename}
INDEX
ADSP-21065L interrupts Analog Front AD1819. Bandpass demo dialog Baud Rate command baud rate settings. Benchmarking example. Blink.dxe. with EPROM. board features. BP.dxe. Break Points/Single Step. Check/Initialization Code listings CPLD file CODEC analog front buffer initialization. hardware specifications slot mode. schemes Codec command. Codec Sample Rate dialog CODEC Transmissions data packets. Comm Port command. Commands Baud Rate. Codec Comm Port Demo menu Test Communications. Computer resources EZ-LAB board Contents package CPLD Equations Customer support data packets. using CODEC transmissions Debugger starting. Default Settings EZ-LAB Demo menu commands Demo programs overview. Demonstration programs bandpass filter Blink. FFT. Peter Gunn theme. Pluck Primes Demonstration Programs. Dialogs Bandpass demo Codec Sample Rate demo. transfers. Electrostatic Discharge. EMAFE Issues EMAFE Programming EPROM operation. EPROM tests. Error codes POST routine ESD. European power specifications. EZ-KIT LITE board layout EZ-LAB default settings features. demo dialog. FFT.dxe. FLAG pins FLAG0-3. FLAG12 FLAG4-10. FLAG11 Gunn.dxe. Hardware devices CODEC CPLD equations
EMAFE EPROM. power supplies. SDRAM UART. Hardware installation IMASK register. Installing EZ-KIT LITE hardware Installing EZ-KIT LITE software. Interrupts IRQ0. IRQ1. memory SDRAM Memory checks Memory Memory select lines MODE2 register. monitor program components Monitor program components. command processing halt loop Package contents Configuration Pluck.dxe. POST errors POST routines. Power Self Test Power Supplies. Power supply specifications European Power-on reset. Primes.dxe. Programming EMAFE. Registers IMASK. MODE1. MODE2.
Resetting board. SDRAM SDRAM data mask SDRAM interface data transfer rate. features. definitionsSee SDRAM interface definitions SDRAM memory SDRAM pins. SDRAM interface definitions Selecting target. Serial communication. SLOT-16 mode Software installation. SPORTs Standard Operation Starting debugger Static discharge Supply current Supply voltage. synchronous serial ports Target selection. Technical support. Test Communications command Timing changes Transfers CODEC Tt.dxe UART aliasing UART Check/Initialization Internal Loop Back. register write transmitted loop back UART segment UART specifications. VisualDSP. Voltage supply.
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