S5T8809 S5T8809 superior low-power-programmable frequency synthes
|
|
|
Top Searches for this datasheet
FREQUENCY SYNTHESIZER PAGER
S5T8809
S5T8809 superior low-power-programmable frequency synthesizer which used high performance Simple application Wide Area Pager system. S5T8809 consists kinds divider block including 19-bit Shift register, 16/18-bit Latch, 13/15bits R-counter 16/18-bit NCounter, 32/33 Prescaler, phase detector block including Phase detector, Lock detector Charge pump. S5T8809 also battery saving mode which control each register block serial control data from µ-controller (MICOM) also boosts signal output fast locking.
16-TSSOP-0044
Magnification
FEATURES
Maximum operating frequency: 330MHz 300mVP-P, VDD1 1.0V, VDD2 3.0V On-chip reference oscillator supports external crystal which oscillates 23MHz Superior supply current: FFIN 310MHz, IDD1 0.8mA (Typ.) VDD1 1.0V, VDD2 3.0V Operating voltage: VDD1 0.95 1.5V VDD2 3.3V Excellent Divider range: Ref. Divider: (0): 65528 (Multiple): Default (1): 32767 Divider: (0): 1056 65535: Default (1): 1056 262143 Boost-up signal output Fast Locking Standby mode, VDD1 block controlled status Standby current consumption: 10µA (Max.) Programmable control output reduce internal noise Programmable 19-bit shift register value controlled Charge pump output circuitry passive filter Package type: 16-TSSOP (0.65mm)
ORDERING INFORMATION
Device S5T8809X01-R0B0 Package 16-TSSOP-0044 Operating Temperature -25°C +75°C
S5T8809
FREQUENCY SYNTHESIZER PAGER
BLOCK DIAGRAM
OSCI OSCO VDD1 VDD2
Prescaler
Divider counter
Schmitt Trigger
Lock Detector
VDD2
18Bit Latch (Test1. LDC) Schmitt Trigger Phase Detector Charge Pump
DATA
Shift Register
Fast Lock
18Bit Latch
Schmitt Trigger
VDD1 VDD1 32/33 Prescaler Swallow Counter Main Counter
Schmitt Trigger
FREQUENCY SYNTHESIZER PAGER
S5T8809
CONFIGURATION
OSCI OSCO VDD2 VDD1
TEST DATA
KS8809D
S5T8809
S5T8809
FREQUENCY SYNTHESIZER PAGER
DESCRIPTION
Symbol OSCI OSCO VDD2 VDD1 Description These input output pins generate reference frequency. case OSCI Pin, external reference frequency used through coupling. highest potential supply terminal that supplied 3.3V. Booster signal output fast locking. output phase detector terminal passive loop filter. There 3-kinds output signal states according loop error. Ground terminal Input terminal frequency from VCO. Output frequency from inputted through coupling Voltage supply terminal Oscillator block. This supplied 0.95 1.5V from VSS. This input programmable control which Schmitt Trigger architecture, Internally biased pull-up. High Bits N-Divider (Default: ND15) Bits N-Divider (ND0 ND7) R-divider bits will changed program output phase detector controlled R-counter register. When R-counter Low, output will disabled reduce noise problem, High, output will enabled show lock unlock status that error width between Ref. signal output signal. These pins controlled µ-controller which Schmitt Trigger architecture, Internally biased pull-down. features these pins follows; Clock input 19-bit Shift Register, Serial data input include TEST1, LDC), Latch enable input. mode (set Low), VDD1 block will powered off, internal latch data still valid because VDD2 supplied continuously. This input Schmitt Trigger architecture internally biased pull-up. This input Fast Locking Control (FLC) which Schmitt Trigger architecture, Internally biased pull-down. Current Charge pump output Normal (Default: High Current Charge pump output increase 1.5) This input TEST which Schmitt trigger architecture, Internally biased Pull-down. block will operated normal state (Default) High state will TEST mode
DATA
TEST
FREQUENCY SYNTHESIZER PAGER
S5T8809
ABSOLUTE MAXIMUM RATINGS
Characteristic Supply Voltage Input Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VDD1 VDD2 TOPR TSTG Value -0.3 +4.0 -0.3 +125 Unit
ELECTRICAL CHARACTERISTICS
25°C, VDD1 1.0V, VDD2 3.0V, unless otherwise specified) Characteristic Operating voltage Symbol VDD1 VDD2 Operating current Test Conditions FOSCI 12.8MHz FFIN 310MHz 0.3VP-P VDD1 1.0V, VDD2 3.0V, BSB=High VDD1 0.0V, VDD2 3.0V, BSB=Low VDD1, High High VFIN 0.3VP-P, VDD1 1.0V VOSCI 0.3VP-P, VDD1 1.0V 0.4V VDD2 0.4V 0.4V VDD2 0.4V Min. 0.95 Typ. Max. Unit
Standby current Input voltage (DATA, CLK, Input voltage (TEST, PBC) Input current (Fin, Xin) Input frequency
ISB1 FFIN FOSCI IOH1 IOL1 IOH2 IOL2
VDD2-0.3 VSS1-0.2
12.8
Output current (PDO, Output current (LD) Setup-time (DATA-CLK, CLK-EN) Hold time
S5T8809
FREQUENCY SYNTHESIZER PAGER
FUNCTIONAL DESCRIPTION
Table N-Counter Register Program Scheme bit) Name Description Function N-Counter Data Program Data bits will valid bits will valid Program Mode Control N-Counter Program Ref. R-Counter Program (LSB)
16/18 N_Counter
N_Counter Divider Data ND17
DATA
1'st INPUT positive edge triggered
Figure Counter Register Programming Timing Programmable N-counter consists 5-bits Swallow Counter, Dual modulars Prescaler 11-bits Main Counter [PBC than 13-bits Main Counter) Divide Ratio Dual Modular Prescaler (32) 5-bits Swallow Counter value 11-bits (PBC High, 2047) 13-bits (PBC Low, 8291) Programmable N-Counter value Main Counter controlled pin, when (pin state Low, Programmable N-counter range will extend 262143
FREQUENCY SYNTHESIZER PAGER
S5T8809
case 16-bits program [PBC High], 325.300MHz, Multiplier 75.975MHz [Fin Freq. Ref. Freq.] 75.975MHz 6.25kHz 1256
Main bits
Swallow 5-bits
NOTE: According above equation, 12156 32(P) 379, left that means, Swallow value "11100", Main value "379"
case 18-bits program [PBC Low], 330MHz [Fin Freq. Ref. Freq.] [330MHz 6.25kHz] 52800
Main bits Swallow 5-bits
NOTE: program mode control bit, [0], N-counter will enabled
Table R-Counter Register Program Scheme bits) Name Description Ref. R-Counter Data Lock Detector Control Frequency Reference Control R_CNT div. R_CNT div. (15bit) TEST TEST mode control Mainly product Test (LSB) Program mode control Program Program
Function
Disable Programmable Ref. R-Counter bits (RD12 RD0) Enable bits (RD14 RD0)
Input Reference Frequency (X-tal Oscillator) will divided Prescaler, then divided preprogrammed R-counter value once more. Programmable R-Counter consists Fixed Prescaler, 15-bits Programmable Counter When Fixed Prescaler 13-bits counter (Min. Divide value: enabled 65528 [Multiple When Fixed Prescaler disabled, using 15-bits counter (Min. Divide value: 32767 [All value]
S5T8809
FREQUENCY SYNTHESIZER PAGER
CONTROL MODE R-COUNTER REGISTER State Normal Operation Description function independent other Control
R-Counter Value R_cnt value (OSCI bits R-Counter R-cnt value (OSC bits R-Counter
Description function independent other Control
TEST1
TEST
state Normal Normal (N-CNT) (N-CNT)
state Normal Normal High state Normal
Description independent other control Test internal register control but, Test external control Test related with Test, when Test High Test Mode
13/15 R-Counter, LDC, FRC, TEST1
R_Counter Divider Data RD14 FRCTEST1 DATA
1'st INPUT positive edge triggered
Figure Ref. R-Counter Register Programming Timing
FREQUENCY SYNTHESIZER PAGER
S5T8809
case 13bits Program, Fosc 12.8MHz prescaler used [(Osc. Freq. Prescaler) Ref. Freq.] [(12.8MHz 6.25kHz]
TEST1 counter bits
case 15bits Program, Fosc 12.8MHz prescaler used [Osc. Freq. Ref. Freq.] [12.8MHz 6.25kHz] 2048
counter bits
TEST1
NOTE: Program Mode Control Bit, [1], R-Counter will Enabled
OSCI 12.8MHz 12.8MHz X-Tal
Prescaler
1.6MHz
13/15 bits Counter
6.25kHz
Figure architecture R-Count Divider
S5T8809
FREQUENCY SYNTHESIZER PAGER
DATA
Figure Serial DATA Input Timing
FREQUENCY SYNTHESIZER PAGER
S5T8809
PHASE DETECTOR LOCK DETECTOR
OSCI
Divider
OSCO
Lock Detector
Phase Detector
32/33 Counter
Divider
Figure Phase Detector Lock Detector
Z-State
VDD1
Z-State
Fast Lock Operation Window Window width OSCI
Figure Phase Detector Lock Detector Fast Lock Output Waveforms
NOTES: Phase detector always compares Phase difference N-counter with R-counter, generates High State much phase difference output level same Phase detector error width
S5T8809
FREQUENCY SYNTHESIZER PAGER
FAST LOCK Fast lock gives faster Acquisition time when S5T8809 starts Fast Lock signal generated time, this circuitry operate again even though goes into unlock state. S5T8809 Fast lock; control Loop band width Loop filter, other control charge pump current. Mode Mode
During operation,
Phae Detector
Charge Pump
Fast Lock Phase Det.
Fast Lock Charge Pump Ref. clock
Ref. clock
CP1: Default charge pump output CP2: When High, goes [On] state, Timming Phase just same signal Mode does used pin, only increase output current same width 1'st phase error
Exceeding Loop Band width during Fast Lock operation When High level, this function will available
FREQUENCY SYNTHESIZER PAGER
S5T8809
Counter output Counter output
Vdd2 Z-state
Ref.
Vdd2
Z-state Vdd2
Time (FLC High)
Z-state
Figure
S5T8809
FREQUENCY SYNTHESIZER PAGER
NOTES
Other recent searches
TSM2N60 - TSM2N60 TSM2N60 Datasheet
ST7571 - ST7571 ST7571 Datasheet
LO494PBL4-B0G - LO494PBL4-B0G LO494PBL4-B0G Datasheet
CP-64-6 - CP-64-6 CP-64-6 Datasheet
CC1070 - CC1070 CC1070 Datasheet
8516980211 - 8516980211 8516980211 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
