CMOS SDRAM 8Mx16 Mobile SDRAM 54CSP (VDD/VDDQ 2.5V/1.8V 2.5V

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CMOS SDRAM 8Mx16 Mobile SDRAM 54CSP (VDD/VDDQ 2.5V/1.8V 2.5V

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K4S28163LD-RF/R
CMOS SDRAM
8Mx16 Mobile SDRAM 54CSP
(VDD/VDDQ 2.5V/1.8V 2.5V/2.5V, TCSR PASR)
Revision February 2002
Rev. Feb. 2002
K4S28163LD-RF/R
Revision History
Revision (December 2000, Preliminary)
First generation 128Mb Power SDRAM 2.5V, VDDQ 1.8V).
CMOS SDRAM
Revision (February 2001, Preliminary)
Fixed below order adjust Power SDRAM characteristics. 2.5ns 1.0ns 133MHz, 3.0ns 1.5ns 100MHz, 4.0ns 2.0ns 66MHz. Fixed 1.44V. Addition Latency
Revision (April 2001, Preliminary)
Part number change from K4S28163LD-RG/SXX K4S28163LD-RF/RXX order define -25'C temperature range semi-extended temperature TCSR option support.
Revision (April 2001, Target)
Changed tRCD from 22.5ns 20ns, order cover 100MHz, 2-2-2 characteristics 133MHz, 3-3-3 part.
Revision (June 2001, Target)
Changed device name from power sdram mobile sdram.
Revision (Jul 2001, Preliminary)
Changed tSAC from 6.5ns case part, from 7.5ns case part. Changed from 2.5ns. Changed min. from 1.44V 0.8xVDDQ min. from 1.6V DDQ.
Revision (October 2001, Preliminary)
Changed current. Changed tSAC from part. Changed tSAC from tSAC from 8ns, tSAC from 18ns 20ns part. Changed tSAC from tSAC from 9ns, tSAC from 22ns 24ns part. Changed from 2.5ns. Changed from 2.5ns 2.0ns part from 3.0ns 2.5ns part, from 4.0ns 3.5ns part. Integration VDDQ 1.8V device 2.5V device. Change from 0.8xVDDQ 0.9xVDDQ from 0.9xVDDQ 0.95xVDDQ. Integration PASR part TCSR part.
Revision (Feb. 2002, Final)
Final Specification. Changed from 0.9xVDDQ 0.8xVDDQ, from 0.95xVDDQ 0.9xVDDQ from 0.95xVDDQ 0.9xVDDQ. Changed tRDL from 2CLK 10ns -75/-1L part from 2CLK 15ns part. Changed tDAL from 2CLK+tRP tRDL+tRP.
Rev. Feb. 2002
K4S28163LD-RF/R
16Bit Banks Mobile sDRAM 54CSP
FEATURES
2.5V power supply. LVCMOS compatible with multiplexed address. Four banks operation. cycle with address programs. latency Burst length Full page). Burst type (Sequential Interleave). EMRS cycle with address programs. inputs sampled positive going edge system clock. Burst read single-bit write operation. Special Function Support. PASR (Partial Array Self Refresh). TCSR (Temperature Compensated Self Refresh). masking. Auto refresh. 64ms refresh period cycle). Commercial Temperature Operation(-25°C~70°C 54balls CSP.
CMOS SDRAM
GENERAL DESCRIPTION
K4S28163LD 134,217,728 bits synchronous high data rate Dynamic organized 2,097,152 words bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with system clock transactions possible every clock cycle. Range operating frequencies, programmable burst length programmable latencies allow same device useful variety high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Part K4S28163LD-RF/R75 Freq. 133MHz(CL=3) 100MHz(CL=2) Interface Package
K4S28163LD-RF/R1L 100MHz(CL=3)*1 LVCMOS K4S28163LD-RF/R15 66MHz(CL=2/3)*2 Super Power, Operating Temperature °C~70 Power, Operating Temperature °C~70°C Note case 40MHz Frequency, supported. case 33MHz Frequency, supported.
FUNCTIONAL BLOCK DIAGRAM
Control
Data Input Register
LDQM
Bank Select
Refresh Counter
Output Buffer
Decoder
Sense
Buffer
Address Register
Column Decoder Col. Buffer
LRAS
LCBR
Latency Burst Length
LCKE LRAS LCBR LCAS
Programming Register LWCBR LDQM
Timing Register
LDQM
UDQM
Samsung Electronics reserves right change products specification without notice.
Rev. Feb. 2002
K4S28163LD-RF/R
Package Dimension Configuration
Bottom View*1
CMOS SDRAM
View*2
54Ball(6x9)
DQ15 DQ13 DQ11
VSSQ VSSQ
VSSQ VSSQ
LDQM
DQ14 DQ12 DQ10 UDQM
Name
Function System Clock Chip Select Clock Enable Address Bank Select Address Address Strobe Column Address Strobe Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground
View
L(U)DQM /VSS /VSSQ
Max. 0.20
Encapsulant
Bottom View View*2
Ball Origin Indicator
Week
[Unit:mm] Symbol 0.90 0.30 0.40 0.95 0.35 8.00 6.40 8.00 6.40 0.80 0.45 1.00 0.40 0.50 0.08
K4S28163LD
RXXX
Rev. Feb. 2002
K4S28163LD-RF/R
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage relative Voltage supply relative Storage temperature Power dissipation Short circuit current Symbol TSTG Value -1.0 -1.0 +150
CMOS SDRAM
Unit
Note Permanent device damage occur ABSOLUTE MAXIMUM RATINGS exceeded. Functional operation should restricted recommended operating condition. Exposure higher than recommended voltage extended periods time could affect device reliability.
OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced 70°C) Parameter Supply voltage Input logic high voltage Input logic voltage Output logic high voltage Output logic voltage Input leakage current Symbol VDDQ 1.65 -0.3 Unit -0.1mA 0.1mA Note
Note (max) 3.0V AC.The overshoot voltage duration 3ns. (min) -1.0V undershoot voltage duration 3ns. input Input leakage currents include Hi-Z output leakage bi-directional buffers with Tri-State outputs. Dout disabled, DDQ.
CAPACITANCE(V 2.5V, 23°C, 1MHz, VREF =0.9V
Clock RAS, CAS, CKE, Address Symbol CADD COUT Unit Note
Rev. Feb. 2002
K4S28163LD-RF/R
CHARACTERISTICS
Recommended operating conditions(Voltage referenced 70°C)
CMOS SDRAM
Version Parameter Symbol Burst length C(min) (max), 10ns Test Condition Operating Current (One Bank Active) Precharge Standby Current power-down mode ICC1 CC2P TCSR Range Banks Self Refresh Current ICC6 0.2V Banks Bank Banks Banks Bank Notes Measured with outputs open. Refresh period 64ms. K4S28163LD-RF** K4S28163LD-RR** Unless otherwise noted, input swing IeveI CMOS(VIH /VIL SSQ) -25~45°C 45~70°C Unit Note
ICC2 (max), (min), H(min), 10ns Input signals changed time during 20ns (min), (max), Input signals stable (max), 10ns
Precharge Standby Current power-down mode
CC2NS CC3P
Active Standby Current power-down mode Active Standby Current power-down mode (One Bank Active) Operating Current (Burst Mode) Refresh Current
ICC3 (max), CC3NS ICC4 ICC5 (min), H(min), 10ns Input signals changed time during 20ns (min), (max), Input signals stable Page burst 4Banks Activated, tCCD 2CLKs (min)
Rev. Feb. 2002
K4S28163LD-RF/R
OPERATING TEST CONDITIONS(V 2.5V 0.2V,
Parameter input levels (Vih/Vil) Input timing measurement reference level Input rise fall time Output timing measurement reference level Output load condition
CMOS SDRAM
Value VDDQ tr/tf VDDQ Fig.
Vtt=0.5 VDDQ
Unit
Output (DC) DDQ, -0.1mA Output (DC) 0.2V, 0.1mA 30pF Z0=50
30pF
(Fig. Output Load Circuit
(Fig. Output Load Circuit
OPERATING PARAMETER(AC operating conditions unless otherwise noted)
Version Parameter active active delay delay precharge time active time cycle time Last data precharge Last data Active delay Last data col. address delay Last data burst stop Col. address col. address delay Symbol D(min) D(min) P(min) S(min) tRAS (max) (min) tRDL (min) tDAL (min) tCDL (min) tBDL (min) D(min) latency=3 Number valid output data latency=2 latency=1 tRDL Unit Note
Notes minimum number clock cycles determined dividing minimum time required with clock cycle time then rounding next higher integer. Minimum delay required complete write. Minimum 2CLK tDAL required complete precharge. parts allow every cycle column address change. case precharge interrupt, auto precharge read burst stop.
Rev. Feb. 2002
K4S28163LD-RF/R
CHARACTERISTICS(AC operating conditions unless otherwise noted)
Parameter latency=3 cycle time latency=2 latency=1 latency=3 valid output delay latency=2 latency=1 latency=3 Output data hold time latency=2 latency=1 high pulse width pulse width Input setup time Input hold time output Low-Z latency=3 output Hi-Z latency=2 latency=1 tSHZ tSLZ tSAC Symbol 1000 1000
CMOS SDRAM
Unit
Note
1000
Notes Parameters depend programmed latency. clock rising time longer than 1ns, (tr/2-0.5)ns should added parameter. Assumed input rise fall time 1ns. longer than 1ns, transient time compensation should considered, i.e., [(tr tf)/2-1]ns should added parameter.
Rev. Feb. 2002
K4S28163LD-RF/R
SIMPLIFIED TRUTH TABLE (V=Valid, X=Dont Care, H=Logic High, L=Logic Low)
COMMAND Register Mode Register Auto Refresh Entry Refresh Self Refresh Exit Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Bank Selection Precharge Banks Clock Suspend Active Power Down Entry Exit Entry Precharge Power Down Mode Exit Operation Command
CKEn-1 CKEn BA0,1
CMOS SDRAM
A11,
Note
CODE
Address
Column Address Column Address
Bank Active Addr. Read Column Address Write Column Address Burst Stop Auto Precharge Disable
Note Code Operand Code Program keys. (@MRS) issued only banks precharge state. command issued after cycles MRS. Auto refresh functions same refresh DRAM. automatical precharge without precharge command meant "Auto". Auto/self refresh issued only banks precharge state. Partial self refresh issued only after setting partial self refresh mode. Bank select addresses. both "Low" read, write, active precharge, bank selected. "Low" "High" read, write, active precharge, bank selected. "High" "Low" read, write, active precharge, bank selected. both "High" read, write, active precharge, bank selected. "High" precharge, ignored banks selected. During burst read write with auto precharge, read/write command issued. Another bank read/write command issued after burst. active associated bank issued after burst. Burst stop command valid every burst length. sampled positive going edge masks data-in that same write operation (Write latency read operation makes data-out Hi-Z state after cycles. (Read latency
Rev. Feb. 2002
K4S28163LD-RF/R
CMOS SDRAM
Note Samsung designed manufactured device system that used under circumstance which human life potentially stake. Please contact memory marketing team samsung electronics when considering product contained herein specific purpose, such medical, aerospace, nuclear, military, vehicular undersea repeater use.
Rev. Feb. 2002
DEVICE OPERATIONS
MODE REGISTER FIELD TABLE PROGRAM MODES
Register Programmed with Normal Address Function BA1*1 Setting Normal A10/AP A9*2 W.B.L Latency
CMOS SDRAM
Burst Length
Test Mode
Normal Mode
Test Mode Type Mode Register Reserved Reserved Reserved Latency Latency Reserved Reserved Reserved Burst Single Reserved Reserved Setting Normal Burst Type Type Sequential Interleave Mode Select Mode Burst Length BT=0 BT=1
Write Burst Length Length
Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved
Full Page Length 512(x16)
Register Programmed with Extended Address Function A10/AP PASR
Mode Select
TCSR
Extended PASR(Partial Array Self Refresh) TCSR(Temperature Compensated Self Refresh)
Mode Select Mode Normal Reserved Extended Mobile DRAM Reserved Reserved Address A10/AP Reserved TCSR Temperature Reserved PASR Banks Banks(All Banks) Banks(1/2 Banks) Bank(1/4 Banks) Reserved Reserved Reserved Reserved
Notes 1.RFU(Reserved future use) should stay during cycle. 2.If high during cycle, "Burst Read Single Write" function will enabled. 3.In case Partial Self Refresh, bank(BA1=BA0=0) selected. case Partial Self Refresh, banks(BA1=0) selected. 4.Mobile DRAM supports PASR banks(128Mb), banks(64Mb) banks(32Mb).
ELECTRONICS
DEVICE OPERATIONS
Partial Array Self Refresh
CMOS SDRAM
order save power consumption, Mobile SDRAM PASR option. Mobile SDRAM supports kinds PASR self refresh mode;4 Banks(128Mb), Banks(64Mb) Bank(32Mb).
Bank
Bank
Bank
Bank
Bank
Bank
Bank
Bank
Bank
Bank
Bank
Bank
Banks
Banks
Bank
Partial Self Refresh Area
Temperature Compensated Self Refresh
order save power consumption, Mobile SDRAM TCSR option. Mobile SDRAM supports kinds TCSR range EMRS setting.
Address
Self Refresh Current (Icc Temperature Range
Banks Banks Bank
Unit
Available
ELECTRONICS
DEVICE OPERATIONS
BURST SEQUENCE BURST LENGTH
Initial Address Sequential
CMOS SDRAM
Interleave
BURST LENGTH
Initial Address Sequential Interleave
ELECTRONICS
DEVICE OPERATIONS
DEVICE OPERATIONS
ADDRESSES 64Mb BANK ADDRESSES (BA0 BA1)
case
This SDRAM organized four independent banks 1,048,576 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
CMOS SDRAM
ADDRESSES 128Mb
BANK ADDRESSES (BA0 BA1) case
This SDRAM organized four independent banks 2,097,152 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
case
This SDRAM organized four independent banks 524,288 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
case
This SDRAM organized four independent banks 1,048,576 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
ADDRESS INPUTS A11)
case
address bits required decode 1,048,576 word locations multiplexed into address input pins addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
ADDRESS INPUTS A11)
case
address bits required decode 2,097,152 word locations multiplexed into address input pins addresses latched along with during bank activate command. column addresses latched along with CAS, during read
write command. case
address bits required decode 1,048,576 word locations multiplexed into address input pins addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
case
address bits required decode 524,288 word locations multiplexed into address input pins addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
ELECTRONICS
DEVICE OPERATIONS
DEVICE OPERATIONS
ADDRESSES 256Mb
BANK ADDRESSES (BA0 BA1) case
This SDRAM organized four independent banks 4,194,304 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
CMOS SDRAM
ADDRESSES 512Mb BANK ADDRESSES (BA0 BA1)
case
This SDRAM organized four independent banks 8,388,608 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
case
This SDRAM organized four independent banks 2,097,152 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
case
This SDRAM organized four independent banks 4,194,304 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
ADDRESS INPUTS A12)
case
address bits required decode 4,194,304 word locations multiplexed into address input pins addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
ADDRESS INPUTS A12)
case
address bits required decode 8,388,608 word locations multiplexed into address input pins addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
case
address bits required decode 2,097,152 word locations multiplexed into address input pins addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
case
address bits required decode 8,388,608 word locations multiplexed into address input pins addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
ELECTRONICS
DEVICE OPERATIONS
DEVICE OPERATIONS (continued)
CLOCK (CLK)
clock input used reference SDRAM operations. operations synchronized positive going edge clock. clock transitions must monotonic between During operation with high inputs assumed valid state (low high) duration set-up hold time around positive edge clock order function well perform specifications.
CMOS SDRAM
OPERATION
used mask input output operations. works similar during read operation inhibits writing during write operation. read latency cycles from zero cycle write, which means masking occurs cycles later read cycle occurs same cycle during write cycle. operation synchronous with clock. signal important during burst interruptions write with read precharge SDRAM. asynchronous nature
CLOCK ENABLE (CKE)
clock enable(CKE) gates clock onto SDRAM. goes synchronously with clock (set-up hold time same other inputs), internal clock suspended from next clock cycle state output burst address frozen long remains low. other inputs ignored from next clock cycle after goes low. When banks idle state goes synchronously with clock, SDRAM enters power down mode from next clock cycle. SDRAM remains power down mode ignoring other inputs long remains low. power down exit synchronous internal clock suspended. When goes high least "1CLK before high going edge clock, then SDRAM becomes active from same clock edge accepting input commands.
internal write, operation critical avoid unwanted incomplete writes when complete burst write required. Please refer timing diagram also.
MODE REGISTER (MRS)
mode register stores data controlling various operating modes SDRAM. programs latency, burst type, burst length, test mode various vendor specific options make SDRAM useful variety different applications. default value mode register defined, therefore mode register must written after power operate SDRAM. mode register written asserting RAS, (The SDRAM should active mode with already high prior writing mode register). state address pins same cycle RAS, going data written mode register. clock cycles required complete write mode register. mode register contents changed using same command clock cycle requirements during operation long banks idle state. mode register divided into various fields depending fields functions. burst length field uses burst type uses latency (read latency from column address) vendor specific options test mode write burst length programmed using must normal SDRAM operation. Refer table specific codes various burst length, burst type latencies.
DEVICE DESELECT
When RAS, high, SDRAM performs operation (NOP). does initiate operation, needed complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. device deselect also entered asserting high. high disables command decoder that RAS, CAS, address inputs ignored.
ELECTRONICS
DEVICE OPERATIONS
DEVICE OPERATIONS (continued)
EXTENDED MODE REGISTER (EMRS)
extended mode register stores data selecting partial self refresh temperature compensated self refresh. EMRS cycle mandatory EMRS command needs issued only when either PASR TCSR used. default state without EMRS command issued banks refreshed. extended mode register written asserting RAS, CAS, high ,low BA0(The SDRAM should bank precharge with already high prior writing into extended mode register). state address pins same cycle RAS, going written extended mode register. clock cycles required complete write operation extended mode register. mode register contents changed using same command clock cycle requirements during operation long banks idle state. used partila self refresh used Temprature compensated self refresh. "Low" "High" used EMRS. other address pins except A0,A1,A2, BA1, must proper EMRS operation. Refer table specific codes.
CMOS SDRAM
SDRAM four internal banks same chip shares part internal circuitry reduce chip area, therefore restricts activation four banks simultaneously. Also noise generated during sensing each bank SDRAM high, requiring some time power supplies recover before another bank sensed reliably. tRRD (min) specifies minimum time required between activating different bank. number clock cycles required between different bank activation must calculated similar tRCD specification. minimum time required bank active initiate sensing restoring complete dynamic cells determined tRAS (min). Every SDRAM bank activate command must satisfy (min) specification before precharge command that active bank asserted. maximum time bank active state determined S(max). number cycles both S(min) (max) calculated similar tRCD specification.
BURST READ BANK ACTIVATE.
bank activate command used select random idle bank. asserting with desired bank address, access initiated. read write operation occur after time delay tRCD (min) from time bank activation. tRCD internal timing parameter SDRAM, therefore dependent operating clock frequency. minimum number clock cycles required between bank activate read write command should calculated dividing tRCD (min) with cycle time clock then rounding result next higher integer. burst read command used access burst data consecutive clock cycles from active active bank. burst read command issued asserting with being high positive edge clock. bank must active least D(min) before burst read command issued. first output appears latency number clock cycles after issue burst read command. burst length, burst sequence latency from burst read command determined mode register which already programmed. burst read initiated column address active row. address wraps around initial address does start from boundary such that number outputs from each equal burst length programmed mode register. output goes into high-impedance burst, unless burst read initiated keep data output gapless. burst read terminated issuing another burst read burst write same bank other active bank precharge command same bank. burst stop command valid every page burst length.
ELECTRONICS
DEVICE OPERATIONS
DEVICE OPERATIONS (continued)
BURST WRITE
burst write command similar burst read command used write data into SDRAM consecutive clock cycles adjacent addresses depending burst length burst sequence. asserting with valid column address, write burst initiated. data inputs provided initial address same clock cycle burst write command. input buffer deselected burst length, even though internal writing completed yet. writing completed issuing burst read blocking data inputs burst write same another active bank. burst stop command valid every burst length. write burst also terminated using blocking data procreating bank after last data input written into active row. OPERATION also.
CMOS SDRAM
AUTO PRECHARGE
precharge operation also performed using auto precharge. SDRAM internally generates timing satisfy tRAS (min) programmed burst length latency. auto precharge command issued same time burst read burst write asserting high /AP. burst read burst write asserting high /AP, bank left active until command asserted. Once auto precharge command given, commands possible that particular bank until bank achieves idle state.
AUTO REFRESH
storage cells 64Mb, 128Mb 256Mb SDRAM need refreshed every 64ms maintain data. auto refresh cycle
accomplishes refresh single storage cells. internal counter increments automatically every auto refresh cycle refresh rows. auto refresh command issued
BANKS PRECHARGE
banks precharged same time using Precharge command. Asserting RAS, with high after banks have satisfied tRAS (min) requirement, performs precharge banks. after performing precharge banks, banks idle state.
asserting with high auto refresh command only asserted with both banks being idle state device power down mode (CKE high previous cycle). time required complete auto refresh operation specified (min). minimum number clock cycles required calculated driving with clock cycle time them rounding next higher integer.
PRECHARGE
precharge operation performed active bank asserting RAS, with valid bank precharged. precharge command asserted anytime after tRAS (min) satisfied from bank active command desired bank. defined minimum number clock cycles required complete precharge calculated dividing with clock cycle time rounding next higher integer. Care should taken make sure that burst write completed used inhibit writing before precharge command asserted. maximum time bank active specified (max). Therefore, each bank activate command. precharge, bank enters idle state ready activated again. Entry Power down, Auto refresh, Self refresh Mode register etc. possible only when banks idle state.
auto refresh command must followed NOP's until auto refresh operation completed. banks will idle state auto refresh operation. auto refresh preferred refresh mode when SDRAM being used normal data transactions. 64Mb 128Mb SDRAM's auto refresh cycle performed once 15.6us burst 4096 auto refresh cycles once 64ms. 256Mb SDRAM's auto refresh cycle performed once 7.8us burst 8192 auto refresh cycles once 64ms.
ELECTRONICS
DEVICE OPERATIONS
DEVICE OPERATIONS (continued)
SELF REFRESH
self refresh another refresh mode available SDRAM. self refresh preferred refresh mode data retention power operation SDRAM. self refresh mode, SDRAM disables internal clock input buffers except CKE. refresh addressing timing internally generated reduce power consumption. self refresh mode entered from banks idle state asserting RAS, with high Once self refresh mode entered, only state being matters, other inputs including clock ignored order remain self refresh mode. self refresh exited restarting external clock then asserting high CKE. This must followed NOP's minimum time before SDRAM reaches idle state begin normal operation. system uses burst auto refresh during normal operation, recommended burst 8192 auto refresh cycles 256Mb burst 4096 auto refresh cycles 128Mb 64Mb immediately after exiting self refresh mode.
CMOS SDRAM
ELECTRONICS
DEVICE OPERATIONS
BASIC FEATURE FUNCTION DESCRIPTIONS
CMOS SDRAM
CLOCK Suspend
Clock Suspended During Write (BL=4)
Masked
Clock Suspended During Read (BL=4)
Internal DQ(CL2) DQ(CL3) Written
Masked
Internal DQ(CL2) DQ(CL3)
Suspended Dout
Operation
Write Mask (BL=4)
Masked byDQM
Read Mask (BL=4)
DQ(CL2) DQ(CL3)
DQ(CL2) DQ(CL3)
Masked Hi-Z
Hi-Z
Data-in Mask
Data-out Mask
with Clock Suspended (Full Page Read) DQ(CL2) DQ(CL3)
Hi-Z Hi-Z
Hi-Z Hi-Z
Hi-Z Hi-Z
*Note disable/enable 1CLK. makes data Hi-Z after 2CLKs which should masked masks both data-in data-out.
ELECTRONICS
DEVICE OPERATIONS
Interrupt
CMOS SDRAM
Read interrupted Read (BL=4) DQ(CL2) DQ(CL3)
tCCD
Write interrupted Write (BL=2)
Write interrupted Read (BL=2)
tCCD
tCCD
DQ(CL2) DQ(CL3)
tCDL
tCDL
*Note Interrupt", meant stop burst read/write external command before burst. "CAS Interrupt", stop burst read/write access read write. tCCD delay. (=1CLK) tCDL Last data column address delay. (=1CLK)
ELECTRONICS
DEVICE OPERATIONS
Interrupt (II) Read Interrupted Write
CL=2, BL=4 iii) CL=3, BL=4 iii) iii)
Hi-Z
CMOS SDRAM
Hi-Z
Hi-Z
Hi-Z
Hi-Z
*Note prevent contention, there should least between data data out.
ELECTRONICS
DEVICE OPERATIONS
Write Interrupted Precharge
tRDL
CMOS SDRAM
tRDL 2CLK
Masked
Masked
*Note prevent contention, should issued which makes least between data data out. inhibit invalid write, should issued. This precharge command burst write command should same bank, otherwise precharge interrupt only another bank precharge four banks operation.
Precharge
Normal Write BL=4 tRDL=1CLK
tRDL
BL=4 tRDL=2CLK
tRDL
Normal Read (BL=4)
DQ(CL2) DQ(CL3)
Auto Precharge
Normal Write (BL=4)
tRDL =1CLK
Normal Read (BL=4) DQ(CL2)
+20ns*4
tDAL =1CLK
DQ(CL3)
Auto Precharge Starts tRDL =2CLK tDAL =2CLK +20ns Auto Precharge Starts @tRDL=1CLK Auto Precharge Starts@tRDL=2CLK
*Note SAMSUNG support L=1CLK tRDL=2CLK memory devices. SAMSUNG recommends tRDL=2 CLK. Number valid output data after precharge Latency respectively. active command precharge bank issued after from this point. read/write command other activated bank issued from this point. burst read/write with auto precharge, interrupt same bank illegal tDAL defined Last data Active delay. SAMSUNG support tDAL=1CLK+20ns 2CLK+20ns ,recommends tDAL=2CLK+20ns.
ELECTRONICS
DEVICE OPERATIONS
Burst Stop Interrupted Precharge
Normal Write BL=4 tRDL=1CLK
tRDL*1
CMOS SDRAM
BL=4 tRDL=2CLK
tRDL*1
Write Burst Stop (BL=8)
tBDL
Read Interrupted Precharge (BL=4)
STOP
DQ(CL2) DQ(CL3)
Read Burst Stop (BL=4) DQ(CL2) DQ(CL3)
STOP
Mode Register
2CLK
*Note SAMSUNG support RDL=1CLK tRDL=2CLK memory devices. SAMSUNG recommends tRDL=2 CLK. tBDL Last data burst stop delay. Read write burst stop command valid every burst length. Number valid output data after precharge burst stop latency= respectively. banks precharge necessary. issued only banks precharge state.
ELECTRONICS
DEVICE OPERATIONS
Clock Suspend Exit Power Down Exit
Clock Suspend (=Active Power Down) Exit
CMOS SDRAM
Power Down (=Precharge Power Down) Exit Internal
Internal
Auto Refresh Self Refresh
Auto Refresh
Self Refresh
Note
*Note Active power down more banks active state. Precharge power down banks precharge state. auto refresh same refresh conventional DRAM. precharge commands required after auto refresh command. During from auto refresh command, other command accepted. Before executing auto/self refresh command, banks must idle state. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. During self refresh mode, refresh interval refresh operation performed internally. After self refresh entry, self refresh mode kept while low. During self refresh mode, inputs except will don't cared, outputs will Hi-Z state. time interval from self refresh exit command, other command accepted. Before/After self refresh mode, burst auto refresh cycle (4096 cycles 64Mb 128Mb, 8192 cycles 256Mb) recommended.
ELECTRONICS
DEVICE OPERATIONS
About Burst Type Control
Sequential Counting Basic MODE Interleave Counting
CMOS SDRAM
"0". BURST SEQUENCE TABLE. (BL=4, BL=1, full page. "1". BURST SEQUENCE TABLE. (BL=4, BL=4, BL=1, Interleave Counting Sequential Counting. Every cycle Read/Write Command with random column address realize Random Column Access. That similar Extended Data (EDO) Operation conventional DRAM.
Random MODE
Random column Access tCCD
About Burst Length Control
A2,1,0 "000". auto precharge, should violated. A2,1,0 "001". auto precharge, should violated. A2,1,0 "010". A2,1,0 "011". A2,1,0 "111". Wrap around mode(infinite burst length) should stopped burst stop. interrupt interrupt. "1". Read burst full page write Burst auto precharge write, tRAS should violated. Valid after burst stop latency respectively Using burst stop command, burst length control possible. Before burst, precharge command same bank stops read/write burst with precharge. tRDL with DQM, valid after burst stop latency respectively. During read/write burst with auto precharge, interrupt issued. Before burst, read/write stops read/write burst starts read/write burst. During read/write burst with auto precharge, interrupt issued.
Basic MODE Full Page
Special MODE Random MODE
BRSW
Burst Stop
Interrupt (Interrupted Precharge) Interrupt MODE Interrupt
ELECTRONICS
DEVICE OPERATIONS
FUNCTION TRUTH TABLE (TABLE
Current State IDLE Active Read Write Read with Auto Precharge Write with Auto Precharge Precharging code Address 10/AP code ILLEGAL Action
CMOS SDRAM
Note
A10/AP ILLEGAL Bank) Active Latch Auto Refresh Self Refresh Mode Register Access ILLEGAL
A10/AP Begin Read latch determine A10/AP Begin Read latch determine 10/AP ILLEGAL Precharge ILLEGAL (Continue Burst Active) (Continue Burst Active) Term burst active
A10/AP Term burst, Read, Determine A10/AP Term burst, Write, Determine 10/AP ILLEGAL Term burst, Precharge timing Reads ILLEGAL (Continue Burst Active) (Continue Burst Active) Term burst active
A10/AP Term burst, read, Determine A10/AP Term burst, Write, Determine 10/AP 10/AP ILLEGAL Term burst, precharge timing Writes ILLEGAL (Continue Burst Precharge) (Continue Burst Precharge) ILLEGAL ILLEGAL ILLEGAL (Continue Burst Precharge) (Continue Burst Precharge) ILLEGAL ILLEGAL ILLEGAL Idle after Idle after ILLEGAL ILLEGAL ILLEGAL Idle after
A10/AP ILLEGAL
A10/AP ILLEGAL
ELECTRONICS
DEVICE OPERATIONS
FUNCTION TRUTH TABLE (TABLE
Current State Activating Refreshing Mode Register Accessing Address 10/AP ILLEGAL Active after tRCD Active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Idle after Idle after ILLEGAL ILLEGAL ILLEGAL Idle after clocks Idle after clocks ILLEGAL ILLEGAL ILLEGAL Action
CMOS SDRAM
Note
Abbreviations Address Operation Command
Bank Address Column Address
Auto Precharge
*Note entries assume active (High) during precharge clock current clock cycle. Illegal bank specified state Function Iegal bank indicated depending state that bank. Must satisfy contention, turn around, and/or write recovery requirements. bank precharging idle state. precharge bank indicated (and 0/AP). Illegal bank idle.
ELECTRONICS
DEVICE OPERATIONS
FUNCTION TRUTH TABLE (TABLE
Current State (n-1) Self Refresh Banks Precharge Power Down Banks Idle State other than Listed above Address Action
CMOS SDRAM
Note
Exit Self Refresh Idle after tRFC (ABI) Exit Self Refresh Idle after tRFC (ABI) Exit Self Refresh Idle after tRFC (ABI) ILLEGAL ILLEGAL ILLEGAL (Maintain Self Refresh) INVALID Exit Power Down Exit Power Down ILLEGAL ILLEGAL ILLEGAL (Maintain Power Mode) Refer Table Enter Power Down Enter Power Down ILLEGAL ILLEGAL Bank) Active Enter Self Refresh Refer Operations Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend
Code Mode Register Access
Abbreviations Banks Idle, Address *Note high transition asynchronous. high transition asynchronous restarts internal clock. minimum setup time 1CLK must satisfied before command other than exit. Power down self refresh entered only from both banks idle state. Must legal command.
ELECTRONICS
TIMING DIAGRAM
Single Read Write Read Cycle(Same Page) @CAS Latency=3, Burst Length=1 Power Sequence Read Write Cycle Same Bank @Burst Length=4, tRDL=1CLK Read Write Cycle Same Bank @Burst Length=4, tRDL=2CLK Page Read Write Cycle Same Bank @Burst Length=4, tRDL=1CLK Page Read Write Cycle Same Bank @Burst Length=4, tRDL=2CLK Page Read Cycle Different Bank @Burst Length=4 Page Write Cycle Different Bank @Burst Length=4, tRDL=1CLK Page Write Cycle Different Bank @Burst Length=4, tRDL=2CLK Read Write Cycle Different Bank @Burst Length=4 Read Write Cycle With Auto Precharge @Burst Length=4 Read Write Cycle With Auto Precharge @Burst Length=4 Clock Suspension Operation Cycle @CAS Letency=2, Burst Length=4 Read Interrupted Precharge Command Read Burst Stop Cycle Full Page Burst
CMOS SDRAM
Write Interrupted Precharge Command Write Burst Stop Cycle Full Page Burst, tRDL=1CLK Write Interrupted Precharge Command Write Burst Stop Cycle Full Page Burst, tRDL=2CLK Burst Read Single Write Cycle @Burst Length Active/precharge Power Dower Down Mode @CAS Latency=2 Burst Length=4 Self Refresh Entry Exit Cycle Exit Cycle Mode Register Cycle Auto Refresh Cycle
ELECTRONICS
TIMING DIAGRAM
Single Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1
CMOS SDRAM
CLOCK
HIGH
*Note
tRAS
tRCD
tCCD
ADDR
*Note
*Note
*Note
*Note *Note
*Note
*Note
*Note
*Note *Note
tRAC tSAC tSLZ
Active
Read
Write
Read Precharge
Active
Don't care
ELECTRONICS
TIMING DIAGRAM
*Note input except don't care when high high going edge. Bank active read/write controlled BA0~BA1.
CMOS SDRAM
64Mb/128Mb
256Mb Active Read/Write Bank Bank Bank Bank
Enable disable auto precharge function controlled A10/AP read/write command
64Mb/128Mb A10/AP
256Mb Operation Disable auto precharge, leave bank active burst. Disable auto precharge, leave bank active burst. Disable auto precharge, leave bank active burst. Disable auto precharge, leave bank active burst. Enable auto precharge, precharge bank burst. Enable auto precharge, precharge bank burst. Enable auto precharge, precharge bank burst. Enable auto precharge, precharge bank burst.
A10/AP BA0~BA1 control bank precharge when precharge command asserted.
A10/AP
64Mb/128Mb
256Mb
Precharge Bank Bank Bank Bank Banks
ELECTRONICS
TIMING DIAGRAM
Power Sequence Mobile DRAM
CMOS SDRAM
Don't care
CLOCK
ADDR
Hi-Z
Hi-Z
High level necessary. Precharge (All Bank) Auto Refresh Auto Refresh Normal Extended Active (A-Bank)
Apply power start clock, Attempt maintain CKE= "H", DQM= other pins condition inputs. Power applied VDDQ (simultaneously). Maintain stable power, stable clock input condition minimum 200us. Issue precharge commands banks devices. Issue more auto-refresh commands. Issue mode register command initialize mode register. Issue extended mode register command define PASR TCSR operating type device after normal MRS. EMRS cycle mandatory EMRS command need issued only when either PASR TCSR used. default state without EMRS command issued +85°C 4banks refreshed.
device ready operation selected EMRS. operating with PASR TCSR, PASR TCSR mode EMRS setting stage. Adjustment another mode state PASR, TCSR mode achieved additional EMRS setting without asserting power sequence again.
ELECTRONICS
TIMING DIAGRAM
Read Write Cycle Same Bank @Burst Length=4, tRDL=1CLK
CLOCK
CMOS SDRAM
HIGH
*Note
tRCD
*Note
ADDR
CL=2
tRAC
*Note
tSAC
tSHZ
*Note
tRDL
CL=3
tRAC
*Note
tSAC
tSHZ
*Note
tRDL
Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Active (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
Don't care
*Note
Minimum cycle times required complete internal DRAM operation. precharge interrupt burst cycle. [CAS Latency number valid output data available after precharge. Last valid output will Hi-Z(t after clcok. Access time from active command. latency tSAC Ouput will Hi-Z after burst. Full page burst)
ELECTRONICS
TIMING DIAGRAM
Read Write Cycle Same Bank @Burst Length=4, tRDL=2CLK
CLOCK
CMOS SDRAM
HIGH
*Note
tRCD
*Note
ADDR
CL=2
tRAC
*Note
tSAC
tSHZ
*Note
tRDL
CL=3
tRAC
*Note
tSAC
tSHZ
*Note
tRDL
Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Active (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
Don't care
*Note
Minimum cycle times required complete internal DRAM operation. precharge interrupt burst cycle. [CAS Latency number valid output data available after precharge. Last valid output will Hi-Z(t after clcok. Access time from active command. latency tSAC Ouput will Hi-Z after burst. Full page burst)
ELECTRONICS
TIMING DIAGRAM
Page Read Write Cycle Same Bank @Burst Length=4, tRDL=1CLK
CLOCK HIGH
CMOS SDRAM
tRCD
*Note
ADDR
tRDL
CL=2 CL=3
tDAL
*Note
tCDL
*Note *Note
Active (A-Bank)
Read (A-Bank)
Read (A-Bank)
Write (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
Adiwe (A-Bank) Don't care
*Note
write data before burst read ends, should asserted three cycle prior write command avoid contention. precharge will interrupt writing. Last data input, tRDL before precharge, will written. should mask invalid input data precharge command cycle when asserting precharge before burst. Input data after precharge cycle will masked internally. tDAL, last data active delay, 1CLK 20ns
ELECTRONICS
TIMING DIAGRAM
Page Read Write Cycle Same Bank @Burst Length=4, tRDL=2CLK
CLOCK HIGH
CMOS SDRAM
tRCD
*Note
ADDR
tRDL
CL=2 CL=3
tDAL
*Note
tCDL
*Note *Note
Active (A-Bank)
Read (A-Bank)
Read (A-Bank)
Write (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
Active (A-Bank) Don't care
*Note
write data before burst read ends, should asserted three cycle prior write command avoid contention. precharge will interrupt writing. Last data input, tRDL before precharge, will written. should mask invalid input data precharge command cycle when asserting precharge before burst. Input data after precharge cycle will masked internally. tDAL ,last data active delay, 2CLK 20ns.
ELECTRONICS
TIMING DIAGRAM
Page Read Cycle Different Bank @Burst Length=4
CLOCK
*Note
CMOS SDRAM
HIGH
*Note
ADDR
CL=2 CL=3
QAa0
QAa1
QAa2 QBb0
QBb1 QBb2
QCc0
QCc1
QCc2
QDd0 QDd1 QDd2
QAa0
QAa1
QAa2
QBb0
QBb1
QBb2 QCc0
QCc1
QCc2 QDd0
QDd1
QDd2
Active (A-Bank)
Read (A-Bank) Active (B-Bank)
Read (B-Bank) Acive (C-Bank)
Read (C-Bank) Active (D-Bank)
Read (D-Bank) Precharge (C-Bank)
Precharge (D-Bank)
Precharge (A-Bank)
Precharge (B-Bank) Don't care
*Note
don't cared when RAS, high clock high going dege. interrupt burst read precharge, both read precharge banks must same.
ELECTRONICS
TIMING DIAGRAM
Page Write Cycle Different Bank @Burst Length=4, tRDL=1CLK
CLOCK HIGH
CMOS SDRAM
*Note
ADDR
10/AP
DAa0
DAa1
DAa2
DAa3
DBb0 DBb1
DBb2 DBb3
DCc0
DCc1
DDd0
DDd1
DDd2
tCDL
tRDL
*Note
Active (A-Bank)
Write (A-Bank) Active (B-Bank)
Write (B-Bank) Active (C-Bank)
Active (D-Bank) Write (C-Bank)
Write (D-Bank)
Precharge (All Banks)
Don't care
*Note
interrupt burst write precharge, should asserted mask invalid input data. interrupt burst write precharge, both write precharge banks must same.
ELECTRONICS
TIMING DIAGRAM
Page Write Cycle Different Bank @Burst Length=4, tRDL=2CLK
CLOCK HIGH
CMOS SDRAM
*Note
ADDR
10/AP
DAa0
DAa1
DAa2
DAa3
DBb0 DBb1
DBb2 DBb3
DCc0
DCc1
DDd0
DDd1
DDd2
tCDL
tRDL
*Note
Active (A-Bank)
Write (A-Bank) Active (B-Bank)
Write (B-Bank) Active (C-Bank)
Active (D-Bank) Write (C-Bank)
Write (D-Bank)
Precharge (All Banks)
Don't care
*Note
interrupt burst write precharge, should asserted mask invalid input data. interrupt burst write precharge, both write precharge banks must same.
ELECTRONICS
TIMING DIAGRAM
Read Write Cycle Different Bank @Burst Length=4
CLOCK HIGH
CMOS SDRAM
ADDR
tCDL
*Note
CL=2 CL=3
QAa0 QAa1
QAa2
QAa3
DDb0
DDb1 DDb2 DDb3
QBc0
QBc1
QBc2
QAa0 QAa1
QAa2
QAa3
DDb0
DDb1 DDb2 DDb3
QBc0
QBc1
Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank) Active (D-Bank)
Write (D-Bank) Active (B-Bank)
Read (B-Bank)
Don't care
*Note
tCDL should complete write.
ELECTRONICS
TIMING DIAGRAM
Read Write Cycle with Auto Precharge @Burst Length=4
CLOCK HIGH
CMOS SDRAM
ADDR
CL=2
QAa0 QAa1
QBb0
QBb1
QBb2 QBb3
DAc0
DAc1
CL=3
QAa0
QAa1
QBb0
QBb1 QBb2
QBb3
DAc0
DAc1
Active (A-Bank)
Read with Auto charge (A-Bank) Active (B-Bank)
Read without Auto precharge(B-Bank) Auto Precharge Start Point (A-Bank)* Note1
Precharge (B-Bank)
Active (A-Bank)
Write with Auto Precharge (A-Bank)
Don't care *Note1: When Read(Write) command with auto precharge issued A-Bank after Bank activation. Read(Write) command without auto precharge issued B-Bank before A-Bank auto precharge starts, A-Bank auto precharge will start B-Bank read command input point command issued A-Bank during after A-Bank auto precharge starts.
ELECTRONICS
TIMING DIAGRAM
Read Write Cycle with Auto Precharge @Burst Length=4
CLOCK HIGH
CMOS SDRAM
ADDR
CL=2
CL=3
*Note1
Active (A-Bank)
Read with Auto Precharge (A-Bank)
Auto Precharge Start Point (A-Bank) Active (B-Bank)
Read with Auto Precharge (B-Bank)
Auto Precharge Start Point (B-Bank)
Don't care *Note command A-bank allowed this period. determined from auto precharge start point
ELECTRONICS
TIMING DIAGRAM
Clock Suspension Operation Cycle @CAS Latency=2, Burst Length=4
CLOCK
CMOS SDRAM
ADDR
0/AP
tSHZ
tSHZ
*Note
Active
Read
Clock Suspension
Read
Read Write
Write Clock Suspension
Write
Don't care *Note1 needed prevent contention.
ELECTRONICS
TIMING DIAGRAM
CMOS SDRAM
Read Interrupted Precharge Command Read Burst Stop Cycle Full Page Burst
CLOCK HIGH
ADDR
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
CL=2
QAa0 QAa1 QAa2
QAa3
QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
CL=3
QAa0
QAa1
QAa2 QAa3 QAa4
Active (A-Bank)
Read (A-Bank)
Burst Stop
Read (A-Bank)
Precharge (A-Bank)
Don't care
*Note
full page mode, burst finished burst stop precharge. About valid after burst stop, same case interrupt. Both cases illustrated above timing diagram. label them. burst write, Burst stop interrupt should compared carefully. Refer timing diagram "Full page write burst stop cycle". Burst stop valid every burst length.
ELECTRONICS
TIMING DIAGRAM
CMOS SDRAM
Write Interrupted Precharge Command Write Burst Stop Cycle Full Page Burst, tRDL=1CLK
CLOCK
HIGH
ADDR
10/AP
tBDL
*Note
tRDL
*Note
DAa0
DAa1
DAa2
DAa3 DAa4
DAb0
DAb1
DAb2
DAb3
DAb4
DAb5
Active (A-Bank)
Write (A-Bank)
Burst Stop
Write (A-Bank)
Precharge (A-Bank) Don't care
*Note
full page mode, burst finished burst stop precharge. Data-in cycle interrupted precharge written into corresponding memory cell. defined parameter tRDL. write interrupted precharge command needed prevent invalid write. should mask invalid input data precharge command cycle when asserting precharge before burst. Input data after precharge cycle will masked internally. Burst stop valid every burst length.
ELECTRONICS
TIMING DIAGRAM
CMOS SDRAM
Write Interrupted Precharge Command Write Burst Stop Cycle Full Page Burst, tRDL=2CLK
CLOCK
HIGH
ADDR
10/AP
tBDL
*Note *Note
tRDL
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
DAa0
DAa1
DAa2
DAa3 DAa4
Active (A-Bank)
Write (A-Bank)
Burst Stop
Write (A-Bank)
Precharge (A-Bank) Don't care
*Note
full page mode, burst finished burst stop precharge. Data-in cycle interrupted precharge written into corresponding memory cell. defined parameter tRDL. write interrupted precharge command needed prevent invalid write. should mask invalid input data precharge command cycle when asserting precharge before burst. Input data after precharge cycle will masked internally. Burst stop valid every burst length.
ELECTRONICS
TIMING DIAGRAM
Burst Read Single Write Cycle @Burst Length=2
CLOCK
*Note
CMOS SDRAM
HIGH
*Note
ADDR
CL=2 CL=3
DAa0
QAb0
QAb1
DBc0
QCd0
QCd1
DAa0
QAb0
QAb1
DBc0
QCd0
QCd1
Active (A-Bank)
Active (B-Bank) Write (A-Bank)
Active (C-Bank) Write with Auto Precharge (B-Bank)
Read (C-Bank)
Precharge (C-Bank)
Read with Auto Precharge (A-Bank)
Don't care
*Note
BRSW modes enabled setting "High" (Mode Register Set). BRSW Mode, burst length write fixed regardless programmed burst length. When BRSW write command with auto precharge executed, keep mind that should violated. Auto precharge executed burst-end cycle, case BRSW write command, next cycle starts precharge.
ELECTRONICS
TIMING DIAGRAM
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
CLOCK
CMOS SDRAM
*Note
ADDR
*Note
*Note
*Note
10/AP
tSHZ
Precharge Power-down Entry
Active
Read
Precharge
Precharge Power-down Exit
Active Power-down Entry
Active Power-down Exit
Don't Care
*Note
Both banks should idle state prior entering precharge power down mode. should high least 1CLK prior active command. violate minimum refresh specification. (64ms)
ELECTRONICS
TIMING DIAGRAM
Self Refresh Entry Exit Cycle
CLOCK
*Note *Note
CMOS SDRAM
*Note
tRCmin
*Note
*Note
*Note
*Note
ADDR
~BA1
10/AP
Hi-Z
Self Refresh Entry
Self Refresh Exit
Auto Refresh Don't care
*Note
ENTER SELF REFRESH MODE with should same clcok cycle. After clock cycle, inputs including system clock don't care except CKE. device remains self refresh mode long stays "Low". cf.) Once device enters self refresh mode, minimum required before exit from self refresh. EXIT SELF REFRESH MODE System clock restart stable before returning high. starts from high. Minimum required after going high complete self refresh exit. cycle(64Mb ,128Mb) cycle(256Mb) burst auto refresh required before self refresh entry after self refresh exit system uses burst refresh.
ELECTRONICS
Hi-Z
TIMING DIAGRAM
Mode Register Cycle
CLOCK
*Note
CMOS SDRAM
Auto Refresh Cycle
HIGH
HIGH
*Note
*Note
ADDR
Hi-Z
Hi-Z
Command
Auto Refresh
Command
Don't care
banks precharge should completed before Mode Register cycle auto refresh cycle.
MODE REGISTER CYCLE *Note RAS, CAS, BA0, activation same clock cycle with address will internal mode register. Minimum clock cycles should before activation. Please refer Mode Register table.
ELECTRONICS
TIMING DIAGRAM
Extended Mode Register Cycle
CLOCK
*Note
CMOS SDRAM
HIGH
*Note
*Note
ADDR
Hi-Z
EMRS
Command
ELECTRONICS

CMOS SDRAM 8Mx16 Mobile SDRAM 54CSP (VDD/VDDQ 2.5V/1.8V 2.5V

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