IS80C54 CMOS SINGLE CHIP 8-BIT MICROCONTROLLER 80C52 based a

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IS80C54 CMOS SINGLE CHIP 8-BIT MICROCONTROLLER 80C52 based a

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IS80C58 IS80C54 IS80C58
IS80C54
CMOS SINGLE CHIP 8-BIT MICROCONTROLLER
80C52 based architecture (80C54) (80C58) Three 16-bit Timer/Counters Full duplex serial channel Boolean processor Four 8-bit ports, lines Memory addressing capability Program memory lock Lock bits Power save modes: Idle power-down Eight interrupt sources Most instructions execute CMOS compatible Maximum speed: Packages available: 40-pin 44-pin PLCC 44-pin PQFP
GENERAL DESCRIPTION
ICSI IS80C54 IS80C58 high-performance microcontroller fabricated using high-density CMOS technology. CMOS IS80C54/58 functionally compatible with industry standard 80C52/32 microcontrollers. IS80C54/58 designed with (IS80C54 )and 32Kx8 (IS80C58); RAM; programmable lines; serial port either multiprocessor communications, expansion full duplex UART; three 16-bit timer/counters; eight-source, twopriority-level, nested interrupt structure; on-chip oscillator clock circuit. IS80C54/58 expanded using standard compatible memory.
T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1
P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
Figure IS80C54/58 Configuration: 40-pin
ICSI reserves right make changes products time without notice order improve design supply best possible product. assume responsibility errors which appear this publication. Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
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IS80C54 IS80C58
P1.1/T2EX
P0.0/AD0
P0.1/AD1
P0.2/AD2
INDEX P1.5 P1.6 P1.7 RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5
P0.3/AD3
P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 PSEN P2.7/A15 P2.6/A14 P2.5/A13
P1.0/T2
P1.4
P1.3
P1.2
VIEW
WR/P3.6
XTAL2
XTAL1
A8/P2.0
A9/P2.1
A10/P2.2
A11/P2.3
Figure IS80C54/58 Configuration: 44-pin PLCC
A12/P2.4
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RD/P3.7
IS80C54 IS80C58
P1.1/T2EX
P0.0/AD0
P0.1/AD1
P0.2/AD2
P1.5 P1.6 P1.7 RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5
P0.3/AD3
P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 PSEN P2.7/A15 P2.6/A14 P2.5/A13
P1.0/T2
P1.4
P1.3
P1.2
WR/P3.6
A8/P2.0
A9/P2.1
XTAL2
XTAL1
A10/P2.2
A11/P2.3
Figure IS80C54/58 Configuration: 44-pin PQFP
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A12/P2.4
RD/P3.7
IS80C54 IS80C58
P2.0-P2.7
P0.0-P0.7
DRIVERS
DRIVERS
ADDRESS DECODER BYTES ADDRESS DECODER 16/32K LOCK BITS
ADDR REGISTER
LATCH
LATCH
REGISTER
STACK POINT
PROGRAM ADDRESS REGISTER
PCON SCON T2CON RCAP2L SBUF
TMOD TCON RCAP2H
TMP2
TMP1
PROGRAM COUNTER
INTERRUPT SERIAL PORT TIMER BLOCK
INCREMENTER
BUFFER
PSEN TIMING CONTROL
INSTRUCTION REGISTER
DPTR
LATCH
LATCH
OSCILLATOR XTAL1 XTAL2 DRIVERS DRIVERS
P3.0-P3.7
P1.0-P1.7
Figure IS80C54/58 Block Diagram
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IS80C54 IS80C58
Table Detailed Description Symbol PDIP PLCC PQFP Name Function Address Latch Enable: Output pulse latching byte address during access external memory. normal operation, emitted constant rate oscillator frequency, used external timing clocking. Note that pulse skipped during each access external data memory. External Access enable: must externally held enable device fetch code from external program memory locations 0000H FFFFH. held high, device executes from internal program memory unless program counter contains address greater than internal seze. Port Port 8-bit open-drain, bidirectional port. Port pins that have written them float used highimpedance inputs. Port also multiplexed low-order address data during accesses external program data memory. this application, uses strong internal pullups when emitting Port Port 8-bit bidirectional port with internal pullups. Port pins that have written them pulled high internal pullups used inputs. inputs, Port pins that externally pulled will source current because internal pullups. (See Characteristics: IIL). Port output buffers sink/source four inputs. Port also receives low-order address byte during verification. P2.0-P2.7 21-28 24-31 18-25 T2(P1.0): Timer/Counter external count input. T2EX(P1.1): Timer/Counter trigger input. Port Port 8-bit bidirectional port with internal pullups. Port pins that have written them pulled high internal pullups used inputs. inputs, Port pins that externally pulled will source current because internal pullups. (See Characteristics: IIL). Port emits high order address byte during fetches from external program memory during accesses external data memory that used 16-bit addresses (MOVX DPTR). this application, Port uses strong internal pullups when emitting During accesses external data memory that 8-bit addresses (MOVX 1]), Port emits contents Special Function Register. Port also receives high-order bits some control signals during verification.
P0.0-P0.7
39-32
43-36
37-30
P1.0-P1.7
40-44
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IS80C54 IS80C58
Table Detailed Description (continued) Symbol P3.0-P3.7 PDIP 10-17 PLCC 13-19 PQFP 7-13 Name Function Port Port 8-bit bidirectional port with internal pullups. Port pins that have written them pulled high internal pullups used inputs. inputs, Port pins that externally pulled will source current because internal pullups. (See Characteristics: IIL). Port also serves special features IS80C54/58, listed below: PSEN (P3.0): Serial input port. (P3.1): Serial output port. INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt (P3.4): Timer external input. (P3.5): Timer external input. (P3.6): External data memory write strobe. (P3.7): External data memory read strobe. Program Store Enable: read strobe external program memory. When device executing code from external program memory, PSEN activated twice each machine cycle except that PSEN activations skipped during each access external data memory. PSEN activated during fetches from internal program memory. Reset: high this machine cycles while oscillator running, resets device. internal resistor permits power-on reset using only external capacitor connected Vcc. Crystal Input inverting oscillator amplifier input internal clock generator circuits. Crystal Output from inverting oscillator amplifier. Ground: reference. Power Supply: This power supply voltage operation.
XTAL XTAL
OPERATING DESCRIPTION
detail description IS80C54/58 included this description are: Memory Registers Timer/Counters Serial Interface Interrupt System Information Another information detail information desription IS80C54/58 refer IS80C52/32 date sheet
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IS80C54 IS80C58
OTHER INFORMATION Reset
reset input pin, which input Schmitt Trigger. reset accomplished holding high least machine cycles oscillator periods), while oscillator running. responds generating internal reset, with timing shown Figure external reset signal asynchronous internal clock. sampled during State Phase every machine cycle. port pins will maintain their current activities oscillator periods after logic been sampled pin; that oscillator periods after external reset signal been applied pin. internal reset algorithm writes SFRs except port latches, Stack Pointer, SBUF. port latches initialized FFH, Stack Pointer 07H, SBUF indeterminate. Table lists SFRs their reset values. Then internal affected reset. power-up content indeterminate. Table Reset Values SFR's Name DPTR P0-P3 TMOD TCON T2CON RCAP2H RCAP2L SCON SBUF PCON Reset Value 0000H 0000H XX000000B 0X000000B Indeterminate 0XXX0000B
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IS80C54 IS80C58
Power-on Reset
automatic reset obtained when goes through capacitor through 8.2K resistor, providing rise time does exceed msec oscillator start-up time does exceed msec. This Power-on reset circuit shown Figure CMOS devices require 8.2K pulldown resistor, although presence does harm. When power turned circuit holds high amount time that depends value capacitor rate which charges. ensure good reset, must high long enough allow oscillator time start-up (normally msec) plus machine cycles. Note that port pins will random state until oscillator start internal reset algorithm written them. With this circuit, reducing quickly causes voltage momentarily fall below However, this voltage internally limited will harm device. IS80C52/32 8.2K
Figure Power-On Reset Circuit
OSC. PERIODS
INTERNAL RESET SIGNAL SAMPLE SAMPLE
PSEN
INST ADDR INST ADDR INST ADDR INST ADDR INST ADDR
OSC. PERIODS
OSC. PERIODS
Figure Reset Timing
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Power-Saving Modes Operation
IS80C54/58 power-reducing modes. Idle Power-down. input through which backup power supplied during these operations Vcc. Figure shows internal circuitry which implements these features. Idle mode (IDL oscillator continues Interrupt, Serial Port, Timer blocks continue clocked, clock signal gated CPU. Power-down oscillator frozen. Idle Power-down modes activated setting bits Special Function Register PCON.
XTAL
XTAL INTERRUPT, SERIAL PORT, TIMER BLOCKS
CLOCK
Idle Mode instruction that sets PCON.0 last instruction executed before Idle mode begins. Idle mode, internal clock signal gated CPU, Interrupt, Timer, Serial Port functions. status preserved entirety; Stack Pointer, Program Counter, Program Status Word, Accumulator, other registers maintain their data during Idle. port pins hold logical states they time Idle activated. PSEN hold logic high levels. There ways terminate Idle. Activation enabled interrupt will cause PCON.0 cleared hardware, terminating Idle mode. interrupt will serviced, following RETI next instruction executed will following instruction that device into Idle. flag bits used indicate whether interrupt occurred during normal operation during Idle. example, instruction that activates Idle also both flag bits. When Idle terminated interrupt, interrupt service routine examine flag bits. other terminating Idle mode with hardware reset. Since clock oscillator still running, hardware reset must held active only machine cycles oscillator periods) complete reset. signal clears directly asynchronously. this time, resumes program execution from where left off; that instruction following that invoked Idle Mode. shown Figure three machine cycles program execution take place before internal reset algorithm takes control. On-chip hardware inhibits access internal during time, access port pins inhibited. eliminate possibility unexpected outputs port pins, instruction following that invokes Idle should write port external data RAM. Integrated Circuit Solution Inc.
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Figure Idle Power-Down Hardware Power-down Mode instruction that sets PCON.1 last instruction executed before Power-down mode begins. Powerdown mode, on-chip oscillator stops. With clock frozen, functions stopped, on-chip Special function Registers held. port pins output values held their respective SFRs. PSEN output lows. Power-down mode operation, reduced However, must reduced before Power-down mode invoked, must restored normal operating level before Power-down mode terminated. reset that terminates Power-down also frees oscillator. reset should activated before restored normal operating level must held active long enough allow oscillator restart stabilize (normally less than msec). only exit from Power-down hardware reset. Reset redefines SFRs does change on-chip RAM.
IS80C54 IS80C58
Table Status External Pins During Idle Power-down Modes. Mode Idle Idle Power-down Power-down Memory Internal External Internal External PSEN PORT Data Float Data Float PORT Data Data Data Data PORT Data Address Data Data PORT Data Data Data Data
On-Chip Oscillators
on-chip oscillator circuitry IS80C54/58 single stage inverter, intended crystalcontrolled, positive reactance oscillator. this application crystal operated fundamental response mode inductive reactance parallel resonance with capacitance external crystal (Figure Examples drive clock with external oscillator shown Figure crystal specifications capacitance values Figure critical. used these positions frequency with good quality crystals. (For ranges greater than refer Figure 11.) ceramic resonator used place crystal cost-sensitive applications. When ceramic resonator used, normally selected somewhat higher values. manufacturer ceramic resonator should consulted recommendation values these capacitors.
XTAL2
XTAL2
XTAL1
EXTERNAL OSCILLATOR SIGNAL
XTAL1
Figure Oscillator Connections
Figure External Clock Drive Configuration
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IS80C54 IS80C58
XTAL2
XTAL1
Figure Oscillator Connections High Speed MHz)
Note: When frequency higher than MHz, please refer Table recommended values
Table Recommended Value Frequency Range pF-30 pF-10 pF-30 pF-10 Apply 6.2K-10K
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Verification address program menory location read applied Port pins P2.5-P2.0 (A14 P3.4 IS80C58). other pins should held "Verify" level indicated Figure contents addressed locations exits Port External pullups required Rort this operation. Figure shows setup verify program memory.
A7-A0
A12-A8
P2.4-P2.0 PSEN P2.7 P2.6 XTAL1
DATA
P2.5 P3.4
IS80C54
XTAL2
IS80C58
Figure Verification
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IS80C54 IS80C58
Lock System
ICSI 80C54/58 contains Program Memory Locking: Security When programmed, this effects masked parts: External MOVC disable, latch reset. Security Bit2: When programmed, this inhibits Verify User ROM.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TBIAS TSTG Parameter Terminal Voltage with Respect GND(2) Temperature Under Bias(3) Storage Temperature Power Dissipation Value -2.0 +7.0 +125 Unit
Note: Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. Minimum input voltage -0.5V. During transitions, inputs undershoot periods less than Maximum voltage output pins 0.5V which overshoot 2.0V periods less than Operating temperature commercial products only defined this specification.
OPERATING RANGE(1)
Range Commercial Ambient Temperature +70°C Oscillator Frequency
Note: Operating ranges define those limits between which functionality device guaranteed.
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CHARACTERISTICS
(Ta=0°C VCC=5V+10%; VSS=0V Symbol VIL1 VIH1 VSCH+ VSCH- VOL(1) Parameter Input voltage (All except Input voltage (EA) Input high voltage (All except XTAL RST) Input high voltage (XTAL positive schmitt-trigger threshold voltage negative schmitt-trigger threshold voltage Output voltage (Ports VOL1
Test conditions
-0.5 -0.5 0.2Vcc 0.7Vcc 0.7Vcc 0.9Vcc 0.75Vcc 0.9Vcc 0.75Vcc
0.2Vcc 0.2Vcc 0.3Vcc 0.45 0.45 -650
Unit
Output voltage (Port ALE, PSEN)
Output high voltage (Ports ALE, PSEN)
4.5V-5.5V
VOH1
Output high voltage (Port ALE, PSEN)
4.5V-5.5V -300 -800
RRST Note:
Logical input current (Ports 0.45V Input leakage current (Port Logical 1-to-0 transition current (Ports pulldown resister 0.45V 2.0V
Under steady state (non-transient) conditions, must externally limited follows: Maximum port pin: Maximum 8-bit port Port Ports Maximum total output pins: exceeds test condition, exceed related specification.
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POWER SUPPLY CHARACTERISTICS
Symbol Parameter Power supply current Active mode
Test conditions 5.0V
Unit
Idle mode
Power-down mode
Note: Figures13,14,15, test conditiions.
CLOCK SIGNAL
XTAL2 XTAL1
CLOCK SIGNAL
XTAL2 XTAL1
Figure Active Mode
Figure Idle Mode
XTAL2 XTAL1
Figure Power-down Mode
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tCLCX
0.5V 0.45V
0.7Vcc 0.2Vcc
tCHCX
tCHCL tCLCL
tCLCH
Figure Clock Signal Waveform Tests Active Idle Mode (tCLCH=t CHCL=5
EXTERNAL MEMORY CHARACTERISTICS
Clock Clock Variable Oscillator (3.5 MHz) 2tCLCL-15 tCLCL-15 tCLCL-10 4tCLCL-20 tCLCL-10 3tCLCL-15 3tCLCL-20 tCLCL-5 5tCLCL-20 6tCLCL-20 6tCLCL-20 4tCLCL-10 2tCLCL-5 7tCLCL-10 8tCLCL-10 3tCLCL-20 3tCLCL+20 4tCLCL-20 tCLCL-15 tCLCL-10 tCLCL-15 tCLCL+15
Symbol 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH
Parameter Oscillator frequency pulse width Address valid Address hold after valid instr PSEN PSEN pulse width PSEN valid instr Input instr hold after PSEN Input instr float after PSEN Address valid instr PSEN address float pulse width pulse width valid data Data hold after Data float after valid data Address valid data Address Data valid transition Data hold after address float high high
Unit
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EXTERNAL MEMORY CHARACTERISTICS
Clock Clock Variable Oscillator (3.5-40 MHz) 12tCLCL-10 12tCLCL+10 10tCLCL-10 2tCLCL-10 10tCLCL
Symbol tXLXL tQVXH tXHQX tXHDX tXHDV
Parameter Serial port clock cycle time Output data setup clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge input data valid
Unit
EXTERNAL CLOCK DRIVE
Symbol 1/tCLCL tCHCX tCLCX tCLCH tCHCL Parameter Oscillator Frequency High time time Rise time Fall time Unit
VERIFICATION CHARACTERISTICS
Symbol 1/tCLCL tAVQV tELQV tEHQZ Parameter Oscillator Frequency Address data valid ENABLE data valid Data float after ENABLE 40tCLCL 48tCLCL 48tCLCL Unit
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TIMING WAVEFORMS
tLHLL
tLLPL tAVLL tPLPH tPLIV tPLAZ tPXIZ
A7-A0
PSEN
tLLAX tPXIX
INSTR
PORT
A7-A0
tLLIV tAVIV
PORT
A15-A8
A15-A8
Figure External Program Memory Read Cycle
tWHLH
PSEN
tLLDV tLLWL tRLRH tRHDZ tRHDX
DATA A7-A0 FROM INSTR
PORT
tAVLL
tRLAZ tLLAX
tRLDV
A7-A0 FROM
tAVWL tAVDV
PORT
A15-A8 FROM
A15-A8 FROM
Figure External Data Memory Read Cycle
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IS80C54 IS80C58
tWHLH
PSEN
tLLWL tWLWH tWHQX
A7-A0 FROM INSTR
PORT
tAVLL tLLAX
A7-A0 FROM
tQVWX
DATA
tAVWL
PORT
A15-A8 FROM
A15-A8 FROM
Figure External Data Memory Write Cycle
INSTRUCTION
tXLXL
CLOCK
tQVXH tXHQX tXHDV tXHDX
VALID
DATAOUT DATAIN
VALID
VALID
VALID
VALID
VALID
VALID
VALID
Figure Shift Register Mode Timing Waveform
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IS80C54 IS80C58
P1.0-P1.7 P2.0-P2.5[A14(P3.4)] PORT
tELQV
ADDRESS
tAVQV
DATA
tEHQZ
P2.7
Figure Verification Waveforms
tCLCX
0.5V 0.45V
0.7Vcc 0.2Vcc
tCHCX
tCHCL tCLCL
tCLCH
Figure External Clock Drive Waveforms
0.5V 0.45V
0.2Vcc 0.9V 0.2Vcc 0.1V
Figure Test Point
Note: inputs during testing driven 0.5V logic 0.45V logic "0". Timing measurements made logic logic "0".
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IS80C54 IS80C58
ORDERING INFORMATION Commercial Temperature: +70°C
Speed Order Part Number IS80C54/58-12PL IS80C54/58-12PQ IS80C54/58-12W IS80C54/58-24PL IS80C54/58-24PQ IS80C54/58-24W IS80C54/58-40PL IS80C54/58-40PQ IS80C54/58-40W Package PLCC PQFP 600mil PLCC PQFP 600mil PLCC PQFP 600mil
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HEADQUARTER: NO.2, TECHNOLOGY SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 106, SEC. HSIN-TAI ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw
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IS80C54 IS80C58
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IS80C54 CMOS SINGLE CHIP 8-BIT MICROCONTROLLER 80C52 based a

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