(16-MBIT) DYNAMIC WITH .AST PAGE MODE compatible inputs outputs;

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(16-MBIT) DYNAMIC WITH .AST PAGE MODE compatible inputs outputs;

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IC41C16105 IC41LV16105
(16-MBIT) DYNAMIC WITH .AST PAGE MODE
compatible inputs outputs; tristate Refresh Interval: 1,024 cycles/16 Refresh Mode: RAS-Only, CAS-before-RAS (CBR), Hidden JEDEC standard pinout Single power supply: (IC41C16105) 3.3V (IC41LV16105) Byte Write Byte Read operation Industrail temperature range -40oC 85oC
DESCRIPTION 1+51 IC41C16105 IC41LV16105 1,048,576
16-bit high-performance CMOS Dynamic Random Access Memories. .ast Page Mode allows 1,024 random accesses within single with access cycle time short 16-bit word. Byte Write control, upper lower byte, makes IC41C16105 ideal 16-, 32-bit wide data systems. These features make IC41C16105 IC41LV16105 ideally suited high-bandwidth graphics, digital signal processing, high-performance computing systems, peripheral applications. IC41C16105 IC41LV16105 packaged 42-pin 400mil 400mil (50-) TSOP-2.
TIMING PARAMETERS
Parameter
Max. Access Time (tRAC) Max. Access Time (tCAC) Max. Column Address Access Time (tAA) Min. .ast Page Mode Cycle Time (tPC) Min. Read/Write Cycle Time (tRC) Unit
CON.IGURATIONS
44(50)-Pin TSOP-2
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
42-Pin
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 LCAS UCAS
I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 LCAS UCAS
DESCRIPTIONS
A0-A9 I/O0-15 UCAS LCAS Address Inputs Data Inputs/Outputs Write Enable Output Enable Address Strobe Upper Column Address Strobe Lower Column Address Strobe Power Ground Connection
ICSI reserves right make changes products time without notice order improve design supply best possible product. assume responsibility errors which appear this publication. Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
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IC41C16105 IC41LV16105
.UNCTIONAL BLOCK DIAGRAM
LCAS UCAS CLOCK GENERATOR CONTROL LOGICS CONTROL LOGIC
CLOCK GENERATOR
DATA
REFRESH COUNTER
DATA BUFFERS
DECODER
COLUMN DECODERS SENSE AMPLIFIERS
I/O0-I/O15
MEMORY ARRAY 1,048,576
ADDRESS BUFFERS A0-A9
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Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
IC41C16105 IC41LV16105
TRUTH TABLE
.unction Standby Read: Word Read: Lower Byte Read: Upper Byte Write: Word (Early Write) Write: Lower Byte (Early Write) Write: Upper Byte (Early Write) Read-Write(1,2) Hidden Refresh RAS-Only Refresh Refresh(4) LCAS UCAS Address tR/tC ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/NA High-Z DOUT Lower Byte, DOUT Upper Byte, High-Z Lower Byte, High-Z Upper Byte, DOUT Lower Byte, Upper Byte, High-Z Lower Byte, High-Z Upper Byte, DOUT, DOUT DOUT High-Z High-Z
Read Write(1,3)
Notes: These WRITE cycles also BYTE WRITE cycles (either LCAS UCAS active). These READ cycles also BYTE READ cycles (either LCAS UCAS active). EARLY WRITE only. least signals must active (LCAS UCAS).
Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
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IC41C16105 IC41LV16105
.unctional Description
IC41C16105 IC41LV16105 CMOS DRAM optimized high-speed bandwidth, power applications. During READ WRITE cycles, each uniquely addressed through address bits. These entered bits (A0-A9) time. address latched Address Strobe (RAS). column address latched Column Address Strobe (CAS). used latch first bits used latter bits. IC41C16105 IS41LV16105 controls, LCAS UCAS. LCAS UCAS inputs internally generates signal functioning identical manner single input other DRAMs. difference that each controls corresponding tristate logic conjunction with RAS). LCAS controls I/O0 through I/O7 UCAS controls I/O8 through I/O15. IC41C16105 IC41LV16105 function determined first (LCAS UCAS) transitioning last transitioning back HIGH. controls give IC41C16105 IC41LV16105 both BYTE READ BYTE WRITE cycle capabilities.
Write Cycle
write cycle initiated falling edge whichever occurs last. input data must valid before falling edge whichever occurs last.
Refresh Cycle
retain data, 1,024 refresh cycles required each period. There ways refresh memory. clocking each 1,024 addresses through with least once every read, write, read-modify-write RAS-only cycle refreshes addressed row. Using CAS-before-RAS refresh cycle. CAS-beforeRAS refresh activated falling edge RAS, while holding LOW. CAS-before-RAS refresh cycle, internal 10-bit counter provides addresses external address inputs ignored. CAS-before-RAS refresh-only mode data access device selection allowed. Thus, output remains High-Z state during cycle.
Memory Cycle
memory cycle initiated bring terminated returning both HIGH. ensures proper device operation data integrity memory cycle, once initiated, must ended aborted before minimum tRAS time expired. cycle must initiated until minimum precharge time tRP, elapsed.
Power-On
After application supply, initial pause required followed minimum eight initialization cycles (any combination cycles containing signal). During power-on, recommended that track with held valid avoid current surges.
Read Cycle
read cycle initiated falling edge whichever occurs last, while holding HIGH. column address must held minimum time specified tAR. Data becomes valid only when tRAC, tAA, tCAC tOEA satisfied. result, access time dependent timing relationships between these parameters.
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Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
IC41C16105 IC41LV16105
ABSOLUTE MAXIMUM RATINGS(1)
Symbol IOUT TSTG Parameters Voltage Relative Supply Voltage Output Current Power Dissipation Commercial Operation Temperature Industrail Operation Temperature Storage Temperature 3.3V 3.3V Rating +7.0 +4.6 +7.0 +4.6 +125 Unit
Note: Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages referenced GND.)
Symbol Parameter Supply Voltage Input High Voltage Input Voltage Commercial Ambient Temperature Industrail Ambient Temperature 3.3V 3.3V 3.3V Min. Typ. Max. Unit
CAPACITANCE(1,2)
Symbol CIN1 CIN2 Parameter Input Capacitance: A0-A9 Input Capacitance: RAS, UCAS, LCAS, Data Input/Output Capacitance: I/O0-I/O15 Max. Unit
Notes: Tested initially after design process changes that affect these parameters. Test conditions: 25°C, MHz,
Integrated Circuit Solution Inc.
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IC41C16105 IC41LV16105
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.) Symbol ICC1 Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Voltage Level Standby Current: Test Condition input Other inputs under test Output disabled (Hi-Z) VOUT (5V) (3.3V) (5V) (3.3V) RAS, LCAS, UCAS Commerical 3.3V Extended Idustrial 3.3V 3.3V Speed Min. Max. Unit
ICC2 ICC3
Standby Current: CMOS Operating Current: Random Read/Write(2,3,4) Average Power Supply Current Operating Current: .ast Page Mode(2,3,4) Average Power Supply Current Refresh Current: RAS-Only(2,3) Average Power Supply Current
RAS, LCAS, UCAS 0.2V RAS, LCAS, UCAS, Address Cycling, (min.) VIL, LCAS, UCAS, Cycling (min.) Cycling, LCAS, UCAS (min.)
ICC4
ICC5
ICC6
Refresh Current: RAS, LCAS, UCAS Cycling CBR(2,3,5) (min.) Average Power Supply Current
Notes: initial pause required after power-up followed eight refresh cycles (RAS-Only CBR) before proper device operation assured. eight cycles wake-up should repeated time tRE. refresh requirement exceeded. Dependent cycle rates. Specified values obtained with minimum cycle time output open. Column-address changed once each .ast page cycle. Enables on-chip refresh address counters.
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Integrated Circuit Solution Inc.
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IC41C16105 IC41LV16105
CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.) Symbol tRAC tCAC tRAS tCAS tCSH tRCD tASR tRAH tASC tCAH tRAD tRAL tRPC tRSH tRHCP tCLZ tCRP tOED tOEHC tOEP tOES tRCS tRRH tRCH tWCH tWCR tWPZ tRWL tCWL tWCS tDHR Parameter Random READ WRITE Cycle Time Access Time from RAS(6, Access Time from CAS(6, Access Time from Column-Address(6) Pulse Width Precharge Time Pulse Width(26) Precharge Time(9, Hold Time (21) Delay Time(10, Row-Address Setup Time Row-Address Hold Time Column-Address Setup Time(20) Column-Address Hold Time(20) Column-Address Hold Time (referenced RAS) Column-Address Delay Time(11) Column-Address Lead Time Precharge Time Hold Time(27) Hold Time from Precharge Output Low-Z(15, Precharge Time(21) Output Disable Time(19, Output Enable Time(15, Output Enable Data Delay (Write) HIGH Hold Time from HIGH HIGH Pulse Width HIGH Setup Time Read Command Setup Time(17, Read Command Hold Time (referenced RAS)(12) Read Command Hold Time (referenced CAS)(12, Write Command Hold Time(17, Write Command Hold Time (referenced RAS)(17) Write Command Pulse Width(17) Pulse Widths Disable Outputs Write Command Lead Time(17) Write Command Lead Time(17, Write Command Setup Time(14, Data-in Hold Time (referenced RAS) Min. Max. Min. Max. Units S2-7
Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
IC41C16105 IC41LV16105
CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.) Symbol tACH tOEH tRWC tRWD tCWD tAWD tRASP tCPA tPRWC tCOH tWHZ tCLCH tCSR tCHR tORD tRE. Parameter Column-Address Setup Time Precharge during WRITE Cycle Hold Time from during READ-MODI.Y-WRITE cycle(18) Data-In Setup Time(15, Data-In Hold Time(15, READ-MODI.Y-WRITE Cycle Time Delay Time during READ-MODI.Y-WRITE Cycle(14) Delay Time(14, Column-Address Delay Time(14) .ast Page Mode READ WRITE Cycle Time(24) Pulse Width Access Time from Precharge(15) READ-WRITE Cycle Time(24) Data Output Hold after Output Buffer Turn-Off Delay from RAS(13,15,19, Output Disable Delay from Last going .irst returning HIGH(23) Setup Time (CBR RE.RESH)(30, Hold Time (CBR RE.RESH)(30, Setup Time prior during HIDDEN RE.RESH Cycle Auto Refresh Period (1,024 Cycles) Transition Time (Rise .all)(2, Min. Max. 100K Min. Max. 100K Units
TEST CONDITIONS
Output load: Loads (Vcc 5.0V ±10%) Load (Vcc 3.3V ±10%)
Input timing reference levels: 2.4V, 0.8V (Vcc 5.0V ±10%); 2.0V, 0.8V (Vcc 3.3V ±10%) Output timing reference levels: 2.0V, 0.8V (Vcc ±10%, 3.3V ±10%)
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IC41C16105 IC41LV16105
Notes: initial pause required after power-up followed eight refresh cycle (RAS-Only CBR) before proper device operation assured. eight cycles wake-up should repeated time tRE. refresh requirement exceeded. (MIN) (MAX) reference levels measuring timing input signals. Transition times, measured between between VIH) assume inputs. addition meeting transition rate specification, input signals must transit between between VIH) monotonic manner. VIH, data output High-Z. VIL, data output contain data from last valid READ cycle. Measured with load equivalent gate Assumes that tRCD tRCD (MAX). tRCD greater than maximum recommended value shown this table, tRAC will increase amount that tRCD exceeds value shown. Assumes that tRCD tRCD (MAX). falling edge RAS, data will maintained from previous cycle. initiate cycle clear data output buffer, must pulsed tCP. Operation with tRCD (MAX) limit ensures that tRAC (MAX) met. tRCD (MAX) specified reference point only; tRCD greater than specified tRCD (MAX) limit, access time controlled exclusively tCAC. Operation within tRAD (MAX) limit ensures that tRCD (MAX) met. tRAD (MAX) specified reference point only; tRAD greater than specified tRAD (MAX) limit, access time controlled exclusively tAA. Either tRCH tRRH must satisfied READ cycle. (MAX) defines time which output achieves open circuit condition; reference VOL. tWCS, tRWD, tAWD tCWD restrictive operating parameters LATE WRITE READ-MODI.Y-WRITE cycle only. tWCS tWCS (MIN), cycle EARLY WRITE cycle data output will remain open circuit throughout entire cycle. tRWD tRWD (MIN), tAWD tAWD (MIN) tCWD tCWD (MIN), cycle READ-WRITE cycle data output will contain data read from selected cell. neither above conditions met, state access time until back VIH) indeterminate. held HIGH taken after goes result LATE WRITE (OE-controlled) cycle. Output parameter (I/O) referenced corresponding input, I/O0-I/O7 LCAS I/O8-I/O15 UCAS. During READ cycle, then taken HIGH before goes HIGH, goes open. tied permanently LOW, LATE WRITE READ-MODI.Y-WRITE possible. Write command defined going low. LATE WRITE READ-MODI.Y-WRITE cycles must have both tOEH HIGH during WRITE cycle) order ensure that output buffers will open during WRITE cycle. I/Os will provide previously written data remains taken back after tOEH met. I/Os open during READ cycles once occur. first edge transition LOW. last edge transition HIGH. These parameters referenced leading edge EARLY WRITE cycles leading edge LATE WRITE READMODI.Y-WRITE cycles. Last falling edge first rising edge. Last rising edge next cycles last rising edge. Last rising edge first falling edge. Each must meet minimum pulse width. Last LOW. I/Os controlled, regardless UCAS LCAS. minimum parameter guaranteed design. Enables on-chip refresh address counters.
Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
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IC41C16105 IC41LV16105
READ CYCLE
tRAS
tCSH tCRP tRCD tRSH tCAS tCLCH tRRH
UCAS/LCAS
tRAD tASR tRAH tASC tRAL tCAH
ADDRESS
tRCS
Column
tRCH
tRAC tCAC tCLC
tOFF(1)
Open
Valid Data
Open
tOES
Don't Care
Note: referenced from rising edge CAS, whichever occurs last.
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Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
IC41C16105 IC41LV16105
READ WRITE CYCLE (LATE WRITE READ-MODI.Y-WRITE Cycles)
tRWC tRAS
tCSH tCRP tRCD tRSH tCAS tCLCH
UCAS/LCAS
tASR tRAD tRAH tRAL tASC tCAH tACH
ADDRESS
tRCS
Column
tRWD tCWD tAWD
tCWL tRWL
tRAC tCAC tCLZ
Open
Valid DOUT
Valid
Open
tOEH
Don't Care
Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
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IC41C16105 IC41LV16105
EARLY WRITE CYCLE DON'T CARE)
tRAS
tCSH tCRP tRCD tRSH tCAS tCLCH
UCAS/LCAS
tRAD tASR tRAH tASC tRAL tCAH tACH
ADDRESS
Column
tCWL tRWL tWCR tWCS tWCH
tDHR
Valid Data
Don't Care
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Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
IC41C16105 IC41LV16105
.AST PAGE MODE READ CYCLE
tRASP
tCSH tCAS tCRP tRCD tPRWC tCAS tRSH tCAS tCRP
UCAS/LCAS
tRAH tASR tRAD tASC tCAH tCPWD tASC tCAH tCPWD tRAL tCAH
tASC
ADDRESS
Column
Column
Column
tRCS
tCAC tCAC tCAC
tRAC tCLZ
tOED tCLZ
tOED tCLZ
tOED
Don't Care
Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
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IC41C16105 IC41LV16105
.AST PAGE MODE READ WRITE CYCLE (LATE WRITE READ-MODI.Y-WRITE Cycles)
tRASP
tCSH tCAS tCRP tRCD tPRWC tCAS tRSH tCAS tCRP
UCAS/LCAS
tRAH tASR tRAD tASC tCAH tCPWD tASC tCWL tRWD tAWD tCWD tCAH tCPWD tRAL tCAH
tASC
ADDRESS
Column
Column
tCWL tAWD tCWD
Column
tCWL tRWL tAWD tCWD
tRCS
tCAC tCAC tCAC
tOEZ tOED tCLZ
tRAC tCLZ
tOEZ tOED tCLZ
tOEZ tOED
I/O0-I/O15
Don't Care
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Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
IC41C16105 IC41LV16105
.AST PAGE MODE EARLY WRITE CYCLE
tRASP
tRHCP tRSH tCAS tCRP
tCSH tCAS tCRP tRCD tCAS
UCAS/LCAS
tRAL tRAH tASR tRAD tASC tCAH tASC tCWL tWCS tWCH tWCS tCAH tASC tCAH
ADDRESS
Column
Column
tCWL tWCH tWCS
Column
tCWL tWCH
tWCR
tDHR
I/O0-I/O15
Valid
Valid
Valid
Don't Care
WAVE.ORMS 4)5-ONLY RE.RESH CYCLE (OE, DON'T CARE)
tRAS
tCRP tRPC
UCAS/LCAS
tASR tRAH
ADDRESS
Open
Don't Care
Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
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IC41C16105 IC41LV16105
RE.RESH CYCLE (Addresses; DON'T CARE)
tRAS
tRAS
tRPC tCHR tCSR tRPC tCSR tCHR
UCAS/LCAS Open
HIDDEN RE.RESH CYCLE(1) HIGH; LOW)
tRAS tRAS
tCRP tRCD tRSH tCHR
UCAS/LCAS
tASR tRAD tRAH tASC tRAL tCAH
ADDRESS
Column
tRAC tCAC tCLZ tOFF(2)
Open
tORD
Valid Data
Open
Don't Care
Notes: Hidden Refresh also performed after Write Cycle. this case, HIGH. referenced from rising edge CAS, whichever occurs last.
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Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
IC41C16105 IC41LV16105
ORDERING IN.ORMATION: 3.3V Commercial Range: 70°C
Speed (ns) Order Part IC41LV16105-50K IC41LV16105-50T IC41LV16105-60K IC41LV16105-60T Package 400mil 400mil TSOP-2 400mil 400mil TSOP-2
ORDERING IN.ORMATION: 3.3V Industrial Temperature Range: 40°C 85°C
Speed (ns) Order Part IC41LV16105-50KI IC41LV16105-50TI IC41LV16105-60KI IC41LV16105-60TI Package 400mil 400mil TSOP-2 400mil 400mil TSOP-2
ORDERING IN.ORMATION: Commercial Range: 70°C
Speed (ns) Order Part IC41C16105-50K IC41C16105-50T IC41C16105-60K IC41C16105-60T Package 400mil 400mil TSOP-2 400mil 400mil TSOP-2
ORDERING IN.ORMATION: Industrial Temperature Range: 40°C 85°C
Speed (ns) Order Part IC41C16105-50KI IC41C16105-50TI IC41C16105-60KI IC41C16105-60TI Package 400mil 400mil TSOP-2 400mil 400mil TSOP-2
Integrated Circuit Solution Inc.
DR014-0A 06/07/2001
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IC41C16105 IC41LV16105
HEADQUARTER: NO.2, TECHNOLOGY SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 .ax: 886-3-5783000
Integrated Circuit Solution Inc.
BRANCH O.ICE: 106, SEC. HSIN-TAI ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 .AX: 886-2-26962252 http://www.icsi.com.tw
S2-18 Integrated Circuit Solution Inc.
DR014-0A 06/07/2001

(16-MBIT) DYNAMIC WITH .AST PAGE MODE compatible inputs outputs;

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