Download

PDF Abstract Text:

SL6442

1GHZ AMPLIFIER / MIXER

THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS
SEPTEMBER 1993
PRELIMINARY INFORMATION
SL6442
1GHZ AMPLIFIER / MIXER
(Supersedes May 1992 Edition)
The SL6442 UHF Amplifier and Mixer is designed for use in cordless telephones, cellular telephones, pagers and lowpower receivers operating at frequencies up to 1GHz. It contains a low noise amplifier (LNA) with AGC facility and two mixers for use in I and Q direct conversion receivers or image cancelling in superheterodyne receivers. Operating from a single supply of 5V, the SL6442 requires a current of 4.6mA (typ.) when powered up and only 11µA (typ.) when powered down using the battery economy facility.
RF VCC VBIAS RF INPUT (CB) RF INPUT (CE) RF DECOUPLE RF OUTPUT RF GROUND MIXER INPUT BANDGAP REF (VBG) BATTERY ECONOMY
AGC AGC DECOUPLE MIXER DECOUPLE VCC LO DECOUPLE MIXER B OUTPUT LO B INPUT LO A INPUT GROUND MIXER A OUTPUT
FEATURES s 1GHz Operation
Fig.1 Pin connections - top view
Very Low Power Suitable for Direct Conversion or Superhet Systems On-Chip RF Amplifier Power Down Facility for Battery Economy AGC Capability
ABSOLUTE MAXIMUM RATINGS
Supply voltage Storage temperature Operating temperature 8V 255°C to1150°C 0°C to 170°C
ORDERING INFORMATION
SL6442 NA MP Miniature Plastic DIL Package
This device has static-sensitive terminations, sensitivity measured as typically 400V using MIL-STD-883 Method 3015. Therefore, ESD handling precautions are essential in order to avoid degradation of performance or permanent damage to the device.
15V RF VCC
15V RF OUTPUT
MIXER INPUT
MIXER A
GAIN CONTROL MIXER B RF BIAS RF AMPLIFIER
MIXER A OUTPUT
MIXER B OUTPUT
RF GROUND
CE INPUT
CB INPUT
LOCAL OSCILLATOR A INPUT
LOCAL OSCILLATOR B INPUT
Fig.2 block diagram
SL6442
AGC DECOUPLE
RF VCC
AGC BUFFER AMP
BIAS 2
BIAS 1
RF GND
CE INPUT
CB INPUT
VBIAS
Fig.3 Circuit schematic of LNA
MIXER A OUTPUT
MIXER B OUTPUT LO B INPUT
LO A INPUT 100 100
BIAS MIXER INPUT STAGE
LO DECOUPLE
MIXER INPUT
MIXER DECOUPLE
GROUND
Fig.4 Circuit schematic of mixer
PIN DESCRIPTIONS
Pin no. 1 2 3 Name RF VCC VBIAS RF input (CB) Description Power supply to the RF amplifier. Normally connected to 15V, it should be adequately bypassed. A 1·6V bias source capable of supplying up to 0·5mA. Common base input to the emitter of the RF transistor. It should be returned to ground for DC using an RF choke or tuned circuit when in common base mode. In common emitter mode it should be connected directly to ground. Common emitter input to the base of the RF transistor. It is DC biased internally but should be decoupled in common base mode. Decoupling of DC bias line. Output port of the RF amplifier. It should be returned to +5V via an RF load. A current of 2mA will flow if pin 20 (AGC) is connected to pin 9 (VBG).
RF input (CE) RF decouple RF output
SL6442
PIN DESCRIPTIONS (Continued)
ELECTRICAL CHARACTERISTICS
Mixer A / B gain match
NOTE: Typical figures are for a VCC of 5·0V
SL6442
ELECTRICAL CHARACTERISTICS OF THE SL6442 DEMONSTRATION BOARD (PAGES 8-10)
NOTE: Refer to Figs. 5, 6 and 7 for typical performance of overall low noise amplifier and mixer configuration (demonstration board) across temperature and supply voltage 4·0V, 5·0V and 7·0V).
SUPPLEMENTARY INFORMATION
IF output bandwidth Output impedance Isolation LO to mix RF I / P Reverse isolation of RF amp Isolation LO to IF Isolation RF to IF
SL6442
PERFORMANCE CHARACTERISTICS OF THE SL6442 DEMONSTRATION BOARD
GAIN (dB)
TEMPERATURE (°C)
Fig. 5 Typical overall power gain
NOISE FIGURE (dB)
TEMPERATURE (°C)
Fig. 6 Typical overall noise figure
THIRD ORDER INTECEPT POINT (dB)
TEMPERATURE (°C)
Fig. 7 Typical overall third order intercept
SL6442
1400MHz
150MHz
1400MHz
150MHz
2j 0.2
150 MHz
1400MHz
150MHz
2j 0.2
2j 0.5
1400MHz
S11 f (MHz) 150 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 Mag. 0·869 0·829 0·765 0·712 0·679 0·640 0·608 0·582 0·561 0·531 0·496 0·401 0·334 0·304 Ang. (°) 222·1 228·5 240·1 249·2 257·7 266·5 274·0 282·2 290·4 2100·0 2114·0 2118·5 2120·6 2117·8 Mag. 0·006 0·002 0·008 0·004 0·010 0·019 0·027 0·036 0·041 0·043 0·063 0·050 0·050 0·049
S12 Ang. (°) 69·0 134·0 111·8 131·2 138·1 140·3 143·7 130·8 118·7 113·5 115·9 100·0 98·1 97·0 Mag. 5·126 4·763 4·140 3·567 3·123 2·672 2·428 2·197 1·935 1·729 1·636 1·512 1·385 1·208
S21 Ang. (°) 149·7 138·6 121·9 108·8 96·6 87·7 79·2 71·7 62·4 56·3 47·2 41·4 34·3 28·4 Mag. 0·994 0·991 0·986 0·967 0·963 0·945 0·921 0·909 0·912 0·913 0·885 0·877 0·853 0·824
S22 Ang. (°) 211·3 215·5 222·7 229·5 236·7 244·0 249·8 254·7 259·8 266·4 274·6 280·2 287·6 295·2
Fig. 8 RF amplifier common emitter S-parameters
SL6442
GAIN (dB)
VAGC (V)
Fig. 9 SL6442 AGC characteristic
f (MHz) 150 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400
Mag. 0·967 0·967 0·949 0·960 0·922 0·887 0·868 0·836 0·826 0·849 0·866 0·856 0·817 0·768
Ang. (°) 212·1 215·9 224·5 230·0 239·3 246·3 253·0 258·8 263·6 270·4 278·6 288·5 298·2 2107·3
150MHz
2j 0.2
1400MHz
Fig. 10 Mixer RF input impedance, S11 (pin 8)
SL6442
APPLICATION CIRCUIT FOR USE AT 950MHz
This Application Note describes a circuit which demonstrates the functions and performance of the SL6442 in a 950MHz amplifier / mixer receiver front end configuration. Fig. 11 is a schematic diagram which illustrates the arrangement of the ancillary components required for optimum performance at 950MHz. Component layout, PCB track and ground plane are shown in Figs. 12, 13 and 14, respectively. Approximate starting values for the components were obtained using Smith charts and data derived from S-parameter analysis (see Figs. 8 and 10). The actual component values were determined by using a linear circuit simulator such as TouchstoneTM. In this case the circuit is optimised for maximum stable gain and minimum input reflection coefficient at the required frequency. The input match is achieved using a stripline shorted-stub network. The LNA output to mixer input match is achieved by using a series inductor, and the mixer output to 50 match consists of a tunable LC network. To prevent possible RF instability, pin 2 (VBIAS) is decoupled with a series RC network as well as a 2·2µF capacitor. The quadrature phase shift components consist of phase lead (R3, C18) and phase lag (R2, C17) networks, which are capacitively coupled to the LO input pins. Inductor L3 serves to resonate out the parasitic capacitance between the two ports. The exact values of the phase shift components were determined empirically and achieve a maximum amplitude and phase imbalance of about 1dB and 4 degrees respectively. The variable capacitors VC1 and VC2 are adjusted to give a maximum output level at an IF of 20MHz. Other intermediate frequencies may require different values of VC1 and VC2 and / or L4 and L5. At zero IF, as in direct conversion receivers, the output matching network is transparent. If the AGC facility is not required it is necessary to connect pin 20 to pin 9 (VBG). The battery economy pin (10) may be connected directly to ground if the power down facility is not required. NOTE: Ensure adequate decoupling is used close to the chip, especially when designing for maximum power gain. Refer to LNA S-parameters to avoid possible stability problems when designing the LNA close to maximum gain.
IF OUT (B)
LO INPUT
IF OUT (A)
C17 C14
100n 3·3p
R3 L3 15n
C10 AGC C9
2·2µ 18p
SL6442
C6 2·2µ C5 18p C2 C1
27p 18p
POWER DOWN POWER UP
C19 L1 15n C3
4·7p 2·2µ
RF INPUT
L6 82n
Fig. 11 SL6442 demonstration board circuit
SL6442
LO I / P AGC INPUT + GND
C8 C9 C10 C11 C12 C13 C15 C16 VC1 L6 C7 C5 C14 C17 R2 C18 L3 R3
COMPONENT LIST
R1, R3 R2 C1 C2, C5, C10, C11, C13, C15 C3 C4, C6, C7, C8 C9, C19 C12 C14 C17 C18 L1, L3 L2 L4, L5 L6 VC1, VC2 47 51 27pF 18pF 4·7p 22pF 2·2µF 1nF 100nF 3·3pF 5·6pF 15nH 100nH 3·3µH 82nH 2 - 20pF
L4 VC2
SL6442
C6 C19 L1
SL6442 AMP & MIXER
950MHz RF INPUT
LO I / P AGC INPUT GND +5V
SL6442 AMP & MIXER
950MHz RF INPUT
SL6442
CUSTOMER NOTES
SL6442
PACKAGE DETAILS
Dimensions are shown thus: mm (in). For further package information, please contact your local Customer Service Centre.
SPOT REF. CHAMFER REF.
0·25 / 0·71 345° (0·010 / 0·028) 0·36 / 0·48 (0·014 / 0·019) 0·23 / 0·33 (0·009 / 0·013) 2·36 / 2·64 (0·093 / 0·104) 0·74 (0·029) MAX. AT 4 PLACES
20 LEADS AT 1·27 (0·050) NOM. SPACING 12·60 / 13·00 (0·496 / 0·512)
20-LEAD MINIATURE PLASTIC DIL - MP20
HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 Fax: (0793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017 1500 Green Hills Road, Scotts Valley, CA95067-0017 United States of America. Tel (408) 438 2900 Fax: (408) 438 5576
For more information about all Zarlink products visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
Purchase of Zarlink s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001, Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE