January 1998 Revised 2000 Dual Flip-Flop with Reset Positive-Edge

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January 1998 Revised 2000 Dual Flip-Flop with Reset Positive-Edge

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CD54/74HC74, CD54/74HCT74
January 1998 Revised 2000
Dual Flip-Flop with Reset Positive-Edge Trigger
Description
'HC74 'HCT74 utilize silicon gate CMOS technology achieve operating speeds equivalent LSTTL parts. They exhibit power consumption standard CMOS integrated circuits, together with ability drive LSTTL loads. This flip-flop independent DATA, SET, RESET CLOCK inputs outputs. logic level present data input transferred output during positive-going transition clock pulse. RESET independent clock accomplished level appropriate input. logic family functionally well compatible with standard logic family.
Features
Hysteresis Clock Inputs Improved Noise Immunity Increased Input Rise Fall Times Asynchronous Reset Complementary Outputs Buffered Inputs Typical fMAX 50MHz 15pF, 25oC Fanout (Over Temperature Range) Standard Outputs LSTTL Loads Driver Outputs LSTTL Loads Wide Operating Temperature Range -55oC 125oC Balanced Propagation Delay Transition Times Significant Power Reduction Compared LSTTL Logic Types Operation High Noise Immunity: 30%, Types 4.5V 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), (Min) CMOS Input Compatibility, VOL,
/Title (CD54H C74, CD74H C74, CD74H CT74) /Subject (Dual FlipFlop with
Ordering Information
PART NUMBER CD54HC74F CD54HC74F3A CD74HC74E CD74HC74M CD54HCT74F CD54HCT74F3A CD74HCT74E CD74HCT74M NOTES: When ordering, entire part number. suffix obtain variant tape reel. available which meets electrical specifications. Please contact your local sales office customer service ordering information. TEMP. RANGE (oC) PACKAGE CERDIP CERDIP PDIP SOIC CERDIP CERDIP PDIP SOIC
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
2000, Texas Instruments Incorporated
CD54/74HC74, CD54/74HCT74 Pinout
CD54HC74, CD54HCT74 (CERDIP) CD74HC74, CD74HCT74 (PDIP, SOIC) VIEW
Functional Diagram
RESET DATA CLOCK RESET CLOCK
DATA
TRUTH TABLE INPUTS RESET (Note OUTPUTS (Note
NOTE: High Level (Steady State) Level (Steady State) Don't Care Low-to-High Transition level before indicated input conditions were established. This configuration nonstable, that will persist when reset inputs return their inactive (high) level.
CD54/74HC74, CD54/74HCT74
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Drain Current, Output, -0.5V 0.5V. .±25mA Output Diode Current, -0.5V 0.5V .±20mA Output Source Sink Current Output Pin, -0.5V 0.5V .±25mA Ground Current, .±50mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (oC/W) PDIP Package SOIC Package CERDIP Package Maximum Junction Temperature (Hermetic Package Die) 175oC Maximum Junction Temperature (Plastic Package) 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range (TA) -55oC 125oC Supply Voltage Range, Types Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Time 1000ns (Max) 4.5V. 500ns (Max) 400ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current -0.02 -5.2 0.02 3.15 3.98 5.48 1.35 0.26 0.26 ±0.1 3.15 3.84 5.34 1.35 0.33 0.33 3.15 1.35 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD54/74HC74, CD54/74HCT74
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Quiescent Device Current TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Input Pin: Unit Load NOTE: dual-supply systems theoretical worst case 2.4V, 5.5V) specification 1.8mA. SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
-0.02
3.98
3.84
0.02
0.26
0.33
±0.1
(Note
Input Loading Table
INPUT UNIT LOADS 0.75
NOTE: Unit Load limit specified Electrical Specifications table, e.g., 360µA 25oC.
Prerequisite Switching Specifications
PARAMETER TYPES Data Setup Time (Figure SYMBOL TEST CONDITIONS 25oC -40oC 85oC -55oC 125oC UNITS
CD54/74HC74, CD54/74HCT74
Prerequisite Switching Specifications
PARAMETER Hold Time (Figure SYMBOL (Continued) Removal Time (Figure tREM Pulse Width (Figure Pulse Width (Figure Frequency fMAX TYPES Data Setup Time (Figure Hold Time (Figure Removal Time (Figure Pulse Width (Figure Pulse Width (Figure Frequency tREM fMAX 25oC -40oC 85oC -55oC 125oC UNITS
TEST CONDITIONS
Switching Specifications Input
PARAMETER TYPES Propagation Delay, (Figure tPLH, tPHL 50pF 50pF 15pF 50pF Propagation Delay, (Figure tPLH, tPHL 50pF 50pF 15pF 50pF Transition Time (Figure tTLH, tTHL 50pF 50pF 50pF Input Capacitance SYMBOL TEST CONDITIONS 25oC -40oC 85oC -55oC 125oC UNITS
CD54/74HC74, CD54/74HCT74
Switching Specifications Input
PARAMETER Frequency Power Dissipation Capacitance (Notes TYPES Propagation Delay, (Figure Propagation Delay, (Figure Transition Time (Figure Input Capacitance Frequency Power Dissipation Capacitance (Notes NOTES: VCC2 VCC2 where input frequency, output frequency, output load capacitance, supply voltage. used determine dynamic power consumption, flip-flop. tPLH, tPHL tPHL, tPLH tTLH, tTHL fMAX 50pF 50pF 50pF 15pF SYMBOL fMAX (Continued) 25oC -40oC 85oC -55oC 125oC UNITS
TEST CONDITIONS 15pF
Test Circuits Waveforms
trCL CLOCK tfCL CLOCK 2.7V 0.3V trCL tfCL 1.3V 0.3V 1.3V 1.3V
NOTE: Outputs should switching from accordance with device truth table. fMAX, input duty cycle 50%. FIGURE CLOCK PULSE RISE FALL TIMES PULSE WIDTH
NOTE: Outputs should switching from accordance with device truth table. fMAX, input duty cycle 50%. FIGURE CLOCK PULSE RISE FALL TIMES PULSE WIDTH
INPUT
INPUT 2.7V 1.3V 0.3V
tTLH
tTHL
tTLH tPHL tPLH
tTHL
INVERTING OUTPUT
INVERTING OUTPUT tPHL tPLH
1.3V
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
CD54/74HC74, CD54/74HCT74 Test Circuits Waveforms
trCL CLOCK INPUT tH(H) tH(L) DATA INPUT tSU(H) tTLH OUTPUT tPLH tREM SET, RESET PRESET tSU(L) tTHL tPHL tREM SET, RESET PRESET tSU(H) tTLH OUTPUT 1.3V tPLH 1.3V tPHL tSU(L) tTHL DATA INPUT tfCL CLOCK INPUT
(Continued)
trCL 2.7V 0.3V tH(H) 1.3V tH(L) 1.3V 1.3V 1.3V tfCL
1.3V
50pF
50pF
FIGURE SETUP TIMES, HOLD TIMES, REMOVAL TIME, PROPAGATION DELAY TIMES EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE SETUP TIMES, HOLD TIMES, REMOVAL TIME, PROPAGATION DELAY TIMES EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Customers responsible their applications using components. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 2000, Texas Instruments Incorporated

January 1998 Revised 2000 Dual Flip-Flop with Reset Positive-Edge

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