Download

PDF Abstract Text:

CD54 / 74HC74, CD54 / 74HCT74

January 1998 - Revised May 2000

CD54 / 74HC74, CD54 / 74HCT74
Data sheet acquired from Harris Semiconductor SCHS124A
January 1998 - Revised May 2000
Dual D Flip-Flop with Set and Reset Positive-Edge Trigger
Description
Features
/ Title (CD54H C74, CD74H C74, CD74H CT74) / Subject (Dual D FlipFlop with Set
Ordering Information
PART NUMBER CD54HC74F CD54HC74F3A CD74HC74E CD74HC74M CD54HCT74F CD54HCT74F3A CD74HCT74E CD74HCT74M NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Die is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
CD54 / 74HC74, CD54 / 74HCT74 Pinout
CD54HC74, CD54HCT74 (CERDIP) CD74HC74, CD74HCT74 (PDIP, SOIC) TOP VIEW
Functional Diagram
12 DATA
CD54 / 74HC74, CD54 / 74HCT74
Absolute Maximum Ratings
Thermal Information
Thermal Resistance (Typical, Note 4) JA (oC / W) JC (oC / W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . 120 CERDIP Package . . . . . . . . . . . . . . . . 130 55 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 4. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
CD54 / 74HC74, CD54 / 74HCT74
DC Electrical Specifications
ICC ICC (Note 5)
5.5 4.5 to 5.5
HCT Input Loading Table
INPUT D R CP S UNIT LOADS 0.5 0.5 0.7 0.75
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC.
Prerequisite For Switching Specifications
PARAMETER HC TYPES Data to CP Setup Time (Figure 5) tSU 2 4.5 6 60 12 10 75 15 13 90 18 15 ns ns ns SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
CD54 / 74HC74, CD54 / 74HCT74
Prerequisite For Switching Specifications
PARAMETER Hold Time (Figure 5) SYMBOL tH (Continued) VCC (V) 2 4.5 6 Removal Time R, S, to CP (Figure 5) tREM 2 4.5 6 Pulse Width R, S (Figure 1) tW 2 4.5 6 Pulse Width CP (Figure 1) tW 2 4.5 6 CP Frequency fMAX 2 4.5 6 HCT TYPES Data to CP Setup Time (Figure 6) Hold Time (Figure 6) Removal Time R, S, to CP (Figure 6) Pulse Width R, S (Figure 2) Pulse Width CP (Figure 2) CP Frequency tSU tH tREM tW tW fMAX 4.5 4.5 4.5 4.5 4.5 4.5 12 3 6 16 18 25 15 3 8 20 23 20 18 3 9 24 27 16 ns ns ns ns ns MHz 25oC MIN 3 3 3 30 6 5 80 16 14 80 16 14 6 30 35 TYP MAX -40oC TO 85oC -55oC TO 125oC MIN 3 3 3 40 8 7 100 20 17 100 20 17 5 25 29 MAX MIN 3 3 3 45 9 8 120 24 20 120 24 20 4 20 23 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz
TEST CONDITIONS -
CD54 / 74HC74, CD54 / 74HCT74
Test Circuits and Waveforms
INVERTING OUTPUT
INVERTING OUTPUT tPHL tPLH
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
CD54 / 74HC74, CD54 / 74HCT74 Test Circuits and Waveforms
(Continued)
trCL 2.7V 0.3V tH(H) 1.3V GND tH(L) 3V 1.3V 1.3V 1.3V GND tfCL 3V
1.3V GND
CL 50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS