8-Bit Programmable System-on-Chip (PSoCTM) Microcontrollers CYPRE
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CY8C25122, CY8C26233, CY8C26443, CY8C26643 Device Data Sheet Silicon Revision
8-Bit Programmable System-on-Chip (PSoCTM) Microcontrollers
CYPRESS MICROSYSTEMS
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
CYPRESS MICROSYSTEMS
family Programmable System-onChip (PSoCTM) microcontrollers replaces multiple MCU-based system components with single-chip, programmable device. PSoC microcontroller includes fast CPU, Flash program memory, SRAM data memory with configurable analog digital peripheral blocks range convenient pin-outs memory sizes. driving force behind this innovative Programmable System-on-Chip comes from user configurability analog digital arrays: PSoC blocks.
Powerful Harvard Architecture Processor with Fast Multiply/Accumulate processor instruction Processor speeds Register speed memory transfers Flexible addressing modes manipulation memory multiply, 32-bit accumulate Flexible On-Chip Memory Flash program storage, bytes, depending device 50,000 erase/write cycles bytes SRAM data storage In-System Serial Programming (ISSP) Partial Flash updates Flexible protection modes EEPROM emulation Flash, 2,304 bytes Programmable System-on-Chip (PSoC) Blocks On-chip, user configurable analog digital peripheral blocks PSoC blocks used individually combination Analog PSoC blocks provide: Delta-Sigma Successive Approximation Incremental Programmable gain amplifier Programmable filters Differential comparators Digital PSoC blocks provide: Multipurpose timers: event timing, real-time clock, pulse width modulation (PWM) with deadband modules Full-duplex UARTs master slave configuration Flexible clocking sources analog PSoC blocks Programmable Configurations Schmitt trigger pins Logic output drive with internal pull-up pull-down resistors, High strong driver Interrupt change Analog output drive Precision, Programmable Clocking Internal 24/48 Oscillator (+/- 2.5%, external components) External 32.768 Crystal Oscillator (optional precision source PLL) Internal Speed Oscillator Watchdog Sleep Dedicated Peripherals Watchdog Sleep Timers Voltage Detection with user-configurable threshold voltages On-chip voltage reference Fully Static CMOS Devices using advanced Flash technology power high speed Operating voltage from 5.25 Operating voltage down using on-chip switch mode voltage pump Wide temperature range: Complete Development Tools Powerful integrated development environment (PSoC Designer) Low-cost, in-circuit emulator programmer
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Cypress MicroSystems, Inc. 22027 17th Avenue Suite Bothell, 98021 Phone: 877.751.6100 Fax: 425.939.0999 http://www.cypressmicro.com/ support@cypressmicro.com
Cypress MicroSystems, Inc. 2000-2002. rights reserved. PSoC
(Programmable System-on-Chip) trademark Cypress MicroSystems, Inc.
other trademarks registered trademarks referenced herein property respective corporations. information contained herein subject change without notice. Cypress MicroSystems assumes responsibility circuitry other than circuitry embodied Cypress MicroSystems product. does convey imply license under patent other rights. Cypress MicroSystems does authorize products critical components life support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress MicroSystems' products life-support system applications implies that manufacturer assumes risk such doing indemnifies Cypress MicroSystems against charges.
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
CYPRESS MICROSYSTEMS
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Table Contents
Functional Overview Features Pin-out Descriptions Architecture Introduction Registers Addressing Modes Instruction Summary Memory Organization Flash Program Memory Organization Data Memory Organization Register Organization Introduction Register Bank Register Bank Ports Introduction Registers Port Data Registers Port Interrupt Enable Registers Port Global Select Registers Clocking Oscillator Options System Clocking Signals Interrupts Overview Interrupt Control Architecture Interrupt Vectors Interrupt Masks Interrupt Vector Register GPIO Interrupt Digital PSoC Blocks Introduction Digital PSoC Block Bank Registers Digital PSoC Block Bank Registers Global Inputs Outputs Available Programmed Digital Functionality 10.0 Analog PSoC Blocks 10.1 Introduction 10.2 Analog System Clocking Signals 10.3 Array Analog PSoC Blocks 10.4 Analog Reference Bias Control 10.5 AGND, REFHI, REFLO 10.6 Analog PSoC Block Clocking Options 10.7 Analog Clock Select Register
Copyright 2000-2002 Cypress MicroSystems Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
10.8 Analog Continuous Time PSoC Blocks 10.9 Analog Switch Type PSoC Blocks 10.10 Analog Switch Type PSoC Blocks 10.11 Analog Comparator .100 10.12 Analog Synchronization .100 10.13 Analog .102 10.14 Analog Modulator .105 10.15 Analog PSoC Block Functionality .106 10.16 Temperature Sensing Capability .107 11.0 Special Features .108 11.1 Multiplier/Accumulator .108 11.2 Decimator .111 11.3 Reset .113 11.4 Sleep States .115 11.5 Supply Voltage Monitor .117 11.6 Switch Mode Pump .118 11.7 Internal Voltage Reference .119 11.8 Supervisor ROM/System Supervisor Call Instruction .119 11.9 Flash Program Memory Protection .121 11.10 Programming Requirements Step Descriptions .121 11.11 Programming Wave Forms .123 11.12 Programming File Format .123 12.0 Development Tools .124 12.1 Overview .124 12.2 Integrated Development Environment Subsystems .125 12.3 Hardware Tools .125 13.0 Characteristics .126 13.1 Absolute Maximum Ratings .126 13.2 Characteristics .128 13.3 Characteristics .137 14.0 Packaging Information .142 14.1 Thermal Impedances Package .148 15.0 Ordering Guide .148
Spec.# 38-12006 R-3.19 Copyright 2000-2002 Cypress MicroSystems
List Tables
Table Device Family Features.14 Table Pin-out Table Pin-out Table Pin-out Table Pin-out Table Pin-out Table Registers Mnemonics Table Flags Register Table Accumulator Register (CPU_A).20 Table Index Register (CPU_X) Table Stack Pointer Register (CPU_SP) Table Program Counter Register (CPU_PC).21 Table Source Immediate Table Source Direct.22 Table Source Indexed Table Destination Direct Table Destination Indexed.23 Table Destination Direct Immediate Table Destination Indexed Immediate Table Destination Direct Direct.24 Table Source Indirect Post Increment Table Destination Indirect Post Increment.24 Table Instruction Summary (Sorted Mnemonic).25 Table Flash Program Memory Table Data Memory Table Bank Table Bank Table Port Data Registers Table Port Interrupt Enable Registers Table Port Global Select Registers Table Port Drive Mode Registers Table Port Drive Mode Registers Table Port Interrupt Control Registers.33 Table Port Interrupt Control Registers.34 Table Internal Main Oscillator Trim Register Table Internal Speed Oscillator Trim Register Table External Crystal Oscillator Trim Register.37 Table Typical Package Capacitances Table System Clocking Signals Definitions Table Oscillator Control Register.40 Table Oscillator Control Register.40 Table 24V1/24V2 Frequency Selection Table Interrupt Vector Table.44 Table General Interrupt Mask Register Table Digital PSoC Block Interrupt Mask Register
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Table Interrupt Vector Register Table Digital Basic Type Communications Type Block Function Register.50 Table Digital Basic Type Communications Type Block Input Register Table Digital Function Data Input Definitions Table Digital Basic Type Communications Type Block Output Register.53 Table Digital Function Outputs Table Digital Basic Type Communications Type Block Data Register 0,1,2.54 Table Variations User Module Selection Table Digital Basic Type Communications Type Block Control Register Table Digital Basic Type A/Communications Type Block Control Register 0.56 Table Digital Communications Type Block Control Register Table Digital Communications Type Block Control Register Table Digital Communications Type Block Control Register Table Global Input Assignments.60 Table Global Output Assignments.60 Table Analog System Clocking Signals.72 Table Analog Reference Control Register.73 Table Analog Column Clock Select Register.74 Table Analog Clock Select Register Table Analog Continuous Time Block Control Register.81 Table Analog Continuous Time Block Control Register.82 Table Analog Continuous Time Type Block Control Register Table Analog Switch Type Block Control Register Table Analog Switch Type Block Control Register Table Analog Switch Type Block Control Register Table Analog Switch Type Block Control Register Table Analog Switch Type Block Control Register Table Analog Switch Type Block Control Register Table Analog Switch Type Block Control Register Table Analog Switch Type Block Control Register Table Analog Comparator Control Register .100 Table Analog Frequency Relationships.101 Table Analog Synchronization Control Register.101 Table Analog Input Select Register .103 Table Analog Output Buffer Control Register .105 Table Analog Modulator Control Register .106 Table Multiply Input Register.109 Table Multiply Input Register.109 Table Multiply Result High Register .110 Table Multiply Result Register .110 Table Accumulator Result Multiply/Accumulator Input Register .110 Table Accumulator Result Multiply/Accumulator Input Register .110 Table Accumulator Result Multiply/Accumulator Clear Register .111 Table Accumulator Result Multiply/Accumulator Clear Register .111 Table Decimator/Incremental Control Register .112 Table Decimator Data High Register.112 Table Decimator Data Register.112 Table Processor Status Control Register .113 Table Reset Register.115 Table Voltage Monitor Control Register .117 Table Bandgap Trim Register.119 Table CY8C25122, CY8C26233, CY8C26443, CY8C26643 (256 Bytes SRAM) .120 Table Table Read Supervisory Call Functions .121 Table Flash Program Memory Protection.121
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Table 100: Programmer Requirements .121 Table 101: Absolute Maximum Ratings.126 Table 102: Temperature Specifications.127 Table 103: Operating Specifications .128 Table 104: Operational Amplifier Specifications .129 Table 105: 3.3V Operational Amplifier Specifications .130 Table 106: Analog Input with Multiplexer Specifications .131 Table 107: Analog Input Block Specifications .131 Table 108: Analog Output Buffer Specifications .131 Table 109: 3.3V Analog Output Buffer Specifications .132 Table 110: Switch Mode Pump Specifications .133 Table 111: Analog Reference Specifications .134 Table 112: 3.3V Analog Reference Specifications .135 Table 113: Analog PSoC Block Specifications.135 Table 114: Programming Specifications.136 Table 115: Operating Specifications.137 Table 116: Operational Amplifier Specifications .138 Table 117: 3.3V Operational Amplifier Specifications .139 Table 118: Analog Output Buffer Specifications .140 Table 119: 3.3V Analog Output Buffer Specifications .140 Table 120: Programming Specifications.141 Table 121: Thermal Impedances.148 Table 122: Ordering Guide .148
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
List Figures
Figure Block Diagram Figure CY8C25122 Figure CY8C26233 Figure 26443 PDIP/SOIC/SSOP Figure 26643 TQFP Figure 26643 PDIP/SSOP Figure General Purpose Pins Figure External Crystal Oscillator Connections Figure PSoC Clock Tree Signals Figure Interrupts Overview Figure GPIO Interrupt Enable Diagram Figure Digital Basic Digital Communications PSoC Blocks Figure Polynomial LFSR Figure Polynomial Figure Waveforms Figure Array Analog PSoC Blocks Figure NMux Connections Figure PMux Connections Figure RBotMux Connections Figure Analog Continuous Time PSoC Blocks Figure Analog Switch Type PSoC Blocks Figure AMux Connections Figure CMux Connections Figure BMuxSCA/SCB Connections Figure Analog Switch Type PSoC Blocks Figure Analog Input Muxing .102 Figure Analog Output Buffers .104 Figure Multiply/Accumulate Block Diagram .109 Figure Decimator Coefficients .111 Figure Execution Reset .114 Figure Three Sleep States .116 Figure Switch Mode Pump .118 Figure Programming Wave Forms .123 Figure PSoC Designer Functional Flow .124 Figure CY8C25xxx/CY8C26xxx Voltage Frequency Graph .126 Figure 44-Lead Thin Plastic Quad Flat Pack .142 Figure 20-Pin Shrunk Small Outline Package .143 Figure 28-Lead (210-Mil) Shrunk Small Outline Package .144 Figure 48-Lead Shrunk Small Outline Package .144 Figure 20-Lead (300-Mil) Molded .145 Figure 28-Lead (300-Mil) Molded .145 Figure 48-Lead (600-Mil) Molded .145 Figure 20-Lead (300-Mil) Molded SOIC .146 Figure 28-Lead (300-Mil) Molded SOIC .146 Figure 8-Lead (300-Mil) Molded .147
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Ports
Analog Input Muxing
Analog Output Drivers
Clocks Analog
Global Programmable Interconnect
Comparator Outputs
Array Analog PSoC Blocks Flash Program Memory
SRAM Memory
Array Digital PSoC Blocks
Oscillator Multiply Accumulate
Core
Internal System
Decimator
Watchdog/ Sleep Timer
LVD/POR
Interrupt Controller
Figure Block Diagram
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Functional Overview
mode, user select drive strength desired. serve interrupt source, selected trigger positive edges, negative edges, change. Digital signal sources routed directly from digital PSoC blocks. Some pins have additional capability route analog signals analog PSoC blocks. Multiple oscillator options available clocking CPU, analog PSoC blocks digital PSoC blocks. These options include internal main oscillator running 48/24 MHz, external crystal oscillator with 32.768 watch crystal, internal lowspeed oscillator clocking PSoC blocks Watchdog/Sleep timer. User selectable clock divisors allow optimizing code execution speed power trade-offs. different device types this family provide various amounts code data memory. code space ranges size from bytes user programmable Flash memory. This memory programmed serially either programming user board. endurance Flash memory 100,000 erase/write cycles. data space bytes user SRAM. powerful flexible protection model secures user's sensitive information. This model allows user selectively lock blocks memory read write protection. This allows partial code updates without exposing proprietary information. Devices this family range from pins through pins PDIP, SOIC SSOP packages.
heart this next generation family microcontrollers high performance, 8-bit, Harvard architecture microprocessor. Separate program memory busses allow faster overall throughput. Processor clock speeds available. processor also lower clock speeds powersensitive applications. rich instruction allows efficient low-level language support. devices this family include both analog digital configurable peripherals (PSoC blocks). These blocks enable user define unique functions during configuration device. Included twelve analog PSoC blocks eight digital PSoC blocks. Potential applications digital PSoC blocks timers, counters, UARTs, generators, PWMs, other functions. analog PSoC blocks used ADCs, Multi-slope ADCs, programmable gain amplifiers, programmable filters, DACs, other functions. Higher order User Modules such modems, complex motor controllers, complete sensor signal chains created from these building blocks. This allows unprecedented level flexibility integration microcontroller-based systems. Multiplier/Accumulator (MAC) available devices this family. implemented this device peripheral that mapped into register space. When instruction writes input registers, result multiply 32-bit accumulate available read from output registers next instruction cycle. number general purpose I/Os available this family parts range from Each these pins variety programmable options. output
Table
Features
Device Family Features CY8C25122 93.7kHz 24MHz 5.25V PDIP CY8C26233 93.7kHz 24MHz 5.25V PDIP SOIC SSOP CY8C26443 93.7kHz 24MHz 5.25V PDIP SOIC SSOP CY8C26643 93.7kHz 24MHz 5.25V 40/44 PDIP SSOP TQFP
Operating Frequency Operating Voltage Program Memory (KBytes) Data Memory (Bytes) Digital PSoC Blocks Analog PSoC Blocks Pins External Switch Mode Pump Available Packages
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Functional Overview
Table Name
Pin-out Descriptions
Pin-out Description Table Name
Pin-out
Description
P0[7] P0[5] P1[1] P1[0] P0[2] P0[4]
Power Power
Port 0[7] (Analog Input) Port 0[5] (Analog Input/Output) Port 1[1] XtalIn SCLK Ground Port 1[0] XtalOut SDATA Port 0[2] (Analog Input/Output) Port 0[4] (Analog Input/Output) Supply Voltage
P0[7] P0[5] P0[3] P0[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] P0[0] P0[2] P0[4] P0[6]
Power Power
Port 0[7] (Analog Input) Port 0[5] (Analog Input/Output) Port 0[3] (Analog Input/Output) Port 0[1] (Analog Input) Switch Mode Pump Port 1[7] Port 1[5] Port 1[3] Port 1[1] XtalIn SCLK Ground Port 1[0] XtalOut SDATA Port 1[2] Port 1[4] Port 1[6] External Reset Port 0[0] (Analog Input) Port 0[2] (Analog Input/Output) Port 0[4] (Analog Input/Output) Port 0[6] (Analog Input) Supply Voltage
CY8C25122
P0[7] P0[5]
XtalIn/SCLK/P1[1]
P0[4] P0[2]
P1[0]/XtalOut/SDATA
XRES
Figure CY8C25122
CY8C26233 PDIP/SOIC/SSOP
P0[7] P0[5] P0[3] P0[1] P1[7] P1[5] P1[3]
XtalIn/SCLK/P1[1]
P0[6] P0[4] P0[2] P0[0] XRES P1[6] P1[4] P1[2]
P1[0]/XtalOut/SDATA
Figure CY8C26233
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Table Name
Pin-out Description
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3]
XtalIn/SCLK/P1[1]
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6]
Power Power
Port 0[7] (Analog Input) Port 0[5] (Analog Input/ Out2 put) Port 0[3] (Analog Input/ Output)
Port 0[1] (Analog Input) Port 2[7] Port 2[5] Port 2[3] (Non-Multiplexed Analog Input) Port 2[1] (Non-Multiplexed Analog Input)
P0[6] P0[4] P0[2] P0[0] P2[6]/External P2[4]/External AGND P2[2] P2[0] Xres P1[6] P1[4] P1[2]
P1[0]/XtalOut/SDATA
Figure 26443 PDIP/SOIC/SSOP
26443 PDIP/SOIC/SSOP
Switch Mode Pump Port 1[7] Port 1[5] Port 1[3] Port 1[1] XtalIn SCLK Ground Port 1[0] XtalOut SDATA Port 1[2] Port 1[4] Port 1[6] External Reset Port 2[0] (Non-Multiplexed Analog Input)
Table Name
Pin-out
Description
P2[5] P2[3] P2[1] P3[7] P3[5] P3[3] P3[1] P4[7] P4[5] P4[3] P4[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] P4[0] P4[2] P4[4]
Power
Port 2[5] Port 2[3] (Non-Multiplexed Analog Input) Port 2[1] (Non-Multiplexed Analog Input)
Port 3[7] Port 3[5] Port 3[3] Port 3[1] Switch Mode Pump Port 4[7] Port 4[5] Port 4[3] Port 4[1] Port 1[7] Port 1[5] Port 1[3] Port 1[1] XtalIn SCLK Ground Port 1[0] XtalOut SDATA Port 1[2] Port 1[4] Port 1[6] Port 4[0] Port 4[2] Port 4[4]
Port 2[2] (Non-Multiplexed Analog Input) Port 2[4] External AGNDIn Port 2[6] External VREFIn Port 0[0] (Analog Input) Port 0[2] (Analog Input/Output) Port 0[4] (Analog Input/Output)
Port 0[6] (Analog Input) Supply Voltage
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Functional Overview
Table
Pin-out Pin, continued
Power Port 4[6] External Reset Port 3[0] Port 3[2] Port 3[4] Port 3[6] Port 2[0] (Non-Multiplexed Analog Input)
P4[6] XRES P3[0] P3[2] P3[4] P3[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1] P2[7]
Table Name
Pin-out
Description
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P3[7] P3[5] P3[3] P3[1] P4[7] P4[5] P4[3] P4[1] P5[3] P5[1]
Power
Port 0[7] (Analog Input) Port 0[5] (Analog Input/Output) Port 0[3] (Analog Input/Output)
Port 0[1] (Analog Input) Port 2[7] Port 2[5] Port 2[3] (Non-Multiplexed Analog Input) Port 2[1] (Non-Multiplexed Analog Input)
Port 2[2] (Non-Multiplexed Analog Input) Port 2[4] External AGNDIn Port 2[6] External VREFIn Port 0[0] (Analog Input) Port 0[2] (Analog Input/Output) Port 0[4] (Analog Input/Output) Port 0[6] (Analog Input) Supply Voltage Port 0[7] (Analog Input) Port 0[5] (Analog Input/Output) Port 0[3] (Analog Input/Output) Port 0[1] (Analog Input) Port 2[7]
Port 3[7] Port 3[5] Port 3[3] Port 3[1] Switch Mode Pump Port 4[7] Port 4[5] Port 4[3] Port 4[1] Port 5[3] Port 5[1] Port 1[7] Port 1[5] Port 1[3] Port 1[1] XtalIn SCLK Ground Port 1[0] XtalOut SDATA Port 1[2] Port 1[4] Port 1[6]
P2[6]/ExVrefIn
P1[7] P1[5] P1[3] P1[1]
P2[4]/Ex AGNDIn
P2[5] P2[3] P2[1] P3[7] P3[5] P3[3] P3[1] P4[7] P4[5] P4[3]
P4[1] P1[7] P1[5] P1[3] XtalIn/SCLK/P1[1] XtalOut/SDATA/P1[0] P1[2] P1[4] P1[6] P4[0]
P2[7] P0[1] P0[3] P0[5] P0[7] P0[6] P0[4] P0[2] P0[0]
P2[2] P2[0] P3[6] P3[4] P3[2] P3[0] Xres P4[6] P4[4] P4[2]
P1[0] P1[2] P1[4] P1[6]
Figure 26643 TQFP
Copyright 2000-2002 Cypress MicroSystems
26643 TQFP
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Table
Pin-out Pin, continued
Power Port 5[0] Port 5[2] Port 4[0] Port 4[2] Port 4[4] Port 4[6] External Reset Port 3[0] Port 3[2] Port 3[4] Port 3[6] Port 2[0] (Non-Multiplexed Analog Input) Port 2[2] (Non-Multiplexed Analog Input)
P5[0] P5[2] P4[0] P4[2] P4[4] P4[6] XRES P3[0] P3[2] P3[4] P3[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6]
Port 2[4] External AGNDIn Port 2[6] External VREFIn Port 0[0] (Analog Input) Port 0[2] (Analog Input/Output) Port 0[4] (Analog Input/Output)
Port 0[6] (Analog Input) Supply Voltage
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P3[7] P3[5] P3[3] P3[1] P4[7] P4[5] P4[3] P4[1] P5[3] P5[1] P1[7] P1[5] P1[3]
XtalIn/SCLK/P1[1]
P0[6] P0[4] P0[2] P0[0] P2[6]/External P2[4] /External AGNDIN P2[2] P2[0] P3[6] P3[4] P3[2] P3[0] Xres P4[6] P4[4] P4[2] P4[0] P5[2] P5[0] P1[6] P1[4] P1[2]
P1[0]/XtalOut/SDATA
Figure 26643 PDIP/SSOP
26643 PDIP/SSOP
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Architecture
Architecture Introduction
instructions, which manage software stack. also affected SWAP instructions. Flag Register (CPU_F) three status bits: Zero Flag [1]; Carry Flag [2]; Supervisory State [3]. Global Interrupt Enable used globally enable disable interrupts. extended space address, [4], used determine which bank register space use. user cannot manipulate Supervisory State status [3]. flags affected arithmetic, logic, shift operations. manner which each flag changed dependent upon instruction being executed (i.e., AND, XOR. Table page 25).
This family microcontrollers based high performance, 8-bit, Harvard architecture microprocessor. Five registers control primary operation core. These registers affected various instructions, directly accessible through register space user. more details addressing with register space, section 4.0.
Table Registers Mnemonics Register Mnemonic
Flags Program Counter Accumulator Stack Pointer Index
CPU_F CPU_PC CPU_A CPU_SP CPU_X
Program Counter Register (CPU_PC) allows direct addressing full Kbytes program memory space available largest members this family. This forms contiguous program space, paging required. Accumulator Register (CPU_A) general-purpose register that holds results instructions that specify source addressing modes. Index Register (CPU_X) holds offset value that used indexed addressing modes. Typically, this used address block data within data memory space. Stack Pointer Register (CPU_SP) holds address current top-of-stack data memory space. affected PUSH, POP, LCALL, CALL, RETI,
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
2.2.1
Registers
Flags Register
Flags Register only reset with logical instruction.
Table Read/ Write Name Flags Register
-Reserved
-Reserved
-Reserved
Super
Carry
Zero
Global
Reserved Reserved Reserved user select between register banks Bank Bank Super Indicates whether executing user code Supervisor Code. (This code cannot accessed directly user displayed debugger.) User Code Supervisor Code Carry indicate whether there been carry previous logical/arithmetic operation Carry Carry Zero indicate whether there been zero result previous logical/arithmetic operation Equal Zero Equal Zero Global Determines whether interrupts enabled disabled Disabled Enabled
2.2.2
Table
Accumulator Register
Accumulator Register (CPU_A)
Read/Write Name
System1 Data
System1 Data
System1 Data
System1 Data
System1 Data
System1 Data
System1 Data
System1 Data
[7:0]: Data [7:0] 8-bit data value holds result logical/arithmetic instruction that uses source addressing mode
System directly accessible user
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Architecture
2.2.3
Index Register
Index Register (CPU_X)
Table Read/ Write Name
System1 Data
System1 Data
System1 Data
System1 Data
System1 Data
System1 Data
System1 Data
System1 Data
[7:0]: Data [7:0] 8-bit data value holds index instruction that uses indexed addressing mode
System directly accessible user
2.2.4
Stack Pointer Register
Stack Pointer Register (CPU_SP)
Table Read/ Write Name
System1 Data
System1 Data
System1 Data
System1 Data
System1 Data
System1 Data
System1 Data
System1 Data
[7:0]: Data [7:0] 8-bit data value holds pointer current top-of-stack
System directly accessible user
2.2.5
Program Counter Register
Program Counter Register (CPU_PC)
Table Read/ Write Name
Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data [15] [14] [13] [12] [11] [10]
Data
[15:0]: Data [15:0] 16-bit data value low-order/high-order byte Program Counter
System directly accessible user
2.3.1
Addressing Modes
Source Immediate
require sources. Instructions using this addressing mode bytes length.
result instruction using this addressing mode placed register, register, register, register, which specified part instruction opcode. Operand immediate value that serves source instruction. Arithmetic instructions
Table
Opcode
Source Immediate
Operand
Instruction
Immediate Value
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Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Examples: this case, immediate ;value added with ;Accumulator, result placed ;Accumulator. this case, immediate ;value moved ;register. this case, immediate ;value logically ;ANDed with register ;and result placed ;the register.
added register forming address that points location either memory space register space that source instruction. Arithmetic instructions require sources, second source register register specified opcode. Instructions using this addressing mode bytes.
Table
Opcode
Source Indexed
Operand
Instruction
Examples:
Source Index
2.3.2
Source Direct
[X+7]
result instruction using this addressing mode placed either register register, which specified part instruction opcode. Operand address that points location either memory space register space that source instruction. Arithmetic instructions require sources, second source register register specified opcode. Instructions using this addressing mode bytes length.
this case, ;value memory ;location address added with ;the Accumulator, ;the result placed Accumulator. this case, ;value ;register space ;address ;moved ;register.
REG[X+8]
Table
Opcode
Source Direct
Operand
2.3.4
Destination Direct
result instruction using this addressing mode placed within either memory space register space. Operand address that points location result. source instruction either register register, which specified
Instruction
Examples:
Source Address
this case, ;value ;memory location ;address added ;with Accumulator, ;and result ;placed ;Accumulator.
part instruction opcode. Arithmetic instructions require sources, second source location specified Operand Instructions using this addressing mode bytes length.
Table
Opcode
Destination Direct
Operand
this case, ;value register REG[8] ;space address ;moved ;register.
Instruction
Destination Address
2.3.3
Source Indexed
result instruction using this addressing mode placed either register register, which specified part instruction opcode. Operand
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Architecture
Examples: this case, ;value memory ;location address added with ;Accumulator, ;result placed ;the memory location address ;Accumulator ;unchanged. this case, ;Accumulator moved register ;space location ;address ;Accumulator ;unchanged.
source instruction Operand which immediate value. Arithmetic instructions require sources, second source location specified Operand Instructions using this addressing mode three bytes length.
[7],
Table
Opcode
Destination Direct Immediate
Operand Operand
Instruction
Examples:
Destination Address Immediate Value
REG[8],
[7],
2.3.5
Destination Indexed
REG[8],
this case, value ;the memory location ;address added ;the immediate value result ;placed memory ;location address this case, ;immediate value ;moved into register ;space location ;address
result instruction using this addressing mode placed within either memory space register space. Operand added register forming address that points location result. source instruction register. Arithmetic instructions require sources, second source location specified Operand added with register. Instructions using this addressing mode bytes length.
2.3.7
Destination Indexed Immediate
result instruction using this addressing mode placed within either memory space register space. Operand added register form address result. source instruction Operand which immediate value. Arithmetic instructions require sources, second source location specified Operand added with register. Instructions using this addressing mode three bytes length.
Table
Opcode
Destination Indexed
Operand
Instruction
Example:
Destination Index
[X+7],
this case, value memory location address added ;with Accumulator, ;and result placed memory location address x+7. ;Accumulator ;unchanged.
Table
Opcode
Destination Indexed Immediate
Operand Operand
Instruction
Destination Index
Immediate Value
2.3.6
Destination Direct Immediate
result instruction using this addressing mode placed within either memory space register space. Operand address result.
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Examples: this case, ;value memory ;location address ;X+7 added with ;the immediate value result placed ;memory location ;address X+7. this case, ;immediate value moved into ;location ;register space ;address X+8.
Language User Guide further details instruc-
tion.
Table
Opcode
Source Indirect Post Increment
Operand
[X+7],
Instruction
Example:
Source Address Address
REG[X+8],
2.3.8
Destination Direct Direct
this case, value memory location ;address indirect ;address. memory ;location pointed ;the indirect address ;moved into ;Accumulator. ;indirect address then ;incremented.
result instruction using this addressing mode placed within memory. Operand address result. Operand address that points location memory that source instruction. This addressing mode only valid instruction. instruction using this addressing mode three bytes length.
2.3.10 Destination Indirect Post Increment
result instruction using this addressing mode placed within memory space. Operand address pointing location within memory space, which contains address (the indirect address) destination instruction. indirect address incremented part instruction execution. source instruction Accumulator. This addressing mode only valid instruction. instruction using this addressing mode bytes length.
Table
Opcode
Destination Direct Direct
Operand Operand
Instruction
Example:
Destination Address Source Address
this case, value memory location [7], ;address moved ;memory location ;address
Table
Opcode
Destination Indirect Post Increment
Operand
Instruction
Example:
Destination Address Address
2.3.9
Source Indirect Post Increment
result instruction using this addressing mode placed Accumulator. Operand address pointing location within memory space, which contains address (the indirect address) source instruction. indirect address incremented part instruction execution. This addressing mode only valid instruction. instruction using this addressing mode bytes length. Section Instruction PSoC Designer: Assembly [8],
this case, ;value memory ;location address indirect ;address. ;Accumulator moved ;into memory ;location pointed ;the indirect address. ;The indirect address then incremented.
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Architecture
Opcode
Instruction Summary
Instruction Summary (Sorted Mnemonic)
Instruction Format Bytes Cycles Flags Instruction Format Bytes Cycles Flags Instruction Format Bytes Cycles Flags Opcode Opcode
Table
expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr expr expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr expr reg[expr], expr reg[X+expr], expr [expr] [X+expr] [expr] [X+expr] CALL expr (A=B) [expr] (A<B) [X+expr] [expr], expr [X+expr], expr [expr] [X+expr] HALT Note: Interrupt acknowledge Interrupt Vector table cycles.
[expr] [X+expr] INDEX JACC LCALL LJMP expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr expr [expr] [X+expr] [expr], reg[expr] reg[X+expr] [expr], [expr] reg[expr], reg[X+expr], reg[expr], expr reg[X+expr], expr [expr]++ [expr]++ expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr reg[expr], expr reg[X+expr], expr expr
PUSH PUSH RETI [expr] [X+expr] ROMX [expr] [X+expr] expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr SWAP SWAP [expr] SWAP [expr] SWAP [expr], expr [X+expr], expr reg[expr], expr reg[X+expr], expr expr expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr reg[expr], expr reg[X+expr], expr
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Memory Organization Flash Program Memory Organization
Flash Program Memory Description
Data Memory Organization
stack this device grows from addresses high addresses. Linker function within PSoC Designer locates bottom stack after Global Variables. This allows stack grow from just after Global Variables until 0xFF. stack will wrap back 0x00 overflow condition.
Table Address Data Memory Description
Table Address
0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040
Reset Vector Supply Monitor Interrupt Vector PSoC Block Interrupt Vector PSoC Block Interrupt Vector PSoC Block Interrupt Vector PSoC Block Interrupt Vector PSoC Block Interrupt Vector PSoC Block Interrupt Vector PSoC Block Interrupt Vector PSoC Block Interrupt Vector Analog Column Interrupt Vector Analog Column Interrupt Vector Analog Column Interrupt Vector Analog Column Interrupt Vector GPIO Interrupt Vector Sleep Timer Interrupt Vector On-Chip User Program Memory Starts Here Flash Maximum Depending Version
0x00 0xXX 0xXY 0xXZ 0xYX 0xYY 0xFF
First General Purpose Location General Purpose General Purpose Last General Purpose Location Bottom Hardware Stack
Stack Grows This
Hardware Stack
Register Organization Introduction
There register banks implemented these devices. Each bank contains addresses. purpose these register banks personalize parameterize on-chip resources well read write data values. user selects between banks setting CPU_F Flag Register. some cases, same register available either bank, convenience. These registers (71h 9fh) accessed from either bank. Note: register addresses shown reserved should never written. addition, unused reserved bits register should always written
0x3FFF
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Register Organization
Register Bank
Bank
Data Sheet Page Data Sheet Page Data Sheet Page Data Sheet Page Address Register Name Address Register Name Address Register Name Address Access Access Access Access
Table
Register Name PRT0DR PRT0IE PRT0GS Reserved PRT1DR PRT1IE PRT1GS Reserved PRT2DR PRT2IE PRT2GS Reserved PRT3DR PRT3IE PRT3GS Reserved PRT4DR PRT4IE PRT4GS Reserved PRT5DR PRT5IE PRT5GS DBA00DR0 DBA00DR1 DBA00DR2 DBA00CR0 DBA01DR0 DBA01DR1 DBA01DR2 DBA01CR0 DBA02DR0 DBA02DR1 DBA02DR2 DBA02CR0 DBA03DR0 DBA03DR1 DBA03DR2 DBA03CR0 DCA04DR0 DCA04DR1 DCA04DR2 DCA04CR0 DCA05DR0 DCA05DR1 DCA05DR2 DCA05CR0 DCA06DR0 DCA06DR1 DCA06DR2 DCA06CR0 DCA07DR0 DCA07DR1 DCA07DR2 DCA07CR0 Reserved
AMX_IN Reserved ARF_CR CMP_CR ASY_CR
ACA00CR0 ACA00CR1 ACA00CR2 Reserved ACA01CR0 ACA01CR1 ACA01CR2 Reserved ACA02CR0 ACA02CR1 ACA02CR2 Reserved ACA03CR0 ACA03CR1 ACA03CR2
ASA10CR0 ASA10CR1 ASA10CR2 ASA10CR3 ASB11CR0 ASB11CR1 ASB11CR2 ASB11CR3 ASA12CR0 ASA12CR1 ASA12CR2 ASA12CR3 ASB13CR0 ASB13CR1 ASB13CR2 ASB13CR3 ASB20CR0 ASB20CR1 ASB20CR2 ASB20CR3 ASA21CR0 ASA21CR1 ASA21CR2 ASA21CR3 ASB22CR0 ASB22CR1 ASB22CR2 ASB22CR3 ASA23CR0 ASA23CR1 ASA23CR2 ASA23CR3
INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH/DEC_CL DEC_DL DEC_CR Reserved MUL_X MUL_Y MUL_DH MUL_DL ACC_DR1/MAC_X ACC_DR0/MAC_Y ACC_DR3/MAC_CL0 ACC_DR2/MAC_CL1 CPU_SCR Reserved Reserved
Copyright 2000-2002 Cypress MicroSystems
Reserved Reserved
Spec.# 38-12006 R-3.19
Reserved
Cypress MicroSystems Family Data Sheet
Register Bank
Bank
Data Sheet Data Sheet Data Sheet Data Sheet
Table Register Name
PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Reserved DBA00FN DBA00IN DBA00OU Reserved DBA01FN DBA01IN DBA01OU Reserved DBA02FN DBA02IN DBA02OU Reserved DBA03FN DBA03IN DBA03OU Reserved DCA04FN DCA04IN DCA04OU Reserved DCA05FN DCA05IN DCA05OU Reserved DCA06FN DCA06IN DCA06OU Reserved DCA07FN DCA07IN DCA07OU Reserved
Address
Register Name
Address
Register Name
Address
Register Name
Address
Access
Access
Access
Access
Page
Page
Page
Page
CLK_CR0 CLK_CR1 ABF_CR AMD_CR Reserved
ACA00CR0 ACA00CR1 ACA00CR2 Reserved ACA01CR0 ACA01CR1 ACA01CR2 Reserved ACA02CR0 ACA02CR1 ACA02CR2 Reserved ACA03CR0 ACA03CR1 ACA03CR2
ASA10CR0 ASA10CR1 ASA10CR2 ASA10CR3 ASB11CR0 ASB11CR1 ASB11CR2 ASB11CR3 ASA12CR0 ASA12CR1 ASA12CR2 ASA12CR3 ASB13CR0 ASB13CR1 ASB13CR2 ASB13CR3 ASB20CR0 ASB20CR1 ASB20CR2 ASB20CR3 ASA21CR0 ASA21CR1 ASA21CR2 ASA21CR3 ASB22CR0 ASB22CR1 ASB22CR2 ASB22CR3 ASA23CR0 ASA23CR1 ASA23CR2 ASA23CR3
OSC_CR0 OSC_CR1 Reserved VLT_CR Reserved Reserved Reserved Reserved IMO_TR ILO_TR BDG_TR ECO_TR
CPU_SCR
Reserved
Reserved
Reserved
Reserved
Read/Write access bit-specific varies function. register.
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Ports
Ports Introduction
Port used conjunction with device Test Mode will function output approximately after XRES. After negating XRES, will held approximately This does prevent from writing this Data Register (PRT0DR, However, written data will appear output until after delay. There restrictions when using input. addition, also configured (e.g., drive strength, interrupts) during this time. device reset with Power Reset (POR) will exhibit this problem because there hold-off time approximately before code execution begins. Port Port have additional analog input and/or analog output capability. specific routing multiplexing analog signals shown following diagram:
five 8-bit-wide ports (P0-P4) 4-bit wide port (P5) implemented. number general purpose I/Os implemented connected pins depends individual part chosen. port bits independently programmable have following capabilities: General-purpose digital input readable CPU. General-purpose digital output writable CPU. Independent control data direction each port bit. Independent access each port Global Input Global Output busses. Interrupt programmable assert rising edge, falling edge, change from last state read. Output drive strength programmable logic states strong, resistive (pull-up pull-down), high impedance.
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
GPIO InterruptEnable (INT_MSK0:5)
Rise
From Other GPIO Pins
GPIO
Fall
Interrupt Mode Output Suppress Interrupt Falling Edge Rising Edge Change from last read
GPIO Read
Change
Global Select
Global Input Line Analog (Ports Only)
Bonding
Analog (Port Only) Drive Mode 5.6K
GPIO Write Global Global Select 5.6K
Output Resistive Pulldown Strong Drive High (off) Resistive Pullup
Figure General Purpose Pins
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Registers
Registers Port Data Registers
Port Data Registers
Table
Data
Data
Data
Data
Data
Data
Data
Data
Read/Write Name
[7:0]: Data [7:0] When written bits output port pins. When read state port pins
Port Data Register (PRT0DR, Address Bank 00h) Port Data Register (PRT1DR, Address Bank 04h) Port Data Register (PRT2DR, Address Bank 08h) Port Data Register (PRT3DR, Address Bank 0Ch) Port Data Register (PRT4DR, Address Bank 10h) Port Data Register (PRT5DR, Address Bank 14h) Note: Port 4-bits wide, [3:0]
Port Interrupt Enable Registers
Port Interrupt Enable Registers
Table
Read/Write Name
[7:0]: [7:0] When written sets interrupt state Interrupt disabled Interrupt enabled
Port Interrupt Enable Register (PRT0IE, Address Bank 01h) Port Interrupt Enable Register (PRT1IE, Address Bank 05h) Port Interrupt Enable Register (PRT2IE, Address Bank 09h) Port Interrupt Enable Register (PRT3IE, Address Bank 0Dh) Port Interrupt Enable Register (PRT4IE, Address Bank 11h) Port Interrupt Enable Register (PRT5IE, Address Bank 15h) Note: Port 4-bits wide
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Port Global Select Registers
Port Global Select Registers
Table
GlobSel
GlobSel
GlobSel
GlobSel
GlobSel
GlobSel
GlobSel
GlobSel
Read/Write Name
[7:0]: Global Select [7:0] When written determines whether connected Global Input Global Output Connected Connected
Drive Mode Global Select Register Standard controlled port (Default) Drive Mode (High Global Select Register Direct Drive associated Global Input line Drive Mode Global Select Register Direct Receive from associated Global Output line Port Global Select Register (PRT0GS, Address Bank 02h) Port Global Select Register (PRT1GS, Address Bank 06h) Port Global Select Register (PRT2GS, Address Bank 0Ah) Port Global Select Register (PRT3GS, Address Bank 0Eh) Port Global Select Register (PRT4GS, Address Bank 12h) Port Global Select Register (PRT5GS, Address Bank 16h) Note: implemented, Port 4-bits wide
6.3.1
Port Drive Mode Registers
Port Drive Mode Registers
Table Read/Write Name
[7:0]: [7:0] Drive Mode bits that control particular port treated pair decoded follows:
Port Data Register Drive Mode Resistive (Default) Port Data Register Drive Mode Strong Port Data Register Drive Mode High Port Data Register Drive Mode Strong Port Data Register Drive Mode Strong Port Data Register Drive Mode Strong Port Data Register Drive Mode High Port Data Register Drive Mode Resistive Port Drive Mode Register (PRT0DM0, Address Bank 00h) Port Drive Mode Register (PRT1DM0, Address Bank 04h) Port Drive Mode Register (PRT2DM0, Address Bank 08h) Port Drive Mode Register (PRT3DM0, Address Bank 0Ch) Port Drive Mode Register (PRT4DM0, Address Bank 10h) Port Drive Mode Register (PRT5DM0, Address Bank 14h) Note: Port 4-bits wide
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Registers
6.3.2
Port Drive Mode Registers
Port Drive Mode Registers
Table
Read/Write Name
[7:0]: [7:0] truth table Port Drive Mode Registers, above
Port Drive Mode Register (PRT0DM1, Address Bank 01h) Port Drive Mode Register (PRT1DM1, Address Bank 05h) Port Drive Mode Register (PRT2DM1, Address Bank 09h) Port Drive Mode Register (PRT3DM1, Address Bank 0Dh) Port Drive Mode Register (PRT4DM1, Address Bank 11h) Port Drive Mode Register (PRT5DM1, Address Bank 15h) Note: Port 4-bits wide
6.3.3
Port Interrupt Control Registers
Port Interrupt Control Registers
Table
Read/Write Name
[7:0]: [7:0] Interrupt Control bits that control particular port treated pair decoded follows: [x], Disabled (Default) [x], Falling Edge [x], Rising Edge [x], Change from Last Direct Read
Port Interrupt Control Register (PRT0IC0, Address Bank 02h) Port Interrupt Control Register (PRT1IC0, Address Bank 06h) Port Interrupt Control Register (PRT2IC0, Address Bank 0Ah) Port Interrupt Control Register (PRT3IC0, Address Bank 0Eh) Port Interrupt Control Register (PRT4IC0, Address Bank 12h) Port Interrupt Control Register (PRT5IC0, Address Bank 16h) Note: Port 4-bits wide
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
6.3.4
Port Interrupt Control Registers
Port Interrupt Control Registers
Table Read/ Write Name
[7:0]: [7:0] truth table Port Interrupt Control Registers, above
Port Interrupt Control Register (PRT0IC1, Address Bank 03h) Port Interrupt Control Register (PRT1IC1, Address Bank 07h) Port Interrupt Control Register (PRT2IC1, Address Bank 0Bh) Port Interrupt Control Register (PRT3IC1, Address Bank 0Fh) Port Interrupt Control Register (PRT4IC1, Address Bank 13h) Port Interrupt Control Register (PRT5IC1, Address Bank 17h) Note: Port 4-bits wide
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Clocking
7.1.1
Clocking Oscillator Options
Internal Main Oscillator
which factory calibration set. factory-programmed trim value selected using Table Read Supervisor Call, documented 11.8. There option phase lock this oscillator External Crystal Oscillator. choice crystal inherent accuracy will determine overall accuracy oscillator. External Crystal Oscillator must stable prior locking frequency Internal Main Oscillator this reference source.
internal main oscillator outputs frequencies, MHz. absence high-precision input source from external oscillator, accuracy this circuit 2.5% (between +85oC). external components required achieve this level accuracy. Internal Main Oscillator Trim Register (IMO_TR) used calibrate this oscillator into specified tolerance. Factory-programmed trim values available 5.0V 3.3V operation. 5.0V value loaded IMO_TR register upon reset. This register must adjusted when operating voltage outside range
Table
Internal Main Oscillator Trim Register
Trim
Trim
Trim
Trim
Trim
Trim
Trim
Trim
Read/Write Name
[7:0]: Trim [7:0] Data value stored will alter trimmed frequency Internal Main Oscillator. larger value this register will increase speed Internal Main Oscillator
Factory trim value
Internal Main Oscillator Trim Register (IMO_TR, Address Bank E8h)
7.1.2
Internal Speed Oscillator
internal speed oscillator nominally available generate sleep wake-up interrupts Watchdog resets user does want attach 32.768 watch crystal. This oscillator also used clocking source digital PSoC blocks. oscillator operates different modes. trim value written Internal Speed Oscillator Trim Register (ILO_TR), shown below, upon reset. section 13.0 accuracy information. When into sleep mode this oscillator drops into ultra current state accuracy reduced. This register sets adjustment Internal Speed Oscillator. value placed this register based factory testing. recommended that user alter this value.
Copyright 2000-2002 Cypress MicroSystems Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Table Read/ Write Name
Internal Speed Oscillator Trim Register
-Reserved
Disable
Trim
Trim
Trim
Trim
Trim
Trim
Reserved Disable Speed Oscillator Speed Oscillator (minimum power state) [5:0]: Trim [5:0] Data value stored will alter trimmed frequency Internal Speed Oscillator. (Not recommended customer alteration)
Factory trim value
Internal Speed Oscillator Trim Register (ILO_TR, Address Bank E9h)
7.1.3
External Crystal Oscillator
interval, created Sleep Interrupt logic. 1-second interval gives oscillator time stabilize before becomes active source. Sleep Interrupt need enabled switch over occur. user want reset sleep timer this does interfere with ongoing real-time clock operation), guarantee interval length. user must wait 1-second stabilization period prior engaging mode lock Internal Main Oscillator frequency External Crystal Oscillator frequency.
XtalIn XtalOut pins support connection 32.768 watch crystal drive clock. connect external crystal, XtalIn XtalOut pins' drive modes must High enable external crystal oscillator, Oscillator Control Register (OSC_CR0) must (default off). Note that Internal Speed Oscillator continues when this external function selected. runs until oscillator automatically switched over when sleep timer reaches terminal count. External feedback capacitors required. firmware steps involved switching between Internal Speed Oscillator External Crystal Oscillator follows: reset, chip begins operation using Internal Speed Oscillator. User immediately selects sleep interval second Oscillator Control Register (OSC_CR0), oscillator stabilization interval. User selects External Crystal Oscillator setting Oscillator Control Register (OSC_CR0) External Crystal Oscillator becomes selected 32.768 source 1-sec-
proper settings selected PSoC Designer, above steps automatically done boot.asm.
Note: Transitions between oscillator domains pro-
duce glitches clock bus. Functions that require accuracy clock should enabled after transition oscillator domains. External Crystal Oscillator Trim Register (ECO_TR) sets adjustment External Crystal Oscillator. value placed this register reset based factory testing. This register does adjust frequency External Crystal Oscillator. recommended that user alter this value.
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Clocking
Table Read/Write Name
External Crystal Oscillator Trim Register
-Reserved
-Reserved
Bias
Bias
PSSDC PSSDC
[7:6]: PSSDC [1:0] Power System Sleep Duty Cycle. (Not recommended customer alteration) 1/128 1/512 1/32 Reserved Reserved [3:2]: [1:0] Sets amplitude adjustment. (Not recommended customer alteration) [1:0]: Bias [1:0] Sets bias adjustment. (Not recommended customer alteration)
Factory trim value
External Crystal Oscillator Trim Register (ECO_TR, Address Bank EBh)
7.1.4
External Crystal Oscillator Component Connections Selections
XtalIn Crys
XtalOut
Figure External Crystal Oscillator Connections
Crystal 32.768 watch crystal such EPSON C-002RX (12.5 load capacitance) Capacitors NPO-type ceramic caps (Package Cap) (Board Parasitic Cap)
Note: this equation employ mode. Table Package Typical Package Capacitances Package Capacitance
PDIP PDIP SOIC SSOP PDIP SOIC SSOP TQFP PDIP SSOP
employ with External Crystal Oscillator, Application Note AN2027 under Support http:// www.cypressmicro.com equation details. error gives about error frequency.
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
7.1.5
Phase-Locked Loop (PLL) Operation
Select frequency less. Enable PLL. Wait least faster frequency, desired. this, write bits CPU[20] USC_CPU register. frequency will immediately change when these bits set.
Phase-Locked Loop (PLL) function generates system clock with crystal accuracy. designed provide 23.986 oscillator when utilized with external 32.768 crystal. Although provides crystal accuracy requires time lock onto reference frequency when first starting. After External Crystal Oscillator been selected enabled, following procedure should followed enable allow proper frequency lock:
proper settings selected PSoC Designer, above steps automatically done boot.asm.
System Clocking Signals
based 32.768 crystal. names these signals their definitions follows:
There twelve system-clocking signals that used throughout device. Referenced frequencies
Table Signal 24V1 System Clocking Signals Definitions
Definition
direct output from Internal Main Oscillator. direct output from Internal Main Oscillator. output from Internal Main Oscillator that been passed through user-selectable divider MHz}. divider value found Oscillator Control Register (OSC_CR1). Note that divider will N+1, based value written into register bits. 24V1 signal that been passed through additional user-selectable divider 16)) 93.7 kHz}. divider value found Oscillator Control Register (OSC_CR1). Note that divider will N+1, based value written into register bits. multiplexed output either Internal Speed Oscillator External Crystal Oscillator. output from Internal Main Oscillator that been passed through divider that user selectable ratios ranging from 1:256, yielding frequencies ranging from 93.7 kHz. system-clocking signal that been passed through divider that user selectable ratios ranging from 1:26 1:215, yielding frequencies ranging from This signal used clock sleep timer period.
24V2
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Clocking
following diagram shows PSoC Clock Tree signals through SLP:
Lock Enable OSC_CR0[6]
Trim Register IMO_TR[7:0]
24V1 Clock isor OSC_CR1[7:4]
Internal Main Oscillator Phase Lock Loop
24V1
24V2 Clock isor OSC_CR1[3:0]
Trim Register ECO_TR[7:0]
24V2
P1[1]
Clock isor OSC_CR0[2:0]
External Crystal Oscillator
P1[0] Trim Register ILO_TR[7:0] Select OSC_CR0[7]
Internal Speed Oscillator
Sleep Clock isor OSC_CR0[4:3]
Figure PSoC Clock Tree Signals 7.2.1 Sleep Timer Clock Options
sleep timer clocked system-clocking signal. SLEEP[1] SLEEP[0] bits Oscillator Control Register (OSC_CR0) allow user select from four available periods.
clocked system-clocking signal, which configured eight rates. This selection independent from other clock selection functions. completely safe change clock rate without timing hazard. clock period determined setting CPU[2:0] bits Oscillator Control Register (OSC_CR0).
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Table Read/ Write Name
Oscillator Control Register
Select
Mode
Reserved
Sleep
Sleep
Select Internal precision oscillator External Crystal Oscillator Mode Disabled Enabled, Internal Main Oscillator locked External Crystal Oscillator Reserved [4:3]: Sleep [1:0] 1.95 period 15.6 period period period [2:0]: [2:0] 187.5 93.7
Oscillator Control Register (OSC_CR0, Address Bank E0h)
Table Read/ Write Name Oscillator Control Register
24V1
24V1
24V1
24V1
24V2
24V2
24V2
24V2
[7:4]: 24V1 [3:0] 4-bit data value determines divider value 24V1 system-clocking signal. Note that 4-bit data value equals n-1, where desired divider value, illustrated PSoC Clock Tree Signals. Table page [3:0]: 24V2 [3:0] 4-bit data value determines divider value 24V2 system-clocking signal. Note that 4-bit data value equals n-1, where desired divider value, illustrated PSoC Clock Tree Signals. Table page
Oscillator Control Register (OSC_CR1, Address Bank E1h)
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Clocking
7.2.2
24V1/24V2 Frequency Selection
24V1 24V2 based value written OSC_CR1 register.
following table shows resulting frequencies
Table
Reg. Value
24V1/24V2 Frequency Selection
24V1 24.00 24.00 24.00 24.00 24.00 24.00 24.00 24.00 24.00 24.00 24.00 24.00 24.00 24.00 24.00 24.00 12.00 12.00 12.00 12.00 12.00 12.00 12.00 12.00 12.00 12.00 12.00 12.00 12.00 12.00 12.00 12.00 8.00 8.00 8.00 8.00 8.00 8.00 8.00 8.00 8.00 8.00 8.00 8.00 8.00 8.00 8.00 8.00 6.00 6.00 6.00 6.00 6.00 6.00 6.00 6.00 6.00 6.00 6.00 6.00 6.00 6.00 6.00 6.00 24V2 Reg. Value 24V1 4.80 4.80 4.80 4.80 4.80 4.80 4.80 4.80 4.80 4.80 4.80 4.80 4.80 4.80 4.80 4.80 4.00 4.00 4.00 4.00 4.00 4.00 4.00 4.00 4.00 4.00 4.00 4.00 4.00 4.00 4.00 4.00 3.43 3.43 3.43 3.43 3.43 3.43 3.43 3.43 3.43 3.43 3.43 3.43 3.43 3.43 3.43 3.43 3.00 3.00 3.00 3.00 3.00 3.00 3.00 3.00 3.00 3.00 3.00 3.00 3.00 3.00 3.00 3.00 24V2 Reg. Value 24V1 2.67 2.67 2.67 2.67 2.67 2.67 2.67 2.67 2.67 2.67 2.67 2.67 2.67 2.67 2.67 2.67 2.40 2.40 2.40 2.40 2.40 2.40 2.40 2.40 2.40 2.40 2.40 2.40 2.40 2.40 2.40 2.40 2.18 2.18 2.18 2.18 2.18 2.18 2.18 2.18 2.18 2.18 2.18 2.18 2.18 2.18 2.18 2.18 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 24V2 Reg. Value 24V1 1.85 1.85 1.85 1.85 1.85 1.85 1.85 1.85 1.85 1.85 1.85 1.85 1.85 1.85 1.85 1.85 1.71 1.71 1.71 1.71 1.71 1.71 1.71 1.71 1.71 1.71 1.71 1.71 1.71 1.71 1.71 1.71 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.50 1.50 1.50 1.50 1.50 1.50 1.50 1.50 1.50 1.50 1.50 1.50 1.50 1.50 1.50 1.50 24V2
24000.00 12000.00 8000.00 6000.00 4800.00 4000.00 3428.57 3000.00 2666.67 2400.00 2181.82 2000.00 1846.15 1714.29 1600.00 1500.00 12000.00 6000.00 4000.00 3000.00 2400.00 2000.00 1714.29 1500.00 1333.33 1200.00 1090.91 1000.00 923.08 857.14 800.00 750.00 8000.00 4000.00 2666.67 2000.00 1600.00 1333.33 1142.86 1000.00 888.89 800.00 727.27 666.67 615.38 571.43 533.33 500.00 6000.00 3000.00 2000.00 1500.00 1200.00 1000.00 857.14 750.00 666.67 600.00 545.45 500.00 461.54 428.57 400.00 375.00
4800.00 2400.00 1600.00 1200.00 960.00 800.00 685.71 600.00 533.33 480.00 436.36 400.00 369.23 342.86 320.00 300.00 4000.00 2000.00 1333.33 1000.00 800.00 666.67 571.43 500.00 444.44 400.00 363.64 333.33 307.69 285.71 266.67 250.00 3428.57 1714.29 1142.86 857.14 685.71 571.43 489.80 428.57 380.95 342.86 311.69 285.71 263.74 244.90 228.57 214.29 3000.00 1500.00 1000.00 750.00 600.00 500.00 428.57 375.00 333.33 300.00 272.73 250.00 230.77 214.29 200.00 187.5
2666.67 1333.33 888.89 666.67 533.33 444.44 380.95 333.33 296.30 266.67 242.42 222.22 205.13 190.48 177.78 166.67 2400.00 1200.00 800.00 600.00 480.00 400.00 342.86 300.00 266.67 240.00 218.18 200.00 184.62 171.43 160.00 150.00 2181.82 1090.91 727.27 545.45 436.36 363.64 311.69 272.73 242.42 218.18 198.35 181.82 167.83 155.84 145.45 136.36 2000.00 1000.00 666.67 500.00 400.00 333.33 285.71 250.00 222.22 200.00 181.82 166.67 153.85 142.86 133.33 125.00
1846.15 923.08 615.38 461.54 369.23 307.69 263.74 230.77 205.13 184.62 167.83 153.85 142.01 131.87 123.08 115.38 1714.29 857.14 571.43 428.57 342.86 285.71 244.90 214.29 190.48 171.43 155.84 142.86 131.87 122.45 114.29 107.14 1600.00 800.00 533.33 400.00 320.00 266.67 228.57 200.00 177.78 160.00 145.45 133.33 123.08 114.29 106.67 100.00 1500.00 750.00 500.00 375.00 300.00 250.00 214.29 187.50 166.67 150.00 136.36 125.00 115.38 107.14 100.00 93.75
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
7.2.3
Digital PSoC Block Clocking Options
pose pins. There total possible clock options each digital PSoC block. Digital
PSoC Block section details.
digital PSoC block clocks user-selectable choice 48M, 24V1, 24V2, 32K, well clocking signals from other digital PSoC blocks general pur-
Interrupts Overview
Interrupts generated General Purpose lines, Power monitor, internal Sleep Timer, eight Digital PSoC blocks, four analog columns. Every interrupt separate enable bit, which contained General Interrupt Mask Register (INT_MSK0) Digital PSoC Block Interrupt Mask Register (INT_MSK1). When user writes particular position, this enables interrupt associated with that position. There single Global Interrupt Enable Flags Register (CPU_F), which disable interrupts, enable those interrupts that also have their individual interrupt enabled. During reset, enable bits General Interrupt Mask Register (INT_MASK0), enable bits Digital PSoC Block Interrupt Mask Register (INT_MSK1) Global Interrupt Enable Flags Register (CPU_F) cleared. Interrupt Vector Register (INT_VC) holds interrupt vector highest priority pending interrupt when read, when written will clear pending interrupts. there only interrupt pending instruction executed that would mask that pending interrupt clearing corresponding either interrupt mask registers address Bank will take that interrupt. Since pending interrupt been cleared there others, resulting interrupt vector 0000h will jump user code beginning Flash. address this issue, macro defined m8c.inc called "M8C_DisableIntMask" PSoC Designer. This macro brackets register write with disable then enable global interrupts.
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Interrupts
General Interrupt Mask Register
Interrupt Source
Flip Flop
Reset Decoded Iwrite INT_VC Register Interrupt Source
Flip Flop
Copyright 2000-2002 Cypress MicroSystems
Priority Decode Logic
Digital PSoC Block Interrupt Mask Register Figure Interrupts Overview
Spec.# 38-12006 R-3.19
Interrupt Vector Table
Interrupt Vector
Cypress MicroSystems Family Data Sheet
Interrupt Control Architecture
Each digital PSoC block unique Interrupt Vector Interrupt Enable bit. There also individual interrupt vectors each Analog columns, Supply Voltage Monitor, Sleep Timer General Purpose I/Os.
interrupt controller contains separate flip-flop each interrupt. When interrupt generated, registered pending interrupt. will stay pending until serviced, reset occurs, there write INT_VC Register. pending interrupt will only generate interrupt request when enabled appropriate mask Digital PSoC Block Interrupt Mask Register (INT_MSK1) General Interrupt Mask Register (INT_MSK0), Global CPU_F register set. Additionally, GPIO Interrupts, appropriate enable interrupt-type bits each must (see section 6.0, Table page Table page Table page 34). Analog Column Interrupts, interrupt source must (see section 10.11 Table page 100). During servicing interrupt, Program Counter Flag registers (CPU_PC CPU_F) stored onto program stack automatic CALL instruction cycles) generated during interrupt acknowledge process. user firmware preserve restore processor state during interrupt using PUSH instructions. memory oriented architecture requires minimal state saving during interrupts, providing very fast interrupt context switching. Program Counter Flag registers (CPU_PC CPU_F) restored when RETI instruction executed. more interrupts pending same time, higher priority interrupt (lower priority number) will serviced first. After copy Flag Register stored stack, Flag Register automatically cleared. This disables interrupts, since Global flag cleared. Executing RETI instruction restores Flag register, re-enables Global Interrupt bit. Nested interrupts accomplished re-enabling interrupts inside interrupt service routine. this, Flag Register. user must store sufficient information maintain machine state this done.
Interrupt Vectors
Interrupt Vector Table
Interrupt Priority Number
Table
Address
Description
0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040
Supply Monitor Interrupt Vector DBA00 PSoC Block Interrupt Vector DBA01 PSoC Block Interrupt Vector DBA02 PSoC Block Interrupt Vector DBA03 PSoC Block Interrupt Vector DCA04 PSoC Block Interrupt Vector DCA05 PSoC Block Interrupt Vector DCA06 PSoC Block Interrupt Vector DCA07 PSoC Block Interrupt Vector Acolumn Interrupt Vector Acolumn Interrupt Vector Acolumn Interrupt Vector Acolumn Interrupt Vector GPIO Interrupt Vector Sleep Timer Interrupt Vector On-Chip Program Memory Starts
interrupt process vectors Program Counter appropriate address Interrupt Vector Table. Typically, these addresses contain instructions start interrupt handling routine interrupt.
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Interrupts
Interrupt Masks
General Interrupt Mask Register
Table
Reserved
Sleep
GPIO
Acolumn3
Acolumn2
Acolumn1
Acolumn0
Voltage Monitor
Read/ Write Name
Reserved Sleep Interrupt Enable (see 11.4) Disabled Enabled GPIO Interrupt Enable (see 8.6) Disabled Enabled [4]: Acolumn Interrupt Enable (see 10.0) Disabled Enabled [3]: Acolumn Interrupt Enable (see 10.0) Disabled Enabled [2]: Acolumn Interrupt Enable (see 10.0) Disabled Enabled [1]: Acolumn Interrupt Enable (see 10.0) Disabled Enabled Voltage Monitor Interrupt Enable (see 11.5) Disabled Enabled
General Interrupt Mask Register (INT_MSK0, Address Bank E0h)
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Table
Digital PSoC Block Interrupt Mask Register
DCA07
DCA06
DCA05
DCA04
DBA03
DBA02
DBA01
DBA00
Read/Write Name
DCA07 Interrupt Enable Disabled Enabled DCA06 Interrupt Enable Disabled Enabled DCA05 Interrupt Enable Disabled Enabled DCA04 Interrupt Enable Disabled Enabled DBA03 Interrupt Enable Disabled Enabled DBA02 Interrupt Enable Disabled Enabled DBA01 Interrupt Enable Disabled Enabled DBA00 Interrupt Enable Disabled Enabled
Digital PSoC Block Interrupt Mask Register (INT_MSK1, Address Bank E1h)
Interrupt Vector Register
Interrupt Vector Register
Table
Data[7]
Data[6]
Data[5]
Data[4]
Data[3]
Data[2]
Data[1]
Data[0]
Read/Write Name
[7:0]: Data [7:0] 8-bit data value holds interrupt vector highest priority pending interrupt. Writing this register will clear pending interrupts
Interrupt Vector Register (INT_VC, Address Bank E2h)
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Interrupts
GPIO Interrupt
Port Interrupt Enable Registers (PRTxIE). There user selectable options generate interrupt change from last read state, rising edge, falling edge. When Interrupt Change selected, state GPIO stored when port read. Changes from this state will then assert interrupt, enabled.
GPIO Interrupts polarity configurable pin-wise maskable (within each Port's configuration registers). They share same interrupt priority vector. general purpose used interrupt source. GPIO General Interrupt Mask Register (INT_MSK0) must enable interrupts, well enable bits each pin, which located
GPIO Cell Logic GPIO Enable INT_MSK0 GPIO INTOUTs Priority Decode Logic
INTOUTn
GPIO PORTX Register (PRT0IE.PRT5IE)
Figure GPIO Interrupt Enable Diagram
GPIO interrupt occur, following steps must taken: Drive Mode must input. must enabled generate interrupt setting appropriate Port interrupt Enable Register (PRTxIE). edge type interrupt must Port Interrupt Control Control Registers (PRTxIC0 PRTxIC1). Edge type must value other than GPIO must General Interrupt Mask Register (INT_MSK0). Global Interrupt Enable must set. Because GPIO interrupts share same interrupt vector, source GPIO interrupt must cleared before other GPIO interrupt will occur (i.e., gate FigureTitle "ors" INTOUTn signals together). INTOUTn signals high, flip-flop FigureTitle will rising edge will occur.
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Digital PSoC Blocks Introduction
dependent overall block function selected user. Control Register (DBA00CR0-DCA07CR0) designated Control function this register mapping dependent overall block function selected user. frequency PSoC timer/ counter 24-bits longer operating MHz, write block Control Register enable (for example, call Timer_1_Start) start block properly. failure case, first count will typically indeterminate upper bytes fail make first count correctly. However, first terminal count, correct period will loaded counted thereafter.
PSoC blocks user configurable system resources. On-chip digital PSoC blocks reduce need many part types external peripheral components. Digital PSoC blocks configured provide wide variety peripheral functions. PSoC Designer Software Integrated Development Environment provides automated configuration PSoC blocks simply selecting desired functions. PSoC Designer then generates proper configuration information print device data sheet unique that configuration. Digital PSoC blocks provide eight, 8-bit multipurpose timers/counters supporting multiple event timers, real-time clocks, Pulse Width Modulators (PWM), CRCs. addition PSoC block functions, communication PSoC blocks support full-duplex UARTs master slave functions. shown FigureTitle there total eight 8-bit digital PSoC blocks this device family configured linear array. Four these Digital Basic Type blocks four Digital Communications Type blocks. Each these digital PSoC blocks configured independently, used combination. Each digital PSoC block unique Interrupt Vector Interrupt Enable bit. Functions stopped started with user-accessible Enable bit. Timer/Counter/CRC/PRS/Deadband functions available Digital Basic Type blocks also Digital Communications Type blocks. UART communications functions only available Digital Communications Type blocks. There three configuration registers: Function Register (DBA00FN-DCA07FN) select block function mode, Input Register (DBA00IN-DCA07IN) select data input clock selection, Output Register (DBA00OU-DCA07OU) select enable function outputs. three data registers designated Data (DBA00DR0-DCA07DR0), Data (DBA00DR1DCA07DR1), Data (DBA00DR2-DCA07DR2). function these registers their mapping
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Digital PSoC Blocks
Global Outputs [3:0] Global Inputs [3:0]
DBA0 (Basic Block)
DBA1 (Basic Block)
DBA2 (Basic Block)
*Decimator/ Incremental
DBA3 (Basic Block)
*Broadcast
DCA4 (Comm Block)
DCA5 (Comm Block)
DCA6 (Comm Block)
*Decimator/ Incremental
DCA7 (Comm Block)
Global Inputs [7:4] Global Outputs [7:4]
Figure Digital Basic Digital Communications PSoC Blocks *Three digital blocks have special functions. DBA3 Broadcast block, with output directly available digital blocks clock data input. Blocks DBA2 DCA6 have selectable connections support Delta Sigma Incremental converters.
9.2.1
Digital PSoC Block Bank Registers
Digital Basic Type Communications Type Block Function Register
Digital Basic Type Communications Type Block Function Register (DBA00FN-DCA07FN) consists bits [2:0] select block function, bits [4:3] select mode operation, indicate last block group chained blocks.
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Table
Digital Basic Type Communications Type Block Function Register
Reserved
Mode
Mode
Function
Function
Function
Read/Write Name
Reserved Reserved
Reserved
PSoC block chained function (End should block DCA07) PSoC block chained function, unchained PSoC block Mode definition Mode depends block function selected Timer: Mode signifies Compare Type Less Than Equal Less Than Counter: Mode signifies Compare Type Less Than Equal Less Than CRC/PRS: Mode unused this function Deadband: Mode unused this function UART: Mode[1] signifies Interrupt Type (Transmitter only) Transmit: Interrupt TX_Reg Empty Transmit: Interrupt Complete SPI: Mode[1] signifies Interrupt Type Master: Interrupt Empty, Slave: Interrupt Full Master: Interrupt Complete, Slave: Interrupt Complete Mode definition Mode depends block function selected Timer: Mode signifies Interrupt Type Terminal Count Compare True Counter: Mode signifies Interrupt Type Terminal Count Compare True CRC/PRS: Mode unused this function Deadband: Mode unused this function UART: Mode signifies Direction Receive Transmit SPI: Mode signifies Type Master Slave [2:0]: Function [2:0] Function [2:0] bits select block function which determines basic hardware configuration Timer (chainable) Counter (chainable) CRC/PRS (Cyclical Redundancy Checker Pseudo Random Sequencer) (chainable) Reserved Deadband Pulse Width Modulator UART (function only available type blocks) (function only available type blocks) Reserved
Digital Basic Type Block Function Register Digital Basic Type Block Function Register Digital Basic Type Block Function Register Digital Basic Type Block Function Register Digital Communications Type Block Function Register
(DBA00FN, Address Bank 20h) (DBA01FN, Address Bank 24h) (DBA02FN, Address Bank 28h) (DBA03FN, Address Bank 2Ch) (DCA04FN, Address Bank 30h)
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Digital PSoC Blocks
Digital Communications Type Block Function Register Digital Communications Type Block Function Register Digital Communications Type Block Function Register
(DCA05FN, Address Bank 34h) (DCA06FN, Address Bank 38h) (DCA07FN, Address Bank 3Ch)
9.2.2
Digital Basic Type Communications Type Block Input Register
select primary data/enable input. actual usage input data/enable function dependent.
Digital Basic Type Communications Type Block Input Register (DBA00IN-DCA07IN) consists bits [3:0] select block input clock bits [7:4]
Table Read/Write Name
Digital Basic Type Communications Type Block Input Register
Data
Data
Data
Data
Clock
Clock
Clock
Clock
[7:4]: Data [3:0] Data Enable Source Select Data Data Digital Block Chain Function Previous Block Analog Column Comparator Analog Column Comparator Analog Column Comparator Analog Column Comparator Global Output[0] (for Digital Blocks Global Output[4] (for Digital Blocks Global Output[1] (for Digital Blocks Global Output[5] (for Digital Blocks Global Output[2] (for Digital Blocks Global Output[6] (for Digital Blocks Global Output[3] (for Digital Blocks Global Output[7] (for Digital Blocks Global Input[0] (for Digital Blocks Global Input[4] (for Digital Blocks Global Input[1] (for Digital Blocks Global Input[5] (for Digital Blocks Global Input[2] (for Digital Blocks Global Input[6] (for Digital Blocks Global Input[3] (for Digital Blocks Global Input[7] (for Digital Blocks [3:0]: Clock [3:0] Clock Source Select Clock Disabled Global Output[4] (for Digital Blocks Global Output[0] (for Digital Blocks Digital Block (Primary Output) Previous Digital PSoC block (Primary Output) 24V1 24V2 Global Output[0] (for Digital Blocks Global Output[4] (for Digital Blocks Global Output[1] (for Digital Blocks Global Output[5] (for Digital Blocks Global Output[2] (for Digital Blocks Global Output[6] (for Digital Blocks Global Output[3] (for Digital Blocks Global Output[7] (for Digital Blocks Global Input[0] (for Digital Blocks Global Input[4] (for Digital Blocks Global Input[1] (for Digital Blocks Global Input[5] (for Digital Blocks Global Input[2] (for Digital Blocks Global Input[6] (for Digital Blocks Global Input[3] (for Digital Blocks Global Input[7] (for Digital Blocks
Digital Basic Type Block Input Register Digital Basic Type Block Input Register Digital Basic Type Block Input Register Digital Basic Type Block Input Register Digital Communications Type Block Input Register Digital Communications Type Block Input Register
(DBA00IN, Address Bank 21h) (DBA01IN, Address Bank 25h) (DBA02IN, Address Bank 29h) (DBA03IN, Address Bank 2Dh) (DCA04IN, Address Bank 31h) (DCA05IN, Address Bank 35h)
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Digital Communications Type Block Input Register Digital Communications Type Block Input Register Data/Enable source select [3:0] bits select between multiple inputs Digital PSoC Blocks. These inputs serve Clock Enables Data Input depending Digital PSoC Block's programmed function. "Chain Function Previous" data input selected Data/ Enable then selected Digital PSoC block receives Data, Enable, Zero Detect, chaining information from previous digital PSoC block. data inputs that selected from GPIO pins (through Global Input Bus) synchronized clock. following table shows function dependent meaning data input.
Table Digital Function Data Input Definitions Data Input
(DCA06IN, Address Bank 39h) (DCA07IN, Address Bank 3Dh) Clock[3:0] bits select multiple sources clock each digital PSoC block. sources each digital PSoC block clock selected from Global Input Bus, System Clocks, other neighboring digital PSoC blocks. shown table, Digital PSoC Blocks interface Global I/Os 00-03, Digital PSoC block 04-07 interface Global I/Os 4-7. important note that clock inputs selected from GPIO pins (through Global Input Bus) synchronized. This cause indeterminate results reads block register changing response external clock. reads must manually synchronized, either through block interrupt, through multiple read voting scheme.
Function
Timer Counter Deadband UART UART Master Slave
Positive Edge Capture Count Enable (Active High) Data Input Kill Signal (Active High) Data MISO (Master In/Slave Out) MOSI (Master Out/Slave
9.2.3
Digital Basic Type Communications Type Block Output Register
digital PSoC block's outputs selected drive associated Global Output signals Output Select bits. addition, output drive selectively enabled this register. Slave auxiliary input which also controlled selections this register.
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Digital PSoC Blocks
Table Read/ Write Name
Digital Basic Type Communications Type Block Output Register
Reserved
Reserved
Enable
Enable
Reserved Reserved Enable Disable Auxiliary Output Enable Auxiliary Output (function dependent) [4:3]: [1:0] Function-dependent selection auxiliary input output Input from Global Input[0] Drive Global Output[0] (for Digital Blocks Input from Global Input[4] Drive Global Output (for Digital Blocks Input from Global Input[1] Drive Global Output[1] (for Digital Blocks Input from Global Input[5] Drive Global Output[5] (for Digital Blocks Input from Global Input[2] Drive Global Output[2] (for Digital Blocks Input from Global Input[6] Drive Global Output[6] (for Digital Blocks Input from Global Input[3] Drive Global Output[3] (for Digital Blocks Input from Global Input[7] Drive Global Output[7] (for Digital Blocks Enable Disable Primary Output Enable Primary Output (function dependant) [1:0]: [1:0] Primary Output Drive Global Output[0] (for Digital Blocks Drive Global Output[4] (for Digital Blocks Drive Global Output[1] (for Digital Blocks Drive Global Output[5] (for Digital Blocks Drive Global Output[2] (for Digital Blocks Drive Global Output[6] (for Digital Blocks Drive Global Output[3] (for Digital Blocks Drive Global Output[7] (for Digital Blocks
Digital Basic Type Block Output Register Digital Basic Type Block Output Register Digital Basic Type Block Output Register Digital Basic Type Block Output Register Digital Communications Type Block Output Register Digital Communications Type Block Output Register Digital Communications Type Block Output Register Digital Communications Type Block Output Register
(DBA00OU, Address Bank 22h) (DBA01OU, Address Bank 26h) (DBA02OU, Address Bank 2Ah) (DBA03OU, Address Bank 2Eh) (DCA04OU, Address Bank 32h) (DCA05OU, Address Bank 36h) (DCA06OU, Address Bank 3Ah) (DCA07OU, Address Bank 3Eh)
Primary Output source "Previous Digital PSoC Block" "Digital Block 03," selections "Clock Source Select" Digital Basic Type A/Communications Type Block Input Register (Table page 51). digital PSoC block have outputs depending function, shown following table:
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Table Function
Digital Function Outputs Primary Output Auxiliary Output Auxiliary Input
Timer Counter Deadband UART UART Master Slave
Terminal Count Compare True Serial Data Data MOSI MISO
Compare True Terminal Count Compare True Compare True SCLK
Digital PSoC Block Bank Registers
used during operation. status/control register (CR0) contains enable that used configurations. addition, contains function-specific status control, which outlined below.
There four user registers within each digital PSoC block: three data registers, status/control register. three data registers DR0, which shifter/ counter, registers, which contain data
9.3.1
Table Read/Write Name
Digital Basic Type Communications Type Block Data Register 0,1,2
Digital Basic Type Communications Type Block Data Register 0,1,2
Data
Data
Data
Data
Data
Data
Data
Data
[7:0]: Data [7:0]
Varies function/User Module selection. (See Table page 55.) (DBA00DR0, Address Bank 20h) (DBA00DR1, Address Bank 21h) (DBA00DR2, Address Bank 22h) (DBA01DR0, Address Bank 24h) (DBA01DR1, Address Bank 25h) (DBA01DR2, Address Bank 26h) (DBA02DR0, Address Bank 28h) (DBA02DR1, Address Bank 29h) (DBA02DR2, Address Bank 2Ah) (DBA03DR0, Address Bank 2Ch) (DBA03DR1, Address Bank 2Dh) (DBA03DR2, Address Bank 2Eh) (DCA04DR0, Address Bank 30h) (DCA04DR1, Address Bank 31h) (DCA04DR2, Address Bank 32h) (DCA05DR0, Address Bank 34h) (DCA05DR1, Address Bank 35h) (DCA05DR2, Address Bank 36h) (DCA06DR0, Address Bank 38h) (DCA06DR1, Address Bank 39h)
Digital Basic Type Block Data Register Digital Basic Type Block Data Register Digital Basic Type Block Data Register Digital Basic Type Block Data Register Digital Basic Type Block Data Register Digital Basic Type Block Data Register Digital Basic Type Block Data Register Digital Basic Type Block Data Register Digital Basic Type Block Data Register Digital Basic Type Block Data Register Digital Basic Type Block Data Register Digital Basic Type Block Data Register Digital Communications Type Block Data Register Digital Communications Type Block Data Register Digital Communications Type Block Data Register Digital Communications Type Block Data Register Digital Communications Type Block Data Register Digital Communications Type Block Data Register Digital Communications Type Block Data Register Digital Communications Type Block Data Register
Spec.# 38-12006 R-3.19
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Digital PSoC Blocks
Digital Communications Type Block Data Register Digital Communications Type Block Data Register Digital Communications Type Block Data Register Digital Communications Type Block Data Register
Table Function Variations User Module Selection
(DCA06DR2, Address Bank 3Ah) (DCA07DR0, Address Bank 3Ch) (DCA07DR1, Address Bank 3Dh) (DCA07DR2, Address Bank 3Eh)
Timer Counter Deadband UART UART
Count Count Current Value/CRC Residue Current Value Count Shifter Shifter Shifter
Period Value Period Value Polynomial Mask Value Polynomial Mask Value Period Value Used Data Register Data Register
Capture Value Compare Value Seed Value Seed Value Used Data Register Used Data Register
Each time register read, value written register.
9.3.2
Table
Digital Basic Type Communications Type Block Control Register
Digital Basic Type Communications Type Block Control Register
Data
Data
Data
Data
Data
Data
Data
Data
Read/Write Name
[7:0]: Data [7:0]
Varies function. (DBA00CR0, Address Bank 23h) (DBA01CR0, Address Bank 27h) (DBA02CR0, Address Bank 2Bh) (DBA03CR0, Address Bank 2Fh) (DCA04CR0, Address Bank 33h) (DCA05CR0, Address Bank 37h) (DCA06CR0, Address Bank 3Bh) (DCA07CR0, Address Bank 3Fh)
Digital Basic Type Block Control Register Digital Basic Type Block Control Register Digital Basic Type Block Control Register Digital Basic Type Block Control Register Digital Communications Type Control Register Digital Communications Type Control Register Digital Communications Type Block Control Register Digital Communications Type Block Control Register
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Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
9.3.3
Digital Basic Type A/Communications Type Block Control Register When Used Timer, Counter, CRC, Deadband
variables selected associated Digital Basic Type Communications Type Block Control Register
Note that data this register, well following three registers, mapping functions
Table Read/Write Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Enable Function Disabled Function Enabled
Digital Basic Type A/Communications Type Block Control Register
-Reserved
-Reserved
-Reserved
-Reserved
-Reserved
-Reserved
-Reserved
Enable
Digital Basic Type Block Control Register Digital Basic Type Block Control Register Digital Basic Type Block Control Register Digital Basic Type Block Control Register Digital Communications Type Control Register Digital Communications Type Control Register Digital Communications Type Block Control Register Digital Communications Type Block Control Register
(DBA00CR0, Address Bank 23h) (DBA01CR0, Address Bank 27h) (DBA02CR0, Address Bank 2Bh) (DBA03CR0, Address Bank 2Fh) (DCA04CR0, Address Bank 33h) (DCA05CR0, Address Bank 37h) (DCA06CR0, Address Bank 3Bh) (DCA07CR0, Address Bank 3Fh)
Spec.# 38-12006 R-3.19
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Digital PSoC Blocks
9.3.4
Table Read/ Write Name
Digital Communications Type Block Control Register When Used UART Transmitter
Digital Communications Type Block Control Register
-Reserved
-Reserved
Complete
Empty
-Reserved
Parity Type
Parity Enable
Enable
Reserved Reserved Complete Indicates that transmission been initiated, still progress Indicates that current transmission complete (including framing bits) Optional interrupt source UART. Reset when this register read. Empty Indicates Data register available accept another byte (writing register will cause data lost) Indicates Data register available accept another byte Note that interrupt does occur until least byte been previously written Data Register Default interrupt source UART. Reset when Data Register (Data Register written. Reserved Parity Type Even Parity Enable Parity Disabled Parity Enabled Enable Function Disabled Function Enabled
Digital Communications Type Control Register Digital Communications Type Control Register Digital Communications Type Block Control Register Digital Communications Type Block Control Register
(DCA04CR0, Address Bank 33h) (DCA05CR0, Address Bank 37h) (DCA06CR0, Address Bank 3Bh) (DCA07CR0, Address Bank 3Fh)
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
9.3.5
Table
Digital Communications Type Block Control Register When Used UART Receiver
Digital Communications Type Block Control Register
Parity Error
Overrun
Framing Error
Active
Full
Parity Type
Parity Enable
Enable
Read/Write Name
Parity Error Indicates parity error detected last byte received Indicates parity error detected last byte received Reset when this register read Overrun Indicates that overrun taken place Indicates Data register overwritten with byte before previous been read Reset when this register read Framing Error Indicates correct stop Indicates missing STOP Reset when this register read Active Indicates communication currently progress Indicates start been received byte currently being received Full Indicates Data register empty Indicates byte been loaded into Data register Interrupt source RXUART. Reset when Data register read (Data Register Parity Type Even Parity Enable Parity Disabled Parity Enabled Enable Function Disabled Function Enabled
Digital Communications Type Control Register Digital Communications Type Control Register Digital Communications Type Block Control Register Digital Communications Type Block Control Register
(DCA04CR0, Address Bank 33h) (DCA05CR0, Address Bank 37h) (DCA06CR0, Address Bank 3Bh) (DCA07CR0, Address Bank 3Fh)
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Digital PSoC Blocks
9.3.6
Table Read/ Write Name
Digital Communications Type Block Control Register When Used Transceiver
Digital Communications Type Block Control Register
First
Overrun
Complete
Empty
Full
Clock Phase
Clock Polarity
Enable
First First First Overrun Indicates that overrun taken place Indicates Data register overwritten with byte before previous been read Reset when this register read Complete Indicates byte process shifting Indicates byte been shifted (reset when register read) Optional interrupt source both Master Slave. Reset when this register read Empty Indicates Data register available accept another byte Indicates Data register available accept another byte Default interrupt source Master. Reset when Data Register (Data Register written. Full Indicates Data register empty Indicates byte been loaded into Data register Default interrupt source Slave. Reset when Data Register (Data Register read Clock Phase Data changes leading edge latched trailing edge Data latched leading edge changed trailing edge Clock Polarity Non-inverted (clock idle state low) Inverted (clock idle state high) Enable Function Disabled Function Enabled
Digital Communications Type Control Register Digital Communications Type Control Register Digital Communications Type Block Control Register Digital Communications Type Block Control Register
(DCA04CR0, Address Bank 33h) (DCA05CR0, Address Bank 37h) (DCA06CR0, Address Bank 3Bh) (DCA07CR0, Address Bank 3Fh)
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Global Inputs Outputs
This allows Digital PSoC blocks route their inputs outputs pins using global buses.
Global Inputs Outputs provide additional capability route clock data signals Digital PSoC blocks. Digital PSoC blocks connected global input output lines configuring PSoC block Input Output registers (DBA00IN-DCA07IN, DBA00OU-DCA07OU). These global input output lines form 8-bit global input 8-bit global output bus. Four Digital PSoC blocks have access upper half these buses, while other four access lower half, configuration register. These global input/output buses connected pins per-pin basis using configuration registers.
9.4.1
Input Assignments
PSoC block Input Register defines selection Global Inputs digital PSoC blocks. Only Global Inputs lines available selections given digital PSoC block shown table below. Once Global Input been selected using PSoC block Input Register selection bits, GPIO must configured drive selected Global Input. This configuration GPIO Global Select Register. GPIO direction must also input mode configuring Drive Mode registers select High
Table Global Input
Global Input Assignments Global Input Global Input Global Input Global Input Global Input Global Input Global Input
Port x[7]
PSoC Block PSoC Block PSoC Block PSoC Block
Port x[6]
PSoC Block PSoC Block PSoC Block PSoC Block
Port x[5]
PSoC Block PSoC Block PSoC Block PSoC Block
Port x[4]
PSoC Block PSoC Block PSoC Block PSoC Block
Port x[3]
PSoC Block PSoC Block PSoC Block PSoC Block
Port x[2]
PSoC Block PSoC Block PSoC Block PSoC Block
Port x[1]
PSoC Block PSoC Block PSoC Block PSoC Block
Port x[0]
PSoC Block PSoC Block PSoC Block PSoC Block
9.4.2
Output Assignments
puts drive GPIO pins. this case, once Global Output been selected using PSoC block Output Register selection bits, GPIO must configured select Global Output drive pin. This configuration GPIO Global Select Register. GPIO direction must also output mode (which default) configuring Drive Mode registers available driving strengths.
PSoC block Output Register defines selection Global Output line driven digital PSoC blocks. Only Global Output lines available selections given digital PSoC block shown table below. Global Output functions. Since Global Outputs also selectable inputs digital PSoC blocks, signals routed between blocks using this bus. addition, Global OutTable Global Output Global Output Assignments Global Output Global Output Global Output
Global Output
Global Output
Global Output
Global Output
Port x[7]
PSoC Block PSoC Block PSoC Block PSoC Block
Port x[6]
PSoC Block PSoC Block PSoC Block PSoC Block
Port x[5]
PSoC Block PSoC Block PSoC Block PSoC Block
Port x[4]
PSoC Block PSoC Block PSoC Block PSoC Block
Port x[3]
PSoC Block PSoC Block PSoC Block PSoC Block
Port x[2]
PSoC Block PSoC Block PSoC Block PSoC Block
Port x[1]
PSoC Block PSoC Block PSoC Block PSoC Block
Port x[0]
PSoC Block PSoC Block PSoC Block PSoC Block
9.5.1 9.5.1.1
Available Programmed Digital Functionality
Timer with Optional Capture Summary
generator. down counter lies heart timer functions. Rate generators divide their clock source integer value. Hardware software generated events
timer function continuously measures amount time "ticks" between events, provides rate
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Digital PSoC Blocks
trigger capture operations that permit calculation elapsed "ticks." Timer-configured PSoC blocks chained arbitrary lengths increments.
current count less than less than equal value Data Register (compare type controlled Mode[1] PSoC block Function Register). auxiliary output routed Global Output lines. PSoC block Output Register (DBA00OU-DCA07OU) controls output options.
9.5.1.2
Registers
Data Register establishes period integer clock division value. Data Register holds current state down counter. function disabled, writing period into Data Register will automatically load Data Register also automatically reloaded clock cycle after reaches zero, terminal count value. When capture event occurs, current value Data Register transferred Data Register captured value Data Register then read CPU. addition hardware capture input, read Data Register generates software capture event. This read will return data. subsequent read Data Register will return captured value. Control Register contains enable/disable function.
9.5.1.5
Interrupts
Interrupts generated either ways. First, PSoC block optionally generate interrupt rising edge Terminal Count rising edge Compare True signal. selection interrupt source determined MODE[0] PSoC block Function Register (DBA00FN-DCA07FN). MODE[1] controls whether comparison operation "less than" "less than equal to." capture events disabled, Data Register used create periodic interrupt with particular offset from terminal count.
9.5.1.6 Inputs
Usage Notes
9.5.1.3
Constraints Hardware/software synchronous capture only available with clocking rate below.
There inputs, Source Clock Hardware Capture signal. down counter decremented rising-edge Source Clock. hardware capture event signaled rising edge Hardware Capture signal. This synchronized system clock data synchronously transferred Data Register Hardware Capture Signal OR'ed with software capture signal that generated when Data Register read directly CPU. order software capture mechanism, Hardware Capture signal input selection must low. multiplexers selecting these input sources controlled PSoC block Input Register (DBA00IN-DCA07IN).
Software Capture When capture event occurs, bytes multibyte timer transfer simultaneously from current count (Data Register capture register (Data Register generate software capture event, only least significant Data Register byte needs read CPU. This causes same simultaneous transfer hardware event. Disabled State When Control Register Enable `0', internal block clock turned off. write Data Register (Period) loaded directly into Data Register (Counter) initialize reset count. outputs block interrupt held low. Disabling timer does affect current count value read CPU. However, since hardware/software capture disabled this state, reads required read each byte multi-byte register. transfer each Data Register count value associated Data Register capture register, then read result Data Register
9.5.1.4
Outputs
Terminal Count signal primary output exhibits duty cycle that reciprocal period value contained Data Register other words, high during source clock cycle when value Data Register zero otherwise. Terminal Count routed additional analog digital PSoC blocks Global Output lines. auxiliary output Compare True signal. This output high when
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
Capture Compare capture event will overwrite Data Register This also register that holds compare value. Therefore, using capture function compatible with using timer compare function.
Register
Control Register contains
enable/disable function.
9.5.2.3
Inputs
There primary inputs, Source Clock Enable signal. When Enable signal high, down counter decremented rising-edge Source Clock. multiplexers selecting these inputs controlled PSoC block Input Register (DBA00INDCA07IN).
9.5.2 9.5.2.1
Counter with Optional Compare (PulseWidth) Output Summary
Conceptually, counter measures number events between "ticks," however, this distinction between counter timer blurs because both functions provide complete range clock selections. counter trades timer's hardware capture clock gate "enable" provides means adjusting duty cycle output that double pulse-width modulator. down counter lies heart counter function. Counter-configured PSoC blocks chained arbitrary lengths increments. Counter User Module, data input enable counting. Normally, when enable goes low, counter will hold current count. However, enable happens same clock period Terminal Count (count 0's), additional count will occur that will reload counter from Period Register. Once counter reloaded from Period Register, counting will stop.
9.5.2.4
Outputs
counter function drives primary output signal, Compare True, high falling edge Source Clock when value Data Register less less than equal value Data Register duty cycle pulse-width modulator formed this ratio Data Register Data Register minus one) Data Register choice compare operators determined MODE[1] bit. Compare value routed additional analog digital PSoC blocks Global Output lines auxiliary output signal Terminal Count signal which routed Global Output lines. PSoC block Output Register (DBA00OU-DCA07OU) controls output options.
9.5.2.5
Interrupts
Interrupts generated either ways. First, PSoC block optionally generate interrupt rising edge Terminal Count rising edge Compare signal. selection interrupt source determined MODE[0] PSoC block Function Register (DBA00FN-DCA07FN). MODE[1] controls whether comparison operation "less than" "less than equal to."
9.5.2.2
Registers
Data Register establishes period counter. Data Register holds current state down counter. function disabled, writing period into Data Register will automatically load Data Register also automatically reloaded clock cycle after reaches zero, terminal count value. value Data Register (compare value) continually compared Data Register (count value) establish output pulse-width (duty cycle). Reading Data Register obtain current value down counter occur only when function disabled. When read, this transfers value from Data Register Data Register returns data bus. value transferred Data Register then directly read CPU. However, reading count value this manner will overwrite previously written compare value Data
9.5.2.6
Usage Notes
Enable Input enable input synchronous when forces counter into `hold' state. Outputs unaffected state enable input. external source selected enable input, synchronized clock.
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Digital PSoC Blocks
Disabled State When Control Register Enable `0', internal block clock turned off. write Data Register (Period) loaded directly into Data Register (Counter) initialize reset count. outputs block interrupt held low. Disabling counter does affect current count value read CPU. reads required read each byte multi-byte register. transfer each Data Register count value associated Data Register capture register, then read result Data Register
9.5.3.3
Inputs
input controls period duty cycle deadband generator outputs. This input fixed derived from primary output previous block. this signal pulse-width modulated, i.e., block configured previous block, dead-band outputs will similarly modulated. output corresponds duty cycle input (less dead time) duty cycle inverted input (again, less dead time). clock input dead-band generator controls rate which down counter decremented. primary data input "Kill" Signal. When this signal asserted high, both outputs will low. multiplexers selecting these input controlled PSoC block Input Register (DBA00IN-DCA07IN).
Reading Count Value read Data Register (count value) will overwrite Data Register (compare value). Therefore, when reading current count, previously written compare value will overwritten.
9.5.3 9.5.3.1
Deadband Generator Summary
9.5.3.4
Outputs
Both outputs driven onto Global Output bus. next PSoC block selects "Previous PSoC block" clock input, only "sees" output dead-band function. PSoC block Output Register (DBA00OU-DCA07OU) controls output options.
Deadband function produces output waveforms, with same frequency input, "under-lapped" they never both high same time. 8-bit down counter controls length "dead time" during which both output signals low. When deadband function detects rising edge input waveform, output signal goes counter decrements from initial value terminal count. When down counter reaches zero, output signal goes high. process reverses falling edge input waveform that after same dead time, goes high until input signal transitions again. Dead-band generator PSoC blocks cannot chained increase width down counter beyond bits dead-time "ticks."
9.5.3.5
Interrupts
rising edge signal provides interrupt this block.
9.5.3.6
Usage Notes
Constraints dead time must exceed minimum input signal's pulse-width high pulse-width time, less clocks. Dead time equals period input clock times plus value written Data Register
9.5.3.2
Registers
Enabling data input Dead-Band function hardware primary output previous block, which typically programmed PWM. proper order enabling these blocks (writing Control Register first, then Dead-Band.
Data Register stores count that controls elapsed dead time. Data Register holds current state dead-time down counter. function disabled, writing period into Data Register will automatically load Data Register with deadband period. This period automatically re-loaded into counter each edge input signal. Data Register unused. Control Register contains enable/disable function.
Disabled State When Control Register Enable `0', internal block clock turned off. write Data Register (Period) loaded directly into Data Reg-
Copyright 2000-2002 Cypress MicroSystems
Spec.# 38-12006 R-3.19
Cypress MicroSystems Family Data Sheet
ister (Counter) initialize reset dead-band time. outputs block interrupt held low. Asserting Kill Signal When Kill signal asserted high, both outputs held low. When Kill signal selected from external source through Global Input, synchronized clock therefore latency. Negating Kill Signal Kill signal negated time. However, output enabled arbitrary time with respect generation. exact timing required when re-enabling outputs, following procedure recommended: 1.Kill asserted. 2.Write Control Register disable block. 3.Write Data Register (Deadband time) initialize period. 4.Kill eventually negated. 5.Write Control Register enable block.
directly into Data Register (The block must disabled when writing this value). Data Register specifies polynomial width numbers sequence (see 9.5.4.6).
9.5.4.3
Inputs
clock input determines rate which output sequence produced. data input must block function PRS. multiplexer selecting these inputs controlled PSoC block Input Register (DBA00IN-DCA07IN).
9.5.4.4
Outputs
function drives output serial data stream synchronous with input clock. output bits change rising edge input clock. output driven Global Output subsequent digital PSoC block. PSoC block Output Register (DBA00OU-DCA07OU) controls output options.
9.5.4.5
Interrupts
function provides interrupt based Compare signal between Data Register Data Register Data Register initially loaded with "seed" value, therefore periodic interrupt will generated when count matches seed value.
9.5.4 9.5.4.1
Pseudo-Random Sequence Generator Summary
9.5.4.6
Determining Polynomial
simple linear-feedback shift register, LFSR, uses function generates output waveform corresponding sequence pseudo-random numbers. linear-feedback shift register generates sequence according user-specified polynomial. width numbers sequence variable initial value determined user-defined "seed" value. PSoC blocks chained increase width numbers and, hence, length sequence. chain PSoC blocks generate numbers from 8N-bits wide sequences 28N-1 distinct values. gate "add" values more bits feed result back into least-significant bit. possible realization 6-bit LFSR providing maximal sequence six-bit values shown here:
Figure Polynomial LFSR
function utilizes different "modular" architecture with gate between each shift register. maximal sequence equivalent that produced previous realization generated following modular LFSR
9.5.4.2
Registers
Data Register implements linear-feedback shift register. Data Register holds "seed" value when block disabled, write Data Register loaded
Spec.# 38-12006 R-3.19
Copyright 2000-2002 Cypress MicroSystems
Digital PSoC Blocks
Figure Polynomial
Denote first implementation LFSR, where gives length output codes indicates which feeds gate along with final bit. Then modular form just shown denoted LFSR. general, equivalent modular form simple LFSR with taps denoted given notation N-t1, N-t2, N-tM]. Once form (and thus notation) determined, value Data Register easily determined. corresponding length bits turned others zero. Thus, polynomial
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