Video Decoder Fusion 878A complete, cost, single-chip solution an
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Fusion878A
Video Decoder
Fusion 878A complete, cost, single-chip solution analog broadcast signal capture bus. Fusion 878A takes advantage PCI-based system's high bandwidth inherent multimedia capability. designed interoperable with other multimedia device component board level. Fusion 878A video audio capture features Bt878, plus whole more. Designed address demanding requirements Personal Computing digital video industry, Fusion 878A meets PC98/PC99 requirements well being fully compliant. Fusion 878A addresses current analog requirements since compatible software compatible with current Bt878. But, Fusion 878A also used array MPEG digital transport stream products well. world turning digital, with standards Television ATSC COFDM Television recording technologies using MPEG compression. Fusion 878A used into connecting multiple analog digital video formats single connection.
Distinguishing Features
NTSC/PAL/SECAM video decoding Supports capture resolutions (full PAL) On-chip mastering bridge functionality Supports HDTV/audio/MPEG2 transport data across High-speed serial port support MPEG transport stream rates Mbps High-speed parallel port supports MPEG transport streams Mbps Flexible 24-bit wide GPIO CCIR656 interface Interfaces Digital data stream from OFDM demodulator Multiple YCrCb pixel formats planar formats supported output Selectable pixel density: bits pixel Performs complex clipping video source video overlay Permits different program control color space/scaling even fields Executes Windows "Scatter Gather" Integrates advanced chroma luma comb filters/scalers Image scaleable direction Y/C, 6-tap luma/2-tap chroma polyphase filter Receives Digital audio serial port Includes data capture (closed captioning, teletext, Intercast data decoding) 100% Rev. compliant 98/PC compliant WHQL-certifiable Accepts Mono audio input Packaged compact 128-pin plastic
Functional Block Diagram
GPIO Digital/Video Port
Pixel Format Conversion
GPIO
Decimation
Video FIFO Target Initiator Controller Audio FIFO Target Initiator
Composite Composite Composite Composite Composite S-Video S-Video
Video Decode Scaling
Controller
Fusion 878A Specific Features
Full stereo decoding both audio (BTSC) radio Enhanced GPIO/I2S ACPI support Byte alignment Vital product data High speed serial port High speed parallel port
Ultralockand Clock Generation
(dig. audio)
Audio Stream Format
Applications
Input Gain Control High Audio
879A_001
television Digital television Digital Desktop video phone Still frame capture data service capture
Data Sheet
100600B December 1999
Ordering Information
Model Number Fusion 878A Package 128-pin PQFP Operating Temperature
Related Documents
Fusion Technical Reference Manual Fusion Programmers Guide
Information provided Conexant Systems, Inc. (Conexant) believed accurate reliable. However, responsibility assumed Conexant use, infringement patents, copyrights, other rights third parties which result from use. license granted implication otherwise under patent rights copyrights Conexant other than circuitry embodied Conexant products. Conexant reserves right change circuitry time without notice. This document subject change without notice. Conexant products designed intended life support appliances, devices, systems where malfunction Conexant product reasonably expected result personal injury death. Conexant customers using selling Conexant products such applications their risk agree fully indemnify Conexant damages resulting from such improper sale. Conexant, Conexant symbol "What's Next Communications Technologies" trademarks Conexant Systems, Inc.
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Table Contents
List Figures List Tables xiii Product Overview.
Functional Overview Detailed Features 1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 1.2.6 1.2.7 1.2.8 1.2.9 1.2.10 1.2.11 1.2.12 1.2.13 1.2.14 1.2.15 Video Capture Audio Capture Analog Video Digital Camera Capture Intel IntercastSupport Video Channels Audio Channels Data Transport Engine Interface UltraLock. Scaling Cropping Input Interface GPIO Port Vertical Blanking Interval Data Capture Interface. HDTV Support
Descriptions
Functional Description
UltraLockFunctionality 2.1.1 2.1.2 Challenge Operating Principles UltraLock
Composite Video Input Formats Separation Chroma Demodulation
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Video Decoder
Video Scaling, Cropping, Temporal Decimation 2.4.1 Down-Scaling 2.4.1.1 Horizontal Vertical Scaling 2.4.1.2 Field Aligned Vertical Scaling 2.4.1.3 Luminance Scaling 2.4.1.4 Peaking 2-10 2.4.1.5 Chrominance Scaling 2-13 2.4.1.6 Scaling Registers 2-13 Image Cropping 2-16 2.4.2.1 Cropping Registers 2-18 Temporal Decimation 2-19 Adjust Register Contrast Adjust Register Saturation Adjust Registers Brightness Register
2.4.2 2.4.3 2.5.1 2.5.2 2.5.3 2.5.4
Video Adjustments 2-21
2-21 2-21 2-21 2-21
Automatic Chrominance Gain Control 2-22 Color Detection Removal 2-22 Coring 2-23 Data Output Interface 2-24 2.9.1 2.10.1 2.10.2 2.10.3 2.10.4 2.10.5 2.10.6 2.11.1 2.11.2 2.11.3 2.11.4 2.12.1 2.12.2 2.12.3 2.12.4 2.12.5 2.12.6 2.12.7 Line Output Mode 2-25 Pixel Data Path 2-27 Video Control Code Status Data 2-27 YCrCb Conversion 2-30 Gamma Correction Removal 2-30 YCrCb Sub-sampling 2-30 Byte Swapping 2-31 Logical Organization 2-32 FIFO Data Interface 2-33 Physical Implementation 2-34 FIFO Input/Output Rates 2-34 Target Memory 2-37 RISC Program Setup Synchronization. 2-37 RISC Instructions 2-38 Complex Clipping 2-43 Executing Instructions 2-44 FIFO Overrun Conditions. 2-45 FIFO Data Stream Resynchronization 2-46
2.10 Video Data Format Conversion 2-27
2.11 Video Control Data FIFO 2-32
2.12 Controller 2-36
2.13 Byte Alignment 2-47
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2.14 Multifunction Arbiter 2-48 2.14.1 2.14.2 2.14.3 2.15.1 2.15.2 Normal Mode 2-48 430FX Compatibility Mode 2-48 Interfacing with Non-PCI Compliant Core Logic 2-49 Muxing Anti-aliasing Filtering 2-50 Input Gain Control 2-50
2.15 Audio 2-50
2.16 High Speed Serial Interface Mode 2-52 2.17 Asynchronous Data Parallel Mode: Data Capture. 2-53 2.18 Digital Audio Packetizer 2-54 2.18.1 2.18.2 2.18.3 2.18.4 2.18.5 2.18.6 2.18.7 2.18.8 Audio FIFO Memory Status Codes 2-54 Latency Tolerance Audio Buffer 2-54 FIFO Interface 2-55 Audio Packets Data Capture 2-56 Digital Audio Input 2-57 2.18.5.1 Digital Audio Input Mode 2-57 Data Packet Mode 2-58 Audio Data Formats 2-59 Audio Dropout Detection 2-59
2.19 Digital Television Support 2-60
Electrical Interfaces
Input Interface. 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.8 Analog Signal Selection Multiplexer Considerations Flash Converters Clamping Power-up Operation Automatic Gain Controls Crystal Inputs Clock Generation Oversampling Input Filtering
Interface General Purpose Port 3-10 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 GPIO Architecture 3-10 GPIO Modes Fusion 878A 3-10 GPIO Normal Mode 3-10 Input Mode 3-12 Output Mode 3-13 GPIO Mode Timing Parameters. 3-17 Digital Video Input Mode 3-18 3.3.7.1 CCIR656 3-18 3.3.7.2 Modified SMPTE-125 3-19 GPIO Timing Diagram Digital Video Input Modes 3-20
3.3.8
Interface 3-21
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Serial EEPROM Interface. 3-23 3.5.1 3.5.2 EEPROM Address Mapping. 3-23 Subsystem Vendor 3-24 3.5.2.1 EEPROM Upload Reset 3-24 3.5.2.2 Register Load from BIOS 3-24 3.5.2.3 Programming Write-Protect 3-25 Vital Product Data 3-25 3.5.3.1 Vital Product Data EEPROM Addressing 3-25 3.5.3.2 Vital Product Data Read Sequence 3-26 3.5.3.3 Vital Product Data Write Sequence. 3-26 PME# 3-28 Power States 3-28 Need Functional Verification JTAG Approach Testability Optional Device Register Verification with Controller
3.5.3
Power Management Interface 3-28 3.6.1 3.6.2
JTAG Interface. 3-29 3.7.1 3.7.2 3.7.3 3.7.4
3-29 3-29 3-30 3-30
Board Layout Considerations
Layout Considerations 4.1.1 4.1.2 Capacitors Components
Split Planes Voltage Regulators Latchup Avoidance
Control Register Definitions-Function
Configuration Space Configuration Registers (Header) 0x00-Vendor Device Register 0x04-Command Status Register 0x08-Revision Class Code Register 0x0C-Header Type, Latency Timer Register 0x10-Base Address Register 0x2C-Subsystem Subsystem Vendor Register 0x3C-Interrupt Line, Interrupt Pin, Min_Gnt, Max_Lat Register. 0x34-Capabilities Pointer Register 0x40-Device Control Register 0x44-VPD Capability Register 0x48-VPD Data Register 0x4C-Power Management Capability Register 0x50-Power Management Support Registers
Local Registers (Memory Mapped) 0x000-Device Status Register (DSTATUS) 0x004-Input Format Register (IFORM) 5-10 0x008-Temporal Decimation Register (TDEC) 5-10
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Cropping Register) 5-11 0x00C-Even Field (E_CROP) 0x08C-Odd Field (O_CROP) 5-11 Vertical Delay Register, Lower Byte 5-11 0x090-Even Field (E_VDELAY_LO) 0x010-Odd Field (O_VDELAY_LO) 5-11 Vertical Active Register, Lower Byte 5-11 0x014-Even Field (E_VACTIVE_LO) 0x094-Odd Field (O_VACTIVE_LO) 5-11 Horizontal Delay Register, Lower Byte 5-12 0x018-Even Field (E_DELAY_LO) 0x098-Odd Field (O_DELAY_LO) 5-12 Horizontal Active Register, Lower Byte 5-12 0x01C-Even Field (E_HACTIVE_LO) 0x09C-Odd Field (O_HACTIVE_LO) 5-12 Horizontal Scaling Register, Upper Byte 5-12 0x020-Even Field (E_HSCALE_HI) 0x0A0-Odd Field (O_HSCALE_HI) 5-12 Horizontal Scaling Register, Lower Byte 5-12 0x024-Even Field (E_HSCALE_LO) 0x0A4-Odd Field (O_HSCALE_LO) 5-12 0x028-Brightness Control Register (BRIGHT) 5-13 Miscellaneous Control Register 5-14 0x02C-Even Field (E_CONTROL) 0x0AC-Odd Field (O_CONTROL) 5-14 0x030-Luma Gain Register, Lower Byte (CONTRAST_LO) 5-15 0x034-Chroma Gain Register, Lower Byte (SAT_U_LO) 5-16 0x038-Chroma Gain Register, Lower Byte (SAT_V_LO) 5-17 0x03C-Hue Control Register (HUE) 5-18 Loop Control Register 5-19 0x040-Even Field (E_SCLOOP) 0x0C0-Odd Field (O_SCLOOP) 5-19 0x044-White Crush Register (WC_UP) 5-20 0x048-Output Format Register (OFORM) 5-20 Vertical Scaling Register, Upper Byte 5-21 0x04C-Even Field (E_VSCALE_HI) 0x0CC-Odd Field (O_VSCALE_HI) 5-21 Vertical Scaling Register, Lower Byte 5-21 0x050-Even Field (E_VSCALE_LO) 0x0D0-Odd Field (O_VSCALE_LO) 5-21 0x054-Reserved 5-21 0x5B-Audio Reset Register (ARESET) 5-22 0x060-AGC Delay Register (ADELAY) 5-22 0x064-Burst Delay Register (BDELAY) 5-22 0x068-ADC Interface Register (ADC) 5-23 Video Timing Control Register 5-24 0x6C-Even Field (E_VTC) 0xEC-Odd Field (O_VTC) 5-24 0x07C-Software Reset Register (SRESET) 5-24 0x078-White Crush Down Register 5-25 0x080-Timing Generator Load Byte (TGLB) 5-25 0x084-Timing Generator Control (TGCTRL) Register 5-26 0x0B0-Total Line Count Register (VTOTAL_LO) 5-27
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Fusion 878A
Video Decoder 0x0B4-Total Line Count Register (VTOTAL_HI) 5-27 0x0D4-Color Format Register (COLOR_FMT) 5-28 0x0D8-Color Control Register (COLOR_CTL) 5-29 0x0DC-Capture Control Register (CAP_CTL) 5-29 0x0E0-VBI Packet Size Register (VBI_PACK_SIZE) 5-30 0x0E4-VBI Packet Size Delay Register (VBI_PACK_DEL) 5-30 0x0E8-Field Capture Counter Register (FCAP) 5-30 0x0F0-PLL Reference Multiplier Register (PLL_F_LO) 5-30 0x0F4-PLL Reference Multiplier Register (PLL_F_HI) 5-30 0x0F8-Integer Register (PLL-XCI) 5-31 0x0FC-Digital Video Signal Interface Format (DVSIF) Register 5-31 0x100-Interrupt Status Register (INT_STAT) 5-32 0x104-Interrupt Mask Register (INT_MASK) 5-33 0x10C-GPIO Control Register (GPIO_DMA_CTL) 5-34 0x110-I2C Data/Control Register 5-35 0x114-RISC Program Start Address Register (RISC_STRT_ADD) 5-36 0x118-GPIO Output Enable Control Register (GPIO_OUT_EN) 5-36 0x120-RISC Program Counter Register (RISC_COUNT) 5-36 0x200-0x2FF-GPIO Data Register (GPIO_DATA) 5-36
Control Register Definitions-Function
Configuration Space Configuration Registers (Header) 0x00-Vendor Device Register 0x04-Command Status Register 0x08-Revision Class Code Register 0x0C-Header Type Register 0x0C-Latency Timer Register 0x10-Base Address Register 0x2C-Subsystem Subsystem Vendor Register 0x34-Capabilities Pointer Register 0x3C-Interrupt Line, Interrupt Pin, Min_Gnt, Max_Lat Register. 0x40-Device Control Register 0x44-VPD Capability Register 0x48-VPD Data Register 0x4C-Power Management Capability Register 0x50-Power Management Support Register
Local Registers (Memory Mapped) 0x100-Interrupt Status Register (INT_STAT) 6-10 0x104-Interrupt Mask Register (INT_MASK) 6-11 0x10C-Audio Control Register (GPIO_DMA_CTL) 6-11 0x110-Audio Packet Lengths Register 6-13 0x114-RISC Program Start Address Register (RISC_STRT_ADD) 6-13 0x120-RISC Program Counter Register (RISC_COUNT) 6-13
Parametric Information
Electrical Parameters Electrical Parameters Package Mechanical Drawing
Appendix Acronym List
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Video Decoder
List Figures
List Figures
Figure 1-1. Figure 1-2. Figure 1-3. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 2-9. Figure 2-10. Figure 2-11. Figure 2-12. Figure 2-13. Figure 2-14. Figure 2-15. Figure 2-16. Figure 2-17. Figure 2-18. Figure 2-19. Figure 2-20. Figure 2-21. Figure 2-22. Figure 2-23. Figure 2-24. Figure 2-25. Figure 2-26. Figure 2-27. Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. Figure 3-7. Fusion 878A Detailed Block Diagram. Fusion 878A Audio/Video Decoder Scaler Block Diagram Fusion 878A Pinout Diagram. UltraLock Behavior NTSC Square Pixel Output Separation Chroma Demodulation Composite Video Separation Filter Responses Filtering Scaling Optional Horizontal Luma Low-Pass Filter Responses Combined Luma Notch, Oversampling Optional Low-Pass Filter Response (NTSC) Combined Luma Notch, Oversampling Optional Low-Pass Filter Response (PAL/SECAM) Combined Luma Notch Oversampling Filter Response Frequency Responses Four Optional Vertical Luma Low-Pass Filters 2-10 Peaking Filters 2-11 Luma Peaking Filters with Oversampling Filter Luma Notch 2-12 Effect Cropping Active Registers 2-17 Regions Video Signal 2-18 Coring 2-23 Regions NTSC Video Frame 2-24 Regions Video Frame (Fields 2-24 Timing 2-25 Section Block Diagram 2-26 Video Data Format Converter 2-28 Data FIFO Block Diagram. 2-32 Audio/Video RISC Block Diagram 2-37 Example Complex Clipping 2-44 Asynchronous Data Parallel Input Multiplexer Block 2-53 FIFO Interface 2-55 Audio Input Timing 2-57 Data Packet Mode Timing 2-58 Audio Data Path. 2-59 Typical External Circuitry. Clock Options Luma Chroma Oversampling Filter Video Block Diagram Audio Block Diagram GPIO Architecture 3-10 GPIO Normal Mode 3-11
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List Figures
Fusion 878A
Video Decoder
Figure 3-8. Figure 3-9. Figure 3-10. Figure 3-11. Figure 3-12. Figure 3-13. Figure 3-14. Figure 3-15. Figure 3-16. Figure 4-1. Figure 5-1. Figure 6-1. Figure 7-1. Figure 7-2. Figure 7-3.
GPIO Input Mode 3-12 GPIO Output Mode 3-13 Basic Timing Relationships Output Mode 3-15 Video Timing Output Mode 3-16 CCIR Interface Digital Input Port 3-19 GPIO Timing Diagram 3-20 Relationship Between 3-21 Typical Protocol Diagram 3-22 Instruction Register. 3-30 Optional Regulatory Circuitry Function Configuration Space Header Function Configuration Space Header Clock Timing Diagram JTAG Timing Diagram 128-pin PQFP Package Mechanical Drawing
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Fusion 878A
Video Decoder
List Tables
List Tables
Table 1-1. Table 1-2. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 2-12. Table 2-13. Table 2-14. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 4-1. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 7-1. Table 7-2. Table 7-3. Table 7-4. Table 7-5. Table 7-6. Table 7-7. Audio/Video Capture Product Family. Descriptions Grouped Function Video Input Formats Supported Fusion 878A Register Values Square Pixel Video Input Formats Scaling Ratios Popular Formats Using Frequency Values 2-16 Square Pixel Values. 2-18 Color Formats 2-29 Byte Swapping 2-31 Status Bits. 2-33 FIFO Full/Almost Full Counts 2-34 Table Access Latencies 2-35 RISC Instructions 2-38 Write Pixels RGB8 Mode 2-47 Gain Control 2-50 Digital Audio Packetizer Programming 2-54 Audio Data Formats. 2-59 Recommended Crystals Input GPIO Signals 3-12 GPIO Output Signals. 3-14 GPIO Mode Timing Parameters 3-17 Definition GPIO Port When Using Digital Video-In Mode 3-18 External EEPROM Memory 3-23 EEPROM Upload Sequence 3-24 Read Sequence 3-26 Write Sequence 3-26 Device Identification Register 3-30 Capacitor Location BRIGHT Parameters 5-13 CONTRAST Parameters. 5-15 (SAT_U_MSB SAT_U_LO) 5-16 SAT_V (SAT_V_MSB SAT_V_LO). 5-17 Parameters 5-18 Recommended Operating Conditions Absolute Maximum Ratings Characteristics. Clock Timing Parameters Power Supply Current Parameters JTAG Timing Parameters. Decoder Performance Parameters
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List Tables
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Product Overview
Functional Overview
Fusion 878A video audio capture chip multi-function peripheral component interconnect (PCI) device intended only operation. video function features direct memory access (DMA)/PCI master analog NTSC/PAL/SECAM composite, S-Video, digital CCIR video capture. audio function features completely independent DMA/PCI master radio sound capture. Fusion 878A based Bt848A video capture chip. Fusion 878A Bt848A upgraded include various audio capture capabilities. main features Bt848A are: NTSC/PAL/SECAM video decoding, multiple YCrCb pixel formats supported output, vertical blanking interval (VBI) data capture closed captioning, teletext, intercast data decoding. complete video audio capture features documented this data sheet. Table indicates which audio capture features added Bt848A produce Fusion 878A.
Table 1-1. Audio/Video Capture Product Family Features Bt848A, Plus:
Mono line level level audio capture Mono audio ACPI Support
CN878A
Figure illustrates block diagram Fusion 878A, Figure illustrates detailed block diagram decoder scaler sections Fusion 878A.
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Product Overview
Functional Overview
Fusion 878A
Video Decoder
Figure 1-1. Fusion 878A Detailed Block Diagram
Digital Audio
Controller Initiator Address Generator FIFO Data Instruction Queue Local Registers Instr Data Arbiter
Analog Audio
Audio Decoder
FIFO 35x36
Config Registers
Target Controller Interrupts
Parity Generator
Video Data Format Converter Analog Video YCrCb 4:2:2, 4:1:1 Video Decoder Video Scaler CSC/Gamma 8-Bit Dither Format FIFOs 70x36 35x36 35x36 DWORDs Instruction Queue Instr Data Address Generator FIFO Data Controller Initiator
Local Registers
GPIO
Master
Config Registers
Target Controller Interrupts
Parity Generator
Digital Video
879A_002
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Fusion 878A
Video Decoder
Product Overview
Functional Overview
Figure 1-2. Fusion 878A Audio/Video Decoder Scaler Block Diagram
Line-Level Audio Digital Audio (I2S) ADATA ALRCK ASCLK
Composite Composite Composite Composite/S-Video
Clocking Digital Audio Packetizer Audio FIFO Video Data Format Converter Audio Audio Processing
Radio-Audio
TV-Audio
AGCCAP
REFP
Hue, Saturation, Brightness Adjust
S-Video
Chroma Demod
879A_003
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Horizontal Vertical Filtering Scaling
Oversampling Low-Pass Filter
Separation
Product Overview
Detailed Features
Fusion 878A
Video Decoder
Detailed Features
1.2.1 Video Capture
Fusion 878A integrates NTSC/PAL/SECAM composite S-Video decoder, scaler, controller, master single device. Fusion 878A place video data directly into host memory video capture applications into target video display frame buffer video overlay applications. initiator, Fusion 878A take control soon available, thereby avoiding need on-board frame buffers. Fusion 878A contains pixel data FIFO decouple high speed from continuous video data stream. video data input scaled, color translated, burst-transferred target location field basis. This allows simultaneous preview field capture other field. Alternatively, Fusion 878A able capture both fields simultaneously preview both fields simultaneously. fields interlaced into memory sent separate field buffers.
1.2.2 Audio Capture
Fusion 878A also capture broadcast audio spectrum over bus. This enables system solutions without analog audio cable. addition, audio capture used implement microphone audio capture complete videoconferencing applications.
1.2.3 Analog Video Digital Camera Capture
Fusion 878A includes digital camera port support digital video capture. This specification defines registers functionality required implementing analog video capture support. Most analog digital video register settings identical. addition standard CCIR digital interface, Fusion 878A accept digital video from digital cameras such Conexant QuartsightTM, Silicon VisionTM, LogitechTM. Internally digital stream routed high-quality down-scaler color adjustment processing. then bus-mastered into system memory displayed graphics frame buffer.
1.2.4 Intel IntercastSupport
Fusion 878A fully supports Intel Intercast technology. Intel Intercast technology combines programming television Internet
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Product Overview
Detailed Features
1.2.5 Video Channels
Fusion 878A enables separate destinations even fields, each controlled pixel RISC instruction list. This instruction list created Fusion 878A device driver placed host memory. instructions control transfer pixels target memory locations byte resolution basis. Complex clipping accomplished instruction list, blocking generation cycles pixels that seen display. channels programmed field basis deliver video data packed planar format. packed mode, YCrCb data stored single continuous block memory. planar mode, YCrCb data separated into three streams which burst different target memory blocks. Having video data planar format useful applications where data compression accomplished software CPU.
1.2.6 Audio Channels
audio channel delivers 8-bit 16-bit digital samples digital frequency-multiplexed analog signal system memory packets DWORDs. RISC program controls audio Program Initiator. flow audio data audio RISC instructions completely independent asynchronous flow video data video RISC instructions. Since audio data path operates continuous transfer mode sync gaps), both analog digital audio inputs used other data capture applications. analog input offers usable effective bits usable effective bits. digital input offers Mbps parallel mode Mbps serial mode. audio channel controller similar video controller that supports packed mode RISC instructions. also only interfaces FIFO associated 6-bit DWORD counter. audio initiator identical video initiator; they have same controller interface same support interrupts configuration space. Since video audio initiators independent, each handle retries without inhibiting other. Thus, audio function initiate transfers host bridge even when target retrying video function. audio target similar video target with respect interrupts, configuration space, memory-mapped registers, parity error checking. main difference audio that memory-mapped registers remain within clock 32-bit interface domain. There register interface audio clock domain. Thus, this target never issues disconnect retry.
1.2.7 Data Transport Engine
Fusion 878A data transport engine operates instruction mode. Video data audio data delivered over under independent control.
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Fusion 878A
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1.2.8 Interface
Fusion 878A designed efficiently utilize available Mbps bus. 32-bit DWORDs output with appropriate image data under control channels. video stream consumes bandwidth with average data rates varying from Mbps full size RGB32, Mbps NTSC RGB16, 0.14 Mbps NTSC ICON 8-bit mode. pixel instruction stream channels consumes minimum Mbps. Fusion 878A provides means handling bandwidth bottlenecks caused slow targets long access latencies that occur some system configurations. overcome these system bottlenecks, Fusion 878A gracefully degrades recovers from FIFO overruns nearest pixel real time.
1.2.9 UltraLockFusion 878A employs proprietary technique known UltraLock lock incoming analog video signal. always generates required number pixels line from analog source which line length vary much microseconds. UltraLock's digital locking circuitry enables VideoStream decoders lock video signals quickly accurately, regardless their source. Since technique completely digital, UltraLock recognize unstable signals caused head switches other deviation adapt locking mechanism accommodate source. UltraLock uses nonlinear techniques that difficult, impossible, implement genlock systems. unlike linear techniques, adapts locking mechanism automatically.
1.2.10 Scaling Cropping
Fusion 878A reduce video image size both horizontal vertical directions independently, using arbitrarily selected scaling ratios. dimensions scaled down one-sixteenth full resolution. Horizontal scaling implemented with 6-tap interpolation filter, while 5-tap interpolation used vertical scaling with line store. video image arbitrarily cropped reducing number active scan lines active horizontal pixels line. Fusion 878A supports temporal decimation feature that reduces video bandwidth. This accomplished allowing frames fields dropped from video sequence fixed arbitrarily selected intervals.
1.2.11 Input Interface
Analog video signals input Fusion 878A four-input multiplexer. multiplexer select between four composite source inputs between three composite single S-Video input source. When S-Video source input Fusion 878A, luma component through input analog multiplexer, chroma component feeds directly into input pin. circuit enables Fusion 878A compensate non-standard amplitudes analog signal input.
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Fusion 878A
Video Decoder
Product Overview
Detailed Features
clock signal interface consists pair pins that connect 28.63636 NTSC Fsc) crystal. Either fundamental third harmonic crystals used. Alternatively, CMOS oscillators used.
1.2.12 GPIO Port
Fusion 878A provides 24-bit GPIO bus. This interface used input output general purpose signals. Alternatively, GPIO port used means input video data. example, Fusion 878A input video data from external digital camera bypass Fusion 878A's internal video decoder block.
1.2.13 Vertical Blanking Interval Data Capture
Fusion 878A provides complete solution capturing decoding data. Fusion 878A operate Line Output Mode, which data only captured during select lines. This mode operation enables concurrent capture lines containing ancillary data normal video image data. addition, Fusion 878A supports Frame Output Mode which every line video frame istreated were line. This mode operation designed with still frame capture/processing applications.
1.2.14 Interface
Fusion 878As interface supports both 99.2 timing transactions 396.8 kHz, repeated start, multi-byte sequential transactions. master, Fusion 878A program other devices video card, such tuner long device address known. Fusion 878A supports multi-byte sequential reads (more than transaction) multi-byte write transactions (greater than three transactions), which enable communication devices that support auto-incremental internal addressing.
1.2.15 HDTV Support
Fusion 878A ability accept either serial parellel HDTV data deliver that data host. Serial parellel inputs both audio channel transfer HDTV MPEG packets host. Serial HDTV streams input high speed serial port, which shares pins with digital audio (I2S) port. Fusion 878A will accept serial HDTV streams Mbps. Parellel HDTV data input GPIO port asychronous parallel mode Mbps.
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Product Overview
Descriptions
Fusion 878A
Video Decoder
Descriptions
Figure displays pinout diagram. Table provides description functions grouped common function.
Figure 1-3. Fusion 878A Pinout Diagram
INTA TRST MUX3 AGND MUX2 MUX1 MUX0 AGND REFP AGCCAP AGND VCCAP RBIAS VCOMO VCOMI VRXP
879A_004
AD[11] AD[10] AD[09] AD[08] CBE[0] AD[07] AD[06] AD[05] AD[04] AD[03] AD[02] AD[01] AD[00] GPIO[23] GPIO[22] GPIO[21] GPIO[20] GPIO[19] GPIO[18]
AD[31] AD[30] AD[29] AD[28] AD[27] AD[26] AD[25] AD[24] CBE[3] IDSEL AD[23] AD[22] AD[21] AD[20] AD[19] AD[18] AD[17] AD[16] CBE[2] FRAME IRDY TRDY DEVSEL STOP PERR SERR CBE[1] AD[15] AD[14] AD[13] AD[12]
Fusion 878A
VRXN BGND BGND SMXC ASCLK ALRCK ADATA GPIO[00] GPIO[01] GPIO[02] GPIO[03] GPIO[04] GPIO[05] GPIO[06] GPIO[07] GPIO[08] GPIO[09] GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] GPIO[16] GPIO[17] GPCLK
Conexant
100600B
Fusion 878A
Video Decoder
Table 1-2. Descriptions Grouped Function Name Signal
Interface Pins) Clock
Product Overview
Descriptions
Description
This input provides timing transactions. signals except INTA sampled rising edge CLK, other timing parameters defined with respect this edge. Fusion 878A supports clock 33.3333 MHz. This input three-states signals asynchronous signal. Agent desires bus. Agent granted bus. This input used select Fusion 878A during configuration read write transactions. These three-state, bidirectional pins transfer both address data information. transaction consists address phase followed more data phases either read write operations. address phase clock cycle which FRAME first asserted. During address phase, AD[31:0] contains byte address operations DWORD address configuration memory operations. During data phases, AD[7:0] contains least significant byte AD[31:24] contains most significant byte. Read data stable valid when TRDY asserted write data stable valid when IRDY asserted. Data transferred during clocks when both TRDY IRDY asserted. These three-state, bidirectional pins transfer both command byte enable information. During address phase transaction, CBE[3:0] signals contain command. During data phase, CBE[3:0] used byte enables. byte enables valid entire data phase determine which byte lanes carry meaningful data. CBE[3] refers most significant byte CBE[0] refers least significant byte. This three-state, bidirectional provides even parity across AD[31:0] CBE[3:0]. This means that number PAR, AD[31:0], CBE[3:0] equals even number. stable valid clock after address phase. data phases, stable valid clock after either TRDY asserted read, IRDY asserted write. Once valid, remains valid until clock after completion current data phase. AD[31:0] have same timing, delayed clock. target drives read data phases; master drives address write data phases.
4-11, 14-18, 21-23, 34-37, 41-44, 46-53
IDSEL AD[31:0]
Reset Request Grant Initialization Device Select Address/Data
CBE[3:0]
Command/Byte Enable
Parity
100600B
Conexant
Product Overview
Descriptions
Fusion 878A
Video Decoder
Table 1-2. Descriptions Grouped Function
Name
FRAME
Signal
Cycle Frame
Description
This sustained, three-state signal driven current master indicate beginning duration access. FRAME asserted signal beginning transaction. Data transfer continues throughout assertion. de-assertion, transaction final data phase. This sustained, three-state signal indicates master's readiness complete current data phase. IRDY used conjunction with TRDY. When both IRDY TRDY asserted, data phase completed that clock. During read, IRDY indicates when initiator ready accept data. During write, IRDY indicates when initiator placed valid data AD[31:0]. Wait cycles inserted until both IRDY TRDY asserted together. This sustained, three-state signal indicates device selection. When actively driven, DEVSEL indicates driving device decoded address target current access. This sustained, three-state signal indicates target's readiness complete current data phase. IRDY used conjunction with TRDY. When both IRDY TRDY asserted, data phase completed that clock. During read, TRDY indicates when target presenting data. During write, TRDY indicates when target ready accept data. Wait cycles inserted until both IRDY TRDY asserted together. This sustained, three-state signal indicates target requesting master stop current transaction. Report data parity error. Report address parity error. Open drain. This signal open drain interrupt output. JTAG Pins)
IRDY
Initiator Ready
DEVSEL
Device Select
TRDY
Target Ready
STOP PERR SERR INTA
Stop Parity Error System Error Interrupt
Test Clock
Used synchronize JTAG test structures. When JTAG operations being performed, this must driven logical low. JTAG input whose transitions drive JTAG state machine through sequences. When JTAG operations being performed, this must left floating tied high. JTAG used loading instructions controller loading test vector data boundary-scan operation. When JTAG operations being performed, this must left floating tied high. JTAG used verifying test results JTAG sampling operations. This output active certain JTAG operations will three-stated other times. JTAG used initialize JTAG controller. When JTAG operations being performed, this must driven logical low.
Test Mode Select
Test Data Input
Test Data Output
TRST
Test Reset
1-10
Conexant
100600B
Fusion 878A
Video Decoder
Table 1-2. Descriptions Grouped Function Name Signal
Interface Pins) Serial Clock Serial Data clock, output open drain.
Product Overview
Descriptions
Description
Data Acknowledge, output open drain.
General Purpose Pins) 56-61, 67-72, 75-86 GPCLK GPIO[23:0] Clock General Purpose Video clock. Internally pulled VDD. Fusion 878A decoding normal mode. Pins pulled VDD. additional information, Tables 3-5.
Digital Audio Input/Audio Test Signals Pins) ADATA ALRCK ASCLK Audio Data Audio Clock Audio Serial Clock serial data. Left/right framing clock. serial clock.
Reference Timing Interface Signals Pins) 28.63636 crystal tied directly these pins, single-ended oscillator connected XTI. Video Input Signals Pins) 114, 116, 118, MUX[0:3] Analog composite video inputs on-chip analog multiplexer. Unused inputs should tied AGND. output direct-coupled Y-A/D. reference ladder video A/Ds. Connect decoupling capacitor AGND. time-constant control capacitor node. Must connected 0.1µF capacitor AGND. Analog chroma input C-A/D. TV/Radio Audio Input Signals Pins) SMXC RBIAS VCOMO VCOMI VCCAP sound input from tuner. sound input from tuner. MIC/line input. Audio anti-alias filter node. Connect through capacitor BGND. Connection point external bias 9.53 resistor. Common mode voltage audio analog circuitry. This should connected external filtering capacitor. Common mode voltage audio analog circuitry. This should connected external filtering capacitor. Audio analog voltage compensation capacitor. This should connected external filtering capacitor.
REFP AGCCAP
100600B
Conexant
1-11
Product Overview
Descriptions
Fusion 878A
Video Decoder
Table 1-2. Descriptions Grouped Function
Name
VRXP VRXN
Signal
Description
Audio input circuitry reference voltage. This should connected external filtering capacitor. Audio input circuitry reference voltage. This should connected external filtering capacitor.
Core Power Ground Pins) Digital outputs power supply.
Digital outputs ground.
Analog Video Power Ground Pins) AGND AGND AGND video ground CREFN. Connect analog ground AGND. Charge pump power supply video power. Connect analog power 0.1µF decoupling capacitor AGND. Charge pump ground return. video power. Connect analog power 0.1µF decoupling capacitor AGND. video power. Connect analog power 0.1µF decoupling capacitor AGND. video ground. Connect analog ground AGND. Analog Audio Power Ground Pins)
NOTE(S):
Specification further documentation. Column Legend: Digital Input Digital Output I/O= Digital Bidirectional Analog Ground Power
BGND
Audio power supply. Ground audio A/D.
1-12
Conexant
100600B
Functional Description
UltraLockFunctionality
2.1.1 Challenge
line length (the interval between midpoints falling edges succeeding horizontal sync pulses) analog video sources constant. stable source such studio quality source test signal generators, this variation very small: However, unstable source such VCR, laser disk player, tuner, line length variation much microseconds. Digital display systems require fixed number pixels line despite these variations. Fusion 878A employs technique known UltraLock implement locking horizontal sync subcarrier incoming analog video signal, generating required number pixels line.
2.1.2 Operating Principles UltraLock
UltraLock based sampling using fixed-frequency, stable clock. Since video line length will vary, number samples generated using fixed-frequency sample clock will also vary from line line. number generated samples line always greater than number samples line required particular video format, number acquired samples reduced required number pixels line. Fusion 878A requires (28.63636 NTSC 35.46895 PAL) reference time source. clock signal, divided down internally (14.31818 NTSC 17.73 PAL). internal signals made available system. UltraLock operates although input waveform sampled then low-pass filtered decimated sample rate. (CLK sample rate there pixels NTSC 1,135 pixels PAL/SECAM within nominal line time interval (63.5 NTSC PAL/SECAM). square pixel NTSC PAL/SECAM formats, there should only pixels video line, respectively. This because square pixel clock rates slower than clock rate; example, 12.27 NTSC 14.75 PAL. UltraLock accommodates line length variations from nominal incoming video always acquiring more samples, effective rate, than required particular video format outputting correct number
100600B
Conexant
Functional Description
UltraLockFunctionality
Fusion 878A
Video Decoder
pixels line. UltraLock then interpolates required number pixels that maintains stability original image despite variation line length incoming analog waveform. Figure illustrates example three successive lines video being decoded square pixel NTSC output. first line shorter than nominal NTSC line time interval 63.5 this line, line time 63.2 sampled (14.31831 MHz) generates only pixels. second line matches nominal line time 63.5 provides expected pixels. Finally, third line long 63.8 within which pixels generated. three cases, UltraLock outputs only pixels.
Figure 2-1. UltraLock Behavior NTSC Square Pixel Output
Analog Waveform 63.2 63.5 63.8
Line Length Pixels Line Pixels Sent FIFO UltraLock879A_005
pixels
pixels
pixels
pixels
pixels
pixels
UltraLock used extract programmable number pixels from original video stream long nominal pixel line length (910 NTSC 1,135 PAL/SECAM) worst case line length validation from nominal active region greater than equal required number output pixels line; i.e.,
Desired
where:
Nominal number pixels line sample rate (910 NTSC, 1,135 PAL/SECAM) Variation pixel count from nominal (can PVar positive negative number) PDesired Desired number output pixels line With stable inputs, UltraLock guarantees time between falling edges HRESET within only pixel. UltraLock does, however, guarantee number active pixels line long above relationship holds.
PNom
NOTE:
Conexant
100600B
Fusion 878A
Video Decoder
Functional Description
Composite Video Input Formats
Composite Video Input Formats
Fusion 878A supports several composite video input formats. Table shows video formats some countries which each format used.
Table 2-1. Video Input Formats Supported Fusion 878A Format
NTSC-M NTSC-Japan(1) PAL-B, PAL-D PAL-I PAL-M PAL-NC PAL-N SECAM
NOTE(S):
Lines
Fields
3.58 3.58 4.43 4.43 4.43 3.58 3.58 3.58 4.406 MHz, 4.250 U.S., many others Japan
Country
Western/Central Europe, others China U.K., Ireland, South Africa Brazil Argentina Paraguay, Uruguay Eastern Europe, France, Middle East
NTSC-Japan setup.
video decoder must programmed appropriately each composite video input formats. Table lists register values that need programmed each input format.
Table 2-2. Register Values Square Pixel Video Input Formats Register
IFORM (0x01) Cropping: HDELAY VDELAY VACTIVE CROP HACTIVE HSCALE ADELAY BDELAY
NOTE(S):
FORMAT [2:0] [7:0] five registers
NTSC-M
desired cropping values registers 0x02AC 0x70 0x5D
NTSC-Japan
NTSC-M square pixel values
PAL-B,
desired cropping values registers 0x033C 0x7F 0x72
PAL-M
NTSC-M square pixel values
PAL-N
PAL-N Combination
SECAM
PAL-B, square pixel values
[15:0] [7:0] [7:0]
0x02AC 0x70 0x5D
0x02AC 0x70 0x5D
0x033C 0x7F 0x72
0x033C(1) 0x7F 0x72
0x033C 0x7F 0xA0
Fusion 878A will output square pixel resolution N-combination. smaller number pixels must output.
100600B
Conexant
Functional Description
Separation Chroma Demodulation
Fusion 878A
Video Decoder
Separation Chroma Demodulation
Figure illustrates separation chroma decoding. Band-pass notch filters implemented separate composite video stream. filter responses illustrated Figure 2-3. optional chroma comb filter implemented vertical scaling block. Section 2.4. Figure schematically describes filtering scaling operations. addition separation chroma demodulation illustrated Figure 2-2, Fusion 878A also supports chrominance comb filtering optional filtering stage after chroma demodulation. chroma demodulation generates baseband (NTSC) (PAL/SECAM) color difference signals. S-Video operation, digitized luma data bypasses separation block completely digitized chrominance passed directly chroma demodulator. monochrome operation, separation block must disabled saturation registers (SAT_U SAT_V)
Figure 2-2. Separation Chroma Demodulation Composite Video
Composite Notch Filter
Pass Filter Band Pass Filter
879A_006
Pass Filter
Conexant
100600B
Fusion 878A
Video Decoder
Figure 2-3. Separation Filter Responses
Luma Notch Filter Frequency Responses NTSC PAL/SECAM
Functional Description
Separation Chroma Demodulation
Chroma Band Pass Filter Frequency Responses NTSC PAL/SECAM
Amplitude [20*log10(ampl)]
NTSC
PAL/SECAM
NTSC
PAL/SECAM
879A_007
Frequency
Frequency
100600B
Conexant
Functional Description
Separation Chroma Demodulation
Fusion 878A
Video Decoder
Figure 2-4. Filtering Scaling
Horizontal Scaler Luminance
Vertical Scaler Luminance Chrominance
Chrominance
(Chroma Comb)
Vertical Filter Options Luminance
Optional Horizontal Pass Filter 6-Tap, 32-Phase Interpolation Horizontal Scaling
On-chip Memory
Luma Comb Vertical Scaling Vertical Filtering
2-Tap, 32-Phase Interpolation Horizontal Scaling
On-chip Memory Chroma Comb Vertical Scaling
879A_008
NOTE(S): refers pixel delay horizontal direction, line delay vertical direction. coefficients
determined UltraLock scaling algorithm.
Conexant
100600B
Fusion 878A
Video Decoder
Functional Description
Video Scaling, Cropping, Temporal Decimation
Video Scaling, Cropping, Temporal Decimation
Fusion 878A provides three mechanisms reduce amount video pixel data output stream: down-scaling, cropping, temporal decimation. three controlled independently.
2.4.1 Down-Scaling
2.4.1.1 Horizontal Vertical Scaling Fusion 878A provides independent arbitrary horizontal vertical down- scaling. maximum scaling ratio 16:1 both dimensions. maximum vertical scaling ratio reduced from 16:1 (when using frames) (when using fields). different methods used scaling luminance chrominance described following sections. Common Interchange Format (CIF) resolution video viewed 60/50 rates, then video fields must field-aligned proper overlay (sequenced each other successively). This could done interlaced Vertical Scaling mode (INT set) which group delays (filters) only field line. fields vertically aligned overlay, fields have different frequency responses. been filtered, while other been line-averaged. option exists filter both fields similar manner maintain proper field alignment. This mode selected setting VSFLDALIGN resetting non-interlaced Vertical Scaling mode.
2.4.1.2 Field Aligned Vertical Scaling
2.4.1.3 Luminance Scaling Horizontal Scaling first stage horizontal luminance scaling optional pre-filter which provides capability reduce anti-aliasing artifacts. generally desirable limit bandwidth luminance spectrum prior performing horizontal scaling because scaling high-frequency components create image artifacts resized image. optional pass filters illustrated Figure reduce horizontal high-frequency spectrum luminance signal. Figure Figure illustrates combined results optional low-pass filters, luma notch filter oversampling filter. Figure illustrates combined responses luma notch filter oversampling filter. Fusion 878A implements horizontal scaling through poly-phase interpolation. Fusion 878A uses different phases accurately interpolate value pixel. This provides effective pixel jitter less than simple pixel- line-dropping algorithms, non-integer scaling ratios introduce step function video signal that effectively introduces high-frequency spectral components. Poly-phase interpolation accurately interpolates correct pixel line position providing more accurate information. This results aesthetically pleasing video well higher compression ratios bandwidth limited applications.
100600B
Conexant
Functional Description
Video Scaling, Cropping, Temporal Decimation
Fusion 878A
Video Decoder
Figure 2-5. Optional Horizontal Luma Low-Pass Filter Responses
NTSC
Amplitude [20*log10(ampl)] Amplitude [20*log10(ampl)]
PAL/SECAM QCIF ICON
QCIF ICON
879A_009
Frequency
Frequency
Figure 2-6. Combined Luma Notch, Oversampling Optional Low-Pass Filter Response (NTSC)
QCIF
Full Spectrum
Pass Band
Amplitude [20*log10(ampl)]
ICON
Amplitude [20*log10(ampl)]
ICON
QCIF
879A_010
Frequency
Frequency
Conexant
100600B
Fusion 878A
Video Decoder
Functional Description
Video Scaling, Cropping, Temporal Decimation
Figure 2-7. Combined Luma Notch, Oversampling Optional Low-Pass Filter Response (PAL/SECAM)
QCIF
Amplitude [20*log10(ampl)]
Full Spectrum
Pass Band
Amplitude [20*log10(ampl)]
ICON
QCIF ICON
Frequency 879A_011
Frequency
Figure 2-8. Combined Luma Notch Oversampling Filter Response
Amplitude [20*log10(ampl)]
PAL/SECAM
NTSC
879A_012
Frequency
Vertical Scaling
vertical scaling, Fusion 878A uses line store implement four different filtering options. filter characteristics illustrated Figure 2-9. Fusion 878A provides 5-tap filtering ensure removal aliasing artifacts. Video Timing Control (VTC) register sets number taps vertical filter. user select taps. number taps must chosen conjunction with horizontal scale factor order ensure needed data fits internal FIFO (see VFILT bits register limitations). scaling ratio increased, number taps available vertical scaling increases. addition low-pass filtering, vertical interpolation also employed minimize artifacts when scaling non-integer scaling ratios.
100600B
Conexant
Functional Description
Video Scaling, Cropping, Temporal Decimation
Fusion 878A
Video Decoder
Figure 2-9. Frequency Responses Four Optional Vertical Luma Low-Pass Filters
2-tap
Amplitude [20*log10(ampl)]
3-tap
4-tap
5-tap
Frequency/Sampling_Frequency
879A_013
2.4.1.4 Peaking
Fusion 878A enables four different peaking levels programming PEAK HFILT bits SCLOOP register. filters illustrated Figure 2-10 Figure 2-11. more information, refer Loop Control Register.
2-10
Conexant
100600B
Fusion 878A
Video Decoder
Functional Description
Video Scaling, Cropping, Temporal Decimation
Figure 2-10. Peaking Filters
Amplitude [20*log10(ampl)]
HFILT HFILT
HFILT HFILT
Frequency
879A_014
Enhanced Resolution Passband
Amplitude [20*log10(ampl)]
HFILT HFILT
HFILT HFILT
Frequency
879A_015
100600B
Conexant
2-11
Functional Description
Video Scaling, Cropping, Temporal Decimation
Fusion 878A
Video Decoder
Figure 2-11. Luma Peaking Filters with Oversampling Filter Luma Notch
Amplitude [20*log10(ampl)]
HFILT HFILT HFILT HFILT
Frequency
Enhanced Resolution Passband HFILT HFILT
Amplitude [20*log10(ampl)]
HFILT HFILT
Frequency
879A_016
2-12
Conexant
100600B
Fusion 878A
Video Decoder
Functional Description
Video Scaling, Cropping, Temporal Decimation
Figure 2-11. Luma Peaking Filters with Oversampling Filter Luma Notch
Enhanced Resolution Passband HFILT HFILT
Amplitude [20*log10(ampl)]
HFILT HFILT
Frequency
879A_016a
2.4.1.5 Chrominance Scaling
2-tap, 32-phase interpolation filter used horizontal scaling chrominance. Vertical scaling chrominance implemented through chrominance comb filtering using line store, followed simple decimation line dropping.
2.4.1.6 Scaling Registers Horizontal Scaling Ratio Register (HSCALE) HSCALE programmed with horizontal scaling ratio. When outputting unscaled video NTSC), Fusion 878A produces pixels line. This corresponds pixel rate fCLK Fsc). This register control scaling video desired size. example, square pixel NTSC requires samples line, while CCIR requires samples line. HSCALE_HI HSCALE_LO 8-bit registers that, when concatenated, form 16-bit HSCALE register. method below uses pixel ratios determine scaling ratio. following formula should used determine scaling ratio entered into 16-bit register: NTSC: HSCALE 910/Pdesired) 4096 PAL/SECAM: HSCALE 1135/Pdesired) 4096 where: Pdesired Desired number pixels line video, including active, sync blanking.
100600B
Conexant
2-13
Functional Description
Video Scaling, Cropping, Temporal Decimation
Fusion 878A
Video Decoder
example, scale PAL/SECAM input square pixel QCIF, total number horizontal pixels desired 236: HSCALE 1135/236 4096 12331 3CF2 alternative method determining HSCALE value uses ratio scaled active region unscaled active region shown below: NTSC: PAL/SECAM: where: HSCALE (754 HACTIVE) 4096 HSCALE (922 HACTIVE) 4096
HACTIVE Desired number pixels line video, including sync blanking.
this equation, HACTIVE value cannot cropped; represents total active region video line. This equation produces roughly same result using full line length ratio shown first example. However, truncation, HSCALE values determined using active pixel ratio method will slightly different from those obtained using total line length pixel ratio method. values Table 2-3, were calculated using full line length ratio. Vertical Scaling Ratio Register (VSCALE) VSCALE programmed with vertical scaling ratio. defines number vertical lines output Fusion 878A. following formula should used determine value entered into this 13-bit register. loaded value two's-complement, negative value. VSCALE 0x10000 scaling_ratio 0x1FFF example, scale PAL/SECAM input square pixel QCIF, total number vertical lines 156: VSCALE 0x10000 0x1FFF 0x1A00 Only LSBs VSCALE value used; five LSBs VSCALE_HI 8-bit VSCALE_LO register form 13-bit VSCALE register. three MSBs VSCALE_HI used control other functions. user must take care alter values three MSBs when writing vertical scaling value.
2-14
Conexant
100600B
Fusion 878A
Video Decoder
Functional Description
Video Scaling, Cropping, Temporal Decimation
following C-code fragment illustrates changing vertical scaling value:
#define VSCALE_HI 0x13 #define VSCALE_LO 0x14 typedef unsigned char BYTE; typedef unsigned WORD; BYTE ReadFromFusion878A(BYTE regAddress); void WriteToFusion878A(BYTE regAddress, BYTE regValue); void SetFusion878AVScaling(WORD VSCALE) BYTE oldVscaleMSByte, newVscaleMSByte; existing VscaleMSByte value from Fusion878A VSCALE_HI register oldVscaleMSByte ReadFromFusion878A(VSCALE_HI); create VscaleMSByte, preserving bits newVscaleMSByte (oldVscaleMSByte 0xE0)|(VSCALE send VscaleMSByte VSCALE_HI WriteToFusion878A(VSCALE_HI, newVscaleMSByte); send VscaleLSByte VSCALE_LO WriteToFusion878A(VSCALE_LO, (BYTE) VSCALE);
where:
bitwise bitwise shift,
your target machine sufficient memory statically store scaling values locally, READ operation eliminated.
NOTE:
When scaling below resolution, useful single field opposed using both fields. Using single field will ensure there inter-field motion artifacts scaled output. When performing single field scaling, vertical scaling ratio will twice large when scaling with both fields. example, scaling from field does require vertical scaling, when scaling from both fields, scaling ratio 50%. Also, non-interlaced should reset when scaling from single field (INT=0 VSCALE_HI register).
Table lists scaling ratios various video formats register values required.
100600B
Conexant
2-15
Functional Description
Video Scaling, Cropping, Temporal Decimation
Fusion 878A
Video Decoder
Table 2-3. Scaling Ratios Popular Formats Using Frequency Values Output Resolution (Active Pixels)
640x480 720x480 720x576 768x576 320x240 360x240 360x288 384x288 160x120 180x120 180x144 192x144 80x60 90x60 90x72 96x72
Scaling Ratio
Format
Total Resolution
HSCALE Register Values
0x02AA 0x00F8 0x0504 0x033C 0x1555 0x11F0 0x1A09 0x1679 0x3AAA 0x3409 0x4412 0x3CF2 0x861A 0x7813 0x9825 0x89E5
VSCALE Register Values Both Fields
0x0000 0x0000 0x0000 0x0000 0x1E00 0x1E00 0x1E00 0x1E00 0x1A00 0x1A00 0x1A00 0x1A00 0x1200 0x1200 0x1200 0x1200
Single Field
0x0000 0x0000 0x0000 0x0000 0x1E00 0x1E00 0x1E00 0x1E00 0x1A00 0x1A00 0x1A00 0x1A00
Full Resolution
NTSC Pixel NTSC CCIR601 CCIR Pixel NTSC Pixel NTSC CCIR601 CCIR Pixel NTSC Pixel NTSC CCIR601 CCIR Pixel NTSC Pixel NTSC CCIR601 CCIR Pixel
780x525 858x525 864x625 944x625 390x262 429x262 432x312 472x312 195x131 214x131 216x156 236x156 97x65 107x65 108x78 118x78
QCIF
ICON
NOTE(S):
Including sync blanking interval.
2.4.2 Image Cropping
Cropping enables user output subsection video image. start active area vertical direction referenced VRESET (beginning field). horizontal direction referenced HRESET (beginning line). dimensions active video region defined HDELAY, HACTIVE, VDELAY, VACTIVE. four registers 10-bit values. CROP register contains MSBs each register, while lower eight bits respective HDELAY_LO, HACTIVE_LO, VDELAY_LO, VACTIVE_LO registers. vertical horizontal delay values determine position cropped image within frame while horizontal vertical active values pixel dimensions cropped image illustrated Figure 2-12.
2-16
Conexant
100600B
Fusion 878A
Video Decoder
Figure 2-12. Effect Cropping Active Registers
Functional Description
Video Scaling, Cropping, Temporal Decimation
Vertically Inactive
Video frame
Beginning Frame
Cropped image
VRESET
Vertically Active
Horizontally Inactive
Horizontally Active
Vertically Inactive
Video frame
Vertically Active
Cropped image scaled size
Horizontally Inactive
Horizontally Active
HRESET
879A_017
Beginning Line
100600B
Conexant
2-17
Functional Description
Video Scaling, Cropping, Temporal Decimation
Fusion 878A
Video Decoder
2.4.2.1 Cropping Registers Horizontal Delay Register (HDELAY) video decoding, HDELAY programmed with number pixels between horizontal sync first pixel each line displayed captured. GPIO SPIOUT, HDELAY programmed with number pixels between falling edge HRESET rising edge HACTIVE. HDELAY should even number first pixel, number register value programmed with respect scaled frequency clock. video decoding, HACTIVE programmed with actual number displayed captured pixels line. GPIO SPIOUT, HACTIVE programmed with number pixels that HACTIVE signal high after HACTIVE signal goes high. register value programmed with respect scaled frequency clock. video line considered combination three components:
Horizontal Active Register (HACTIVE)
Back porch Sync: defined HDELAY Active Video: defined HACTIVE Front Porch: total scaled pixels-HDELAY through HACTIVE
uncropped images, square pixel values these components displayed Table 2-4.
Table 2-4. Square Pixel Values Video Standard
NTSC PAL/SECAM
Front Porch
HDELAY
HACTIVE
Total
1135
Therefore, uncropped images values are: HDELAY (NTSC) (135/754 HACTIVE) 0x3FE HDELAY(PAL) (186/922 HACTIVE) 0x3FE cropped images, HDELAY increased HACTIVE decreased that HDELAY HACTIVE HSCALE NTSC 1108 HSCALE PAL. HDELAY HACTIVE much, then will front back porch pixels. Regions video signal illustrated Table 2-13.
Figure 2-13. Regions Video Signal
HDELAY
879A_018
Front Porch
HACTIVE
2-18
Conexant
100600B
Fusion 878A
Video Decoder
Functional Description
Video Scaling, Cropping, Temporal Decimation
Vertical Delay Register (VDELAY)
video decoding, VDELAY programmed with number half lines between serration pulses first line displayed captured. GPIO SPIOUT, VDELAY programmed with number half lines between rising edge VRESET rising edge VACTIVE. register value programmed with respect unscaled input signal. VDELAY must programmed even number avoid apparent field reversal. video decoding GPIO SPIOUT, VACTIVE programmed with number lines frame source video.
NOTE:
Vertical Active Register (VACTIVE)
important note difference between implementation horizontal registers (HSCALE, HDELAY, HACTIVE) vertical registers (VSCALE, VDELAY, VACTIVE). Horizontally, HDELAY HACTIVE programmed with respect scaled pixels defined HSCALE. Vertically, VDELAY VACTIVE programmed with respect number lines before scaling (before VSCALE applied).
GPIO SPIIN, registers HDELAY, HACTIVE, VDELAY, VACTIVE used.
2.4.3 Temporal Decimation
Temporal decimation provides solution video synchronization during periods when full frame rate cannot supported bandwidth system restrictions. example, when capturing live video storage, system limitations such hard disk transfer rates system bandwidth limit frame capture rate. these restrictions limit frame rate frames second, Fusion 878As time scaling operation enables system capture every other frame instead allowing hard disk timing restrictions dictate which frame capture. This maintains even distribution captured frames alleviates "jerky" effect caused systems that simply burst data when bandwidth becomes available. Fusion 878A provides temporal decimation either field frame basis. temporal decimation register (TDEC) loaded with value from (NTSC) (PAL/SECAM). This value number fields frames skipped chip during sequence NTSC PAL/SECAM. Skipped fields frames considered inactive, which indicated ACTIVE remaining low. Examples: TDEC 0x02 Decimation performed frames. frames skipped frames video, assuming NTSC decoding. Frames 1-29 output normally, then ACTIVE remains frame. Frames 31-59 then output followed another frame inactive video.
100600B
Conexant
2-19
Functional Description
Video Scaling, Cropping, Temporal Decimation
Fusion 878A
Video Decoder
TDEC 0x9E Decimation performed fields. Thirty fields output fields video, assuming NTSC decoding. This value outputs every other field (every field) video starting with field frame TDEC 0x01 Decimation performed frames. frame frames video skipped, assuming PAL/SECAM decoding. TDEC 0x00 Decimation performed. Full frame rate video output Fusion 878A. When changing programming temporal decimation register, 0x00 should loaded first, then decimation value. This ensures that decimation counter reset loaded first, decimation start field frame sequence PAL/SECAM). power-up, this preload necessary because counter internally reset. When decimating fields, FLDALIGN TDEC register programmed choose whether decimation starts with field even field. FLDALIGN logical first field dropped during decimation process will field. Conversely, setting FLDALIGN logical causes even field dropped first decimation process.
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Fusion 878A
Video Decoder
Functional Description
Video Adjustments
Video Adjustments
Fusion 878A provides programmable hue, contrast, saturation, brightness.
2.5.1 Adjust Register
Adjust Register (HUE) used offset decoded signal. NTSC, video signal defined phase subcarrier with reference burst. value programmed this register added subtracted from phase subcarrier, which effectively changes video. shifted degrees. Because nature PAL/SECAM encoding, adjustments made when decoding PAL/SECAM.
2.5.2 Contrast Adjust Register
Contrast Adjust Register (CONTRAST) (also called luma gain) provides ability change contrast from approximately 200% original value. decoded luma value multiplied 9-bit coefficient loaded into this register.
2.5.3 Saturation Adjust Registers
Saturation Adjust Registers (SAT_U, SAT_V) additional color adjustment registers. multiplicative gain signals. value programmed these registers coefficients multiplication. saturation range from approximately 200% original value.
2.5.4 Brightness Register
Brightness Register (BRIGHT) simply offset decoded luma value. programmed value added subtracted from original luma value which changes brightness video output. luma output range 255. Brightness adjustment made over range -128 +127.
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Functional Description
Automatic Chrominance Gain Control
Fusion 878A
Video Decoder
Automatic Chrominance Gain Control
Automatic Chrominance Gain Control (ACGC) compensates reduced chrominance color-burst amplitudes. Here, color-burst amplitude calculated compared nominal. color-difference signals then increased decreased amplitude according color-burst amplitude difference from nominal. range chrominance gain 0.5-2 times original amplitude. This compensation coefficient then multiplied saturation adjust value total chrominance gain range times original signal. Automatic chrominance gain control disabled.
Color Detection Removal
color-burst percent (NTSC) percent (PAL/SECAM) less nominal amplitude detected consecutive scan lines, color-difference signals When color detection active, reduced chrominance signal still separated from composite signal generate luminance portion signal. resulting values 128. Output chrominance signal re-enabled when color-burst percent (NTSC) percent (PAL/SECAM) greater nominal amplitude detected consecutive scan lines. color detection removal disabled.
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Fusion 878A
Video Decoder
Functional Description
Coring
Coring
Fusion 878A video decoder perform coring function, which forces values below programmed level This useful human more sensitive variations black images. taking near-black images turning them into black, image appears clearer eye. Four coring values selected: above black. total luminance level below selected limit, luminance signal truncated black value. luma range limited (i.e., black 16), then coring circuitry automatically takes this into account references appropriate value black. Coring illustrated Figure 2-14.
Figure 2-14. Coring
Output Luma Value Calculated Luma Value
879A_019
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Functional Description
Data Output Interface
Fusion 878A
Video Decoder
Data Output Interface
frame video composed lines NSTC PAL/SECAM. Figure 2-15 illustrates NTSC video frame, which there number distinct regions. video image picture data contained even fields within lines lines 525, respectively. Each field video also contains region vertical synchronization (lines through through 272) well region which contain non-video ancillary data (lines through through 283). These regions between vertical synchronization region video picture region referred portion video signal. Figure 2-16 illustrates video frame.
Figure 2-15. Regions NTSC Video Frame
Lines Lines 10-20 Vertical Synchronization Region Vertical Blanking Interval Field Even Field Field Even Field
Lines 21-263
Video Image Region
Lines 264-272 Lines 273-283
Vertical Synchronization Region Vertical Blanking Interval
Lines 284-525
Video Image Region
879A_020
Figure 2-16. Regions Video Frame (Fields
Lines Lines 7-23 Vertical Synchronization Region Vertical Blanking Interval
Lines 24-310
Video Image Region
Lines 311-318 Lines 319-335
Vertical Synchronization Region Vertical Blanking Interval
Lines 336-625
Video Image Region
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Fusion 878A
Video Decoder
Functional Description
Data Output Interface
Fusion 878A able capture data store host memory later processing Fusion 878A decoder software. modes capture exist: line output mode frame output mode. Both types data captured during same field.
2.9.1 Line Output Mode
line output mode, capture occurs during vertical blanking interval. start data capture VBI_HDELAY Packet Size/Delay register, reference trailing edge HRESET signal. number DWORDs data selected user. Each DWORD contains bytes, each pixel consists samples. example, given pixel line region, there exist 1600 samples, which equivalent DWORDs data. VBI_PKT_HI VBI_PKT_LO register bits concatenated create 9-bit value number DWORDs captured. line data capture occurs when CAPTURE_VBI_EVEN register enabled even field, CAPTURE_VBI_ODD register enabled field. data sampled rate stored FIFO sequence 8-bit samples. Line mode data starts horizontally beginning VBI_HDELAY pixels from trailing edge HRESET ending after VBI_PKT number DWORDs. Line mode data starts vertically beginning first line following VRESET ending VACTIVE. register settings changed only per-frame basis. timing illustrated Figure 2-17.
Figure 2-17. Timing
VRESET VBI_HDELAY VDELAY Line Data Capture HRESET VACTIVE VBI_PKT
879A_022
Once data been captured stored Fusion 878A FIFO, treated other type data. output over RISC instructions. number lines desired user smaller than entire vertical blanking region, extra data will discarded SKIP RISC instruction. Alternatively, user desires larger region line output mode, vertical blanking region extended setting VDELAY register appropriate value. line output mode effect extend region entire field. Figure 2-18 illustrates block diagram section.
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Functional Description
Data Output Interface
Fusion 878A
Video Decoder
Figure 2-18. Section Block Diagram
Video Data Format Converter Analog Video Data YCrCb 4:2:2, 4:1:1 CSC/Gamma 8-Bit Dither Format
FIFOs 70x36 35x36 35x36 Dwords
Controller
Initiator
Address Generator FIFO Data Instruction Queue
879A_023
frame output mode, data capture occurs active video region includes horizontal blank/sync information data stream. This feature used provide high quality still-capture video. data vertically bound beginning first line during VACTIVE ending after fixed number packets. data stream packetized into series 256-DWORD blocks. fixed number DWORD blocks (434 NTSC PAL) captured during each field. This equivalent 111,104 DWORDs NTSC (434 DWORDs) 166,400 DWORDs (650 DWORDs) field. frame capture region extended include lines prior default VACTIVE region setting EXT_FRAME register bit. VDELAY must also minimum value extended DWORD block size DWORD blocks NTSC DWORD blocks PAL. frame data capture occurs during even field when CAPTURE_EVEN register COLOR_EVEN mode, during field when CAPTURE_ODD register COLOR_ODD mode. captured data stream continuous aligned with HSYNC.
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Fusion 878A
Video Decoder
Functional Description
2.10 Video Data Format Conversion
2.10 Video Data Format Conversion
2.10.1 Pixel Data Path
video decoder/scaler portion Fusion 878A generates video data stream packed 4:2:2 YCrCb format. video data then color space-converted formatted 32-bit wide DWORD. Figure 2-19 illustrates steps converting video data from packed 4:2:2 YCrCb desired format. YCrCb 4:2:2 data up-sampled 4:4:4 format prior conversion RGB. then dithered, have gamma correction removed, presented directly byte swap circuit. case where 4:1:1 data desired, 4:2:2 data first down-sampled, then packed into BtYUV format (see Table 2-6) converted planar format vertically sub-sampled achieve YUV9 format. Alternatively, packed 4:2:2 data converted planar 4:2:2 vertically sub-sampled YUV12 format. vertical sub-sampling achieved appropriate instructions (see Section 2.12). Fusion 878A also offers color format, which chroma component packed 4:2:2 data stripped luma component packed into bits. This format otherwise known gray scale. Table lists various color formats supported Fusion 878A mapping bytes onto 32-bit DWORDs.
2.10.2 Video Control Code Status Data
addition pixel information, Fusion 878A's Video Data Format Converter provides four bits video control status code FIFO. These four bits status code STATUS[3:0] based inputs from video decoder/scaler block Fusion 878A convey information about pixel data state video timing (see Figure 2-19). STATUS[3:0] bits have four uses: specify FIFO mode (packed planar) provide information regarding pixel data (respective position pixel number valid bytes) indicate whether pixel data valid signal capture enabled field
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Functional Description
2.10 Video Data Format Conversion
Fusion 878A
Video Decoder
Figure 2-19. Video Data Format Converter
From Bt879 Family Video Decoder/Scaler Packed 4:2:2
Gamma Correction Removal Up-Sample Chroma Color Space Conversion Strip Chroma Pack Luma Sub-Sample Chroma Packed 4:1:1 Packed Planar Conversion Dither
Linear 8-Bit dithered
FI[31:0] FIFO
4:4:4
Byte
(Gray Scale) Swap
Packed 4:2:2
Planar 4:2:2 Planar 4:1:1
From FIFO
Packed 4:2:2
BtYUV
Planar 4:1:1
Packed Planar Conversion Internal Control Signals from Bt879 Family Video Decoder
Planar 4:2:2
Controller Vertical Sub-Sample Chroma
Status[3:0]
FI[35:32] Planar YUV12 Planar YUV9
Video FIFO Write Signals Control Code FIFO FIFO Write Clock Generator
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Video Decoder
Table 2-5. Color Formats
Functional Description
2.10 Video Data Format Conversion
Pixel Data [31:0] Format DWORD Byte Lane [31:24]
Alpha
Byte Lane [23:16]
Byte Lane [15:8]
Byte Lane [7:0]
RGB32(1) RGB24
RGB16 RGB15 YUY2-YCrCb 4:2:2(2)
{R1[7:3],G1[7:2],B1[7:3]} {0,R1[7:3],G1[7:3],B1[7:3]}
{R0[7:3],G0[7:2],B0[7:3]} {0,R0[7:3],G0[7:3],B0[7:3]}
BtYUV-YCrCb 4:1:1
(Gray Scale) Dithered Data YCrCb 4:2:2 Planar
FIFO1 FIFO1 FIFO2 FIFO3
YUV12 Planar YCrCb 4:1:1 Planar FIFO1 FIFO1 FIFO1 FIFO1 FIFO2 FIFO3 YUV9 Planar
NOTE(S):
Vertically sub-sampled 4:2:2 controller Cb12 Cr12
Vertically sub-sampled 4:1:1 controller
alpha byte written data, written. UYVY achieved byte swapping. planar modes require HACTIVE register multiple pixels.
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Functional Description
2.10 Video Data Format Conversion
Fusion 878A
Video Decoder
2.10.3 YCrCb Conversion
4:2:2 YCrCb data stream from video decoder portion Fusion 878A must converted 4:4:4 YCrCb before conversion occurs, using interpolation filter chroma data path. even valid chroma data passes through unmodified, while data generated averaging adjacent even data. chroma component up-sampled using following equations: etc. Cbn+1 (Cbn Cbn+2)/2 Crn+1 (Crn Crn+2)/2 Conversion: 1.164(Y-16) 1.596(Cr-128) 1.164(Y-16) 0.813(Cr-128) 0.391(Cb-128) 1.164(Y-16) 2.018(Cb-128) range [16,235] Cr/Cb range [16,240] range [0,255]
2.10.4 Gamma Correction Removal
Fusion 878A provides gamma correction removal capability. available gamma values are: NTSC: RGBout RGBin2.2 PAL: RGBout RGBin2.8 Gamma correction removal capability programmable field basis. Furthermore, gamma correction removal available when YCrCb data output.
2.10.5 YCrCb Sub-sampling
4:2:2 data stream horizontally sub-sampled 4:1:1 using following equations: etc.: (Cbn Cbn+2) (Crn Crn+2) Vertical sub-sampling supported Fusion 878As YUV9 YUV12 planar modes. these modes, video data first planarized placed FIFO 4:2:2 planar 4:1:1 planar data. FIFO data then vertically sub-sampled 4:1:1 YUV9 4:2:2 YUV12 formats. vertical sub-sampling performed RISC instructions that executed controller. Table 2-5, shows example 4-pixel line YUV9 YUV12 formats. YUV12 format, line Cr/Cb data discarded, hence 4:2:2 vertical
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Fusion 878A
Video Decoder
Functional Description
2.10 Video Data Format Conversion
sub-sampling achieved. YUV9 format, lines Cr/Cb data discarded, hence 4:1:1 vertical sub-sampling achieved.
2.10.6 Byte Swapping
Before data enters FIFO passes through 4-way allow swapping bytes support Macintosh (big endian) color data formats. pixel DWORD PD[31:0] maps onto FIFO input FI[31:0]. byte-swap remaps data bytes, byte lane bits[7:0] will still considered first byte scan line. Table 2-6.
Table 2-6. Byte Swapping Word Swap Byte Swap FIFO Inputs
FI[31:24] FI[23:16] FI[15:8] FI[7:0] PD[31:24] PD[23:16] PD[15:8] PD[7:0]
Outputs FIFO Data Formatter
PD[23:16] PD[31:24] PD[7:0] PD[15:8] PD[15:8] PD[7:0] PD[31:24] PD[23:16] PD[7:0] PD[15:8] PD[23:16] PD[31:24]
NOTE(S): byte swapping mode disabled during data.
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Functional Description
2.11 Video Control Data FIFO
Fusion 878A
Video Decoder
2.11 Video Control Data FIFO
FIFO block accepts data from video data format conversion process, buffers data FIFO memory, then outputs DWORDs Controller burst onto bus.
2.11.1 Logical Organization
630-byte data FIFO logically organized into three segments:
FIFO1 words deep bits wide FIFO2 bits FIFO3 bits
Each FIFO data words provide DWORD pixel data four bits video control code status. This illustrated Figure 2-20. FIFOs large enough support efficient size burst transfers data phases) planar well packed mode.
Figure 2-20. Data FIFO Block Diagram
From FIFO Input Data Formatter FI[35:32] FI[31:0] Control Status Code FIFO Write Signals (From VDFC) Pixel Data
FIFO1 FIFO2 FIFO3
FIFO Read Signals (From Controller)
FIFO Enable Signal (From Control Register) FIFO Write Clock (Synchronous Video Decoder Pixel Clock)
FIFO Read Clock (Synchronous Clock)
FIFO1 Output
879A_025
FIFO2 FIFO3 Output Output
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Video Decoder
Functional Description
2.11 Video Control Data FIFO
2.11.2 FIFO Data Interface
Loading data into FIFO begin only when valid pixels present during even field. pixel DWORD Pixel Data (PD) [31:0] stored FI[31:0], video control code STATUS[3:0] stored FI[35:32]. data will included captured sequence capture capability enabled. Four bits STATUS used encode information about pixel data state video timing unit (see Table 2-7). Video timing control information, along with data stream, passes through FIFO. FIFO buffer isolates asynchronous video input output domains. Control input stream occur only from video timing unit video decoder from configured registers. interaction synchronization controller RISC instruction sequence relies solely output side FIFO.
Table 2-7. Status Bits Status[3:0]
0110 1110 0010 0001 1101 1001 0101 0100 1100 0000
Code
Description
FIFO Mode: packed data follow FIFO Mode: planar data follow First active pixel/data DWORD scan line Last active pixel/data DWORD scan line, valid bytes Last active pixel/data DWORD scan line, valid bytes Last active pixel/data DWORD scan line, valid bytes Last active pixel/data DWORD scan line, valid byte VRESET following even field-falling edge FIELD VRESET following field-rising edge FIELD Valid pixel/data DWORD
Capturing data FIFO always begins with FIFO mode indicator code followed pixel data. FIFO mode indicator stored FIFOs beginning every capture-enabled field, when data format changed mid-field such transitioning from packed data planar mode, when video capture field asynchronously enabled. mode status codes always stored planar format. FIFO1 receives copies status code, while FIFO2 FIFO3 each receive copy. code packed FIFO with first valid pixel data byte, which first pixel DWORD scan line. code packed FIFO with last valid pixel data byte, which last DWORD location written FIFO scan line. code indicates valid bytes. VRE/VRO code stored FIFO capture-enabled field. controller activates appropriate byte-enable time given DWORD arrives output side FIFO. controller guarantees that FIFO does fill; therefore VDFC responsibility FIFO overruns. Controller will able resynchronize data streams that shorter longer than expected.
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Functional Description
2.11 Video Control Data FIFO
Fusion 878A
Video Decoder
Planar mode packed mode data present FIFOs same time access latency persists across FIELD transition, packed data proceeds planar YCrCb data.
2.11.3 Physical Implementation
three FIFO outputs delivered parallel that controller monitor FIFOs perform skipping (reading discarding data), necessary, three simultaneously. latency determining number DWORDs placed each FIFO, FIFO Full (FFULL) condition indicated prior FIFO count reaching maximum FIFO Size. FIFO considered FFULL when FIFO Count (FCNT) value equals exceeds FFULL value. Table indicates FIFO size FIFO Full/Almost Full counts units DWORDs.
Table 2-8. FIFO Full/Almost Full Counts FIFO
FIFO1 FIFO2 FIFO3 Total
Size
FFULL
FAFULL
read must occur same cycle FFULL, otherwise data will overflow will overwritten. maximum latencies various video formats modes shown Table 2-9. planar mode three FIFOs operate concurrently independently. packed mode, however, three FIFOs operate merged mode provide maximum size buffer. FSIZE1, indicate physical size each FIFO. FSIZET represents total buffer size when FIFOs work together packed mode.
2.11.4 FIFO Input/Output Rates
input output ports Fusion 878A's FIFO operate simultaneously asynchronous another. maximum FIFO input rate consecutive writes video 17.73 MHz. However, there never consecutive-pixel-cycle writes same FIFO. fastest FIFO write sequence Therefore, fastest write rate FIFO less than equal half pixel rate. maximum FIFO output read rate FIFO word clock rate MHz). three FIFOs read simultaneously. Some systems designed with clocks slower than MHz. Fusion 878A data FIFO only supports systems where maximum input data rate less than output data rate. support input video clock (17.73 MHz) faster than clock MHz) long video data rate does exceed available burst rate.
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Video Decoder
Table 2-9. Table Access Latencies Video Format
NTSC
Functional Description
2.11 Video Control Data FIFO
Resolution
RGB32 RGB24
Mode
Latency Before FIFO Overflow (µs)
RGB16/YCrCb 4:2:2 YCrCb 4:1:1 8-bit dithered, NTSC RGB32 RGB24 RGB16/YCrCb 4:2:2 YCrCb 4:1:1 8-bit dithered, PAL/SECAM RGB32 RGB24 RGB16/YCrCb 4:2:2 YCrCb 4:1:1 8-bit dithered, PAL/SECAM RGB32 RGB24 RGB16/YCrCb 4:2:2 YCrCb 4:1:1 8-bit dithered, Effective Rate NTSC NTSC NTSC
NOTE(S):
Pixels/Sec 12.27 6.14 13.50 14.75 7.38
above figures based 33.33 bus. Maximum latency before FIFO Overflow (µs) FIFO FAFULL Limit (Effective Rate Number Bytes/Pixel)
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Functional Description
2.12 Controller
Fusion 878A
Video Decoder
2.12 Controller
Fusion 878A incorporates unique controller architecture that gives capture system great flexibility ability deliver data memory. designed small RISC engine that runs instructions generated maintained host system memory Fusion 878A device driver software. video audio controllers identical except that audio controller does support planar mode instructions. this architecture, dynamically change target memory address from video line next. This enables multiple memory targets established various components each video frame. example, NTSC video frame contains four discrete components which require separate target memory locations: Even-field video image data Odd-field video image data Line closed captioning data Line teletext data
Fusion 878A concurrently support display memory target even-field image three separate system memory targets odd-field image, line data, line data images respectively. Fusion 878A device driver software creates RISC program which runs controller. RISC program resides host system memory. Through target, RISC program puts starting address Fusion 878A register makes available controller. controller then requests initiator fetch instruction. RISC instructions available WRITE, SKIP, SYNC, JUMP. Decoded composite video data stored Fusion 878A FIFO. controller then presents data initiator requests that data output target memory. initiator outputs pixel data after gaining access bus. responsibility controller prevent manage overflow Fusion 878A FIFOs. This process illustrated Figure 2-21.
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Video Decoder
Figure 2-21. Audio/Video RISC Block Diagram
Control Signals Controller Address/Data Decoder Code RISC Decoder RISC Instruction Buffer Address Byte Counter FIFO Data Buffer RISC Instructions
Functional Description
2.12 Controller
Initiator
Interface
FIFO Read Signals FIFO Status Bits Number bytes available FIFO FIFO Output [31:0]
From FIFO
Pixel Data [31:0] Address
RISC Program Start Address
RISC Program Counter
879A_026
2.12.1 Target Memory
Fusion 878A's FIFO DWORDs perfectly aligned bus: i.e., FIFO DWORDs lines with AD[0] bus. Thus, video scan line data aligned target memory locations, data path combinational logic between FIFO required. target memory given scan line data assumed linear, incrementing, contiguous. 1024-pixel scan line, maximum contiguous physical memory required. Each scan line stored anywhere 32-bit address space. scan line broken into segments with each segment sent different target area. image buffer allocated line fragments anywhere physical memory, because line sequence arbitrary.
2.12.2 RISC Program Setup Synchronization
There independent sets RISC instructions host memory: field other even field. first field begins with synchronization instruction (See SYNC Table 2-10) indicating packed planar data from FIFO (STATUS[3:0] FM3). first field ends with SYNC instruction indicating even field follow (STATUS[3:0] VRO). second field begins with SYNC instruction ends with SYNC instruction followed JUMP instruction back first field. SYNC instructions allow synchronization FIFO output RISC program start/end points.
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Functional Description
2.12 Controller
Fusion 878A
Video Decoder
software will pixel data flow creating RISC instruction sequence host memory even fields. controller normally branches through RISC instruction sequence JUMP instructions. RISC program sequence needs changed only when parameters video capture/preview mode change. Otherwise, controller continuously cycles through same program, which once control entire frame.
2.12.3 RISC Instructions
There five types packed mode RISC instructions-WRITE, WRITEC, SKIP, SYNC, JUMP-that control data stored FIFO. Three additional planar mode instructions exist, which replace simple packed mode WRITE/SKIP instructions. Instruction details listed Table 2-10. controller switches from packed mode planar mode vice versa based status codes flowing through FIFOs along with pixel data.
Table 2-10. RISC Instructions Instruction
WRITE
Opcode
0001
DWORDs
Description
Write packed mode pixels memory from FIFO beginning specified target address. DWORD0: [11:0] [15:12] [23:16] [24] [25] [26] [27] [31:28] Byte count Byte offset Byte enables Reset/Set RISC_STATUS Reserved Opcode
DWORD1:(1) [31:0]
NOTE(S):
32-bit target address
Byte address first pixel byte.
[1:0] Byte offset.
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Video Decoder
Table 2-10. RISC Instructions Instruction
WRITE123
Functional Description
2.12 Controller
Opcode
1001
DWORDs
Description
Write pixels memory planar mode from FIFOs beginning specified target addresses. DWORD0: [11:0] [15:12] [23:16] [24] [25] [26] [27] [31:28] DWORD1: [11:0] [27:16] DWORD2: [31:0] DWORD3: [31:0] DWORD4: [31:0] 32-bit target address Byte address data from FIFO3 32-bit target address Byte address data from FIFO2 32-bit target address Byte address data from FIFO1 Byte count Byte count Byte transfer count from FIFO2 Byte transfer count from FIFO3 Byte count Byte enables Reset/Set RISC_STATUS Reserved Opcode Byte transfer count from FIFO1
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Functional Description
2.12 Controller
Fusion 878A
Video Decoder
Table 2-10. RISC Instructions Instruction
WRITE1S23
Opcode
1011
DWORDs
Description
Write pixels memory planar mode from FIFO1 beginning specified target addresses. Skip pixels from FIFO2 FIFO3. This instruction used achieve YUV9 YUV12 color modes, where chroma components sub-sampled. DWORD0: [11:0] [15:12] [23:16] [24] [25] [26] [27] [31:28] DWORD1: [11:0] [27:16] DWORD2: [31:0] 32-bit target address Byte address data from FIFO1 Byte count Byte count Byte skip count from FIFO2 Byte skip count from FIFO3 Byte count Byte enables Reset/Set RISC_STATUS Reserved Opcode Byte transfer count from FIFO1
WRITEC
0101
Write packed mode pixels memory from FIFO continuing from current target address. DWORD0: [11:0] [15:12] [23:16] [24] [25] [26] [27] [31:28] Byte count Byte enables Reset/Set RISC_STATUS Reserved Opcode Cannot
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Video Decoder
Table 2-10. RISC Instructions Instruction
SKIP
Functional Description
2.12 Controller
Opcode
0010
DWORDs
Description
Skip pixels discarding byte-count number bytes from FIFO. This start stop middle DWORD. DWORD0: [11:0] [13:12] [15:14] [23:16] [24] [25] [26] [27] [31:28] Byte Count Byte Offset Reserved Reset/Set RISC_STATUS Reserved Opcode
SKIP123
1010
Skip pixels planar mode discarding byte count bytes from FIFO1 byte count from FIFO2 FIFO3. This start stop middle DWORD. DWORD0: [11:0] [15:12] [23:16] [24] [25] [26] [27] [31:28] DWORD1: [11:0] [27:16] Byte count Byte count Byte Count Reserved Reset/Set RISC_STATUS Reserved Opcode
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Functional Description
2.12 Controller
Fusion 878A
Video Decoder
Table 2-10. RISC Instructions Instruction
JUMP
Opcode
0111
DWORDs
Description
Jump RISC program counter jump address. This allows unconditional branching sequencer program. DWORD0: [15:0] [23:16] [24] [27:25] [31:28] DWORD1: [31:0] Jump address DWORD-aligned Reserved Reset/Set RISC_STATUS Reserved Opcode
SYNC
1000
Synchronize data FIFO until RISC instruction status bits equal FIFO status bits. DWORD0: [3:0] [14:4] [15] [23:16] [24] [27:25] [31:28] DWORD1: [31:0] Reserved Status Reserved RESYNC Reset/Set RISC_STATUS Reserved Opcode value disables FDSR errors
Each RISC instruction consists DWORDs. 32-bits DWORDs relay information such opcode, target address, status codes, synchronization codes, byte count/enables, start/end line codes. WRITE SKIP instructions indicates that this particular instruction first instruction scan line. WRITE SKIP instructions indicates that this particular instruction last instruction scan line. flag from FIFO last DWORD scan line coincide with finishing last instruction scan line. FIFO condition occurs early, current instruction instructions leading that contains flag will aborted. there only instruction process line, both bits will set. WRITE, WRITEC, SKIP control processing active pixel data stored FIFO. These three instructions alone control sequence packed mode data written target memory byte resolution basis. WRITEC instruction does supply target address. Instead, relies continuing from current pointer contained target address counter. This value updated kept current even during SKIP mode FIFO overruns. However,
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Video Decoder
Functional Description
2.12 Controller
WRITEC cannot used begin line; i.e., this instruction cannot have set. WRITE123, WRITE1S23, SKIP123 control processing active pixel data stored FIFOs. These three instructions alone control sequence planar mode data written target memory byte resolution basis. WRITE1S23 instruction supports further decimation chroma line basis. each these instructions, same number bytes will processed from FIFO2 FIFO3. JUMP instruction useful repeating same even/odd program every frame, switching program when sequence needs changed without interrupting pixel flow. SYNC instruction used synchronize RISC program pixel data stream. controller achieves this using status bits DWORD0 SYNC instruction matching them four FIFO status bits provided along with pixel data. Once controller matched status bits between FIFO RISC instruction, proceeds with outputting data. Prior establishing synchronization, controller reads discards FIFO data. Opcodes 0000 1111 reserved detect instruction errors. these opcodes other unused opcodes detected, interrupt will set. controller will stop processing until RISC program re-enabled. This also applies SYNC instructions specifying unused reserved status codes. Detecting RISC instruction errors useful detecting software errors programming, ensuring that controller following valid RISC sequence. other words, ensures that program counter pointing wrong location. unused/reserved bits instruction DWORDs must
2.12.4 Complex Clipping
When writing video data directly into on-screen display memory, necessary able clip video image before onto bus. Fusion 878A supports complex clipping video image those applications which require displayed video picture occluded graphics objects such pull-down menu, overlaying graphics window, etc. Typically, target graphics frame buffer controller cannot provide overlay control video pixel data stream when provided master peripheral graphics host interface. Fusion 878A implements clipping blocking video image being onto areas where graphics displayed, that where graphics objects "overlaying" video image. Fusion 878A cuts portions video image that "inlay" around displayed graphics objects clip list provided through graphics system DirectDRAW Interfaceprovider Fusion 878A device driver software. This indicates areas display where video image occluded. Fusion 878A driver software interprets clip list generates RISC program that blocks writing video pixels that occluded, illustrated Figure 2-22.
100600B
Conexant
2-43
Functional Description
2.12 Controller
Fusion 878A
Video Decoder
Figure 2-22. Example Complex Clipping
System DRAM Write #Bytes Line Write L40, Skip SYNC Write123 SYNC JUMP Field Prog Packed Frame Buffer Video Window Dialog Graphics Controller
Even Field Prog Planar 4:2:2
Host Bridge
Fusion 878A Family
879A_027
2.12.5 Executing Instructions
Once controller achieved synchronization between FIFO RISC program, starts executing RISC instructions. data FIFO will aligned with data bytes expected RISC instructions. controller reads RISC instructions performs burst writes from FIFO. controller programmed wait DWORDs FIFO before executing WRITE instruction. Setting this FIFO trigger point optimizes efficiency allowing controller access every time DWORD enters FIFO. However, FIFO trigger point ignored when controller near instruction number DWORDs left transfer less than number DWORDS FIFO. allowing instruction complete, even FIFO below trigger point, RISC instructions flushed sooner every scan line. Otherwise, controller have wait many scan lines before required number DWORDs present FIFO, especially when capturing highly scaled down images. There several horizontal lines before another DWORD enters FIFO. FIFO trigger point ignored controller during SKIP instructions. planar mode, trigger points FIFOs should same level, even though luma data being stored FIFO least twice fast chroma data being stored FIFOs. This ensures that FIFO will selected first burst data onto bus. When initiator disconnected from while planar mode, essential regain control soon possible deliver
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Fusion 878A
Video Decoder
Functional Description
2.12 Controller
queued DWORDs. controller will ignore FIFO trigger point because needs empty FIFO immediately. Otherwise have chance empty rest FIFOs before relinquish bus. This concern packed mode because three FIFOs treated large FIFO. When target detects parity error while initiator reading instruction data, controller immediately stops burst data writes RISC instruction reads. This condition also causes interrupt.
2.12.6 FIFO Overrun Conditions
There cases where Fusion 878A initiator cannot gain control bus, controller able execute necessary WRITE instructions. Instead writing data bus, controller reads data FIFO discards data. FIFO, appears controller outputting bus. This allows FIFO overruns handled gracefully, with minimal loss data. Fusion 878A required abort whole scan during FIFO overruns. controller keeps track data nearest byte, able deliver rest scan line case FIFO overrun condition cleared. Fusion 878A controller normally monitors FIFO Full (FFULL) counters determine full FIFOs are. However, before controller begins burst write operation process WRITE instruction, desirable have some headroom FIFO allowing more data enter while initiator waiting target respond. Hence, Fusion 878A monitors FIFO Almost Full (FAFULL) counters. difference between FFULL FAFULL provides necessary headroom handle target latency. Before controller executes address phase write transaction process WRITE instruction, FIFO count value must below FAFULL level. other times, FIFOs must maintained below FFULL level. FIFO counters three FIFOs monitored full/almost full conditions both planar packed modes. Once controller begins transaction, committed target start address. FIFO overflows while waiting target respond, initiator must terminate transaction just after target responds. This because controller start discarding FIFO data, since target pointer data sync. This terminating condition will communicated Fusion 878A device driver setting interrupt that indicates interfacing unreasonably slow targets (FBUS). instruction exhausted while FIFO overrun condition, Fusion 878A controller will continue discarding FIFO data during next pre-fetched instruction well. controller runs RISC instructions FIFO continues fill then access still denied. controller continues discarding FIFO data remainder that scan line. Once Fusion 878A controller detects control bits from FIFO, will attempt gain access resynchronize itself with RISC instruction status bits. However, controller successful getting control bus, will keep track number scan lines discarded FIFO will resynchronize itself with RISC program based number control signals detected.
100600B
Conexant
2-45
Functional Description
2.12 Controller
Fusion 878A
Video Decoder
planar mode requires that controller give priority FIFO emptied first. there very long latency getting access bus, three FIFOs will almost full when finally granted. While bursting data, CrCb data likely overflow. Attempting deliver data from each FIFO will yield poor performance. Preference given FIFO finish burst write operation, FIFOs each reach full condition, controller will discard their data parallel delivering data.
2.12.7 FIFO Data Stream Resynchronization
Fusion 878A controller constantly monitoring whether there mismatch between amount data expected RISC instruction amount data being provided FIFO. controller then corrects mismatches realigns RISC program FIFO data stream. example, FIFO contains shorter video line than expected RISC instruction, controller detects control code from FIFO earlier than expected. controller then aborts rest RISC instructions until detects control code from RISC program. FIFO contains longer video line than expected RISC instruction, controller will detect control code from FIFO expected time. controller will continue reading FIFO data; however will discard additional FIFO data until reaches control code from FIFO. Similarly, FIFO provides smaller number scan lines field than expected RISC program, field control codes from FIFO (VRE/VRO) will arrive early. controller then aborts RISC instructions until SYNC status codes from RISC instruction match field status codes from FIFO. FIFO provides larger number scan lines field than expected RISC program, field control codes from FIFO (VRE/VRO) will arrive expected time. Again, FIFO data read controller discarded until SYNC status codes from RISC instruction match field status codes from FIFO. controller manages above error conditions, FIFO Data Stream Resynchronization (FDSR) interrupt will well.
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Fusion 878A
Video Decoder
Functional Description
2.13 Byte Alignment
2.13 Byte Alignment
video function controllers initiators enhanced byte resolution target addresses packed color modes. FIFO DWORD-aligned data realigned with correct byte lanes according target address. Byte alignment Fusion 878A, which applies only packed modes, disables byte enables C/BE# during initial part line transfer. Since disabled bytes transferred written, they must still included total byte count. example, non-DWORD aligned target address begins line with offset then first byte (byte from FIFO shifted byte lane transferred first DWORD data with byte lanes disabled. remaining FIFO bytes (bytes 1-3) combined with following FIFO byte (byte form next DWORD transfer. Again, since RISC instruction's byte count represents number bytes transferred, number written, byte count must increased order account disabled bytes that were transferred first DWORD.
Table 2-11. Write Pixels RGB8 Mode RISC Instruction
WRITE WRITE WRITE WRITE
Byte Count
Target Address
F0040004 F0040005 F0040006 F0040007
Pixel/Byte Offset
target address used byte lane offset (relative address), opposed absolute byte address. multiple WRITE instructions used video line, each would have same byte offset matter which byte lane SKIP starts stops Formerly reserved bits [13:12] SKIP instruction must contain byte offset (two LSB's target address) they using byte aligned addresses. Byte alignment applies only video packed mode, only byte alignment occur line. video line transferred segments with byte alignments. notable case arises when combining SKIP WRITE with byte alignment offset. This produce WRITE transaction with byte enables active. example, first bytes skipped combined with WRITE address offset first data phase will have byte enables active. master will prevent null data transaction because will advance address. reason this SKIP consumes only bytes, address gets advanced only entire DWORD consumed going bus. second data phase then consists bytes with byte lane disabled.
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Conexant
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Functional Description
2.14 Multifunction Arbiter
Fusion 878A
Video Decoder
2.14 Multifunction Arbiter
internal arbiter necessary determine whether video audio controller claims when issued Fusion 878A. Only functions actually active during clock cycle. This also ensures that only function park bus. following rules outline arbitration algorithm. Internal signals REQ[0:1] GNT[0:1] video Function audio Function respectively.
2.14.1 Normal Mode
signal logical incoming function requests. internal GNT[0:1] signals gated asynchronously with demultiplexed audio request signal. Thus arbiter defaults video function power-up parks there during requests access. This desirable since video will request more often. However, audio will have highest access priority. Thus, audio will have first access even when issuing request after video request before external arbiter granted access Fusion 878A. Neither function preempt other once bus. Emptying entire video FIFO onto very short duration compared access latency that audio FIFO tolerate.
2.14.2 430FX Compatibility Mode
When using 430FX PCI, following rules will ensure compatibility: assert same time asserting FRAME. reassert request another transaction until after finishing previous transaction. Since individual masters have direct control REQ, simple logical video audio requests would violate rules. Thus, both arbiter initiator contain 430FX compatibility mode logic. enable 430FX mode, EN_TBFX indicated 0x40-Device Control Register. When EN_TBFX enabled, arbiter ensures that compatibility rules satisfied. Before asserted arbiter, this internal arbiter still logical requests. However, once issued, this arbiter must lock decision route only granted request pin. arbiter decision lock happens regardless state FRAME because does know when FRAME will asserted. (Typically, each initiator will assert FRAME cycle following GNT.) When FRAME asserted, initiator's responsibility remove request same time. arbiter's responsibility allow this request flow through allow other request hold asserted. decision lock removed transaction: example, when idle (FRAME IRDY). arbiter decision then continue asynchronously until again asserted.
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Conexant
100600B
Fusion 878A
Video Decoder
Functional Description
2.14 Multifunction Arbiter
2.14.3 Interfacing with Non-PCI Compliant Core Logic
small percentage core logic devices start transaction during same cycle that de-asserted. This compliant. ensure compatibility when using with these controllers, EN_VSFX must enabled (refer 0x40-Device Control Register). When this mode, arbiter does pass internal functions unless asserted. This prevents transaction from starting same cycle when asserted. This also side effect being able take advantage parking, thus lowering arbitration performance. Fusion 878A drivers must query these non-compliant devices, EN_VSFX only required.
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Conexant
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Functional Description
2.15 Audio
Fusion 878A
Video Decoder
2.15 Audio
2.15.1 Muxing Anti-aliasing Filtering
Before entering audio A/D, microphone/line audio inputs selected A_SEL multiplexed. selects break-before-make. A_SEL enabled. Thus SMXC used direct connect pre-amp (bypass MUX) only analog input required. Refer 0x10C-Audio Control Register (GPIO_DMA_CTL) Chapter register information. SMXC leads directly single-ended differential converter. resistive load seen audio inputs approximately
2.15.2 Input Gain Control
audio frequency (AF) output level from tuners ranges from mVRMS mVRMS, typically riding offset. nominal operating point VRMS (1.414 Vp-p), then input gain needs vary from -3.5 +6.0 input signal gained discrete linear steps A_GAIN[3:0]. Table 2-12 shows calculated gain values. A_GAIN value 0x10C-Audio Control Register (GPIO_DMA_CTL) Chapter 6.0.
Table 2-12. Gain Control A_GAIN
Input GAIN
0.500 0.667 0.833 1.000 1.167 1.333 1.500 1.667 1.833 2.000 2.167 2.333 2.500
-6.02 -3.52 -1.58 0.00 1.34 2.50 3.52 4.44 5.26 6.02 6.72 7.36 7.96
Nominal Input Vrms
1.000 0.750 0.600 0.500 0.429 0.375 0.333 0.300 0.273 0.250 0.231 0.214 0.200
Vp-p
2.828 2.121 1.697 1.414 1.212 1.061 0.943 0.849 0.771 0.707 0.653 0.606 0.566
2-50
Conexant
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Fusion 878A
Video Decoder
Table 2-12. Gain Control A_GAIN
Functional Description
2.15 Audio
Input GAIN
2.667 2.833 3.000
8.52 9.05 9.54
Nominal Input Vrms
0.188 0.176 0.167
Vp-p
0.530 0.499 0.471
addition switched capacitor gain control, there switch pre-amp. This additional amplification enabled A_G2X high. Thus, when A_GAIN equals A_G2X equals maximum signal input would 0.25 VRMS. boost useful very small input signals.
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Conexant
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Functional Description
2.16 High Speed Serial Interface Mode
Fusion 878A
Video Decoder
2.16 High Speed Serial Interface Mode
same interface used digital audio used other types digital serial data. With default settings, maximum data rate into serial interface 16.6 MHz, clock resampling ASCLK. Changing DA_APP DA_IOM bits allows direct ASCLK sampling increases maximum speed interface Mbps. DA_SBR must also proper transfer serial byte packets. ADATA input clocked into 8-bit shift register. basic timing relationship between ASCLK ADATA pins identical timing Digital Audio input mode (refer Figure 3-3). DA_SCE determines whether data clocked rising edge falling edge ASCLK. When DA_SCE (default) data clocked rising edge. falling-edge clocking desired, DA_SCE must changed DA_MLB determines order. When DA_MLB (default), "MSB first" format used. DA_MLB high, "LSB first" format used. There ways getting registered data into audio path packetization. DA_DPM low, ALRCK signal must transition every eighth signal input byte boundaries. (Both rising falling edges ALRCK used clock bytes.) Alternatively, DA_DPM high, 4-bit counter provided eliminate need continuos ALRCK. this case, recommended that ALRCK still used synchronized counter, less frequent basis.
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Fusion 878A
Video Decoder
Functional Description
2.17 Asynchronous Data Parallel Mode: Data Capture
2.17 Asynchronous Data Parallel Mode: Data Capture
asynchronous data parallel port interface allows user multiplex data from GPIO port into audio packetizer. Normally, audio processor selects 16-bit digitized analog data from audio from 16-bit digital audio input data. setting DA_APP Audio Control Register (0x10C), user configure part disregard 16-bit digital audio data, either information GPIO [23:8] high speed serial mode input from data port, illustrated Figure 2-23.
Figure 2-23. Asynchronous Data Parallel Input Multiplexer Block
DA_IOM[0]
Audio data Digita Audio
Audio formatter Channel
GPIO[23:8] High Speed Serial
DA_APP
879A_056
Asynchronous Data Parallel mode, DA_APP switches functionality ALRCK pin. When DA_APP high, ALRCK clock data GPIO [23:8]. This interface dubbed asynchronous, because clock requ
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