Memory ATL25 0.25µ Compiled Gate Level SRAMs Compiled Gate Level
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ATL25 Memory SRAMs 08/00
Memory ATL25 0.25µ Compiled Gate Level SRAMs
Compiled Gate Level SRAM Loading Common Single Port SRAM Sizes: Table. Common Port SRAM Sizes: Table. PRAM4X4 PRAM4X4R1W1 PRAM48X4 PRAM64X4 Single Port Operation Best Case Process Typical Case Process Worst Case Process. Port Operation Best Case Process Typical Case Process 9-10 Worst Case Process. 9-11 Atmel Compiled Embedded Megacell Library. 9-12 General Characteristics Atmel Megacell Compilers 9-12 Compiled Synchronous Megacells 9-12 Compiled Large Synchronous Megacells. 9-12 Compiled Asynchronous Megacells. 9-12 Compiled Asynchronous Dual-Port Megacells 9-13 Compiled Asynchronous Two-Port Megacells. 9-13 Compiled Synchronous Megacells 9-13
ATL25 Memory SRAMs 08/00
Compiled Gate Level SRAMs
Atmel offers variety compiled personalization RAMs ATL25 series gate arrays. These static asynchronous SRAMs utilize personalization layers occupy standard gate array sites. SRAMs come either port single port architectures. port SRAMs have sets address inputs, read address write address. output SRAM word which pointed read address. When (Write Enable) input goes low, word written address specified write address. single port SRAMs have address inputs which controls both write read operations. output SRAM always word which pointed address inputs. When input goes low, word written address specified address input. Both single port port SRAMs have enables their outputs. outputs stay high while output enable signal high. SRAMs compiled depths ranging from words words. following tables give size information some common SRAM sizes. Note that site count listed tables includes unusable sites immediately around SRAM. Contact Atmel exact size SRAM listed.
SRAM Loading
Single Port SRAM Inputs Port SRAM Inputs LOADS (unit loads): A0=4.0 A1=4.0 A2=4.0 A3=4.0 A4=4.0 LOADS (unit loads): A0=4.0 A1=4.0 A2=4.0 A3=4.0 A4=4.0 B0=4.0 N=4.0 WE=4.0 DIN=4.0 B1=4.0 B2=4.0 B3=4.0 B4=4.0 AN=4.0 BWE=4.0 DIN=4.0
Common Single Port SRAM Sizes
SRAM Width (bits)
sites PRAM4X8 sites PRAM8X8 sites PRAM12X8 sites PRAM16X8 1302 sites PRAM24X8 1694 sites PRAM32X8
sites PRAM4X12 sites PRAM8X12 sites PRAM12X12 1170 sites PRAM16X12 1674 sites PRAM24X12 2178 sites PRAM32X12
sites PRAM4X16 sites PRAM8X16 1122 sites PRAM12X16 1430 sites PRAM16X16 2046 sites PRAM24X16 2662 sites PRAM32X16
sites PRAM4X24 1110 sites PRAM8X24 1530 sites PRAM12X24 1950 sites PRAM16X24 2790 sites PRAM24X24 3630 sites PRAM32X24
sites PRAM4X32 1406 sites PRAM8X32 1938 sites PRAM12X32 2470 sites PRAM16X32 3534sites PRAM24X32 4598 sites PRAM32X32
Depth (words)
ATL25 Memory SRAMs
ATL25 Memory SRAMs 08/00
Common Port SRAM Sizes
SRAM Width (bits)
sites PRAM4X8R1W1 sites PRAM8X8R1W1 sites PRAM12X8R1W1 1005 sites PRAM16X8R1W1 1425 sites PRAM24X8R1W1 1845 sites PRAM32X8R1W1
sites PRAM4X12R1W1 sites PRAM8X12R1W1 1007 sites PRAM12X12R1W1 1273 sites PRAM16X12R1W1 1805 sites PRAM24X12R1W1 2337 sites PRAM32X12R1W1
sites PRAM4X16R1W1 sites PRAM8X16R1W1 1219 sites PRAM12X16R1W1 1541 sites PRAM16X16R1W1 2185 sites PRAM24X16R1W1 2829 sites PRAM32X16R1W1
sites PRAM4X24R1W1 1209 sites PRAM8X24R1W1 1643 sites PRAM12X24R1W1 2077 sites PRAM16X24R1W1 2945 sites PRAM24X24R1W1 3813 sites PRAM32X24R1W1
sites PRAM4X32R1W1 1521 sites PRAM8X32R1W1 2067 sites PRAM12X32R1W1 2613 sites PRAM16X32R1W1 3705 sites PRAM24X32R1W1 4797 sites PRAM32X32R1W1
DEPTH (words)
Below symbols single port SRAMs (PRAM4X4 PRAM4X4R1W1). Note that unused address inputs must tied SRAM will function properly (i.e. ADDR4 tied
SRAMs smaller than words, ADDR3 SRAMs smaller than words, ADDR2 SRAMs smaller than words, ADDR1 word SRAM). This also true port memories.
PRAM4X4
PRAM4X4R1W1
DIN0 DIN1 DIN2 DIN3
DOUT0 DOUT1 DOUT2 DOUT3
BDIN0 BDIN1 BDIN2 BDIN3
ADOUT0 ADOUT1 ADOUT2 ADOUT3
ATL25 Memory SRAMs 08/00
PRAM48X4
SRAMs multiplexed create deeper SRAM. example build single port SRAM shown below.
BUF2 BUF2 BUF2 BUF2 BUF2 INV2
A5BAR INV2
DIN0 DIN1 DIN2 DIN3
DOUT0 DOUT1 DOUT2 DOUT3
NAN2H
DOUT0
NAN2H
DOUT1
PRAM32X4
NAN2H
DOUT2 DOUT3
NAN2H
INV2 DIN0 INV2 DIN1 INV2 DIN2 INV2 DIN3
A5BAR
DIN0 DIN1 DIN2 DIN3
DOUT0 DOUT1 DOUT2 DOUT3
PRAM16X4
VSS!
ORR2
A5BAR
ORR2
following pages contain SRAM write read timing which gathered from running Spice simulations. write timing determined measuring propagation delay from ADDR, pins memory latch large (32x36) small (2x2) SRAM. times given were measured from input pins when actual data memory changed. This done initializing SRAM specific state such that only input under analysis changed, memory would changed. delays were measured memory rising
falling. longest path memory latch large SRAM represents maximum delay shortest path memory latch small SRAM represents minimum delay. setup hold timing were derived from these delays. equations used given with specifications. read timing determined measuring propagation delay through SRAMs. These Spice simulations were with best, typical worst temperature process conditions. Four unit loads were applied SRAM outputs Spice simulations.
ATL25 Memory SRAMs
ATL25 Memory SRAMs 08/00
PRAM64X4
SRAMs also connected with latched inputs create synchronous SRAM. example build single port synchronous SRAM shown below. Note: necessary initialize flop forcing reset beginning simulation.
DIN<3:0>
INV2 BUF2
D<3:0>
AL<0> AL<1> AL<2> AL<3> AL<4>
DIN0 DIN1 DIN2 DIN3
DOUT0 DOUT1 DOUT2 DOUT3
NAN2H
DOUT0
ADDR<4:0>
AL<4:0>
NAN2H
DOUT1
PRAM32X4
NAN2H
DOUT2 DOUT3
ADDR<5>
INV2
AL5B
INV2
WE_A
NAN2H
DEC4N VSS!
WE_B WE_A AL<0> AL<1> AL<2> AL<3> AL<4> AL5B WE_B
DIN0 DIN1 DIN2 DIN3
DOUT0 DOUT1 DOUT2 DOUT3
NAN2
DLY2 INV1
PRAM32X4
ATL25 Memory SRAMs 08/00
Single Port Operation 0.25µ Best Case Process
Compiled Personalization SRAMs
Conditions
Process Temperature Voltage Best Case
-55°C
Volts
Input (R/F) Output Load
0.250 0.024
Write Cycle*
MPWL ADDRSU DINSU
MPWH
ADDRHOLD DINHOLD
Minimum (PRAM 2X2) AHOLD DINSU DINHOLD WEMPWL WEMPWH 0.163 0.000 0.000 0.126 0.256 0.289
Maximum (PRAM 32x36) 0.184 0.000 0.000 0.596 0.844 0.780
*All time nanoseconds
ATL25 Memory SRAMs
ATL25 Memory SRAMs 08/00
Read Cycle*
Case DOUT, DOUT
PDA-DOUT PDN-DOUT DOUT
Case DOUT
PDWE-DOUT DOUT
Case DOUT
PDDIN-DOUT DOUT
Minimum (PRAM 2X2) PDA-DOUT PDN-DOUT PDWE-DOUT PDDIN-DOUT
*All time nanoseconds
Maximum (PRAM 32x36) 1.162 0.374 1.107 0.669
0.437 0.097 0.475 0.265
ATL25 Memory SRAMs 08/00
Single Port Operation 0.25µ Typical Case Process
Compiled Personalization SRAMs
Conditions
Process Voltage Temperature Typical Case Volts
25°C
Input (R/F) Output Load
0.250 0.024
Write Cycle*
MPWL ADDRSU DINSU
MPWH
ADDRHOLD
DINHOLD
Minimum (PRAM 2X2) AHOLD DINSU DINHOLD WEMPWL WEMPWH
*All time nanoseconds
Maximum (PRAM 32x36) 0.272 0.000 0.000 0.840 1.244 1.112
0.247 0.000 0.000 0.189 0.360 0.436
ATL25 Memory SRAMs
ATL25 Memory SRAMs 08/00
Read Cycle*
Case DOUT, DOUT
PDA-DOUT PDN-DOUT DOUT
Case DOUT
PDWE-DOUT DOUT
Case DOUT
PDDIN-DOUT DOUT
Minimum (PRAM 2X2) PDA-DOUT PDN-DOUT PDWE-DOUT PDDIN-DOUT
*All time nanoseconds
Maximum (PRAM 32x36) 1.681 0.527 1.617 0.970
0.636 0.130 0.674 0.385
ATL25 Memory SRAMs 08/00
Single Port Operation 0.25µ Worst Case Process
Compiled Personalization SRAMs
Conditions
Process Voltage Temperature Worst Case Volts 125°C Input (R/F) Output Load 0.250 0.024
Write Cycle*
MPWL ADDRSU DINSU
MPWH
ADDRHOLD DINHOLD
Minimum (PRAM 2X2) AHOLD DINSU DINHOLD WEMPWL WEMPWH
*All time nanoseconds
Maximum (PRAM 32x36) 0.605 0.000 0.000 1.262 1.889 1.867
0.422 0.000 0.000 0.307 0.549 0.729
9-10
ATL25 Memory SRAMs
ATL25 Memory SRAMs 08/00
Read Cycle*
Case DOUT, DOUT
PDA-DOUT PDN-DOUT DOUT
Case DOUT
PDWE-DOUT DOUT
Case DOUT
PDDIN-DOUT DOUT
Minimum (PRAM 2X2) PDA-DOUT PDN-DOUT PDWE-DOUT PDDIN-DOUT
*All time nanoseconds
Maximum (PRAM 32x36) 2.938 0.919 3.345 1.964
1.041 0.232 1.133 0.684
9-11
ATL25 Memory SRAMs 08/00
Dual Port Operation 0.25µ Best Case Process
Compiled Personalization SRAMs
Conditions
Process Voltage Temperature Best Case Volts -55°C Input (R/F) Output Load 0.250 0.024
Write Cycle*
BWEMPWL BDIN BDIN
MPWH
BHOLD
BDINHOLD
Minimum (PRAM 2X2R1W1) BHOLD BDINSU BDINHOLD BWEMPWL BWEMPWH
*All time nanoseconds
Maximum (PRAM 32x36R1W1) 0.112 0.000 0.000 0.599 0.848 0.711
0.068 0.000 0.000 0.130 0.258 0.198
9-12
ATL25 Memory SRAMs
ATL25 Memory SRAMs 08/00
Read Cycle*
Case ADOUT, ADOUT (BWE
PDA-ADOUT PDAN-ADOUT ADOUT
Case ADOUT
BDIN PDBWE-ADOUT ADOUT
Case BDIN ADOUT
BDIN PDBDIN-ADOUT ADOUT
Minimum (PRAM 2X2R1W1) PDA-DOUT PDAN-ADOUT PDBWE-ADOUT PDBDIN-ADOUT
*All time nanoseconds
Maximum (PRAM 32x36R1W1) 1.142 0.378 1.113 0.699
0.424 0.099 0.479 0.265
9-13
ATL25 Memory SRAMs 08/00
Dual Operation 0.25µ Typical Case Process
Compiled Personalization SRAMs
Conditions
Process Voltage Temperature Typical Case Volts 25°C Input (R/F) Output Load 0.250 0.024
Write Cycle*
BWEMPWL BDIN BDIN
MPWH
BHOLD
BDINHOLD
Minimum (PRAM 2X2R1W1) BHOLD BDINSU BDINHOLD BWEMPWL BWEMPWH
*All time nanoseconds
Maximum (PRAM 32x36R1W1) 0.112 0.000 0.000 0.599 1.254 1.019
0.068 0.000 0.000 0.130 0.368 0.436
9-14
ATL25 Memory SRAMs
ATL25 Memory SRAMs 08/00
Read Cycle*
Case ADOUT, ADOUT (BWE
PDA-ADOUT PDAN-ADOUT ADOUT
Case ADOUT
BDIN PDBWE-ADOUT ADOUT
Case BDIN ADOUT
BDIN PDBDIN-ADOUT ADOUT
Minimum (PRAM 2X2R1W1) PDA-ADOUT PDAN-ADOUT PDBWE-ADOUT PDBDIN-ADOUT
*All time nanoseconds
Maximum (PRAM 32x36R1W1) 1.681 0.528 1.624 0.969
0.614 0.136 0.681 0.383
9-15
ATL25 Memory SRAMs 08/00
Dual Operation 0.25µ Worst Case Process
Compiled Personalization SRAMs
Conditions
Process Voltage Temperature Worst Case Volts 125°C Input (R/F) Output Load 0.250 0.024
Write Cycle*
BWEMPWL BDIN BDIN
MPWH
BHOLD
BDINHOLD
Minimum (PRAM 2X2R1W1) BHOLD BDINSU BDINHOLD BWEMPWL BWEMPWH
*All time nanoseconds
Maximum (PRAM 32x36R1W1) 0.409 0.000 0.000 1.271 1.902 1.558
0.216 0.000 0.000 0.313 0.558 0.529
9-16
ATL25 Memory SRAMs
ATL25 Memory SRAMs 08/00
Read Cycle*
Case ADOUT, ADOUT (BWE
PDA-ADOUT PDAN-ADOUT ADOUT
Case ADOUT
BDIN PDBWE-ADOUT ADOUT
Case BDIN ADOUT
BDIN PDBDIN-ADOUT ADOUT
Minimum (PRAM 2X2R1W1) PDA-ADOUT PDAN-ADOUT PDBWE-ADOUT PDBDIN-ADOUT
*All time nanoseconds
Maximum (PRAM 32x36R1W1) 2.888 0.920 3.356 1.962
1.013 0.237 1.143 0.681
9-17
ATL25 Memory SRAMs 08/00
Atmel Compiled Embedded Megacell Library
Atmel Compiled Megacell Library enables compilation megacells functions Synchronous RAM, Large Synchronous RAM, Asynchronous RAM, Asynchronous Dual-Port RAM, Asynchronous TwoPort Synchronous ROM, according user's precise requirements.
Large Synchronous Configurations
range permitted Large Synchronous megacell configurations follows:
Number bits Number words Word Size 16K, 2.25M bits bits
Large Synchronous Example Characteristics
following table shows range performances particular Large Synchronous configurations under typical conditions.
(64K bits) (256K bits) bits) 0.29 0.55 1.22
General Characteristics Atmel Megacell Compilers
Atmel megacells instanced often required designs. megacell representations required synthesis, simulation, layout generation, place route, verification created automatically.
Configuration Density (Kbits/mm2) Frequency (MHz) Dynamic Power (mW/MHz)
Compiled Synchronous Megacells
General Synchronous Characteristics
Atmel Synchronous compiler bidirectional separate ports, configured multi-bank form, with maximum four banks.
Compiled Asynchronous Megacells
General Asynchronous Characteristics
Atmel Asynchronous compiler bidirectional separate ports, configured multi-bank form, with maximum four banks.
Synchronous Configurations
range permitted Synchronous megacell configurations follows:
Number bits Number words Word Size 128, 144K bits bits
Asynchronous Configurations
range permitted Asynchronous megacell configurations follows:
Number bits Number words Word Size 128, 128K bits bits
Synchronous Example Characteristics
following table shows range performances particular Synchronous configurations under typical conditions.
Configuration Density (Kbits/mm2) Frequency (MHz) Dynamic Power (mW/MHz) bits) (32K bits) (128K bits) 0.17 0.36 0.73
Asynchronous Example Characteristics
following table shows range performances particular Asynchronous configurations under typical conditions.
bits) (32K bits) (128K bits) 0.24 0.38 0.63
Configuration Density (Kbits/mm2) Frequency (MHz) Dynamic Power (mW/MHz)
Compiled Large Synchronous Megacells
General Large Synchronous Characteristics
Atmel Large Synchronous compiler bidirectional separate ports, configured multi-bank form, with maximum four banks.
9-18
ATL25 Memory SRAMs
ATL25 Memory SRAMs 08/00
Compiled Asynchronous Dual-Port Megacells
General Asynchronous Dual-Port Characteristics
bidirectional separate ports, configured multi-bank form, with maximum four banks.
Asynchronous Two-Port Example Characteristics
following table shows range performances particular Asynchronous Two-Port configurations under typical conditions.
bits) 0.06 bits) 0.10 (32K bits) 0.18
Configuration Density (Kbits/mm2) Frequency (MHz) Dynamic Power (mW/MHz)
Asynchronous Dual-Port Configurations
range permitted Asynchronous Dual-Port Megacell configurations follows:
Number bits Number words(1) Word Size(1) 128, bits
Compiled Synchronous Megacells
General Synchronous Characteristics
Atmel Synchronous diffusion programmable applicable power solutions. configured multi-bank form, with maximum four banks.
Note:
Must same both ports.
Asynchronous Dual-Port Example Characteristics
following table shows range performances particular Asynchronous Dual Port configurations under typical conditions.
Configuration Density (Kbits/mm2) Frequency (MHz) Dynamic Power (mW/MHz) bits) 0.09 bits) 0.31 (16K bits) 0.41
Synchronous Configurations
range permitted Synchronous Megacell configurations follows:
Number bits Number words Word Size 256, 576K bits
Synchronous Example Characteristics
following table shows range performances particular Synchronous configurations under typical conditions.
Configuration Density (Kbits/mm2) Frequency (MHz) Dynamic Power (mW/MHz) (16K bits) (64K bits) (256K bits) 0.13 0.26 0.54
Compiled Asynchronous Two-Port Megacells
General Asynchronous Two-Port Characteristics
Atmel Asynchronous Two-Port configured multi-bank form, with maximum four banks, used achieve FIFO functions.
Asynchronous Two-Port Configurations
range permitted Asynchronous Two-Port Megacell configurations follows:
Number bits Number words(1) Word Size(1) 128, bits
Note:
Must same both ports.
9-19
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