MN102H51K/F51K/57K/F57K User's Manual Pub.No.22357-036E Pana
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MN102H51K/F51K/57K/F57K User's Manual
Pub.No.22357-036E
PanaXSeries trademark Matsushita Electric Industrial Co., Ltd. other corporation names, logotypes product names written this manual trademarks registered trademarks their corresponding corporations. MN102F51K/F57K manufactured sold under License Agreement with BULL Inc., MN102F51K/F57K into card allowed.
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Contents
Contents
About This Manual Using This Manual. Text Conventions Register Conventions Related Documents Questions Comments 1.6.1 1.6.2 1.7.1 1.7.2 2.2.1 2.2.2 3.1.1 3.1.2 3.1.3 General Description MN102H Series Overview. MN102H Series Features MN102H Series Description
General Specifications Block Diagram Descriptions MN102H51K Description MN102H57K Description Interface Description Interface Control Registers Interrupts Description. Interrupt Setup Examples. Setting External Interrupt Setting Watchdog Timer Interrupt Interrupt Control Registers Low-Power Modes Modes Description Exiting from SLOW Mode NORMAL Mode Notes Invoking Exiting STOP HALT Modes Turning Individual Functions Control Register Timers 8-Bit Timer Description 8-Bit Timer Features 8-Bit Timer Block Diagrams 8-Bit Timer Setup Examples 8-Bit Timer Timing
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Contents
4.5.1 4.5.2 4.10 4.11 4.11.1 4.11.2 4.11.3 4.11.4 4.11.5 4.11.6 4.11.7 4.11.8 4.11.9 4.11.10 4.12 5.3.1 5.3.2 5.3.3 5.5.1 5.5.2 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 6.4.1
Setting Event Counter Using Timer Setting Interval Timer Using Timers 8-Bit Timer Control Registers 16-Bit Timer Description 16-Bit Timer Features 16-Bit Timer Block Diagrams 16-Bit Timer Timing 16-Bit Timer Setup Examples Setting Event Counter Using Timer Setting Single-Phase Output Signal Using Timer Setting Two-Phase Output Signal Using Timer Setting Single-Phase Capture Input Using Timer Setting Two-Phase Capture Input Using Timer Setting Two-Phase Encoder Input Using Timer Setting Two-Phase Encoder Input Using Timer Setting One-Shot Pulse Output Using Timer Setting External Count Direction Controller Using Timer Setting External Reset Control Using Timer 16-Bit Timer Control Registers Serial Interfaces Description. Features Connecting Serial Interfaces Synchronous Serial Mode Connections UART Mode Connections Mode Connection UART Mode Baud Rates .129 Serial Interface Timing Synchronous Serial Mode Timing UART Mode Timing Serial Interface Setup Examples Setting UART Transmission Using Serial Interface Setting Synchronous Serial Reception Using Serial Interface Setting Serial Interface Clock. Setting Transmission Using Serial Interface Setting Reception Using Serial Interface Serial Interface Control Registers Analog-to-Digital Converter. Description. Features Block Diagram Conversion Timing. Selecting Clock Source.
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Contents
6.4.2 6.4.3 6.4.4 6.4.5 6.5.1 6.5.2 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.6.1 7.6.2 7.7.1 7.7.2 7.8.1 7.8.2 7.8.3 7.9.1 7.9.2 7.10 7.10.1 7.10.2 7.10.3 7.10.4 7.11 7.12 7.13 7.13.1 7.13.2
Single Channel/Single Conversion Timing Multiple Channel/Single Conversion Timing Single Channel/Continuous Conversion Timing Multiple Channel/Continuous Conversion Timing Setup Examples Setting Software-Controlled Single-Channel Conversion Setting Hardware-Controlled Intermittent Three-Channel Conversion Control Registers Caution about Analog-to-Digital Converter. On-Screen Display Description. Features Block Diagram Power-Saving Considerations Block. Operation. Clock External Input Sync Signals Multi-Layer Format Output Setup Microcontroller Interface VRAM Conditions VRAM Writes Standard Extended Display Modes Cursor Layer Display Modes Graphics Layer Display Modes Display Setup Examples Setting Graphics Layer. Setting Text Layer VRAM VRAM Operation. VRAM Organization Cautions about number display code VRAM. ROM. Organization Graphics Organization Different Color Modes Setting Setting Display Colors. Text Layer Functions Display Sizes Setting Display Position Interrupt Timing Selecting Clock Controlling Shuttering Effect. Controlling Shuttered Area Controlling Shutter Movement.
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Contents
7.13.3 7.13.4 7.14 7.14.1 7.14.2 7.14.3 7.15 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.5.1 8.3.5.2 8.3.5.3 8.3.5.4 8.3.6 9.3.1 9.3.2 9.3.3 9.3.3.1 9.3.3.2 9.3.3.3 9.3.4 9.3.5 9.3.5.1 9.3.5.2 10.1 10.2 10.3
Controlling Shuttering Effects Controlling Line Shuttering Field Detection Circuit. Block Diagram Description Considerations Interlaced Displays Registers Remote Signal Receiver Description. Block Diagram Remote Signal Receiver Operation Operating Modes Noise Filter. 8-Bit Data Reception Identifying Data Format Generating Interrupts .221 Leader Detection Trailer Detection. 8-Bit Data Reception Detection Edge Detection Controlling SLOW Mode. Remote Signal Receiver Control Registers Closed-Caption Decoder Description. Block Diagram Functional Description. Analog-to-Digital Converter Clamping Circuit Sync Separator Circuit HSYNC Separator VSYNC Separator Field Detection Circuit Data Slicer Controller Sampling Circuit Detection Sampling Clock Generation Data Capture Control Closed-Caption Decoder Registers Pulse Width Modulator. Description. Block Diagram Data Registers
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Contents
11.1 11.2 11.3 12.1 12.2 12.3 12.4 13.1 13.2 13.3 13.4 13.5 13.6 13.6.1 13.6.1.1 13.6.1.2 13.6.1.3 13.6.1.4 13.6.2 13.6.2.1 13.6.2.2 13.6.2.3 13.6.2.4 13.7 14.1 14.2 14.3 14.4
Ports. Description. Port Circuit Diagrams Port Control Registers Correction Description. Block Diagram Programming Considerations. Correction Control Registers Controller. Description. Block Diagram Functional Description. Setting Connection Waveform Characteristics Interface Setup Examples Setting Transition from Master Transmitter Master Receiver Pre-configuring. Setting First Interrupt Setting Second Interrupt Setting Third Interrupt Setting Transition from Slave Receiver Slave Transmitter Pre-configuring. Setting First Interrupt Setting Second Interrupt Setting Third Interrupt Interface Registers Counter Description. Block Diagram Counter Operation Counter Control Registers
Appendix Register Map. Appendix MN102HF51K Flash EEPROM Version B.4.1 Description. Benefits Using PROM Writer Mode Using Onboard Serial Programming Mode Configuring System Onboard Serial Programming
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Contents
B.4.2 B.4.3 B.4.3.1 B.4.3.2 B.4.4 B.4.4.1 B.4.4.2 B.4.5 B.4.6 B.4.7 B.4.7.1 B.4.7.2
Circuit Requirements Target Board Microcontroller Hardware Used Onboard Serial Programming Serial Writer Interface Description Serial Writer Interface Block Diagram Microcontroller Memory Used During Onboard Serial Programming Flash Address Space. Address Space Microcontroller Clock Target Board Setting Onboard Serial Programming Mode Branching User Program Branching Reset Start Routine Branching Interrupt Start Routine Reprogramming Flow Programming Times.
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List Tables
List Tables
7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 General Specifications Block Diagram Explanation Functions Wait Count Settings Comparison MN102H51K/57K MN102L35G Interrupt Features Handler Preprocessing Handler Postprocessing Interrupt Control Registers Peripheral Function On/Off Switches Mode Settings 8-Bit Timer Functions Features 8-Bit Timer Control Registers 16-Bit Timer Functions Features Count Direction Two-Phase Encoder Timing Example Count Direction Two-Phase Encoder Timing Example 16-Bit Timer Control Registers Serial Interface Functions Features. Example Baud Rate Settings UART Mode Serial Interface Control Registers Functions Features. .143 Control Registers Functions Features .153 Power-Saving Control Bits OSDPOFF OSDREGE Settings Associated Tiles Cursor Tile Code Registers. Example Graphics VRAM Settings. Example Text VRAM Settings VRAM Allocation Internal Color Palette Registers. RGB, Output Control Settings Clock Source Settings Clock Division Settings Settings Controlling Shuttered Area Settings Controlling Shutter Movement. Settings Controlling Shuttering Effects EOMON Output Criteria Cursor Vertical Size Settings .205 Graphics Vertical Size Settings Text Vertical Size Settings Logic Level Conditions Data Formats Long Short Data Identification Leader Detection Conditions .221 Differences between SLOW NORMAL Modes
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List Tables
10-1 11-1 12-1 13-1 13-2 13-3 13-4 13-5 13-6 14-1
Remote Signal Receiver Registers HEAMA 5-/6-Bit Data Pulse Widths Pins Used CCD0 CCD1 Caption decoder register setting Clamping Reference Compare Levels Current Level Control Control Registers Clamping Circuit. Control Registers Sync Separator Circuit Control Registers Data Slicer. Control Registers Controller Sampling Circuit Closed-Caption Decoder Register Register Settings Internal Pullup Port Pins Correction Address Match Data Registers Terminology Operating Modes Devices Control Registers Clamping Circuit. Registers Settings SDA0/SCL0 SDA1/SCL1 Ports. Waveform Characteristics Settings Counter Pins. Register Map: x'007E00' x'007FFF' Register Map: x'00FC00' x'00FDFF'. Register Map: x'00FE00' x'00FFFF' Programmable Areas Each Programming Mode PROM Writer Hardware Descriptions Target Board-Serial Writer Connection Flash Address Space Serial Programming Mode Address Space Serial Programming Mode Microcontroller Clock Frequencies during Serial Programming Programming Times PROM Serial Writers.
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List Figures
List Figures
1-10 1-11 1-12 1-13 1-14 1-15 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 Conventional MN102H Series Code Assignments Three-Stage Pipeline MN102H Series Interrupt Servicing Internal Registers, Memory, Special Function Registers Address Space Interrupt Controller Configuration Interrupt Servicing Sequence. Functional Block Diagram. MN102H51K Configuration Single-Chip Mode. MN102H57K Configuration Single-Chip Mode. Power Supply Wiring. OSC1and OSC2 Connection Examples. Reset Connection Example OSDXI OSDXO Connection Examples Memory Space External Extension Mode Interrupt Controller Block Diagram Interrupt Vector Group Class Assignments. Interrupt Servicing Time Block Diagram External Interrupt. Timing External Interrupt Setup (Example) Block Diagram Watchdog Timer Interrupt Timing Watchdog Timer Interrupt Setup (Example) State Changes Clock Switch (NORMAL/SLOW Modes) Timer Configuration Examples Block Diagram 8-Bit Timers Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Event Timer Input Timing (8-Bit Timers) Clock Output Interval Timer Timing (8-Bit Timers) Block Diagram Event Counter Using Timer Event Counter Timing (Timer Configuration Example Interval Timer Using Timers Block Diagram Interval Timer Using Timers Interval Timer Timing (Timers Block Diagram 16-Bit Timers Timer Block Diagram Timer Block Diagram Single-Phase Output Timing (16-Bit Timers) Single-Phase Output Timing with Data Change (16-Bit Timers) Two-Phase Output Timing (16-Bit Timers)
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List Figures
4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 4-41 4-42 4-43 4-44 4-45 4-46 4-47 4-48 4-49 4-50 4-51 4-52 4-53 5-10 5-11
One-Shot Pulse Output Timing (16-Bit Timers) External Count Direction Control Timing (16-Bit Timers) Event Timer Input Timing (16-Bit Timers) Single-Phase Capture Input Timing (16-Bit Timers). Two-Phase Capture Input Timing (16-Bit Timers) Two-Phase Encoder Timing (16-Bit Timers) Two-Phase Encoder Timing (16-Bit Timers) Block Diagram Event Counter Using Timer Event Counter Timing (Timer Block Diagram Single-Phase Output Using Timer Single-Phase Output Timing (Timer Single-Phase Output Timing with Dynamic Duty Changes (Timer Block Diagram Two-Phase Output Using Timer Two-Phase Output Timing (Timer Two-Phase Output Timing with Dynamic Duty Changes (Timer Block Diagram Single-Phase Capture Input Using Timer Single-Phase Capture Input Timing (Timer Block Diagram Two-Phase Capture Input Using Timer Two-Phase Capture Input Timing (Timer Block Diagram Two-Phase Capture Input Using Timer Configuration Example Two-Phase Capture Input Using Timer Configuration Example Two-Phase Capture Input Using Timer Two-Phase Encoder Input Timing (Timer Block Diagram Two-Phase Capture Input Using Timer Configuration Example Two-Phase Capture Input Using Timer Configuration Example Two-Phase Capture Input Using Timer Two-Phase Encoder Input Timing (Timer Block Diagram One-Shot Pulse Output Using Timer One-Shot Pulse Output Timing (Timer Block Diagram External Count Direction Control Using Timer Configuration Example External Count Direction Control Using Timer External Count Direction Control Timing (Timer Block Diagram External Reset Control Using Timer External Reset Control Timing (Timer Serial Interface Configuration Example Synchronous Serial Mode Connections. UART Mode Connections Mode Connection Synchronous Serial Transmission Timing Synchronous Serial Reception Timing UART Transmission Timing UART Reception Timing Block Diagram UART Transmission Using Serial Interface UART Transmission Timing (Serial Interface Block Diagram Serial Interface Clock
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List Figures
5-12 5-13 5-14 6-10 6-11 6-12 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30
Serial Interface Clock Timing Master Transmitter Timing Mode (with ACK) Master Receiver Timing Mode (with ACK) Architecture Block Diagram Timing Single Channel/Single Conversion Timing Multiple Channel/Single Conversion Timing Single Channel/Continuous Conversion Timing Multiple Channel/Continuous Conversion Timing Single-Channel Conversion Timing Software-Controlled Single-Channel Conversion. Multiple-Channel Conversion Timing Hardware-Controlled Intermittent Three-Channel Conversion Cautions Analog-to-Digital Converter Block Diagram Cursor Tiles Standard Extended Modes Graphic Tiles Standard Extended Modes Graphics Display Example Text Display Example VRAM Organization (When GEXTE Graphics VRAM Organization Modes. Timing data Organization. Graphics Setup Example Single Line Graphics Four Color Modes (16W Tiles) Graphics Four Color Modes (16W Tiles) Graphics Organization 16-Color Mode (16W Tiles) Graphics Organization 8-Color Mode (16W Tiles) Graphics Organization 4-Color Mode (16W Tiles) Graphics Organization 2-Color Mode (16W Tiles) Graphics Organization 16-Color Mode (16W Tiles) Graphics Organization 8-Color Mode (16W Tiles) Graphics Organization 4-Color Mode (16W Tiles) Graphics Organization 2-Color Mode (16W Tiles) Signal Waveform Signal Output Switches Character Outlining Example Character Shadowing Example Shadowing Example. Italicizing Underlining Example. Graphic Tile Size Combinations Character Size Combinations HPmax Horizontal Display Position. Interrupt Timing
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List Figures
7-31 7-32 7-33 7-34 7-35 7-36 7-37 9-10 9-11 9-12 9-13 9-14 9-15 10-1 10-2 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15
Shuttered Area Setup Examples Shutter Movement Setup Examples. Text-Layer Shuttering Setup Examples Shutter Blanking Setup Examples Line Shuttering Setup Example Field Detection Circuit Block Diagram. Field Detection Timing Remote Signal Receiver Block Diagram Remote Signal Noise Filtering Reception 8-Bit Data with Leader. Reception 8-Bit Data with Leader. Conditions Detecting Data Formats Edge Detection Closed-Caption Decoder Block Diagram Recommended Configuration External Connection with Both CCD0 CCD1 Unused External Connection with Only CCD1 Unused. Clamping Circuit Sync Separator Circuit Block Diagram HSYNC Securement Interpolation VSYNC Masking. Data Slice Level Calculation .233 Sampling Clock Timing Determination. Caption Data Capture Timing SLSF SLHD Multiplexing Backporch Position Setting Sync Separator Level Multiplexing Output Waveform Block Diagram P00/RMIN/IRQ0 (Port P03/ADIN0 P07/ADIN4 (Port P10/ADIN5/IRQ1, P11/ADIN6/IRQ2, P12/ADIN7/IRQ3 (Port P13/ADIN8/WDOUT P14/ADIN9/STOP (Port P15/ADIN10/PWM0 P16/ADIN11/PWM1 (Port /PWM2 (Port P20/PWM3, P21/PWM4, P22/PWM5, P23/PWM6 (Port P24/TM4IC/SBT1 (Port P27/TM0IO (Port P35/DAROUT/R, P36/DAGOUT/G, P37/DABOUT/B (Port P40/DAYMOUT/YM (Port P25/TM4IOB/SBI1/SBD1 P26/TM4IOA/SBO1 (Port (Port P57/SBT0 (Port P02/SCL1 (Port P61/SCL0 (Port P01/SDA1 (Port P60/SDA0 (Port P31/CVBS0 P32/CVBS1 (Port
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List Figures
11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 11-24 11-25 11-26 12-1 12-2 12-3 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 14-1 14-2 14-3 B-10 B-11 B-12
P30/CLH P33/CLL (Port P34/VREF (Port P41/TM1IO, P42/TM5IOA, P43/TM5IOB/HI0 (Port P44/TM5IC/HI1 (Port P45/OSDXO P46/OSDXI (Port P47/HSYNC (Port P50/SYSCLK (Port P51/YS (Port P52/IRQ4/VI0 (Port P53/RST (Port P54/IRQ5/VSYNC (Port Area Schematic Diagram Correction Flow Correction Block Diagram. Example Application Connection Microcontrollers Bus. Interface Operation Controller Block Diagram Control Circuit Controller Waveforms Waveform Master Transmitter Transitioning Master Receiver Waveform Slave Receiver Transitioning Slave Transmitter. Counter Block Diagram Counter Operation Example Counter Input Signal Timing Memory Onboard Serial Programming Mode PROM Writer Hardware Setup Configuration Socket Adaptor Serial Writer Programming Configuration Serial Writer Hardware Setup Target Board-Serial Writer Connection Serial Writer Interface Block Diagram Timing Serial Writer Interface Load Program Start Flow. Flow Branch Reset Start Routine Flow Branch Interrupt Start Routine EEPROM Programming Flow
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About This Manual
Using This Manual
About This Manual
This manual intended assembly-language programming engineers. describes internal configuration hardware functions MN102H51K MN102H57K microcontrollers. Except when discussing differing specifications, this manual refers microcontrollers single device: MN102H51K/57K.
Using This Manual
chapters this manual deal with internal blocks MN102H51K/ 57K. Chapters provide overview MN102H51K/57K's general specifications, interrupts, power modes, timers, serial connections. Chapters describe on-screen display other specialized functions available with MN102H51K/57K. Chapter provides port specifications, chapter describes correction feature, chapter describes interface, chapter describes scan line counter. Appendix provides register map, Appendix describes flash EEPROM version.
Text Conventions
Where applicable, this manual provides special notes warnings. Helpful supplementary comments appear sidebar. addition, following symbols indicate information warnings: information These notes summarize points relating operation.
Warning Please read follow these instructions prevent damage reduced performance.
Register Conventions
This manual presents 16-bit registers following format:
REGISTER: Register Name
Bit: Reset: R/W:
x'000000'
Name Name Name Name Name Name Name Name Name Name Name Name Name
hexadecimal value (x'000000') indicates register address. register diagram holds numbers. most significant (MSB). second holds field names. dash indicates reserved bit. third shows reset values, fourth shows accessibility. read only, write only, readable/writable.)
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About This Manual
Related Documents
Related Documents
MN10200 Series Linear Addressing High-Speed Version User Manual (Describes core hardware.) MN10200 Series Linear Addressing High-Speed Version Instruction Manual (Describes instruction set.) MN10200 Series Linear Addressing High-Speed Version Compiler User Manual: Usage Guide (Describes installation, commands, options compiler.) MN10200 Series Linear Addressing High-Speed Version Compiler User Manual: Language Description (Describes syntax compiler.) MN10200 Series Linear Addressing High-Speed Version Compiler User Manual: Library Reference (Describes standard libraries compiler.) MN10200 Series Linear Addressing High-Speed Version Cross-Assembler User Manual (Describes assembler syntax notation.) MN10200 Series Linear Addressing Version Source Code Debugger User Manual (Describes source code debugger.) MN10200 Series Linear Addressing Version PanaX Series Installation Manual (Describes installation compiler, cross-assembler, source code debugger procedures using in-circuit emulator.)
Questions Comments
welcome your questions, comments, suggestions. Please contact semiconductor design center closest you. last page this manual list addresses telephone numbers. also find contact product information World Wide http://www.psdc.com/
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General Description
MN102H Series Overview
General Description
MN102H Series Overview
16-bit MN102H series high-speed linear addressing version MN10200 series. architecture this series designed C-language programming based detailed analysis requirements embedded applications. From miniaturization power savings, provides wide range needs user systems, surpassing previous architectures speed functionality. This series uses load/store architecture computing within registers rather than accumulator system computing within memory space, which Panasonic used most previous major series. basic instructions byte/one machine cycle, drastically shrinking code size improving compiler efficiency. circuit designed submicron technology, providing optimized hardware system power consumption. devices this series contain megabytes linear address space enable highly efficient program development. addition, optimized hardware structure allows system-wide power consumption even large systems.
MN102H Series Features
Designed embedded applications, MN102H series contains flexible optimized hardware architecture well simple efficient instruction set. provides both economy speed. This section provides features MN102H series CPU. High-speed signal processing internal multiplier multiplies 16-bit registers 32-bit product single cycle. addition, hardware contains saturation calculator ensure that signal processing missed increase signal processing speed. Linear addressing large systems MN102H series provides megabytes linear address space. With linear addressing, does detect borders between memory banks, which provides effective development environment. hardware architecture also optimized large-scale designs. memory divided into instruction data areas, operations share instructions.
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General Description
MN102H Series Features
Single-byte basic instruction length MN102H series replaced general registers with eight internal registers divided functionally into four address registers four data registers D3). program address register pair four less bits, basic instructions such register-to-register operations load/store operations occupy only byte.
Conventional code assignment general register instructions
Register specification (GRn)
Register specification (An/Dn)
Panasonic code assignments
Figure Conventional MN102H Series Code Assignments
High-speed pipeline throughput MN102H series executes instructions high-speed three-stage pipeline: fetch, decode, execute. With this architecture, MN102H series execute single-byte instructions only machine cycle MHz).
machine cycle Time Instruction Fetch Decode Address calculation Instruction Fetch Execute
Decode Address calculation Execute
Figure Three-Stage Pipeline
Simple instruction MN102H series uses streamlined instructions, designed specifically programming model embedded applications. shrink code size, instructions have variable length seven bytes, most frequently used basic instructions single-byte.
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General Description
MN102H Series Features
Fast interrupt response MN102H series devices stop executing instructions, even those with long execution cycles, service interrupts immediately. After interrupt occurs, program branches interrupt service routine within cycles less. architecture also includes programmable interrupt handler, which allows adjust interrupt servicing speed within software when necessary, improving real-time control performance.
Main Program Instruction Interrupt Service Routine Instruction Interrupt Request
Instruction Instruction
Figure MN102H Series Interrupt Servicing
Flexible interrupt control structure interrupt controller supports maximum interrupt vectors. (Vectors nonmaskable interrupts.) Groups four vectors assigned classes, each class seven priority levels. This gives software designer great flexibility fine control. core also backwards compatible with software from previous Panasonic peripheral modules. High-speed, high-functionality external interface MN102H series provides DMA, handshaking, arbitration, other functions that ensure fast, efficient interface with other devices. Optimal C-Language development environment MN102H series combines hardware optimized language programming with highly efficient compiler, resulting assembly codes same size that produced directly assembly language. This gives designers advantage short development time language environment without trade-off code size expansion. PanaXSeries development tools support MN102H series devices.
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General Description
MN102H Series Description
Outstanding power savings MN102H series contains separate buses instructions, data, peripheral functions, which distributes reduces load capacitance, dramatically reducing overall power consumption. series also supports three HALT STOP modes even greater power savings.
MN102H series flagship product Panasonic's high-performance architecture. Panasonic will expand series strives improve core's performance speed, develops devices incorporating ASSPs, ASICs, internal EPROM, other products meet needs wide array embedded designs.
MN102H Series Description
This section describes basic architecture functions MN102H series devices.
Processor status word (PSW)
contains operation status flags interrupt mask levels flags. Note that MN102H series contains flags both 24-bit operation results.
Bit: Reset: Flags Bits Flags Low-Order Bits
Saturation
This controls whether calculates saturation limit operation. When executes saturate operation, when executes normal operation. PXST instruction reverse meaning this next (and only next) instruction.
S[1:0]: Software control
These bits control field software. reserved
Interrupt enable
set, this flag enables maskable interrupts; reset, disables them.
IM[2:0]: Interrupt mask level
This field indicates mask level (from interrupts that will accept from seven interrupt input pins. will accept interrupt from higher level than that indicated here.
Extension overflow
operation causes sign change 24-bit signed number, this flag set; otherwise reset.
Extension carry flag
operation resulted carry into (from addition) borrow (from subtraction comparison) most significant bit, this flag set; otherwise reset.
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General Description
MN102H Series Description
Extension negative flag
most significant result operation value this flag set; that this flag reset.
Extension zero flag
bits result operation have value this flag set; otherwise reset.
Overflow flag
operation causes sign change 16-bit signed number, this flag set; otherwise reset.
Carry flag
operation resulted carry into (from addition) borrow (from subtraction comparison) this flag set; otherwise reset.
Negative flag
result operation value this flag set; that this flag reset.
Zero flag
least significant bits result operation have value this flag set; otherwise reset.
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General Description
MN102H Series Description
Internal registers, memory, special function registers
Program Counter Address Registers Data Registers Multiplication/Division Register Processor Status Word Memory, SFRs, Ports CPUM, EFCR, IAGR NMICR, xxICR
program counter specifies 24-bit address program instruction being executed.
four address registers specify location data memory. assigned stack pointer.
four data registers handle arithmetic logic operations. When byte-length (8-bit) word-length (16-bit) data transferred memory another register, instruction adds zero sign extension.
dedicated multiplication/division register stores highorder bits 32-bit product multiplication operations. division operations, before execution stores high-order bits 32-bit dividend, after execution stores 16-bit remainder quotient.
Memory (ROM RAM), special function registers controlling peripheral functions, ports assigned same address space.
Internal control registers1 Interrupt control registers1 Serial interface registers1 converter registers1 Timer/counter registers1 Memory control registers1 port registers1
SCCTRn, TRXBUFn, SCSTRn ANCTR, ANnBUF TMn, BCn, BRn, MEMMD PnOUT, PnIN, PnDIR Note:
This allocation representative example. Actual memory, peripheral, SFR, port configuration depends product. Figure Internal Registers, Memory, Special Function Registers
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MN102H Series Description
Address space
memory MN102H series configured linear address space. instruction data areas separated, basic segments internal ROM, internal RAM, special function registers. Figure shows address space MN102H51K/57K.The internal contains instructions font data on-screen display (OSD), location. internal contains data VRAM OSD, location.
x'007E00' x'007FFF' x'008000'
Special Function Registers
Internal Data
Text VRAM Graphics VRAM
x'009FFF'
x'00FC00'
Special Function Registers
x'00FFFF'
Program start address x'080000' Interrupt handler start address x'080000'
x'080000'
Internal
Program
Text fonts Graphic tiles
x'0BFFFF'
Figure Address Space Note: writing, MOVB instruction access Special Function Registers (x'00FC00' x'00FFFF'), access word. reading, access byte possible.
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General Description
MN102H Series Description
Interrupt controller
interrupt controller external core controls nonmaskable maskable interrupts except reset. There maximum sixteen interrupt classes (class 15). Each class have four interrupt factors seven priority levels.
Core
Maskable Interrupt Receive
Interrupt Enable
Nonmaskable Interrupt Receive
Reset Receive
Reset
Interrupt Controller
Nonmaskable interrupts Groups Nonmaskable Interrupt Controllers
Nonmaskable Interrupt Control Registers (NMICR) (WDICR) (UNICR) (EIICR)
Interrupt Masking
External input Watchdog timer Undefined instruction Interrupt occurred, vector exists
Group Maskable Interrupt Controllers
Maskable Interrupt Control Registers ICR)
Maskable interrupts Max. vectors
Group Maskable Interrupt Controllers
Maskable Interrupt Control Registers ICR)
External interrupts Peripheral interupts
Note: Interrupt control hardware configuration varies between products. Figure Interrupt Controller Configuration
checks processor status word determine whether accept interrupt request. accepts request, automatic hardware servicing begins contents program counter other necessary registers pushed stack. program then looks branches entry address interrupt service routine interrupt that occurred.
Interrupt preprocessing
Push registers, branch entry address, etc. Main program x'080008'
Hardware processing
Push
Interrupt service routine Header resets interrupt vector JMP, etc.
Interrupt
Max. machine cycles machine cycles
Figure Interrupt Servicing Sequence
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General Description
General Specifications
General Specifications
Specification
Internal multiplier (16-bit 16-bit 32-bit) saturate calculator Load/store architecture Eight registers: Four 24-bit data registers Four 24-bit address registers Other: 24-bit program counter 16-bit processor status word 16-bit multiply/divide register
Table General Specifications Parameter
Structure
Instruction
instructions addressing modes 1-byte basic instruction length Code assignment: byte (basic) bytes (extension)
Performance
12-MHz internal operating frequency (with 4-MHz external oscillator) Instruction execution clock cycles: Minimum clock cycle (83.3 register-to-register operations Minimum clock cycle (83.3 load/store operations Minimum clock cycles (167 branch operations
Pipeline Address space
3-stage: fetch, decode, execute Linear address space Shared instruction/data space
Interrupts
external internal priority level settings
Low-power modes
STOP HALT SLOW
Oscillation frequency
with internal PLL)
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General Description
General Specifications
Table General Specifications Parameter
Timer/counters Four 8-bit timers: Cascading function (forming 32-bit timers) Timer output Selectable clock source (internal external) Serial interface clock generation Start timing generation analog-to-digital converter 16-bit timers: Compare/capture registers Selectable clock source (internal external) one-shot pulse output Two-phase encoder input formats) 16-bit watchdog timer correction SYSCLK output Serial interfaces bytes (8-bit SYSCLK SYSCLK/214 (732.42 UART/synchronous serial/I2C (master only) interfaces interface (multimaster; 2-channel with internal circuit) Analog-to-digital converter remote signal receiver Closed-caption decoder On-screen display 8-bit with channels Automatic scanning Automatic HEAMA 5-/6-bit detection 1-bit interrupt 8-bit with channels (3.3-volt tolerance) channels Internal sync separator Three-layer format Text layer: pixels closed caption mode), blinking, outlining, shadowing (foreground background), shutter effect, italics mode), underlining mode) Graphics layer: pixels Cursor layer: pixels cursor, displaying graphic tile) Color depth: 16-color palette 4096 colors clock Internal frequencies: External clock: 16-32 blocking oscillator: 16-32 ports Package (MN102H51K HF51K) (MN102H57K HF57K) 64-pin SDIL (MN102H51K HF51K) 84-pin-QFP (MN102H57K HF57K)
Specification
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General Description
Block Diagram
Address registers
Block Diagram
Data registers
Multiplier Program Counter Incrementer
Multiplication/Division Register
Clock generator
Clock source
Instruction execution controller Instruction decoder Quick decoder
Instruction queue Program address Operand address
Interrupt controller Interrupt
controller
Peripherals extension
External interface Internal Internal External extension Internal peripheral functions
Figure Functional Block Diagram
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General Description
Block Diagram
Table Block Diagram Explanation Block
Clock generator Program counter
Description
oscillation circuit connected external crystal supplies clock blocks within CPU. program counter generates addresses queued instructions. Normally increments based sequencer indications, branch instructions branch head address, interrupt servicing, result operation. This block contains four bytes prefetched instructions. instruction decoder decodes contents instruction queue, generates, proper sequence, control signals necessary executing instruction, controls every block chip execute instruction. This block decodes instructions that bytes larger much faster rate than previously possible. This block controls operation every block within using results from instruction decoder interrupt requests. Arithmetic logic unit. This block calculates operand addresses arithmetic operations, logic operations, shift operations, relative indirect register addressing, indexed addressing, indirect register addressing. This block multiplies bits bits bits. These memory blocks contain program, data, stack areas. address registers store addresses memory accessed data transfers. relative indirect, indexed, indirect addressing modes, they store base address. data registers store data transferred memory results operations. indexed indirect addressing modes, they store offset address. multiplication/division register stores data multiplication division operations.
Instruction queue Instruction decoder
Quick decoder Instruction execution controller
Multiplier Internal Address registers (An) Operation registers (Dn, MDR)
processor status word contains flags that indicate status interrupt controller provide information about operation results. This block detects interrupt requests from peripheral function blocks requests service interrupt. This block controls connection between CPU's internal external buses. also contains arbitration function. MN102H series devices contain wide range internal peripheral devices, such timers, serial interfaces, ADCs, DACs.
Interrupt controller controller Internal peripheral functions
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General Description
Descriptions
1.6.1
Descriptions
MN102H51K Description
P00, RMIN, IRQ0 P01, SDA1 P02, SCL1 P03, ADIN0 P04, ADIN1 P05, ADIN2 P06, ADIN3 P07, ADIN4 P10, ADIN5, IRQ1 P11, ADIN6, IRQ2 P12, ADIN7, IRQ3 P13, ADIN8, WDOUT P14, ADIN9, STOP P15, ADIN10, PWM0 P16, ADIN11, PWM1 P17, PWM2 P20, PWM3 P21, PWM4 P22, PWM5 P23, PWM6 P24, TM4IC, SBT1 P25, TM4IOB, SBI1, SBD1 P26, TM4IOA, SBO1 P27, TM0IO (VPP) P30, VREFHS P31, CVBS0 P32, CVBS1 VREFLS P33,
64-Pin SDIP View
OSC2 OSC1 P61, SCL0 P60, SDA0 P57, SBT0 P56, SBI0, SBD0 P55, SBO0 P54, IRQ5, VSYNC P53, P52, IRQ4, TEST P51, P50, SYSCLK P47, HSYNC P46, OSDXI P45, OSDXO P44, TM5IC, P43, TM5IOB, P42, TM5IOA P41, TM1IO VCOI P40, DAYMOUT, P37, DABOUT, P36, DAGOUT, P35, DAROUT, VREF, IREF COMP AVDD
Notes:
Pins marked with asterisk N-channel, open-drain pins. MN102H51K MN102HF51K. Figure MN102H51K Configuration Single-Chip Mode
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Descriptions
1.6.2
P56, SBI0, SBD0
MN102H57K Description
P00, RMIN, IRQ0
P60, SDA0
P01, SDA1
P61, SCL0
P02, SCL1
P03, ADIN0
P04, ADIN1
P05, ADIN2
P06, ADIN3
P07, ADIN4
P57, SBT0
OSC1
OSC2
P55, SBO0 P54, IRQ5, VSYNC P53, P52, IRQ4, TEST P51, P50, SYSCLK P47, HSYNC P46, OSDXI P45, OSDXO P44, TM5IC, P43, TM5IOB, P42, TM5IOA P41, TM1IO VCOI
P10, ADIN5, IRQ1 P11, ADIN6, IRQ2 P12, ADIN7, IRQ3 P13, ADIN8, WDOUT P14, ADIN9, STOP P15, ADIN10, PWM0 P16, ADIN11, PWM1 P17, PWM2 P20, PWM3 P21, PWM4 P22, PWM5 P23, PWM6 P24, TM4IC, SBT1 P25, TM4IOB, SBI1, SBD1 P26, TM4IOA, SBO1 P27, TM0IO
84-Pin View
P40, DAYMOUT,
P37, DABOUT,
P32, CVBS1
P36, DAGOUT,
P31, CVBS0
VREF,
P33,
VREFLS
VREFHS
P35, DAROUT,
P30,
IREF
AVDD
(VPP)
COMP
Notes:
Pins marked with asterisk N-channel, open-drain pins. MN102H57K MN102HF57K. Figure 1-10 MN102H57K Configuration Single-Chip Mode
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General Description
Descriptions
Table Functions Block Name
Power AVDD VDD/VPP SYSCLK OSC1 Clocks OSC2 OSDXI OSDXO Reset Interrupts (external) IRQ0-IRQ5 HSYNC VSYNC TMnIOA (n=4,5) 16-bit Timers TMnIC (n=4,5) 8-bit TMnIO (n=0,1) SBI0/SBI1 SBD0/SBD1 Serial interfaces SBO0/SBO1 SBT0/SBT1 interfaces remote signal receiver (8-bit, 7-channel) SDA0/SDA1 SCL0/SCL1 RMIN PWM0-PWM6 Serial data output Serial clock signal data clock Remote signal input Pulse width modulator output Timer/counter clear signal Timer clock input/timer output Serial data input Serial data input TMnIOB (n=4,5)
Count
Voltage supply Ground reference
Description
Analog voltage supply Voltage supply: mask version EEPROM version System clock output Oscillator input connection (with internal PLL) Oscillator output connection (with internal PLL) oscillator input connection (alt. function: P46) oscillator output connection (alt. function: P45) Reset (alt. function: P53) External interrupt request microcontroller (alt. functions: P00, P10, P11, P12, P52, P54) Horizontal sync signal input Vertical sync signal input Video signal Input capture/output compare Input capture/output compare
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Descriptions
Table Functions (Continued) Block Name
P00-P07 P10-P17 ports MN102H51K/HF51K: total pins MN102H57K/HF57K: total pins P20-P27 P30-P37 P40-P47 P50-P57 P60-P61 ports only MN102H57K/HF57K P70-P77 P80-P87 CVBS0/CBVS1 Closed-caption decoders VREFHS VREFLS converter (12-channel) ADIN0-ADIN11 DAROUT
Count
Description
General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port Composite video signal input Clamp level high input Clamp level input reference voltage input reference voltage input Analog signal input output (red) output (green) output (blue) output (YM) Resistance connection bias current setting reference voltage connection phase compensator connection Internal input (external input) Internal phase compare output (external output) STOP mode status signal Watchdog timer overflow signal Test (Connect ground.)
DAGOUT DABOUT converter (4-bit, 4-channel)
DAYMOUT IREF VREF COMP VCOI
STOP Mode WDOUT Test TEST
Notes:
When DAROUT, DAGOUT, DABOUT, DAYMOUT used digital output, their names respectively.
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General Description
Descriptions
Considerations power supply, clock, reset pins
AVDD MN102H51K MN102H57K AVSS
Power Supply
Note: circuit uses same power supply digital analog supplies, connect pins location closest power supply. Figure 1-11 Power Supply Wiring
OSC1
OSC2
OSC1
OSC2
Oscillation Circuit
Note: capacitance values vary depending oscillator. Figure 1-12 OSC1 OSC2 Connection Examples
Figure 1-13 Reset Connection Example
OSDXI
OSDXO
OSDXI
OSDXO
16MHz 32MHz
16MHz 32MHz Oscillation Circuit
Note: capacitance values vary depending oscillator. Figure 1-14 OSDXI OSDXO Connection Examples
Connection circuit
MN102H51K/57K contains internal circuit. this circuit, must connect external (lag-lead) filter.
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General Description
Interface
1.7.1
Interface
Description
interface operates external extension mode. Figure 1-15 provides memory space this mode.
External Expansion Mode
x'000000'
External devices
x'008000' x'00A000' (*4) x'00FC00'
Internal (8192 bytes (*3))
Peripheral registers
x'010000'
External devices
Reset start x'080000'
External memory space (CS0 signal): remote signal receive CCD0 CCD1 counter External memory space (CS1 signal) External memory space (CS2 signal) External memory space (CS3 signal)
Internal masked (256 Kbytes (*1))
x'0C0000' (*2) x'200000' x'400000'
External devices
x'800000' x'C00000'
Cannot accessed.
x'FFFFFF'
Expandable
MN102H51K Kbytes x'0C0000' 8192 bytes x'00A000'
Figure 1-15 Memory Space External Extension Mode
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Interface
1.7.2
Interface Control Registers
external memory wait register (EXWMD) memory mode register (MEMMD1) control interface.
EXWMD: External Memory Wait Register
Bit:
x'00FF80'
EW33 EW32 EW31 EW30 EW23 EW22 EW21 EW20 EW13 EW12 EW11 EW10 EW03 EW02 EW01 EW00 Reset: R/W:
EW[33:30], EW[23:20], EW[13:10], EW[03:00]
These fields contain wait settings external memory spaces respectively. wait corresponds instruction cycle. When external oscillator MHz, wait OSD, VBI0, VBI1, I2C, remote signal receiver, counter blocks apply external memory space
Table Wait Count Settings EW[n3:n0] Setting Wait Count
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Cycles
MEMMD1: Memory Mode Register
Bit: EB31 Reset: R/W: EB32 EB21 EB20 EB11 EB10 EB01 EB00
x'00FF82'
BRS1 BRS0 BRC3 BRC2 BRC1 BRC0 IOW1 IOW0
Write bits
IOW[1:0]: Wait setting internal space
wait Reserved waits waits
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Interrupts
Description
Interrupts
Description
most important factor real-time control MCU's speed servicing interrupts. MN102H51K/57K extremely fast interrupt response time ability abort instructions, such multiply divide, that require multiple clock cycles. MN102H51K/57K re-executes aborted instruction after returning from interrupt service routine. This section describes interrupt system MN102H51K/57K. MN102H51K/57K contains interrupt group controllers. Each controls single interrupt group. Because each group contains only interrupt vector, MN102H51K/57K handle interrupts much quicker than previously possible. Each interrupt group belongs twelve classes, which defines interrupt priority level. With exception reset interrupts, interrupts from timers, other peripheral circuits, external pins must registered interrupt group controller. Once they registered, interrupt requests sent accordance with interrupt mask level interrupt group controller. Groups dedicated system interrupts. Table compares interrupt parameters MN102H51K/57K those MN102L35G, comparable previous generation 16-bit series.
Table Comparison MN102H51K/57K MN102L35G Interrupt Features Parameter MN102L35G MN102H51K/57K
Interrupt groups (IAGR group numbers Interrupt response time Interrupt level settings Software compatibility vectors group (Separated interrupt service routine) Good vectors level vector group (Group number generated each interrupt) Excellent vectors level Easily modified
MN102H51K/57K external interrupt pins. interrupt condition (positive edge, negative edge, either edge, active low) EXTMD register.
Internal interrupts
Interrupt
EXTMD IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Edge/level Edge/level Edge/level Edge/level Edge/level Edge/level
Interrupt arbitration
Figure Interrupt Controller Block Diagram Panasonic Semiconductor Development Company Panasonic MN102H51K/57K User Manual
Interrupts
Description
Group NMIs Group Group Group Group Group Group Group Group
Interrupt Vector Watchdog timer Undefined instruction Error interrupt External interrupt External interrupt
Priority Level
Register Address 00FC42 (R/W) 00FC44 (R/W) 00FC46 (R/W) 00FC48 (R/W) 00FC4A (R/W)
MN102H Core
Class
Levels
Class
Group External interrupt Group External interrupt Group Group Group External interrupt Group External interrupt Group Group Group Group Group Group Group Group Group Group Group Group Group Group Group Group Group Group Timer compare/capture Timer compare/capture Timer underflow interrupt interrupt Timer compare/capture Timer compare/capture Timer underflow interrupt interrupt Timer underflow interrupt Timer underflow interrupt Timer underflow interrupt Remote signal receive int. Address match interrupt Address match interrupt Address match interrupt Address match interrupt
Class
00FC50 (R/W) 00FC52 (R/W)
Class
00FC58 (R/W) 00FC5A (R/W)
Class
00FC60 (R/W) 00FC62 (R/W) 00FC64 (R/W) 00FC66 (R/W) 00FC68 (R/W) 00FC6A (R/W) 00FC6C (R/W) 00FC6E (R/W) 00FC70 (R/W) 00FC72 (R/W) 00FC74 (R/W) 00FC76 (R/W) 00FC78 (R/W) 00FC7A (R/W) 00FC7C (R/W) 00FC7E (R/W) 00FC80 (R/W) 00FC82 (R/W) 00FC84 (R/W) 00FC88 (R/W) 00FC8A (R/W) 00FC8C (R/W) 00FC90 (R/W) 00FC92 (R/W)
Class
Class
Class
Group conversion int. Group Serial transmission Group Serial reception Group Group VBIVSYNC interrupt Group VBIVSYNC interrupt Group Timer underflow interrupt Group Group interrupt (graphics) Group interrupt (text) Group Group Group Serial transmission Group Serial reception Group interrupt Group
Class
Class
Class
Class
00FC98 (R/W) 00FC9A (R/W) 00FC9C (R/W)
Figure Interrupt Vector Group Class Assignments
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Interrupts
Description
Program
Interrupt
Max. cycles
Address 80008
Handler (preprocessing)
cycles
interrupt request Interrupt service deleted header routine (Included cycle count shown left.)
Handler (postprocessing)
cycles
Registers popped
Figure Interrupt Servicing Time Table Handler Preprocessing Sequence
Push registers movx Interrupt Generate header address interrupt service routine Branch Total
Assembler
-8,A3 A0,(A3) D0,(4,A3) (FC0E),D0 BASE,A0 (D0,A0),A0 (A0)
Bytes
Cycles
Table Handler Postprocessing Sequence
registers movx Total
Assembler
(A3),A0 (4,A3),D0 8,A3
Bytes
Cycles
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Interrupt Setup Examples
2.2.1
Interrupt Setup Examples
Setting External Interrup
this example, interrupt occurs falling-edge signal from IRQ0 (P00) external interrupt pin, interrupt priority level reset, external edge setting EXTMD register (b'00' activelow interrupt), IQ0IR IQ0ICL register
IRQ0 CORE Interrupts Timers ROM, Controller Serial I/Fs Figure Block Diagram External Interrupt
Enabling external interrupt
interrupt conditions IRQ0 (P00) pin. this example, IQ0TG[1:0] bits EXTMD b'10' (negative-edge-triggered interrupt).
x'00FCF8'
IQ5TG IQ5TG IQ4TG IQ4TG IQ3TG IQ3TG IQ2TG IQ2TG IQ1TG IQ1TG IQ0TG IQ0TG
EXTMD (example)
Bit: Setting:
Cancel existing interrupt requests enable IRQ0 interrupts. this, IQ0IR IQ0ICL IQ0LV[2:0] bits IQ0ICH b'101' (priority level IQ0IE
x'00FC48'
IQ0IR IQ0ID
IQ0ICL (example)
Bit: Setting:
IQ0ICH (example)
Bit: Setting: IQ0IE
x'00FC49'
IQ0LV2 IQ0LV1 IQ0LV0
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Interrupt Setup Examples
Enable interrupts writing interrupt enable flag (IE) setting interrupt masking level (IM[2:0]) (b'111'). falling edge occurs IRQ0 (P00), interrupt will occur. accepts interrupt, program branches address x'080008'.
main program normally generates branches interrupt start address.
Servicing interrupt
During interrupt preprocessing, read accepted interrupt group number register (IAGR) determine interrupt group (group this case). Branch interrupt service routine. beginning interrupt service routine, clear IQ0IR IQ0ICL
During interrupt service routine, prevent from accepting other maskable interrupts setting IM[2:0] bits accept same interrupt during interrupt service routine, clear flag beginning
After service routine ends, return main program with instruction.
(IRQ0) EXTMD IQ0IE IQ0IR Interrupt servicing Registers [R/W] Sequence EXTMD(W) IQ0ICH(B) IQ0ICL(B) (2)(3) IQ0ICL(B) (4)(5)(6)(7) IQ0ICL(B) (4)(5)(6)(7) level Falling edge
Figure Timing External Interrupt Setup (Example)
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Interrupt Setup Examples
2.2.2
Setting Watchdog Timer Interrupt
watchdog timer interrupt provided detecting handling racing. Normal operation guaranteed program returns after watchdog interrupt. actions requiring returns, timer interrupt.
this example, watchdog timer reset occurs. watchdog timer starts running after reset, when NWDEN flag mode register (CPUM) enabled (set When watchdog timer overflows, nonmaskable interrupt occurs. This means that watchdog timer must cleared main program.
CORE Interrupts Timers
ROM, Controller Serial I/Fs
Figure Block Diagram Watchdog Timer Interrupt
Enabling watchdog timer interrupts
WDM[1:0] watchdog interrupt occurs when watchdog timer counts cycles (5.4613 4-MHz fOSC/12MHz fSYSCLK). settings have following meanings: (5.46 (1.33 (0.34 (1.37
Enable interrupts writing interrupt enable flag (IE) setting interrupt masking level (IM[2:0]) (b'111'). Activate watchdog timer clearing NWDEN CPUM register. time limit racing detection function WDM[1:0] field.
x'00FC00'
CPUM (example)
Bit: Setting:
STOP HALT OSC1 OSC0
main program normally clears watchdog timer prior watchdog interrupt.
Clearing watchdog timer
NWDEN CPUM then immediately reset watchdog timer clears when NWDEN
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Interrupts
Interrupt Setup Examples
main program normally generates branches interrupt start address.
accepts interrupt, program branches address x'080008'. oscillator delay timer shares counter watchdog timer. oscillator delay timer activated when circuit exits STOP mode, program must clear WDID flag prior entering STOP mode. must also reclear WDID after returning NORMAL mode. further details, section 2-6, "Standby Function," MN10200 Series Linear Addressing Version User Manual.
Overflow count NWDEN (CPUM) WDID (WDICR) Interrupt servicing Registers [R/W] Sequence CPUM CPUM Clear CPUM
Figure Timing Watchdog Timer Interrupt Setup (Example)
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Interrupts
Interrupt Control Registers
Interrupt Control Registers
control register assigned each interrupt vector group. Except class registers (WDICR, PIICR, EIICR), control registers allow enable priority level interrupt groups. Below general format registers class classes
Class (X):
(watchdog overflow interrupts) (undefined instruction interrupts) (interrupt error interrupts)
XICR (System Interrupt)
Bit:
Interrupt detect flag
Interrupt undetected Interrupt detected
Classes 1-11 (X):
(external interrupts) (timer interrupts) (serial interrupts) (I2C interrupts) (OSD interrupts) (A/D conversion interrupts) (remote signal receive interrupts) (VBI interrupts) (address match interrupts)
XnICH (System Interrupt)
Bit:
LV[2:0]: Interrupt priority level
Sets priority from (000 etc.). When interrupts serviced. Note that some registers contain theLV field. this case, these bits always read
Interrupt enable flag
Disable Enable
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XnICL (System Interrupt)
Bit:
Interrupt request flag
interrupt requested Interrupt requested
Interrupt detect flag
Interrupt undetected Interrupt detected following example program setting interrupt group's priority level field) enabling interrupt group (IE) interrupt control register (XnICH). Note that interrupts must disabled during this routine.
Example Setting Interrupt Priority Level
0xf7ff,psw d0,(XnICH) (XnICH),d0 0x0800,psw
;Clear PSW. Inserted ensure that clears completely, XnICH accessible. ;Write LV/IE ;Synchronize with store buffer. ;Set PSW.
program does need clear disable interrupts during interrupt servicing, since interrupt service routine already cleared replace instructions example above with instruction except those that modify bits XnICH register. Inserting these instructions would cause interrupt error occur. example includes instructions ensure that minimum number cycles required write have passed. However, also insert more than NOPs. Table provides list interrupt control registers, description fields each register follows.
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Table Interrupt Control Registers
Register
IAGR WDICR PIICR EIICR EXTMD IQ0ICL IQ0ICH IQ1ICL IQ1ICH IQ2ICL IQ2ICH IQ3ICL IQ3ICH IQ4ICL IQ4ICH IQ5ICL IQ5ICH TM4CBICL TM4CBICH TM4CAICL TM4CAICH TM4UDICL TM4UDICH VBIICL VBIICH TM5CBICL TM5CBICH TM5CAICL TM5CAICH TM5UDICL TM5UDICH VBIWICL VBIWICH TM2UDICL TM2UDICH TM1UDICL TM1UDICH TM0UDICL TM0UDICH RMCICL RMCICH
Address
x'00FC0E' x'00FC42' x'00FC44' x'00FC46' x'00FCF8' x'00FC48' x'00FC49' x'00FC4A' x'00FC4B' x'00FC50' x'00FC51' x'00FC52' x'00FC53' x'00FC58' x'00FC59' x'00FC5A' x'00FC5B' x'00FC60' x'00FC61' x'00FC62' x'00FC63' x'00FC64' x'00FC65' x'00FC66' x'00FC67' x'00FC68' x'00FC69' x'00FC6A' x'00FC6B' x'00FC6C' x'00FC6D' x'00FC6E' x'00FC6F' x'00FC70' x'00FC71' x'00FC72' x'00FC73' x'00FC74' x'00FC75' x'00FC76' x'00FC77'
Description
Accepted interrupt group number register Watchdog interrupt control register Undefined instruction interrupt control register Interrupt error interrupt control register External interrupt mode register External interrupt interrupt control register (low) External interrupt interrupt control register (high) External interrupt interrupt control register (low) External interrupt interrupt control register (high) External interrupt interrupt control register (low) External interrupt interrupt control register (high) External interrupt interrupt control register (low) External interrupt interrupt control register (high) External interrupt interrupt control register (low) External interrupt interrupt control register (high) External interrupt interrupt control register (low) External interrupt interrupt control register (high) Timer compare/capture interrupt control register (low) Timer compare/capture interrupt control register (high) Timer compare/capture interrupt control register (low) Timer compare/capture interrupt control register (high) Timer underflow interrupt control register (low) Timer underflow interrupt control register (high) interrupt control register (low) interrupt control register (high) Timer compare/capture interrupt control register (low) Timer compare/capture interrupt control register (high) Timer compare/capture interrupt control register (low) Timer compare/capture interrupt control register (high) Timer underflow interrupt control register (low) Timer underflow interrupt control register (high) interrupt control register (low) interrupt control register (high) Timer underflow interrupt control register (low) Timer underflow interrupt control register (high) Timer underflow interrupt control register (low) Timer underflow interrupt control register (high) Timer underflow interrupt control register (low) Timer underflow interrupt control register (high) Remote signal receive interrupt control register (low) Remote signal receive interrupt control register (high)
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Table Interrupt Control Registers
Register
ADM3ICL ADM3ICH ADM2ICL ADM2ICH ADM1ICL ADM1ICH ADM0ICL ADM0ICH ANICL ANICH SCT0ICL SCT0ICH SCR0ICL SCR0ICH VBIVICL VBIVICH VBIVWICL VBIVWICH TM3UDICL TM3UDICH OSDGICL OSDGICH OSDCICL OSDCICH SCT1ICL SCT1ICH SCR1ICL SCR1ICH I2CICL I2CICH
Address
x'00FC78' x'00FC79' x'00FC7A' x'00FC7B' x'00FC7C' x'00FC7D' x'00FC7E' x'00FC7F' x'00FC80' x'00FC81' x'00FC82' x'00FC83' x'00FC84' x'00FC85' x'00FC88' x'00FC89' x'00FC8A' x'00FC8B' x'00FC8C' x'00FC8D' x'00FC90' x'00FC91' x'00FC92' x'00FC93' x'00FC98' x'00FC99' x'00FC9A' x'00FC9B' x'00FC9C' x'00FC9D'
Address Address Address Address Address Address Address Address match match match match match match match match
Description
interrupt control register interrupt control register interrupt control register interrupt control register interrupt control register interrupt control register interrupt control register interrupt control register (low) (high) (low) (high) (low) (high) (low) (high)
conversion interrupt control register (low) conversion interrupt control register (high) Serial transmission interrupt control register (low) Serial transmission interrupt control register (high) Serial reception interrupt control register (low) Serial reception interrupt control register (high) VBIVSYNC interrupt control register (low) VBIVSYNC interrupt control register (high) VBIVSYNC interrupt control register (low) VBIVSYNC interrupt control register (high) Timer underflow interrupt control register (low) Timer underflow interrupt control register (high) (graphics) interrupt control register (low) (graphics) interrupt control register (high) (text) interrupt control register (low) (text) interrupt control register (high) Serial transmission interrupt control register (low) Serial transmission interrupt control register (high) Serial reception interrupt control register (low) Serial reception interrupt control register (high) interrupt control register (low) interrupt control register (high)
Note: interrupt error interrupt control register does exist hardware, matching interrupt vector found interrupt that occurs, writes IAGR indicate that detected abnormality.
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Interrupts
Interrupt Control Registers
IAGR: Accepted Interrupt Group Number Register
Bit: Reset: R/W:
x'00FC0E'
IAGR returns group number accepted interrupt, indicated 6-bit field. When interrupt handler calculates header address interrupt service routine, merely needs contents IAGR header address table which registered vector addresses servicing interrupts. IAGR 16-bit access register.
GN[5:0]: Group Number
Contains group number multiplied four.
EXTMD: External Interrupt Mode Register
Bit: Reset: R/W:
x'00FCF8'
IQ5TG IQ5TG IQ4TG IQ4TG IQ3TG IQ3TG IQ2TG IQ2TG IQ1TG IQ1TG IQ0TG IQ0TG
EXTMD sets trigger conditions external interrupts. IQnTG[1:0] sets interrupt mode associated pin. Each have polarity edge setting. EXTMD 16-bit access register. Active-low interrupt Either-edge-triggered interrupt (positive negative) Negative-edge-triggered interrupt Positive-edge-triggered interrupt
WDICR: Watchdog Interrupt Control Register
Bit: WDID
x'00FC42'
watchdog timer interrupt provided detecting handling racing. Normal operation guaranteed program returns after watchdog interrupt. actions requiring returns, timer interrupt.
Reset: R/W:
WDICR 8-bit access register.
WDID: Watchdog interrupt detect flag
Interrupt undetected Interrupt detected
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Interrupts
Interrupt Control Registers
PIICR: Undefined Instruction Interrupt Control Register
Bit: Reset: R/W: PIID
x'00FC44'
PIICR 8-bit access register.
PIID: Undefined instruction interrupt detect flag
Interrupt undetected Interrupt detected
EIICR: Interrupt error Interrupt Control Register
Bit: Reset: R/W:
x'00FC46'
EIICR does exist hardware, finds matching interrupt vector interrupt that occurs, writes IAGR indicate that detected abnormality. EIICR 8-bit access register.
IQ0ICL: External Interrupt Interrupt Control Register (Low)
Bit: Reset: R/W: IQ0IR IQ0ID
x'00FC48'
IQ0ICL requests verifies interrupt requests external interrupt 8-bit access register. MOVB instruction access
IQ0IR: External interrupt interrupt request flag
interrupt requested Interrupt requested
IQ0ID: External interrupt interrupt detect flag
Interrupt undetected Interrupt detected
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IQ0ICH: External Interrupt Interrupt Control Register (High)
Bit: Reset: R/W: IQ0IE
x'00FC49'
IQ0LV2 IQ0LV1 IQ0LV0
IQ0ICH sets priority level enables external interrupt 8-bit access register. MOVB instruction access
IQ0LV[2:0]: External interrupt interrupt priority level
Sets priority from
IQ0IE: External interrupt interrupt enable flag
Disable Enable
IQ1ICL: External Interrupt Interrupt Control Register (Low)
Bit: Reset: R/W: IQ1IR IQ1ID
x'00FC4A'
IQ1ICL requests verifies interrupt requests external interrupt 8-bit access register. MOVB instruction access
IQ1IR: External interrupt interrupt request flag
interrupt requested Interrupt requested
IQ1ID: External interrupt interrupt detect flag
Interrupt undetected Interrupt detected
IQ1ICH: External Interrupt Interrupt Control Register (High)
Bit: Reset: R/W: IQ1IE
x'00FC4B'
IQ1ICH enables external interrupt 8-bit access register. MOVB instruction access priority level external interrupt written IQ0LV[2:0] field IQ0ICH register.
IQ1IE: External interrupt interrupt enable flag
Disable Enable
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Interrupts
Interrupt Control Registers
IQ2ICL: External Interrupt Interrupt Control Register (Low)
Bit: Reset: R/W: IQ2IR IQ2ID
x'00FC50'
IQ2ICL requests verifies interrupt requests external interrupt 8-bit access register. MOVB instruction access
IQ2IR: External interrupt interrupt request flag
interrupt requested Interrupt requested
IQ2ID: External interrupt interrupt detect flag
Interrupt undetected Interrupt detected
IQ2ICH: External Interrupt Interrupt Control Register (High)
Bit: Reset: R/W: IQ2IE
x'00FC51'
IQ2LV2 IQ2LV1 IQ2LV0
IQ2ICH sets priority level enables external interrupt 8-bit access register. MOVB instruction access
IQ2LV[2:0]: External interrupt interrupt priority level
Sets priority from
IQ2IE: External interrupt interrupt enable flag
Disable Enable
IQ3ICL: External Interrupt Interrupt Control Register (Low)
Bit: Reset: R/W: IQ3IR IQ3ID
x'00FC52'
IQ3ICL requests verifies interrupt requests external interrupt 8-bit access register. MOVB instruction access
IQ3IR: External interrupt interrupt request flag
interrupt requested Interrupt requested
IQ3ID: External interrupt interrupt detect flag
Interrupt undetected Interrupt detected
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Interrupts
Interrupt Control Registers
IQ3ICH: External Interrupt Interrupt Control Register (High)
Bit: Reset: R/W: IQ3IE
x'00FC53'
IQ3ICH enables external interrupt 8-bit access register. MOVB instruction access priority level external interrupt written IQ2LV[2:0] field IQ2ICH register.
IQ3IE: External interrupt interrupt enable flag
Disable Enable
IQ4ICL: External Interrupt Interrupt Control Register (Low)
Bit: Reset: R/W: IQ4IR IQ4ID
x'00FC58'
IQ4ICL requests verifies interrupt requests external interrupt 8-bit access register. MOVB instruction access
IQ4IR: External interrupt interrupt request flag
interrupt requested Interrupt requested
IQ4ID: External interrupt interrupt detect flag
Interrupt undetected Interrupt detected
IQ4ICH: External Interrupt Interrupt Control Register (High)
Bit: Reset: R/W: IQ4IE
x'00FC59'
IQ4LV2 IQ4LV1 IQ4LV0
IQ4ICH sets priority level enables external interrupt 8-bit access register. MOVB instruction access
IQ4LV[2:0]: External interrupt interrupt priority level
Sets priority from
IQ4IE: External interrupt interrupt enable flag
Disable Enable
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Interrupts
Interrupt Control Registers
IQ5ICL: External Interrupt Interrupt Control Register (Low)
Bit: Reset: R/W: IQ5IR IQ5ID
x'00FC5A'
IQ5ICL requests verifies interrupt requests external interrupt 8-bit access register. MOVB instruction access
IQ5IR: External interrupt interrupt request flag
interrupt requested Interrupt requested
IQ5ID: External interrupt interrupt detect flag
Interrupt undetected Interrupt detected
IQ5ICH: External Interrupt Interrupt Control Register (High)
Bit: Reset: R/W: IQ5IE
x'00FC5B'
IQ5ICH enables external interrupt 8-bit access register. MOVB instruction access priority level external interrupt written IQ4LV[2:0] field IQ4ICH register.
IQ5IE: External interrupt interrupt enable flag
Disable Enable
TM4CBICL: Timer Compare/Capture Interrupt Control Register (Low) x'00FC60'
Bit: Reset: R/W: TM4CB TM4CB
TM4CBICL detects requests timer compare/capture interrupts. 8-bit access register. MOVB instruction access
TM4CBIR: Timer compare/capture interrupt request flag
interrupt requested Interrupt requested
TM4CBID: Timer compare/capture interrupt detect flag
Interrupt undetected Interrupt detected
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Interrupts
Interrupt Control Registers
TM4CBICH: Timer Compare/Capture Interrupt Control Register (High)x'00FC61'
Bit: Reset: R/W: TM4CB TM4CB TM4CB TM4CB
TM4CBICH sets priority level enables timer compare/capture interrupts. 8-bit access register. MOVB instruction access
TM4CBLV[2:0]: Timer compare/capture interrupt priority level
Sets priority from
TM4CBIE: Timer compare/capture interrupt enable flag
Disable Enable
TM4CAICL: Timer Compare/Capture Interrupt Control Register (Low) x'00FC62'
Bit: Reset: R/W: TM4CA TM4CA
TM4CAICL detects requests timer compare/capture interrupts. 8-bit access register. MOVB instruction access
TM4CAIR: Timer compare/capture interrupt request flag
interrupt requested Interrupt requested
TM4CAID: Timer compare/capture interrupt detect flag
Interrupt undetected Interrupt detected
TM4CAICH: Timer Compare/Capture Interrupt Control Register (High)x'00FC63'
Bit: Reset: R/W: TM4CA
TM4CAICH enables timer compare/capture interrupts. 8-bit access register. MOVB instruction access priority level timer compare/capture interrupts written TM4CBLV[2:0] field TM4CBICH register.
TM4CAIE: Timer compare/capture interrupt enable flag
Disable Enable
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Interrupt Control Registers
TM4UDICL: Timer Underflow Interrupt Control Register (Low)
Bit: Reset: R/W: TM4UD TM4UD
x'00FC64'
TM4UDICL detects requests timer underflow interrupts. 8bit access register. MOVB instruction access
TM4UDIR: Timer underflow interrupt request flag
interrupt requested Interrupt requested
TM4UDID: Timer underflow interrupt detect flag
Interrupt undetected Interrupt detected
TM4UDICH: Timer Underflow Interrupt Control Register (High)
Bit: Reset: R/W: TM4UD
x'00FC65'
TM4UDICH enables timer underflow interrupts. 8-bit access register. MOVB instruction access priority level timer underflow interrupts written TM4CBLV[2:0] field TM4CBICH register.
TM4UDIE: Timer underflow interrupt enable flag
Disable Enable
VBIICL: Interrupt Control Register (Low)
Bit: Reset: R/W:
x'00FC66'
VBIICL detects requests interrupts. 8-bit access register. MOVB instruction access
VBIIR: interrupt request flag
interrupt requested Interrupt requested
VBIID: interrupt detect flag
Interrupt undetected Interrupt detected
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VBIICH: Interrupt Control Register (High)
Bit: Reset: R/W:
x'00FC67'
VBIICH enables interrupts. 8-bit access register. MOVB instruction access priority level interrupts written TM4CBLV[2:0] field TM4CBICH register.
VBIIE: interrupt enable flag
Disable Enable
TM5CBICL: Timer Compare/Capture Interrupt Control Register (Low) x'00FC68'
Bit: Reset: R/W: TM5CB TM5CB
TM5CBICL detects requests timer compare/capture interrupts. 8-bit access register. MOVB instruction access
TM5CBIR: Timer compare/capture interrupt request flag
interrupt requested Interrupt requested
TM5CBID: Timer compare/capture interrupt detect flag
Interrupt undetected Interrupt detected
TM5CBICH: Timer Compare/Capture Interrupt Control Register (High)x'00FC69'
Bit: Reset: R/W: TM5CB TM5CB TM5CB TM5CB
TM5CBICH sets priority level enables timer compare/capture interrupts. 8-bit access register. MOVB instruction access
TM5CBLV[2:0]: Timer compare/capture interrupt priority level
Sets priority from
TM5CBIE: Timer compare/capture interrupt enable flag
Disable Enable
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Interrupts
Interrupt Control Registers
TM5CAICL: Timer Compare/Capture Interrupt Control Register (Low) x'00FC6A'
Bit: Reset: R/W: TM5CA TM5CA
TM5CAICL detects requests timer compare/capture interrupts. 8-bit access register. MOVB instruction access
TM5CAIR: Timer compare/capture interrupt request flag
interrupt requested Interrupt requested
TM5CAID: Timer compare/capture interrupt detect flag
Interrupt undetected Interrupt detected
TM5CAICH: Timer Compare/Capture Interrupt Control Register (High) x'00FC6B'
Bit: Reset: R/W: TM5CA
TM5CAICH enables timer compare/capture interrupts. 8-bit access register. MOVB instruction access priority level timer compare/capture interrupts written TM5CBLV[2:0] field TM5CBICH register.
TM5CAIE: Timer compare/capture interrupt enable flag
Disable Enable
TM5UDICL: Timer Underflow Interrupt Control Register (Low)
Bit: Reset: R/W: TM5UD TM5UD
x'00FC6C'
TM5UDICL detects requests timer underflow interrupts. 8bit access register. MOVB instruction access
TM5UDIR: Timer underflow interrupt request flag
interrupt requested Interrupt requested
TM5UDID: Timer underflow interrupt detect flag
Interrupt undetected Interrupt detected
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TM5UDICH: Timer Underflow Interrupt Control Register (High)
Bit: Reset: R/W: TM5UD
x'00FC6D'
TM5UDICH enables timer underflow interrupts. 8-bit access register. MOVB instruction access priority level timer underflow interrupts written TM5CBLV[2:0] field TM5CBICH register.
TM5UDIE: Timer underflow interrupt enable flag
Disable Enable
VBIWICL: Interrupt Control Register (Low)
Bit: Reset: R/W: VBIW VBIW
x'00FC6E'
VBIWICL detects requests interrupts. 8-bit access register. MOVB instruction access
VBIWIR: interrupt request flag
interrupt requested Interrupt requested
VBIWID: interrupt detect flag
Interrupt undetected Interrupt detected
VBIWICH: Interrupt Control Register (High)
Bit: Reset: R/W: VBIW
x'00FC6F'
VBIWICH register enables interrupts. 8-bit access register. MOVB instruction access priority level interrupts written TM5CBLV[2:0] field TM5CBICH register.
VBIWIE: interrupt enable flag
Disable Enable
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Interrupt Control Registers
TM2UDICL: Timer Underflow Interrupt Control Register (Low)
Bit: Reset: R/W: TM2UD TM2UD
x'00FC70'
TM2UDICL register detects requests timer underflow interrupts. 8-bit access register. MOVB instruction access
TM2UDIR: Timer underflow interrupt request flag
interrupt requested Interrupt requested
TM2UDID: Timer underflow interrupt detect flag
Interrupt undetected Interrupt detected
TM2UDICH: Timer Underflow Interrupt Control Register (High)
Bit: Reset: R/W: TM2UD TM2UD TM2UD TM2UD
x'00FC71'
TM2UDICH sets priority level enables timer underflow interrupts. 8-bit access register. MOVB instruction access
TM2UDLV[2:0]: Timer underflow interrupt priority level
Sets priority from
TM2UDIE: Timer underflow interrupt enable flag
Disable Enable
TM1UDICL: Timer Underflow Interrupt Control Register (Low)
Bit: Reset: R/W: TM1UD TM1UD
x'00FC72'
TM1UDICL detects requests timer underflow interrupts. 8bit access register. MOVB instruction access
TM1UDIR: Timer underflow interrupt request flag
interrupt requested Interrupt requested
TM1UDID: Timer underflow interrupt detect flag
Interrupt undetected Interrupt detected
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TM1UDICH: Timer Underflow Interrupt Control Register (High)
Bit: Reset: R/W: TM1UD
x'00FC73'
TM1UDICH enables timer underflow interrupts. 8-bit access register. MOVB instruction access priority level timer underflow interrupts written TM2UDLV[2:0] field TM2UDICH register.
TM1UDIE: Timer underflow interrupt enable flag
Disable Enable
TM0UDICL: Timer Underflow Interrupt Control Register (Low)
Bit: Reset: R/W: TM0UD TM0UD
x'00FC74'
TM0UDICL register detects requests timer underflow interrupts. 8-bit access register. MOVB instruction access
TM0UDIR: Timer underflow interrupt request flag
interrupt requested Interrupt requested
TM0UDID: Timer underflow interrupt detect flag
Interrupt undetected Interrupt detected
TM0UDICH: Timer Underflow Interrupt Control Register (High)
Bit: Reset: R/W: TM0UD
x'00FC75'
TM0UDICH enables timer underflow interrupts. 8-bit access register. MOVB instruction access priority level timer underflow written TM2UDLV[2:0] field TM2UDICH register.
TM0UDIE: Timer underflow interrupt enable flag
Disable Enable
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Interrupt Control Registers
RMCICL: Remote Signal Receive Interrupt Control Register (Low)
Bit: Reset: R/W:
x'00FC76'
RMCICL detects requests remote signal receive interrupts. 8bit access register. MOVB instruction access
RMCIR: Remote signal receive interrupt request flag
interrupt requested Interrupt requested
RMCID: Remote signal receive interrupt detect flag
Interrupt undetected Interrupt detected
RMCICH: Remote Signal Receive Interrupt Control Register (High)
Bit: Reset: R/W:
x'00FC77'
RMCICH enables remote signal receive interrupts. 8-bit access register. MOVB instruction access priority level remote signal receive interrupts written TM2UDLV[2:0] field TM2UDICH register.
RMCIE: Remote signal receive interrupt enable flag
Disable Enable
ADM3ICL: Address Match Interrupt Control Register (Low)
Bit: Reset: R/W: ADM3 ADM3
x'00FC78'
ADM3ICL detects requests address match interrupts. 8-bit access register. MOVB instruction access
ADM3IR: Address match interrupt request flag
interrupt requested Interrupt requested
ADM3ID: Address match interrupt detect flag
Interrupt undetected Interrupt detected
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ADM3ICH: Address Match Interrupt Control Register (High)
Bit: Reset: R/W: ADM3 ADM3 ADM3 ADM3
x'00FC79'
ADM3ICH sets priority level enables address match interrupts. 8-bit access register. MOVB instruction access
ADM3LV[2:0]: Address match interrupt priority level
Sets priority from
ADM3IE: Address match interrupt enable flag
Disable Enable
ADM2ICL: Address Match Interrupt Control Register (Low)
Bit: Reset: R/W: ADM2 ADM2
x'00FC7A'
ADM2ICL detects requests address match interrupts. 8-bit access register. MOVB instruction access
ADM2IR: Address match interrupt request flag
interrupt requested Interrupt requested
ADM2ID: Address match interrupt detect flag
Interrupt undetected Interrupt detected
ADM2ICH: Address Match Interrupt Control Register (High)
Bit: Reset: R/W: ADM2
x'00FC7B'
ADM2ICH enables address match interrupts. 8-bit access register. MOVB instruction access priority level address match interrupts written ADM3LV[2:0] field ADM3ICH register.
ADM2IE: Address match interrupt enable flag
Disable Enable
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Interrupt Control Registers
ADM1ICL: Address Match Interrupt Control Register (Low)
Bit: Reset: R/W: ADM1 ADM1
x'00FC7C'
ADM1ICL detects requests address match interrupts. 8-bit access register. MOVB instruction access
ADM1IR: Address match interrupt request flag
interrupt requested Interrupt requested
ADM1ID: Address match interrupt detect flag
Interrupt undetected Interrupt detected
ADM1ICH: Address Match Interrupt Control Register (High)
Bit: Reset: R/W: ADM1
x'00FC7D'
ADM1ICH enables address match interrupts. 8-bit access register. MOVB instruction access priority level address match interrupts written ADM3LV[2:0] field ADM3ICH register.
ADM1IE: Address match interrupt enable flag
Disable Enable
ADM0ICL: Address Match Interrupt Control Register (Low)
Bit: Reset: R/W: ADM0 ADM0
x'00FC7E'
ADM0ICL detects requests address match interrupts. 8-bit access register. MOVB instruction access
ADM0IR: Address match interrupt request flag
interrupt requested Interrupt requested
ADM0ID: Address match interrupt detect flag
Interrupt undetected Interrupt detected
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ADM0ICH: Address Match Interrupt Control Register (High)
Bit: Reset: R/W: ADM0
x'00FC7F'
ADM0ICH enables address match interrupts. 8-bit access register. MOVB instruction access priority level address match interrupts written ADM3LV[2:0] field ADM3ICH register.
ADM0IE: Address match interrupt enable flag
Disable Enable
ANICL: Conversion Interrupt Control Register (Low)
Bit: Reset: R/W: ANIR ANID
x'00FC80'
ANICL detects requests conversion interrupts. 8-bit access register. MOVB instruction access
ANIR: conversion interrupt request flag
interrupt requested Interrupt requested
ANID: conversion interrupt detect flag
Interrupt undetected Interrupt detected
ANICH: Conversion Interrupt Control Register (High)
Bit: Reset: R/W: ANIE
x'00FC81'
ANLV2 ANLV1 ANLV0
ANICH sets priority level enables conversion interrupts. 8-bit access register. MOVB instruction access
ANLV[2:0]: conversion interrupt priority level
Sets priority from
ANIE: conversion interrupt enable flag
Disable Enable
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SCT0ICL: Serial Transmission Interrupt Control Register (Low) x'00FC82'
Bit: Reset: R/W: SCT0 SCT0
SCT0ICL detects requests serial transmission interrupts. 8-bit access register. MOVB instruction access
SCT0IR: Serial transmission interrupt request flag
interrupt requested Interrupt requested
SCT0ID: Serial transmission interrupt detect flag
Interrupt undetected Interrupt detected
SCT0ICH: Serial Transmission Interrupt Control Register (High) x'00FC83'
Bit: Reset: R/W: SCT0
SCT0ICH enables serial transmission interrupts. 8-bit access register. MOVB instruction access priority level serial transmission interrupts written ANLV[2:0] field ANICH register.
SCT0IE: Serial transmission interrupt enable flag
Disable Enable
SCR0ICL: Serial Reception Interrupt Control Register (Low)
Bit: Reset: R/W: SCR0 SCR0
x'00FC84'
SCR0ICL detects requests serial reception interrupts. 8bit access register. MOVB instruction access
SCT0IR: Serial reception interrupt request flag
interrupt requested Interrupt requested
SCT0ID: Serial reception interrupt detect flag
Interrupt undetected Interrupt detected
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SCR0ICH: Serial Reception Interrupt Control Register (High)
Bit: Reset: R/W: SCR0
x'00FC85'
SCR0ICH enables serial reception interrupts. 8-bit access register. MOVB instruction access priority level serial reception interrupts written ANLV[2:0] field ANICH register.
SCR0IE: Serial reception interrupt enable flag
Disable Enable
VBIVICL: VBIVSYNC Interrupt Control Register (Low)
Bit: Reset: R/W: VBIVIR VBIVID
x'00FC88'
VBIVICL detects requests VBIVSYNC interrupts. 8-bit access register. MOVB instruction access
VBIVIR: VBIVSYNC interrupt request flag
interrupt requested Interrupt requested
VBIVID: VBIVSYNC interrupt detect flag
Interrupt undetected Interrupt detected
VBIVICH: VBIVSYNC Interrupt Control Register (High)
Bit: Reset: R/W: VBIV VBIV VBIV VBIV
x'00FC89'
VBIVICH sets priority level enables VBIVSYNC interrupts. 8-bit access register. MOVB instruction access
VBIVLV[2:0]: VBIVSYNC interrupt priority level
Sets priority from
VBIVIE: VBIVSYNC interrupt enable flag
Disable Enable
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VBIVWICL: VBIVSYNC Interrupt Control Register (Low)
Bit: Reset: R/W: VBIVW VBIVW
x'00FC8A'
VBIVWICL detects requests VBIVSYNC interrupts. 8-bit access register. MOVB instruction access
VBIVWIR: VBIVSYNC interrupt request flag
interrupt requested Interrupt requested
VBIVWID: VBIVSYNC interrupt detect flag
Interrupt undetected Interrupt detected
VBIVWICH: VBIVSYNC Interrupt Control Register (High)
Bit: Reset: R/W: VBIVW
x'00FC8B'
VBIVWICH enables VBIVSYNC interrupts. 8-bit access register. MOVB instruction access priority level VBIVSYNC interrupts written VBIVLV[2:0] field VBIVICH register.
VBIVWIE: VBIVSYNC interrupt enable flag
Disable Enable
TM3UDICL: Timer Underflow Interrupt Control Register (Low)
Bit: Reset: R/W: TM3UD TM3UD
x'00FC8C'
TM3UDICL detects requests timer underflow interrupts. 8bit access register. MOVB instruction access
TM3UDIR: Timer underflow interrupt request flag
interrupt requested Interrupt requested
TM3UDID: Timer underflow interrupt detect flag
Interrupt undetected Interrupt detected
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TM3UDICH: Timer Underflow Interrupt Control Register (High)
Bit: Reset: R/W: TM3UD
x'00FC8D'
TM3UDICH enables timer underflow interrupts. 8-bit access register. MOVB instruction access priority level timer underflow interrupts written VBIVLV[2:0] field VBIVICH register.
TM3UDIE: Timer underflow interrupt enable flag
Disable Enable
OSDGICL: (Graphics) Interrupt Control Register (Low)
Bit: Reset: R/W: OSDG OSDG
x'00FC90'
OSDGICL detects requests (graphics) interrupts. 8-bit access register. MOVB instruction access
OSDGIR: (graphics) interrupt request flag
interrupt requested Interrupt requested
OSDGID: (graphics) interrupt detect flag
Interrupt undetected Interrupt detected
OSDGICH: (Graphics) Interrupt Control Register (High)
Bit: Reset: R/W: OSDG OSDG OSDG OSDG
x'00FC91'
OSDGICH sets priority level enables (graphics) interrupts. 8-bit access register. MOVB instruction access
OSDGLV[2:0]: (graphics) interrupt priority level
Sets priority from
OSDGIE: (graphics) interrupt enable flag
Disable Enable
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OSDCICL: (Text) Interrupt Control Register (Low)
Bit: Reset: R/W: OSDC OSDC
x'00FC92'
OSDCICL detects requests (text) interrupts. 8-bit access register. MOVB instruction access
OSDCIR: (text) interrupt request flag
interrupt requested Interrupt requested
OSDCID: (text) interrupt detect flag
Interrupt undetected Interrupt detected
OSDCICH: (Text) Interrupt Control Register (High)
Bit: Reset: R/W: OSDC
x'00FC93'
OSDCICH enables timer (text) interrupts. 8-bit access register. MOVB instruction access priority level (text) interrupts written OSDGLV[2:0] field OSDGICH register.
OSDCIE: (text) interrupt enable flag
Disable Enable
SCT1ICL: Serial Transmission Interrupt Control Register (Low) x'00FC98'
Bit: Reset: R/W: SCT1 SCT1
SCT1ICL detects requests serial transmission interrupts. 8-bit access register. MOVB instruction access
SCT1IR: Serial transmission interrupt request flag
interrupt requested Interrupt requested
SCT1ID: Serial transmission interrupt detect flag
Interrupt undetected Interrupt detected
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SCT1ICH: Serial Transmission Interrupt Control Register (High) x'00FC99'
Bit: Reset: R/W: SCT1 SCT1 SCT1 SCT1
SCT1ICH sets priority level enables serial transmission interrupts. 8-bit access register. MOVB instruction access
SCT1LV[2:0]: Serial transmission interrupt priority level
Sets priority from
SCT1IE: Serial transmission interrupt enable flag
Disable Enable
SCR1ICL: Serial Reception Interrupt Control Register (Low)
Bit: Reset: R/W: SCR1 SCR1
x'00FC9A'
SCR1ICL detects requests serial reception interrupts. 8bit access register. MOVB instruction access
SCT1IR: Serial reception interrupt request flag
interrupt requested Interrupt requested
SCT1ID: Serial reception interrupt detect flag
Interrupt undetected Interrupt detected
SCR1ICH: Serial Reception Interrupt Control Register (High)
Bit: Reset: R/W: SCR1
x'00FC9B'
SCR1ICH enables serial reception interrupts. 8-bit access register. MOVB instruction access priority level serial reception interrupts written SCT1LV[2:0] field SCT1ICH register.
SCR1IE: Serial reception interrupt enable flag
Disable Enable
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Interrupt Control Registers I2CICL: Interrupt Control Register (Low)
Bit: Reset: R/W:
x'00FC9C'
I2CICL detects requests interrupts. 8-bit access register. MOVB instruction access
I2CIR: interrupt request flag
interrupt requested Interrupt requested
I2CID: interrupt detect flag
Interrupt undetected Interrupt detected
I2CICH: Interrupt Control Register (High)
Bit: Reset: R/W:
x'00FC9D'
I2CICH enables interrupts. 8-bit access register. MOVB instruction access priority level interrupts written SCT1LV[2:0] field SCT1ICH register.
I2CIE: interrupt enable flag
Disable Enable
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Low-Power Modes
Modes
Low-Power Modes
MN102H51K/57K provides ways reduce power consumption, controlling operating standby modes overall consumption shutting down unused functions stopping system clock supplied them.
3.1.1
Modes
Description
MN102H51K/57K operating modes, NORMAL SLOW, standby modes, HALT STOP. Effective these modes significantly reduce power consumption. Figure shows states different modes.
Program (Write CPUM register) Clock CPU: System clock: stopped,
NORMAL Mode
Interrupt Clock CPU: System clock:
Program (Write CPUM register)
STOP Mode
Clock CPU: System clock: Program (Write CPUM register)
IDLE State
HALT Mode
Clock CPU: System clock:
Program (Write CPUM register) Program (Write CPUM register) Clock CPU: System clock:
Program (Write CPUM register)
SLOW Mode
Interrupt Clock CPU: System clock: Interrupt
Figure State Changes
mode control register (CPUM) controls transitions between NORMAL SLOW modes from NORMAL SLOW modes standby modes. normal reset interrupt wakes from standby mode.
cannot enter STOP mode from NORMAL mode.
Note that cannot invoke STOP mode from NORMAL mode.You only enter STOP from SLOW mode.
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Low-Power Modes
Modes
3.1.2
Exiting from SLOW Mode NORMAL
MN102H51K/57K recovers from power reset SLOW mode. normal operation, program must switch from SLOW NORMAL mode.
MN102H51K/57K contains circuit that, NORMAL mode, multiplies clock input through OSC1 OSC2 pins divides signal then sends resulting clock CPU. (See figure 3-2.) starts SLOW mode power recovery from reset. SLOW mode (system clock MHz), clock from pins feeds directly CPU, without going through circuit. This means that program must switch from SLOW NORMAL mode (system clock MHz).
circuit
Divide-by-2 circuit
Clock select (CPUM register)
NORMAL mode SLOW mode
function blocks System clock: SLOW: NORMAL:
Oscillator Circuit
Figure Clock Switch (NORMAL/SLOW Modes)
Below example routine exiting SLOW mode. should this routine immediately after power
Example Exiting SLOW Mode
x'FC00',A1 (A1),D0 x'FFFD',D0 (D0),A1 (A1),D0 x'FFF0',D0 (D0),A1
;Read CPUM register ;Invoke IDLE mode ;Read CPUM register ;Invoke NORMAL mode
Because system clock SLOW mode MHz, does function. specifications also differ function functions such remote signal receiver counter that waveforms.
cannot display SLOW mode.
information invoking SLOW mode from NORMAL mode, MN10200 Series Linear Addressing High-Speed Version User Manual.
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Low-Power Modes
Modes
3.1.3
Notes Invoking Exiting STOP HALT Modes
When invoking STOP HALT modes.
reduce power consumption before invoking STOP HALT mode, stop current flow from output pins stabilize input level input pins. output pins, either match output level external level input. input pins, ensure that external level fixed. further reduce power consumption, shut down unnecessary functions through control registers. (See section 3.2, "Turning Individual Functions Off," page 75.) Before entering STOP mode, bits shown table disable these functions. Disable functions NORMAL mode except circuit, which only shut down once have entered SLOW mode. allow exit STOP HALT mode reset interrupt, must interrupt registers before invoke standby mode. specify particular interrupt vector signal waking enable that vector interrupt registers. (For more information controlling interrupts, "section "Interrupts," page 37.)
Using OSDX clock (both blocking oscillator external source), OSDXI OSDXO must port (P46, P45) output before invoking STOP mode.
When exiting STOP HALT modes.
exits STOP HALT modes reset interrupt. information exiting interrupt, Figure 3-1, "CPU State Changes," page When exits reset, always exits SLOW mode.
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Low-Power Modes
Turning Individual Functions
Turning Individual Functions
cannot function control during NORMAL mode. must from SLOW mode.
MN102H51K/57K allows turn each peripheral function through writing registers. significantly reduce power consumption turning unused functions. Table shows register bits controlling each function block. used functions turned reset. Write function enable when necessary. cannot read from write registers associated with function that disabled. Turning function enables register reads writes. sections each these peripheral functions more information.
turn block save power: Write (OSD1, bit10). Wait next VSYNC input. Write OSDPOFF(PCNT0, turning clock off. turn clock before VSYNC input, power usage drop microcontroller halt.
Table Peripheral Function On/Off Switches Block Name Description Name
block control function control register control control CCD1 control CCD0 CCD1 function control CCD0 function control counter function control counter function control VBI1OFF VBI0OFF PLLPOFF HCNTOFF OSDPOFF OSDREG ADC1ON ADC0ON
Address
PCNT0, x'00FF90', OSD1, x'007F06', PCNT2, x'00FF92', PCNT0, x'00FF90', PCNT0, x'00FF90', PCNT0, x'00FF90', PCNT0, x'00FF90', PCNT0, x'00FF90', PCNT0, x'00FF90', PCNT0, x'00FF90', PCNT2, x'00FF92', PCNT2, x'00FF92',
Operation
block block enabled function function register register enabled CCD1 CCD1 enabled CCD0 CCD0 enabled CCD1 block CCD1 block enabled CCD0 block CCD0 block enabled block enabled block counter block enabled counter block remote signal receiver block remote signal receiver block enabled block enabled block block enabled block
Reset Value
remote signal receiver
remote signal receiver function control
RMCOFF
function control function control
I2COFF PWMOFF
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Low-Power Modes
Control Register
Bit: Reset: R/W:
Control Registe
x'00FC00'
CPUM: Mode Control Register
STOP HALT OSC1 OSC0
This register controls invoking modes.
NWDEN: Watchdog timer reset
Enable watchdog timer Disable clear watchdog timer Setting watchdog timer then setting clears restarts watchdog timer.
OSCID: Oscillator select
System clock monitor Fast Slow
STOP: STOP mode request
operating state control. table 3-2.
HALT: HALT mode request
operating state control. table 3-2.
OSC[1:0]: Oscillator control
table 3-2.
Table Mode Settings STOP HALT OSC1 OSC0
Mode
NORMAL SLOW HALT0 (Invoked from NORMAL) HALT1 (Invoked from SLOW) STOP
Clock System Clock
Note: unindicated settings reserved.
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Timers
8-Bit Timer Description
Timers
8-Bit Timer Description
MN102H51K/57K contains four 8-bit timers that serve interval timers, event timer/counters, clock generators (divide-by-2 output underflow), reference clocks serial interfaces, start timers conversions. clock source internal clock (oscillator frequency divided external clock (1/4 less oscillator frequency input). timer interrupt generated timer underflow.
passages below assume clock BOSC MHz.
8-bit timers cascadable into true 16-bit timers. instance, cascade timers timer sends cascaded output timer result true 16-bit division, rather than successive 8-bit divisions.
Cascading Connections 8-bit Configuration example 16-bit 8-bit 8-bit 8-bit 8-bit 16-bit
Clock output
Interval timer
Sync. UART transfer transfer clock clock
Event timer
Event timer
Figure Timer Configuration Examples
TM0UDIR 16-bit timer, serial I/F) TM1UDIR
conversion start
16-bit timer, serial I/F)
TM2UDIR TM3UDIR
TMIO
TMIA TMIB TMIC TMID TMIO TMIA TMIB TMIC TMID
BOSC/4 BOSC/256 BOSC/512
TM0O
TMIO
TMIA TMIB TMIC TMID
BOSC/64
TM0I
TMIO
TMIA TMIB TMIC TMID
TM1I
TM1O
Note: BOSC Figure Block Diagram 8-Bit Timers
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Timers
8-Bit Timer Features
Function/Feature
Interrupt request flag(s) Interrupt source(s) Interval timer function Event counter function Clock source 16-bit timer Timer output function
8-Bit Timer Features
Timer
TM1UDICL register (TM1UDIR bit) Timer underflow
Table 8-Bit Timer Functions Features Timer
TM0UDICL register (TM0UDIR bit) Timer underflow (TM0O signal) Serial interface transfer clock source conversion trigger function Clock sources Cascade connection BOSC/4 BOSC/64 BOSC/512 TM0I signal BOSC/4 BOSC/64 Cascade connection TM1I signal BOSC/4 BOSC/256 Cascade connection BOSC/512 (TM1O signal) BOSC/4 BOSC/256 Cascade connection BOSC/512
Timer
TM2UDICL register (TM2UDIR bit) Timer underflow
Timer
TM3UDICL register (TM3UDIR bit) Timer underflow
Note: When BOSC MHz: BOSC/4 BOSC/64 BOSC/256 93.75 BOSC/512 48.875 kHz.
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Timers
8-Bit Timer Block Diagrams
8-Bit Timer Block Diagrams
Data
(FE10)
Timer base register TM0BR Load
(FE20)
Reload
(FE00)
Cascade from timer TM1I
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TM0EN
TM0LD
TM0S1
TM0S0
Timer binary counter TM0BC Count
Underflow
TM0MD
Timer underflow interrupt
Reset BOSC BOSC/64 BOSC/412 TM0I Multiplexer
TM0O
P2MD7,P2DIR7 setting
Figure Timer Block Diagram
Data
(FE11)
Timer base register TM1BR Load
(FE21) TM1EN TM1LD TM1S1 TM1S0
Reload
(FE01)
Timer binary counter TM1BC Underflow Count
TM1MD
Timer underflow interrupt
Reset BOSC/4 BOSC/64 Multiplexer
TM1O
P4MD1,P4DIR1 setting
Figure Timer Block Diagram
MN102H51K/57K User Manual
Timers
8-Bit Timer Block Diagrams
Data
(FE12)
Timer base register TM2BR Load
(FE22) TM2EN TM3EN TM2LD TM2S1 TM2S0
Reload
(FE02)
Timer binary counter TM2BC Underflow Count
TM2MD
Timer underflow interrupt
BOSC/4 BOSC/256 Cascade from timer BOSC/512
Multiplexer
Figure Timer Block Diagram
Data
(FE13)
Timer base register TM3BR Load
(FE23) TM3LD TM3S1 TM3S0
Reload
(FE03)
Timer binary counter TM3BC Underflow Count
TM3MD
Timer underflow interrupt
BOSC/4 BOSC/256 Cascade from timer BOSC/512
Multiplexer
Figure Timer Block Diagram
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Timers
8-Bit Timer Timing
8-Bit Timer Timing
value
Load value
Time
TMnIO input Figure Event Timer Input Timing (8-Bit Timers)
value Load value
Time Interrupt
TMnIO input TMnIO output Figure Clock Output Interval Timer Timing (8-Bit Timers)
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Timers
8-Bit Timer Setup Examples
4.5.1
8-Bit Timer Setup Examples
Setting Event Counter Using Timer
this example, timer generates underflow interrupt fourth rising edge TM0IO signal. event counter continues operate during STOP mode. modes STOP, TMnIO signal input synchronized OSC. STOP mode, timer counts TMnIO signal directly. When interrupt occurs, returns NORMAL mode after oscillator stabilization wait. event counter continues count TMnIO signal during stabilization wait, same time that returns NORMAL mode, event counter begins counting signal resulting from BOSC sampling TMnIO signal input.
TM0I
CORE Interrupts Timers Timers
ROM, Controller Serial I/Fs
Figure Block Diagram Event Counter Using Timer
interrupt enable flag (IE) processor status word (PSW) Disable timer counting timer mode register (TM0MD). This step unnecessary immediately after reset, since TM0MD resets
x'00FE20'
TM0MD (example)
Bit: Setting:
TM2UDICH, TM0UDICL, TM0UDICH 8-bit access registers. MOVB instruction access them.
Cancel existing interrupt requests enable timer underflow interrupts. this, TM2UDLV[2:0] bits TM2UDICH (priority level this example), TM0UDIE TM0UDIR TM0UDICL (Note that priority level timer interrupts timer interrupt control register.) From this point interrupt request generated whenever timer underflows.
x'00FC71'
TM2UD
TM2UDICH (example)
Bit: Setting: TM2UD TM2UD TM2UD
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Timers
8-Bit Timer Setup Examples
TM0UDICL (example)
Bit: Setting: TM0UD TM0UD
x'00FC74'
TM0UDICH (example)
Bit: Setting: TM0UD
x'00FC75'
divide-by ratio timer Since timer will count TM0IO cycles, write x'03' timer base register (TM0BR). (The valid range TM0BR 255.)
x'00FE10'
TM0BR (example)
Bit: Setting:
TM0LD TM0MD register This loads value base register binary counter. same time, select clock source TM0IO signal input writing b'11' TM0S[1:0].
x'00FE20'
change clock source once select Selecting clock source while count operation control will corrupt value binary counter.
TM0MD (example)
Bit: Setting:
bank linear addressing versions MN102 series, necessary TM0EN TM0LD between steps ensure stable operation. This unnecessary high-speed linear addressing version.
TM0LD TM0EN This starts timer. Counting begins start next cycle. When binary counter reaches loads value x'03' from base register, preparation next count, timer underflow interrupt request sent CPU.
Interrupt enable TM0BR TM0BC
Timer underflow interrupt
TM0IO Sequence TM0UDICH(B) TM0MD(B) TM0BR(B) TM0MD(B)
Figure 4-10 Event Counter Timing (Timer
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8-Bit Timer Setup Examples
4.5.2
Setting Interval Timer Using Timers
this example, timers cascaded divide OSC/4 60,000 generate underflow interrupt.
16-bit timer BOSC MHz) (Divide Timer (Divide 60,000) (x'EA60') Timer Timer underflow interrupt
Figure 4-11 Configuration Example Interval Timer Using Timer
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