MN1021617/F1617 User's Manual Pub.No.22317-041E PanaXSeries
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MICROCOMPUTER MN102H00
MN1021617/F1617 User's Manual
Pub.No.22317-041E
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About This Manual
This manual intended assembly-language programming engineers. describes internal configuration hardware functions MN102H55D/55G/F55G microcontrollers.
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Contents
Chapter General Description
Chapter Interface
Chapter Interrupts
Chapter Timers
Chapter Serial Interface
Chapter Analog Interface Chapter (Data Automatic Transfer Function) Chapter Ports
Chapter Appendix
Contents
Contents
Chapter General Description
General Description 1-1-1 Introduction 1-1-2 Features 1-1-3 Overview Basic Specification Block Diagram Description 1-4-1 Single-chip Mode 1-4-2 Processor Mode with 16-bit Address/Data Multiplex Mode 1-4-3 Processor Mode with 8-bit Address/Data Multiplex Mode 1-4-4 Processor Mode with 16-bit Address/Data Separate Mode 1-4-5 Processor Mode with 8-bit Address/Data Separate Mode 1-4-6 List MN1021617/F1617 Pins 1-4-7 MN1021617/F1617 External Dimensions
Chapter Interface
Summary Interface 2-1-1 Overview 2-1-2 Control Registers 2-1-3 Memory Connection Examples 2-1-4 Access External Memory 2-1-5 Each Mode Activation Sequence
Chapter Interrupts
Interrupt Groups 3-1-1 Overview 3-1-2 Control Registers Interrupt Setup Examples 3-2-1 External Interrupt Setup Examples 3-2-2 Input Interrupt Setup Examples. 3-2-3 Watchdog Timer Interrupt Setup Examples
Chapter Timers
Summary 8-bit Timer Functions 4-1-1 Overview 4-1-2 8-bit Timer Control Registers 4-1-3 8-bit Timer Block Diagrams 8-bit Timer Setup Examples 4-2-1 Event Counter Using 8-bit Timer 4-2-2 Clock Output Using 8-bit Timer 4-2-3 Interval Timer Using 8-bit Timer Summary 16-bit Timer Functions 4-3-1 Overview 4-3-2 16-bit Timer Control Registers 4-3-3 16-bit Timer Block Diagrams 16-bit Timer Setup Examples 4-4-1 Event Counter Using 16-bit Timer 4-4-2 One-phase Output Using 16-bit Timer 4-4-3 Two-phase Output Using 16-bit Timer 4-4-4 One-phase Capture Input Using 16-bit Timer 4-4-5 Two-phase Capture Input Using 16-bit Timer 4-4-6 Two-phase Encoder Input (4x) Using 16-bit Timer 4-4-7 Two-phase Encoder Input (1x) Using 16-bit Timer 4-4-8 One-shot Pulse Using 16-bit Timer 4-4-9 External Count Direction Control Using 16-bit Timer 4-4-10 External Reset Control Using 16-bit Timer Summary 24-bit Timer Functions 4-5-1 Overview 4-5-2 24-bit Timer Control Registers 4-5-3 Servo Control Using 24-bit Timer 4-5-4 Servo Control Setup Examples
Chapter Serial Interface
Summary Serial Interface 5-1-1 Overview 5-1-2 Control Registers 5-1-3 Serial Interface Connection Serial Interface Setup Examples 5-2-1 Serial Transmission Asynchronous Mode 5-2-2 Serial Reception Synchronous Mode 5-2-3 Serial Clock Operation Example 5-2-4 Transmission 5-2-5 Reception
Chapter Analog Interface
Summary Converter 6-1-1 Overview 6-1-2 Control Registers Converter Setup Examples 6-2-1 Single Channel Conversion 6-2-2 Three Channel Conversion
Chapter (Data Automatic Transfer Function)
Summary 7-1-1 Overview 7-1-2 Control Registers Setup Examples 7-2-1 Serial Reception
Chapter Ports
Summary Ports 8-1-1 Overview 8-1-2 Control Registers Port Setup Examples 8-2-1 General-purpose Port Setup
Chapter Appendix
Electrical Characteristics 9-1-1 MN1021617 9-1-2 MN102F1617 Data Appendix 9-2-1 List Special Registers 9-2-2 MN1021617/F1617 Register Address Initialization Program Flash EEPROM Version 9-4-1 Overview 9-4-2 Flash EEPROM Programming 9-4-3 PROM Writer Mode 9-4-4 Onboard Serial Programming Mode 9-4-5 Hardware Used Serial Programming Mode 9-4-6 Connecting Onboard Serial Programming Mode 9-4-7 System Configuration Onboard Serial Programming 9-4-8 Onboard Serial Programming Mode Setup 9-4-9 Branch User Program 9-4-10 Serial Interface Onboard Serial Programming 9-4-11 PROM Writer/Onboard Serial Programming 9-4-12 List Adaptors List MN102H00 Series Linear Address High-speed Edition Instructions
Figures
Figure 1-1-1 Figure 1-1-2 Figure 1-1-3 Figure 1-1-4 Figure 1-3-1 Figure 1-4-1 Figure 1-4-2 Figure 1-4-3 Figure 1-4-4 Figure 1-4-5 Figure 1-4-6 Figure 1-4-7 Figure 1-4-8 Figure 1-4-9 Figure 1-4-10 Figure 2-1-1 Figure 2-1-2 Figure 2-1-3 Figure 2-1-4 Figure 2-1-5 Figure 2-1-6 Figure 2-1-7 Figure 2-1-8 Figure 2-1-9 Figure 2-1-10 Figure 3-1-1 Figure 3-1-2 Figure 3-2-1 Figure 3-2-2 Figure 3-2-3 Figure 3-2-4 Figure 3-2-5
Processor Status Word (PSW) Address Space (Memory Expansion Mode) Interrupt Controller Configuration Interrupt Servicing Sequence Block Diagram Configuration Single-chip Mode Configuration Processor Mode with 16-bit Address/Data Multiplex Mode Configuration Processor Mode with 8-bit Address/Data Multiplex Mode Configuration Processor Mode with 16-bit Address/Data Separate Mode Configuration Processor Mode with 8-bit Address/Data Separate Mode Power Source Writing Precaution OSCI, OSCO Connection Example Reset Connection Example Reset Connection Example External Dimensions; 128-pin LQFP Address Space SRAM Connection Example (16-bit Width) SRAM Connection Example (8-bit Width) PSRAM Connection Example (16-bit Width) PSRAM Connection Example (8-bit Width) DRAM (2WE Method) Connection Example (16-bit Width) DRAM Connection Example (8-bit Width) External Access wait) External Access (0.5 wait cycle) Each Mode Activation Sequence Interrupt Controller Block Diagram Interrupt Servicing Time External Interrupt Block Diagram External Interrupt Timing Input Interrupt Block Diagram Matrix Example Input Interrupt Timing
Figure 3-2-6 Figure 3-2-7 Figure 4-1-1 Figure 4-1-2 Figure 4-1-3 Figure 4-1-4 Figure 4-1-5 Figure 4-1-6 Figure 4-1-7 Figure 4-1-8 Figure 4-1-9 Figure 4-1-10 Figure 4-1-11 Figure 4-1-12 Figure 4-1-13 Figure 4-1-14 Figure 4-1-15 Figure 4-1-16 Figure 4-1-17 Figure 4-1-18 Figure 4-1-19 Figure 4-1-20 Figure 4-2-1 Figure 4-2-2 Figure 4-2-3 Figure 4-2-4 Figure 4-2-5 Figure 4-2-6 Figure 4-2-7 Figure 4-2-8 Figure 4-3-1 Figure 4-3-2 Figure 4-3-3
Watchdog Timer Interrupt Block Diagram Watchdog Timer Interrupt Timing 8-bit Timer Block Diagram Timer Configuration 8-bit Event Counter Input Timing 8-bit Timer Output Interval Timer Timing Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Timer Block Diagram Event Counter Block Diagram Event Counter Timing (8-bit Timer) Clock Output Configuration Example (8-bit Timer) Clock Output Block Diagram (8-bit Timer) Clock Output Timing (8-bit Timer) Interval Timer Configuration Example (8-bit Timer) Interval Timer Block Diagram (8-bit Timer) Interval Timer Timing (8-bit Timer) 16-bit Timer Block Diagram One-phase Output Timing One-phase Output Timing (with Data Rewrite)
Figure 4-3-4 Figure 4-3-5 Figure 4-3-6 Figure 4-3-7 Figure 4-3-8 Figure 4-3-9 Figure 4-3-10 Figure 4-3-11 Figure 4-3-12 Figure 4-3-13 Figure 4-3-14 Figure 4-3-15 Figure 4-3-16 Figure 4-4-1 Figure 4-4-2 Figure 4-4-3 Figure 4-4-4 Figure 4-4-5 Figure 4-4-6 Figure 4-4-7 Figure 4-4-8 Figure 4-4-9 Figure 4-4-10 Figure 4-4-11 Figure 4-4-12 Figure 4-4-13 Figure 4-4-14 Figure 4-4-15 Figure 4-4-16 Figure 4-4-17 Figure 4-4-18 Figure 4-4-19 Figure 4-4-20 Figure 4-4-21
Two-phase Output Timing One-shot Pulse Output Timing External Control Timing Event Counter Input Timing Input Capture Timing Input Capture Timing Two-phase Encoder (4x) Timing Two-phase Encoder (1x) Timing Timer Block Diagram Timer Block Diagram Timer Block Diagram .100 Timer Block Diagram .100 Timer Block Diagram .100 Event Counter Block Diagram .101 Event Counter Timing (16-bit Timer) .103 One-phase Output Block Diagram (16-bit Timer) One-phase Output Timing (16-bit Timer) .107 One-phase Output Timing (16-bit Timer) (Dynamical Duty Change) Two-phase Output Block Diagram (16-bit Timer) Two-phase Output Timing (16-bit Timer) .113 Two-phase Output Timing (16-bit Timer) (Dynamical Duty Change) One-phase Capture Input Block Diagram (16-bit Timer) One-phase Capture Input Timing (16-bit Timer) .117 Two-phase Capture Input Block Diagram (16-bit Timer) Two-phase Capture Input Timing (16-bit Timer) .121 Two-phase Encoder Input (4x) Block Diagram (16-bit Timer) .122 Two-phase Encoder Input (4x) Configuration Example .122 Two-phase Encoder Input (4x) Configuration Example .122 Two-phase Encoder Input Timing (4x) (16-bit Timer) .124 Two-phase Encoder Input (1x) Block Diagram (16-bit Timer) .125 Two-phase Encoder Input (1x) Configuration Example .125 Two-phase Encoder Input (1x) Configuration Example .125 Two-phase Encoder Input Timing (1x) (16-bit Timer) .127 One-shot Pulse Output Block Diagram (16-bit Timer) .128
Figure 4-4-22 Figure 4-4-23 Figure 4-4-24 Figure 4-4-25 Figure 4-4-26 Figure 4-4-27 Figure 4-5-1 Figure 4-5-2 Figure 4-5-3 Figure 4-5-4 Figure 4-5-5 Figure 5-1-1 Figure 5-1-2 Figure 5-1-3 Figure 5-1-4 Figure 5-1-5 Figure 5-1-6 Figure 5-1-7 Figure 5-1-8 Figure 5-2-1 Figure 5-2-2 Figure 5-2-3 Figure 5-2-4 Figure 5-2-5 Figure 5-2-6 Figure 5-2-7 Figure 6-1-1 Figure 6-1-2 Figure 6-1-3 Figure 6-1-4 Figure 6-1-5 Figure 6-1-6
One-shot Pulse Output Timing (16-bit Timer) .130 External Count Direction Control Block Diagram (16-bit Timer) External Count Direction Control Configuration Example .131 External Count Direction Control Timing (16-bit Timer) .133 External Reset Control Block Diagram (16-bit Timer) .134 External Reset Control Timing (16-bit Timer) .136 24-bit Timer Block Diagram .137 Servo Timer Block Diagram .140 DRUM_PG, DRUM_FG Timing .141 CAP_FG Timing .142 Timer Mask Timing .142 Serial Interface Configuration .152 Synchronous Mode Connections .158 Asynchronous Mode Connections .158 Mode Connection .158 Asynchronous Serial Timing (Transmission) .159 Asynchronous Serial Timing (Reception) .159 Synchronous Serial Timing (Transmission) .160 Synchronous Serial Timing (Reception) .160 Asynchronous Transmission Block Diagram .161 Serial Asynchronous Transmission Timing .163 Clock Generation Synchronous Reception .164 Serial Clock Block Diagram .166 Serial Clock Timing .169 Master Transmission Timing (With ACK) .171 Master Reception Timing .173 Analog Interface Configuration .176 Analog Converter Timing .177 Single Channel/Single Conversion Timing .178 Multiple Channel/Single Conversion Timing .179 Single Channel/Continuous Conversion Timing .180 Multiple Channel/Continuous Conversion Timing .181
Figure 6-1-7 Figure 6-2-1 Figure 6-2-2 Figure 6-2-3 Figure 6-2-4 Figure 6-2-5 Figure 6-2-6 Figure 7-1-1 Figure 7-2-1 Figure 7-2-2 Figure 8-1-1 Figure 8-2-1 Figure 8-2-2 Figure 8-2-3 Figure 9-1-1 Figure 9-1-2 Figure 9-1-3 Figure 9-1-4 Figure 9-1-5 Figure 9-1-6 Figure 9-1-7 Figure 9-1-8 Figure 9-1-9 Figure 9-1-10 Figure 9-1-11 Figure 9-1-12 Figure 9-1-13
Converter Block Diagram .182 Analog Voltage Input Example .186 Single Channel Conversion Block Diagram .186 Single Channel Conversion Timing .187 3-channel Conversion Configuration .188 3-channel Conversion Block Diagram 3-channel Conversion Timing .190 Acquisition Timing .192 Serial Reception Block Diagram .197 Serial Reception Sequence .197 Port Configuration .202 General-purpose Port Setup Example .217 Basic Flowchart General-purpose Port Input .218 Basic Flowchart General-purpose Port Output .218 Voltage Level Timing Measurement .241 System Clock Timing .242 Reset Timing .242 Interrupt Signal Timing .242 Interrupt Signal Timing .242 Serial Interface Signal Timing (Synchronous Serial Transmission) Serial Interface Signal Timing (Synchronous Serial Reception) .243 Timer/Counter Signal Timing .243 Timer/Counter Signal Timing .243 Data Transfer Signal Timing (Read) 16-bit Width SRAM, 8-bit Width SRAM Data Transfer Signal Timing (Write) 16-bit Width SRAM, 8-bit Width SRAM Data Transfer Signal Timing (Read) 16-bit Width SRAM, 8-bit Width SRAM Data Transfer Signal Timing (Write) 16-bit Width SRAM, 8-bit Width SRAM
Figure 9-1-14 Figure 9-4-1 Figure 9-4-2 Figure 9-4-3 Figure 9-4-4 Figure 9-4-5 Figure 9-4-6 Figure 9-4-7 Figure 9-4-8 Figure 9-4-9 Figure 9-4-10 Figure 9-4-11 Figure 9-4-12 Figure 9-4-13
Data Transfer Signal Timing 16-bit Width, 8-bit Width Address/Data Multiplex Mode Flash EEPROM Memory Flash EEPROM Program Flow 8-bit Serial Interface Block Diagram Serial Writer Flash EEPROM Memory Space .421 Configuration During Serial Programming .423 System Configuration Onboard Serial Writer Target Board Serial Writer Connection .424 Timing Onboard Serial Programming Mode Load Program Start Flow .427 Reset Service Routine Flow .428 Interrupt Service Routine Flow Data Transfer Timing .429 Programming Flow .430
Tables
Table 1-1-1 Table 1-2-1 Table 1-3-1 Table 1-4-1 Table 2-1-1 Table 2-1-2 Table 2-1-3 Table 2-1-4 Table 2-1-5 Table 2-1-6 Table 2-1-7 Table 2-1-8 Table 2-1-9 Table 2-1-10 Table 3-1-1 Table 3-1-2 Table 3-1-3 Table 3-1-4 Table 3-1-5 Table 4-1-1 Table 4-1-2 Table 4-3-1 Table 4-3-2 Table 4-5-1 Table 5-1-1 Table 5-1-2 Table 5-1-3 Table 5-2-1 Table 6-1-1 Table 6-1-2
Memory Modes Basic Specifications Block Functions List Functions Mode Setting List Interface Control Registers Address/Data Multiplex Mode (16-bit Data Access) Address/Data Multiplex Mode (8-bit Data Access) Address/Data Separate Mode (16-bit Data Access) Address/Data Separate Mode (8-bit Data Access) Address/Data Separate Mode (16-bit PSRAM) Address/Data Separate Mode (8-bit PSRAM) Address/Data Separate Mode (16-bit DRAM) Address/Data Separate Mode (8-bit DRAM) Comparison MN1021617/F1617 MN102B00/MN102L00 Interrupt Vector Class Assignment Handler Preprocessing Handler Postprocessing List Interrupt Control Registers 8-bit Timer Functions List 8-bit Timer Control Registers 16-bit Timer Functions List 16-bit Timer Control Registers List 24-bit Timer Control Registers .140 Serial Interface Functions .153 List Serial Interface Control Registers Baud Rate Setting Example Asynchronous Mode Transfer Clock Setup Example Converter Functions .177 List Converter Control Registers
Table 7-1-1 Table 7-1-2 Table 8-1-1 Table 9-4-1
Functions .193 List Control Registers .196 List Port Control Registers .216 Clock Frequency .425
Chapter General Description
Chapter General Description
1-1-1
General Description
Introduction
16-bit MN102 series high-speed linear addressing version designs architecture C-language programming based detailed analysis embedded applications. This improves previous system architecture speed function meet requirements user systems including miniaturization power consumption.
This series adapts load/store architecture method computing within registers instead accumulator system computing within memory space previous series. basic instructions byte/one machine cycle. This reduces code size improves compiler efficiency. This series uses circuit designed submicron technology providing optimized hardware system power consumption. This series Mbytes linear address space develop highly efficient programs. optimized hardware architecture allows lower power consumption even large systems.
1-1-2
Features
This series contains flexible optimized hardware architecture well simple efficient instruction set. This allows economy speed. This section describes features this series CPU. High-speed Signal Processing
internal multiplier operates 16-bit x16-bit 32-bit single cycle. addition, hardware contains saturation calculator which must used signal processing increases signal processing speed.
Linear Addressing Large Systems
MN102H series contains Mbytes linear address space. does detect borders between address spaces, which provides effective development environment. hardware architecture also optimized large systems. memory divided into instruction areas data areas that operations share instructions.
MN1021617/F1617
Chapter General Description
Single-byte Basic Instruction Length
Conventional Register Assignment
MN102H series replaced general registers with eight internal registers divided four address registers (A0-A3) four data registers (D0-D3). register specification fields four bits less, code size basic instructions including register-to register operations load/store operations byte.
Register Specification Field
Register Specification Field
Register Assignement
High-speed Pipeline Processing
MN102H series executes instructions 3-stage pipeline: fetch, decode, execute. This allows MN102H series execute instructions single byte machine cycle with 40-MHz oscillator).
Machine Cycle
Instruction
Fetch
Decode Address calculation Execute
Instruction
Fetch
Decode Address calculation Execute
Simple Instruction
MN102H series uses instruction instructions, designed specially programming model embedded applications. shrink code size, instructions have variable length seven bytes. most frequently used instructions C-language compiler single byte.
High-speed Interrupt Response
MN102H series halts instructions execution even during execution instruction with long execution cycles. After interrupt occurs, program moves interrupt service routine within cycles less. MN102H series improves real-time control performance using interrupt handler which adjusts interrupt servicing speed.
Main Program
Instruction
Interrupt Service Routine
Instruction Interrupt Request
Instruction
Instruction
MN1021617/F1617
Chapter General Description
Flexible Interrupt Control Structure
interrupt controller supports maximum interrupt vectors them, interrupt vectors reserved nonmaskable interrupts). addition, groups four vectors assigned classes. Each class seven priority levels. This provides software design flexibility control. compatible with software from previous Panasonic peripheral modules.
High-speed, High-functional External Interface
MN102H series supports external interface functions including DMA, handshake function arbitration.
C-language Development Environment
MN102H series simple hardware optimized C-language programming highly efficient compiler. With this advantage, this series improves development environment C-language embedded applications without expanding program size. PanaXSeries development tools support MN102H series devices.
Outstanding Power Savings
MN102H series contains separate buses instructions, data peripheral functions, which distribute reduce load capacitance. This reduces overall power consumption. MN102H series also supports modes HALT STOP power savings.
PanaXSeries trademark Matsushita Electric Industrial Co., Ltd.
MN1021617/F1617
Chapter General Description
1-1-3
Overview
This section describes basic configuration functions MN1021617/F1617. Processor Status Word (PSW)
register contains operating result flags interrupt mask level flags.
Note Note
Note These bits change depending bits operation result. Note These bits change depending lower bits operation result. flag should before IM[2:0] flags changed.
Reset
Zero flag (ZF) lower bits operation result otherwise reset. Negative flag (NF) operation result otherwise reset. Carry flag (CF) operation resulted carry borrow otherwise reset.
Overflow flag (VF) operation causes sign change 16-bit signed number; otherwise reset. Extension zero flag (ZX) bits operation result otherwise reset. Extension negative flag (NX) operation result reset Extension carry flag (CX) operation resulted carry borrow MSB; otherwise reset.
Extension overflow flag (VX) operation causes sign change 24-bit signed number; otherwise reset. IM[2:0] indicate mask level (from interrupts that will accept from seven interrupt input pins. will accept interrupt higher level than indicated level here. Interrupt enable flag (IE) controls maskable interrupt enable. flag IE=1, reset IE=0. S[1:0] software control bits. These reserved Saturation flag controls whether performs saturation operation. When this execute saturate operation. When this operates normal operation. PXST instruction reserve meaning this next instruction.
Figure 1-1-1 Processor Status Word (PSW)
Please refer "9-5 MN102H00 series High-speed Linear Address Instruction Set" flags reflected instructions.
MN1021617/F1617
Chapter General Description
Internal Registers, Memory, Special Function Registers
Program Counter
program counter specifies 24-bit address program during execution.
Address Registers
address registers specify data location memory. four registers, assigned stack pointer.
Data Registers
data registers perform arithmetic logic operations. When byte-length (8-bit) word-length (16-bit) data transferred memory another register, instruction adds zero sign extension.
Multiplication/Division Register
multiplication/division register stores upper bits 32-bit product multiplication operations. division operations, this register stores upper bits 32-bit dividend before execution, 16-bit remainder quotient after execution.
Processor Status Word
Memory, Special Function Registers, Ports
Internal Control Registers Interrupt Control Registers Serial Interfacel Registers Converter Registers Timer/Counter Registers Memory Control Registers Port Registers This allocation example. Actual memory, peripheral functions, special function registers port allocation depends model. Memory (ROM, RAM), special function registers peripheral function control ports assigned same address space.
CPUM, EFCR, IAGR NMICR, xxICR SCCTRn, TRXBUFn, SCSTRn ANCTR, ANnBUF TMn, BCn, MEMMD PnOUT, PnIN, PnDIR
MN1021617/F1617
Address Space
memory contains Mbytes linear address space. instruction data areas separated, that internal RAM, special function registers internal peripheral functions allocated into first kbytes memory basic configuration. There three memory modes following depending models.
x'000000' x'008000' Internal x'009000' Reserved x'00FC00' x'010000'
External Memory
Control Registers
External Memory Program start address x'080000' Interrupt handler start address x'080008' x'0A0000' Reserved x'200000' x'080000' Internal
External Memory
x'FFFFFF'
Figure 1-1-2 Address Space (Memory Expansion Mode)
Table 1-1-1 Memory Modes
Mode Single-chip mode Memory expansion mode Processor mode bits None Address Width Capacity kbytes
kbytes kbytes kbyte Mbytes kbytes External Memory Access accessible Accessible MN1021617/F1617
Chapter General Description
Chapter General Description
Interrupt Controller
interrupt controller allocated outside core controls nonmaskable maskable interrupts except reset. Each class four interrupt vectors specifies seven priority levels.
Core
Maskable Interrupt Receive
Interrupt Enable
Nonmaskable Interrupt Receive
Reset Receive
Reset
Interrupt Controller
Nonmaskable interrupts Groups Nonmaskable Interrupt Controllers
Nonmaskable Interrupt Control Register (NMICR)
Interrupt Masking
(WDICR) (UNICR) (EIICR)
External input Watchdog timer Undefined instruction vector exists when interrupt occurs.
Group Maskable Interrupt Controller
Maskable Interrupt Control Register (xxICR)
Maskable interrupts Max. vectors External interrupts Peripheral interrupts
Group Maskable Interrupt Controller
Maskable Interrupt Control Register (xxICR)
hardware configuration interrupt controller depends model.
Figure 1-1-3 Interrupt Controller Configuration
checks processor status word determine whether interrupt request accepted not. interrupt accepted, automatic servicing hardware starts program counter pushed stack. Next, program moves interrupt, searches interrupt vector branches entry address interrupt service routine that interrupt.
Interrupt preprocessing
Push registers, branch entry address, etc. Main program x'080008' Interrupt service routine Resets interrupt vector beginning JMP, etc.
Hardware processing Push
Interrupt
Max. machine cycles machine cycles
Figure 1-1-4 Interrupt Servicing Sequence
MN1021617/F1617
Chapter General Description
Basic Specification
Table 1-2-1 Basic Specifications
Structure
Internal multiplier internal saturate operation calculator Load/store architecture Eight registers: Four 24-bit data registers Four 24-bit address registers Others: 24-bit program counter 16-bit processor status word 16-bit multiplication/division register
Instruction
instructions addressing modes 1-byte basic instruction length Code assignment: byte (basic) bytes (extension)
Performance
Maximum 20-MHz internal operating frequency with 40-MHz external oscillator MN1021617 Maximum 16-MHz internal operating frequency with 32-MHz external oscillator MN102F1617 Maximum 17.5-MHz internal operating frequency with 35-MHz external oscillator MN1021617 Instruction execution clock cycles: register-to-register operations, minimum cycle with 40-MHz oscillator) MN1021617 minimum cycle (62.5 with 32-MHz oscillator) MN102F1617 minimum cycle (57.1 with 35-MHz oscillator) MN1021617 branch operations, minimum cycles (100 with 40-MHz oscillator) MN1021617 minimum cycles (125 with 32-MHz oscillator) MN102F1617 minimum cycles (114.3 with 35-MHz oscillator) MN1021617 load/store operations, minimum cycle with 40-MHz oscillator) MN1021617 minimum cycle (62.5 with 32-MHz oscillator) MN102F1617 minimum cycle (57.1 with 35-MHz oscillator) MN1021617
Pipeline Address Space Interrupt
stage: instruction fetch, decode, execute 16-Mbyte linear address space Shared instruction/data space external nonmaskable interrupt maskable interrupts priority level settings
Low-power Mode Oscillation Frequency Timer/Counter
STOP, HALT (MN1021617) (MN102F1617) Sixteen 8-bit timers Cascading function (form 16-bit 32-bit timer) Timer output Internal clock source external clock source Serial Interface clock generation Start timing generation converter
MN1021617/F1617
Chapter General Description
Table 1-2-1 Basic Specifications Timer/Counter Five 16-bit timers (up/down counters) channels compare/capture registers Selectable internal external clock PWM/one-shot pulse output Two-phase encoder input method) 24-bit timer (down counter) Four channels capture registers channels compare registers 16-bit watchdog timer Four Channels Automatic transfer possible between memories, memory peripheral each interrupt vector. Transfer unit: byte word Transfer mode: single-chip burst mode Transfer addressing: source, destination pointer, increment 4096 words transferred Access 16-Mbyte address space Serial Interface Converter External Expansion Memory Interface Port Synchronous Interfaces shared UART/Synchronous/I2C (single master only) Interfaces 10-bit with channels channels (can used 8-bit) Automatic Scanning Address/data multiplex port function Address/data separate port function DRAM Interface (8-bit/16-bit width) PSRAM Interface (8-bit/16-bit width) Maximum ports single-chip mode Maximum ports address/data multiplex mode Maximum ports address/data separate mode Package 128-pin LQFP pitch square external dimension
MN1021617/F1617
Chapter General Description
Block Diagram
Address Registers Data Registers
Multiplier Program Counter Incrementer
Multiplication/Division Register
Clock Generator
Clock Source
Instruction Execution Controller Instruction Decoder
Instruction Queue Program Address Operand Address
Interrupt Controller Interrupt
Controller
Peripheral Execution
External Interface Internal Internal External Extension Internal Peripheral Functions
Figure 1-3-1 Block Diagram
MN1021617/F1617
Chapter General Description
Table 1-3-1 Block Functions
Blcok Clock Generator Program Counter
Function oscillation circuit connected external crystal supplies clock blocks CPU. program counter generates addresses instruction queues. Normally increments based sequencer indications, branch instructions interrupt acceptance, sets branch address operation result. instruction queue contains four bytes prefetched instructions. instruction decoder decodes contents instruction queue generates control signals needed instruction execution. instruction executes controlling each block CPU. instruction execution controller controls operations based results from instruction decoder interrupt requests. calculates operand addresses arithmetic operations, logic operations, shift operations, register relative indirect addressing, indexed addressing, register indirect addressing. multiplier calculates bits bits bits. These memory allocate program, data stack areas. address registers (An) store addresses memory accessed during data transfer. They also store base addresses register relative indirect addressing, indexed addressing register indirect addressing modes. data registers (Dn) store data transferred memory results arithmetic operations. They also store offset addresses indexed addressing register indirect addressing modes. multiplication/division register (MDR) stores data multiplication/division operations.
Instruction Queue Instruction Decoder
Instruction Execution Controller
Multiplier Internal Address Registers (An)
Operation Registers
Interrupt Controller Controller Internal Peripheral Function
processor status word register stores flags that indicate status interrupt controller operation results. interrupt controller detects interrupt requests from peripheral functions, requests move interrupt servicing routine. Controller controls connection between internal external bus. also contains arbitration function. MN1021617/F1617 contains internal peripheral functions including timers, serial interface converter. Internal peripheral functions vary depending chip models.
MN1021617/F1617
Chapter General Description
1-4-1
Description
Single-chip Mode
P45,A21 P44,A20 P43,A19 P42,A18 P41,A17 P40,A16 P37,A15 P36,A14 PC4,TM12O,TM8I,TM21IA P35,A13 P34,A12 P33,A11 P32,A10 P31,A9 PD7,RTP7 PD6,RTP6 P30,A8 P27,A7,KI7,TM17IB P26,A6,KI6 P25,A5,KI5 P24,A4,KI4 P23,A3,KI3 P22,A2,KI2 P21,A1,KI1 P20,A0,KI0 P56,CS3,BIBT1 P55,CAS,BIBT2 P54,RAS,RFSH P53,CS2,ALE
P46,A22,CS0 P47,A23,CS1 P00,AD0,D0 P01,AD1,D1 P02,AD2,D2 P03,AD3,D3 P04,AD4,D4 P05,AD5,D5 P06,AD6,D6 P07,AD7,D7 P10,AD8,D8 P11,AD9,D9 P12,AD10,D10 PD0,RTP0 PD1,RTP1 P13,AD11,D11 P14,AD12,D12 P15,AD13,D13 P16,AD14,D14 P17,AD15,D15 MODE0 MODE1 MODE2 PC3,TM10O,TM7I,TM21IR PC2,TM8O,TM6I PC1,TM6O,TM11I OSCI OSCO
MN1021617 (MN102F1617) (TOP VIEW)
P52,RE P51,WEH,WE P50,WEL PC7,BRACK PC6,BREQ P97,AN15 P96,AN14,TM15O P95,AN13,TM13O P94,AN12,TM11O AVDD Vref+ P93,AN11 P92,AN10 P91,AN9 P90,AN8 PD5,RTP5 PD4,RTP4 P87,AN7 P86,AN6 P85,AN5 P84,AN4 P83,AN3 P82,AN2 P81,AN1 P80,AN0 VrefAVSS PB5,SBT3,SCL3 PB4,SBO3,SDA3 PB3,SBI3
Unused pins require handling circuit (input pins connected VDD/VSS, output pins leave open, input/output pins connected VDD/VSS leave open depending direction setting).
P57,DMUX,BOSC PC5,NMI PC0,TM4O,TM10I P76,TM19IOA P60,IRQ0 P61,IRQ1,TM3I P62,IRQ2,TM16IA P63,IRQ3,TM16IB P64,IRQ4,TM17IA P65,IRQ5,TM18IA P66,IRQ6 P67,IRQ7,EXTDK P70,TM16OA P71,TM16OB,WDOUT PD2,RTP2 PD3,RTP3 P77,TM20IOA P72,TM17OA P73,TM17OB,STOP P74,TM18OA P75,TM18IOB,TM21ID PA0,SBI0 PA1,SBO0 PA2,SBT0 PA3,SBI1 PA4,SBO1,SDA1 PA5,SBT1,SCL1 PB0,SBI2,TM16IC PB1,SBO2,TM17IC PB2,SBT2,TM18IC
Figure 1-4-1 Configuration Single-chip Mode
MN1021617/F1617
Chapter General Description
1-4-2
Processor Mode with 16-bit Address/Data Multiplex Mode
AD10 PD0,RTP0 PD1,RTP1 AD11 AD12 AD13 AD14 AD15 MODE0 MODE1 MODE2 PC3,TM10O,TM7I,TM21IR PC2,TM8O,TM6I PC1,TM6O,TM11I OSCI OSCO
PC4,TM12O,TM8I,TM21IA PD7,RTP7 PD6,RTP6 P27,KI7,TM17IB P26,KI6 P25,KI5 P24,KI4 P23,KI3 P22,KI2 P21,KI1 P20,KI0 P56,CS3,BIBT1 P55,CAS,BIBT2 P54,RAS,RFSH
MN1021617 (MN102F1617) (TOP VIEW)
PC7,BRACK PC6,BREQ P97,AN15 P96,AN14,TM15O P95,AN13,TM13O P94,AN12,TM11O AVDD Vref+ P93,AN11 P92,AN10 P91,AN9 P90,AN8 PD5,RTP5 PD4,RTP4 P87,AN7 P86,AN6 P85,AN5 P84,AN4 P83,AN3 P82,AN2 P81,AN1 P80,AN0 VrefAVSS PB5,SBT3,SCL3 PB4,SBO3,SDA3 PB3,SBI3
Figure 1-4-2 Configuration Processor Mode with 16-bit Address/Data Multiplex Mode
Unused pins require handling circuit (input pins connected VDD/VSS, output pins leave open, input/output pins connected VDD/VSS leave open depending direction setting).
MN1021617/F1617
P57,DMUX,BOSC PC5,NMI PC0,TM4O,TM10I P76,TM19IOA P60,IRQ0 P61,IRQ1,TM3I P62,IRQ2,TM16IA P63,IRQ3,TM16IB P64,IRQ4,TM17IA P65,IRQ5,TM18IA P66,IRQ6 P67,IRQ7,EXTDK P70,TM16OA P71,TM16OB,WDOUT PD2,RTP2 PD3,RTP3 P77,TM20IOA P72,TM17OA P73,TM17OB,STOP P74,TM18OA P75,TM18IOB,TM21ID PA0,SBI0 PA1,SBO0 PA2,SBT0 PA3,SBI1 PA4,SBO1,SDA1 PA5,SBT1,SCL1 PB0,SBI2,TM16IC PB1,SBO2,TM17IC PB2,SBT2,TM18IC
Chapter General Description
1-4-3
Processor Mode with 8-bit Address/Data Multiplex Mode
PC4,TM12O,TM8I,TM21IA PD7,RTP7 PD6,RTP6 P27,KI7,TM17IB P26,KI6 P25,KI5 P24,KI4 P23,KI3 P22,KI2 P21,KI1 P20,KI0 P56,CS3,BIBT1 P55,CAS,BIBT2 P54,RAS,RFSH
AD10 PD0,RTP0 PD1,RTP1 AD11 AD12 AD13 AD14 AD15 MODE0 MODE1 MODE2 PC3,TM10O,TM7I,TM21IR PC2,TM8O,TM6I PC1,TM6O,TM11I OSCI OSCO
MN1021617 (MN102F1617) (TOP VIEW)
P51,WEH PC7,BRACK PC6,BREQ P97,AN15 P96,AN14,TM15O P95,AN13,TM13O P94,AN12,TM11O AVDD Vref+ P93,AN11 P92,AN10 P91,AN9 P90,AN8 PD5,RTP5 PD4,RTP4 P87,AN7 P86,AN6 P85,AN5 P84,AN4 P83,AN3 P82,AN2 P81,AN1 P80,AN0 VrefAVSS PB5,SBT3,SCL3 PB4,SBO3,SDA3 PB3,SBI3
Figure 1-4-3 Configuration Processor Mode with 8-bit Address/Data Multiplex Mode
Unused pins require handling circuit (input pins connected VDD/VSS, output pins leave open, input/output pins connected VDD/VSS leave open depending direction setting).
P57,DMUX,BOSC PC5,NMI PC0,TM4O,TM10I P76,TM19IOA P60,IRQ0 P61,IRQ1,TM3I P62,IRQ2,TM16IA P63,IRQ3,TM16IB P64,IRQ4,TM17IA P65,IRQ5,TM18IA P66,IRQ6 P67,IRQ7,EXTDK P70,TM16OA P71,TM16OB,WDOUT PD2,RTP2 PD3,RTP3 P77,TM20IOA P72,TM17OA P73,TM17OB,STOP P74,TM18OA P75,TM18IOB,TM21ID PA0,SBI0 PA1,SBO0 PA2,SBT0 PA3,SBI1 PA4,SBO1,SDA1 PA5,SBT1,SCL1 PB0,SBI2,TM16IC PB1,SBO2,TM17IC PB2,SBT2,TM18IC
MN1021617/F1617
Chapter General Description
1-4-4
Processor Mode with 16-bit Address/Data Separate Mode
PC4,TM12O,TM8I,TM21IA PD7,RTP7 PD6,RTP6 P55,CAS,BIBT2 P54,RAS,RFSH
PD0,RTP0 PD1,RTP1 MODE0 MODE1 MODE2 PC3,TM10O,TM7I,TM21IR PC2,TM8O,TM6I PC1,TM6O,TM11I OSCI OSCO
MN1021617 (MN102F1617) (TOP VIEW)
PC7,BRACK PC6,BREQ P97,AN15 P96,AN14,TM15O P95,AN13,TM13O P94,AN12,TM11O AVDD Vref+ P93,AN11 P92,AN10 P91,AN9 P90,AN8 PD5,RTP5 PD4,RTP4 P87,AN7 P86,AN6 P85,AN5 P84,AN4 P83,AN3 P82,AN2 P81,AN1 P80,AN0 VrefAVSS PB5,SBT3,SCL3 PB4,SBO3,SDA3 PB3,SBI3
Figure 1-4-4 Configuration Processor Mode with 16-bit Address/Data Separate Mode
Unused pins require handling circuit (input pins connected VDD/VSS, output pins leave open, input/output pins connected VDD/VSS leave open depending direction setting).
MN1021617/F1617
P57,DMUX,BOSC PC5,NMI PC0,TM4O,TM10I P76,TM19IOA P60,IRQ0 P61,IRQ1,TM3I P62,IRQ2,TM16IA P63,IRQ3,TM16IB P64,IRQ4,TM17IA P65,IRQ5,TM18IA P66,IRQ6 P67,IRQ7,EXTDK P70,TM16OA P71,TM16OB,WDOUT PD2,RTP2 PD3,RTP3 P77,TM20IOA P72,TM17OA P73,TM17OB,STOP P74,TM18OA P75,TM18IOB,TM21ID PA0,SBI0 PA1,SBO0 PA2,SBT0 PA3,SBI1 PA4,SBO1,SDA1 PA5,SBT1,SCL1 PB0,SBI2,TM16IC PB1,SBO2,TM17IC PB2,SBT2,TM18IC
Chapter General Description
1-4-5
Processor Mode with 8-bit Address/Data Separate Mode
PC4,TM12O,TM8I,TM21IA PD7,RTP7 PD6,RTP6 P55,CAS,BIBT2 P54,RAS,RFSH
P10,D8 P11,D9 P12,D10 PD0,RTP0 PD1,RTP1 P13,D11 P14,D12 P15,D13 P16,D14 P17,D15 MODE0 MODE1 MODE2 PC3,TM10O,TM7I,TM21IR PC2,TM8O,TM6I PC1,TM6O,TM11I OSCI OSCO
MN1021617 (MN102F1617) (TOP VIEW)
P51,WEH PC7,BRACK PC6,BREQ P97,AN15 P96,AN14,TM15O P95,AN13,TM13O P94,AN12,TM11O AVDD Vref+ P93,AN11 P92,AN10 P91,AN9 P90,AN8 PD5,RTP5 PD4,RTP4 P87,AN7 P86,AN6 P85,AN5 P84,AN4 P83,AN3 P82,AN2 P81,AN1 P80,AN0 VrefAVSS PB5,SBT3,SCL3 PB4,SBO3,SDA3 PB3,SBI3
Figure 1-4-5 Configuration Processor Mode with 8-bit Address/Data Separate Mode
Unused pins require handling circuit (input pins connected VDD/VSS, output pins leave open, input/output pins connected VDD/VSS leave open depending direction setting).
P57,DMUX,BOSC PC5,NMI PC0,TM4O,TM10I P76,TM19IOA P60,IRQ0 P61,IRQ1,TM3I P62,IRQ2,TM16IA P63,IRQ3,TM16IB P64,IRQ4,TM17IA P65,IRQ5,TM18IA P66,IRQ6 P67,IRQ7,EXTDK P70,TM16OA P71,TM16OB,WDOUT PD2,RTP2 PD3,RTP3 P77,TM20IOA P72,TM17OA P73,TM17OB,STOP P74,TM18OA P75,TM18IOB,TM21ID PA0,SBI0 PA1,SBO0 PA2,SBT0 PA3,SBI1 PA4,SBO1,SDA1 PA5,SBT1,SCL1 PB0,SBI2,TM16IC PB1,SBO2,TM17IC PB2,SBT2,TM18IC
MN1021617/F1617
1-4-6
Chapter General Description
Reset Schmitt Pull-up Single-chip mode HALT STOP BRACK Processor mode multiplex mode (16-bit) Processor mode multiplex mode (8-bit) Processor mode separated mode (16-bit) Processor mode separated mode (8-bit)
1-4-1 List Functions (1/3)
Input Level
Name
Dual Purpose
Function
Power supply (2.0
MN1021617/F1617
LVTTL LVTTL LVTTL LVTTL CMOS CMOS LVTTL LVTTL LVTTL with With With With With With With With With With With With AVDD AVSS Vref+ VrefRST MODE0 MODE1 MODE2 OSCI OSCO P07-00 AVDD AVSS Vref+ VrefRST MODE0 MODE1 MODE2 OSCI OSCO AD7-0 AVDD AVSS Vref+ VrefRST MODE0 MODE1 MODE2 OSCI OSCO AD7-0 AVDD AVSS Vref+ VrefRST MODE0 MODE1 MODE2 OSCI OSCO D7-0 AVDD AVSS Vref+ VrefRST MODE0 MODE1 MODE2 OSCI OSCO D7-0 AVDD AVSS Vref+ VrefRST MODE0 MODE1 MODE2 OSCI OSCO Unreflected Pull-up Pull-up AVDD AVSS Vref+ VrefRST MODE0 MODE1 MODE2 OSCI OSCO Unreflected Pull-up Pull-up AVDD AVSS Vref+ VrefRST MODE0 MODE1 MODE2 OSCI OSCO Unreflected Pull-up Pull-up LVTTL LVTTL LVTTL With With With With With With P17-10 AD15-8 AD15-8 D15-8 P17-10 Unreflected Pull-up Pull-up Unreflected Pull-up Pull-up Unreflected Pull-up Pull-up LVTTL LVTTL LVTTL With With With With With With P27-20 P27-20 P27-20 A7-A0 Undefined A7-A0 Undefined Unreflected Unreflected KI7-0 Unreflected Unreflected KI7-0 Unreflected Pull-up KI7-0 LVTTL LVTTL LVTTL With With With With With With TM17IB P37-30 TM17IB P37-30 TM17IB P37-30 TM17IB A15-8 Undefined TM17IB A15-8 Undefined TM17IB Unreflected Unreflected Unreflected Unreflected TM17IB Unreflected Pull-up
Power supply
List MN1021617/F1617 Pins
AVDD AVSS Vref+ VrefRST MODE0 MODE1 MODE2 OSCI OSCO P07-00
Power analog (VDD fixed) Power analog (VSS fixed) Standard power convertor (AVDD) Standard power convertor (AVSS) Reset input Mode setting input
P07-00 D7-0 AD7-0
40MHz-oscillation input 40MHz-oscillation output only Data input Memory address/Data multiplex
P17-10
P17-10 D15-8 AD15-8
only Data Memory address/Data multiplex
P27-20
P27-20 A7-A0 KI7-0
only Address interrupt input input)
P37-30
TM17IB P37-30 A15-8
16-bit timer input only Address
1-4-1 List Functions (2/3)
Reset Schmitt Pull-up Single-chip mode P47-40 A23-16 Undefined A23-16 Undefined A21-16 Undefined A21-16 Unreflected Undefined Unreflected Unreflected Unreflected Unreflected Pull-up
Processor mode multiplex mode (16-bit) Processor mode multiplex mode (8-bit) Processor mode separated mode (16-bit) Processor mode separated mode (8-bit)
Name HALT STOP BRACK LVTTL LVTTL With With With With
Input Level
Dual Purpose
Function
P47-40
P47-40 A23-16
only Address-bus
Unreflected Unreflected Unreflected Unreflected Unreflected Unreflected
P57-50
BOSC Unreflected IRQ7-0 Unreflected Unreflected IRQ7-0
P67-60
P57-50 BSTRE RFSH LCAS BIBT2 UCAS BIBT1 DMUX BOSC P67-60 IRQ7-0 LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With P57-50 P67-60 IRQ7-0 P57-54 BSTRE P67-60 IRQ7-0 P57-54 BSTRE P67-60 IRQ7-0 P57,55,54 BSTRE P67-60 IRQ7-0 P57,55,54 BSTRE P67-60 IRQ7-0 TM3I TM16IA TM16IB TM17IA TM18IA TM3I Pull-up Pull-up Pull-up Pull-up With With With With With With With With With With LVTTL LVTTL LVTTL LVTTL LVTTL
Chip select signal Chip-select signal only Memory write Memory write Memory write signal Memory read signal Memory read signal Chip select signal Address strobe signal signal Refresh signal signal LCAS signal Internal status signal Chip select signal UCAS signal Internal status signal Address switch signal Oscillator clock Input only External interrupt input
Pull-up Pull-up Unreflected Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up BIBT2 Pull-up Pull-up BIBT1 Pull-up BOSC Unreflected IRQ7-0 TM3I TM16IA TM16IB TM17IA TM18IA
TM31 TM16IA TM16IB TM17IA TM18IA
8-bit timer input 16-bit timer input 16-bit timer input 16-bit timer input 16-bit timer input
P77-70
Pull-up Unreflected TM16OA TM16OB Unreflected TM17OA TM17OB
Pull-up Unreflected Unreflected Unreflected Unreflected Unreflected Unreflected
Pull-up Unreflected TM16OA TM16OB Unreflected TM17OA TM17OB
Chapter General Description
MN1021617/F1617
LVTTL LVTTL With With P97-90
P87-80
EXTDK P77-70 TM16OA TM16OB WDOUT TM17OA TM17OB STOP TM18OA TM18IOB TM21ID TM19IOA TM20IOA P87-80 AN7-0 LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL With With With With With With With With With With With With With With With With P77-70 P87-80 P77-70 P87-80
Wait only 16-bit timer output 16-bit timer output Watchdog timer overflow signal 16-bit timer output 16-bit timer output Stop status signal 16-bit timer output 16-bit timer 24-bit timer input 16-bit timer 16-bit timer only conversion input
P77-70 P87-80
P77-70 P87-80
P77-70 P87-80
TM18OA TM18IOB TM21ID TM19IOA TM20IOA Unreflected AN7-0
Unreflected Unreflected Unreflected Unreflected Unreflected Unreflected
TM18OA TM18IOB TM21ID TM19IOA TM20IOA Unreflected AN7-0
P97-90 P97-90 P97-90 P97-90 Unreflected AN15-8 Unreflected Unreflected AN15-8
P97-90
P97-90 AN15-8
only conversion input
Chapter General Description
Reset Schmitt Pull-up Single-chip mode HALT STOP BRACK
Processor mode multiplex mode (16-bit) Processor mode multiplex mode (8-bit) Processor mode separated mode (16-bit) Processor mode separated mode (8-bit)
1-4-1 List Functions (3/3)
Input Level
Name
Dual Purpose
Function
MN1021617/F1617
Unreflected RTP7-0
PA5-A0
PB5-B0
PC7-0
TM11O TM4I TM13O TM2I TM15O TM19IB TM20IB Unreflected SBI0 SBO0 SBT0 SBI1 SBO1 SDA1 SBT1 SCL1 Unreflected SBI2 TM16IC SBO2 TM17IC SBT2 TM18IC SBI3 SBO3 SDA3 SBT3 SCL3 Unreflected TM4O TM10I TM6O TM11I TM8O TM6I TM10O TM7I TM21IR TM12O TM8I TM21IA
PD7-0
TM11O TM4I TM13O TM2I TM15O TM19IB TM20IB PA7-A0 SBI0 SBO0 SBT0 SBI1 SBO1 SDA1 SBT1 SCL1 PB7-B0 SBI2 TM16IC SBO2 TM17IC SBT2 TM18IC SBI3 SBO3 SDA3 SBT3 SCL3 PC7-0 TM4O TM10I TM6O TM11I TM8O TM6I TM10O TM7I TM21IR TM12O TM8I TM21IA BREQ BRACK PD7-0 RTP7-0 LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With With PA7-A0 PB7-B0 PC7-0 PD7-0 PA7-A0 PB7-B0 PC7-0 PD7-0 PA7-A0 PB7-B0 PC7-0 PD7-0 PA7-A0 PB7-B0 PC7-0 PD7-0 PA7-A0 PB7-B0 PC7-0 PD7-0 TM11O TM4I TM13O TM2I TM15O TM19IB TM20IB Unreflected SBI0 SBO0 SBT0 SBI1 SBO1 SDA1 SBT1 SCL1 Unreflected SBI2 TM16IC SBO2 TM17IC SBT2 TM18IC SBI3 SBO3 SDA3 SBT3 SCL3 Unreflected TM4O TM10I TM6O TM11I TM8O TM6I TM10O TM7I TM21IR TM12O TM8I TM21IA Unreflected RTP7-0 Unreflected TM4I Unreflected TM2I Unreflected Unreflected Unreflected Unreflected Unreflected TM10I Unreflected TM11I Unreflected TM6I Unreflected TM7I Unreflected TM8I Unreflected Unreflected
8-bit timer output 8-bit timer input 8-bit timer output 8-bit timer input 8-bit timer output 16-bit timer input 16-bit timer input only Serial data output Serial data output Serial clock Serial data input Serial data output I2Cdata Serial clock clock only Serial data input 16-bit timer input Serial data output 16-bit timer input Serial clock 16-bit timer input Serial data input Serial data output data Serial clock clock only 8-bit timer output 8-bit timer input 8-bit timer output 8-bit timer input 8-bit timer output 8-bit timer input 8-bit timer output 8-bit timer input 24-bit timer input 8-bit timer output 8-bit timer input 24-bit timer input Nonmaskable interrupt open request input open acknowledge output only 24-bit timer synchronous output
Chapter General Description
Connection Examples Power Pins, Oscillator Circuits, Reset Pins
Power Source AVDD
MN1021617 AVSS
When digital analog power supplies obtained from same source, connect each power supply power source.
Figure 1-4-6 Power Source Wiring Precaution
OSCI
OSCO
OSCI
OSCO
Ocillation Circuit
Note capacitance values vary depending crystal oscillator.
Figure 1-4-7 OSCI, OSCO Connection Example
Figure 1-4-8 Reset Connection Example
Connection Examples Reset Pins Internal Unused
When internal unused, cannot return normal operations even watchdog interrupt occurs because data cannot read from external memory external memory access setting written errors. Referring "Figure 1-4-9 Reset Connection Example make reset when watchdog interrupt occurs. When resets, functions port input pin. Therefore, needs selected WDOUT output watchdog interrupt reset.
<Examples Setup Program> input MOVB (P7DIR), x'FD', MOVB (P6MD), x'0040', MOVB (P7DIR), (P7DIR) (P6MD) (P7DIR)
WDOUT
output x'02',
MOVB
WDOUT (P71)
Figure 1-4-9 Reset Connection Example
MN1021617/F1617
Chapter General Description
1-4-7
MN1021617/F1617 External Dimension
Package Code: LQFP128-P-1818C
Body Material: Epoxy Resin, Lead Material: Lead Finish Method: Solder Plating
Figure 1-4-10 External Dimensions 128-pin LQFP
External dimensions subject change. Before using, please contact your nearest sales office latest product specifications.
MN1021617/F1617
Chapter Interface
Chapter Interface
2-1-1
Summary Interface
Overview
MN1021617/F1617 function expand memory external devices. Table 2-1-1 shows memory modes.
Selecting MODE2 MODE sets external connecting mode external data width processor mode. Selecting address/data output conditions corresponding pins P10MD register, P32MD register P4LMD register sets external connecting mode external data width memory expansion mode. However, setting bits[7:6] MEMMD2 register sets external data width address/data multiplex mode expansion mode.
Table 2-1-1 Mode Setting
Mode Single-chip mode Memory Expansion External Connecting Mode Address/data separate mode Address/data multiplex mode Processor mode Address/data separate mode Address/data multiplex mode External Data Width MODE2 MODE1 MODE0 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit Port Mode Registers Note Note Note Note Note Note Note Note
Note each mode register input output address/data control signal from single-chip mode using user program internal becuase starts single-chip mode after reset. Note Initialize setting input output address/data control signal after reset release.
Memory Expansion Mode
x'000000' x'000000'
Processor Mode
External Device
x'008000' x'009000' x'00FC00'
External Device
x'008000' x'009000' x'00FC00'
Internal (4096 bytes)
Internal (4096 bytes)
External Memory Space (CS0 output)
Peripheral Register
x'010000'
Peripheral Register
External Memory Space (CS0 output)
Reset Start x'010000' x'080000'
External Device
Reset Start x'080000'
Internal (128 kbytes)
x'0A0000' x'200000' x'400000' x'400000' x'800000' x'C00000'
External Device
External Device
x'800000' x'C00000'
External Memory Space (CS1 output) External Memory Space (CS2 output) External Memory Space (CS3 output)
External Memory Space (CS1 output) External Memory Space (CS2 output) External Memory Space (CS3 output)
x'FFFFFF'
space expansion possible.
x'FFFFFF'
space exapnsion possible.
Figure 2-1-1 Address Space
MN1021617/F1617
Chapter Interface
2-1-2
Control Registers
These registers control interface: external memory wait register (EXWMD), memory mode setup register (MEMMD1), memory mode setup register (MEMMD2), DRAM control register (DRAMMD1), DRAM control register (DRAMMD2).
EXWMD: x'00FF80'
EW33 EW32 EW31 EW30 EW23 EW22 EW21 EW20 EW13 EW12 EW11 EW10 EW03 EW02 EW01 EW00 Reset:
EW[03:00] EW[13:10] EW[23:20] EW[33:30]
number wait external memory space number wait external memory space number wait external memory space number wait external memory space
Please refer Figure 2-1-1 Address Space page address allocation external memory spaces.
Wait 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Cycle
wait cycle corresponds BOSC cycle. wait corresponds cycle instruction. With 40-MHz external oscillator, wait: wait:
Handshake access EXTDK
MN1021617/F1617
Chapter Interface
MEMMD1: x'00FF82'
EB31 EB30 EB21 EB20 EB11 EB10 EB01 EB00 BRS1 BRS0 BRC3 BRC2 BRC1 BRC0 IOW1 IOW0 Reset
IOW[1:0] Wait Setting Internal Space wait cycle wait cycles wait cycles wait cycles
Reserved Reserved EB[01:00] Width Setting External Memory Space
MODE2 MODE0 pins setup processor mode 8-bit width when MPX8 (memory expansion mode) 16-bit width when MPX16 (memory expansion mode)
8-bit width Reserved 8-bit width when high 16-bit width when
EB[11:10] Width Setting External Memory Space 16-bit width 8-bit width Reserved 8-bit width when high 16-bit width when
EB[21:20] Width Setting External Memory Space 16-bit width 8-bit width Reserved 8-bit width when high 16-bit width when
EB[31:30] Width Setting External Memory Space 16-bit width 8-bit width Reserved 8-bit width when high 16-bit width when
Please refer Figure 2-1-1 Memory Space page address allocation external memory spaces.
MN1021617/F1617
Chapter Interface
MEMMD2: x'00FF84'
REG3 REG2 REG1 REG0 WEG3 WEG2 WEG1 WEG0 OICK Reset
BST2 BST1 BST0
Reserved OICK Rising Edge Timing WEG[3:0] REG[3:0] Forward wait cycle Forward 0.75 wait cycle Clock Select Input clock signal from OSCO Input clock signal from OSCI (reserved) Maximum Width Setup (when address/data multiplex mode selected memory expansion mode) Reserved 16-bit width 8-bit width Reserved
WEG[3:0] WEH,WEL Rising Edge Timing External Memory Space Unchanged Forward cycle REG[3:0] Rising Edge Timing External Memory Space Unchanged Forward cycle
Setting flag changes from cycle 0.75 cycle.
MN1021617/F1617
Chapter Interface
DRAMMD1: x'00FF90'
ARE3 ARE2 ARE1 ARE0 MMD1 MMD0 ASFN SEL2 SEL1 SEL0 CAS2 CAS1 CAS0 RAS2 RAS1 RAS0 Reset
RAS[2:0] CAS[2:0] SEL[2:0] ASFN
Timing Setting RAS's Falling Edge beginning cycle beginning cycle beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles Timing Setting CAS's Falling Edge beginning cycle beginning cycle beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles Timing Setting SEL's Falling Edge beginning cycle beginning cycle beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles Shift Setting from Address Column Address Falling Edge shift Shift
internal signal. When falls, address output from pin-A8 shifts from column (when ASFN=1). MMD[1:0] Shift Size DRAM Address
MMD[1:0]
8-bit 9-bit 10-bit 11-bit
Shift Shift (A11) (A10) (Low) (Low) Shift Shift (A11) (A10) (A0) (Low) (A0)
Address
Column Address
ARE[3:0] DRAM (PSRAM) Operation External Memory Space 3-0* Disable Enable
Please refer Figure 2-1-1 Memory Space page address allocation external memory spaces.
MN1021617/F1617
Chapter Interface
DRAMMD2: x'00FF92'
PSON OERF RCY3 RCY2 RCY1 RCY0 RCS2 RCS1 RCS0 RRS2 RRS1 RRS0
Reset
RRS[2:0] RCS[2:0] RCY[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Others
Timing Setting RAS(RFSH)'s Falling Edge Refresh beginning cycle beginning cycle beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles Timing Setting CAS(CS)'s Falling Edge Refresh beginning cycle beginning cycle beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles beginning cycles Cycle Setting Refresh cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles DRAM (PSRAM) Refresh Enable Disable Enable
DRAM refreshed once when timer underflow interrupt generated. times/8 refresh interval 31.25 less.
OERF PSON Reserved MPXDLY
Refresh when PSRAM Selected refresh Refresh PSRAM Select Select PSRAM (Default) Select PSRAM Address/Data Shift Timing Mode Table 2-1-3 Table 2-1-4 Delay 0.25 cycle from cycle Table 2-1-3 Table 2-1-4
Table 2-1-2 List Interface Control Registers
Register EXWMD MEMMD1 MEMMD2 DRAMMD1 DRAMMD2 Address x'00FF80' x'00FF82' x'00FF84' x'00FF90' x'00FF92' Function External Memory Wait Register Memory Mode Setup Register Memory Mode Setup Register DRAM Control Register DRAM Control Register
MN1021617/F1617
Chapter Interface
2-1-3
Memory Connection Examples
MN1021617/F1617 connect SRAM, PSRAM, DRAM mask ROM. This section shows connection examples. Example SRAM (Mask ROM) Connection (16-bit Width)
MN1021617 SRAM (256 k*8bit) A18-A0 D7-D0 SRAM (256K*8bit) A18-A0 D7-D0
(P46)
necessary connect when connecting mask ROM.
(P52) (P51) (P50)
A19-A1 D15-D8 D7-D0
Figure 2-1-2 SRAM Connection Example (16-bit Width)
EXWMD
MEMMD1
DRAMMD1
P10MD
P32MD
P4MD
P5MD
MN1021617/F1617
Chapter Interface
Example SRAM (Mask ROM) Connection (8-bit Width)
MN1021617 SRAM (256 k*8bit) A18-A0 D7-D0
necessary connect when connecting mask ROM.
(P46)
A18-A0 D7-D0
(P52) (P50)
Figure 2-1-3 SRAM Connection Example (8-bit Width)
EXWMD
MEMMD1
DRAMMD1
P10MD
P32MD
P4MD
P5MD
MN1021617/F1617
Chapter Interface
Example PSRAM Connection With RFSH (16-bit Width)
MN1021617 PSRAM (256 k*8bit) A18-A0 D7-D0 RFSH PSRAM (256 k*8bit) A18-A0 D7-D0 RFSH
(P55)
MN1021617/F1617 cannot connect DRAM PSRAM simultaneously.
(P52) (P51) (P50) (P54)
A19-A1 D15-D8 D7-D0 RFSH
Figure 2-1-4 PSRAM Connection Example (16-bit Width)
EXWMD
MEMMD1
MEMMD2
ASEN
DRAMMD1
DRAMMD2
P10MD
P32MD
P4MD
P5MD
MN1021617/F1617
Chapter Interface
Example PSRAM Connection Refresh) (8-bit Width)
MN1021617 PSRAM (256 k*8bit) A18-A0 D7-D0
MN1021617/F1617 cannot connect DRAM PSRAM simultaneously.
(P55)
A18-A0 D7-D0 RFSH
(P54) (P50)
Figure 2-1-5 PSRAM Connection Example (8-bit Width)
EXWMD
MEMMD1
MEMMD2
DRAMMD1
DRAMMD2
P10MD
P32MD
P4MD
P5MD
MN1021617/F1617
Chapter Interface
Example DRAM (2WE Method) Connection (16-bit Width)
MN1021617
DRAM
MN41V4170 (256 k*16bit) D15-D8 D7-D0 Row=10 Colum=8
MN1021617/F1617 cannot connect DRAM PSRAM simultaneously.
(P54) (P55) (P52) (P51) (P50)
D15-D8 D7-D0
Figure 2-1-6 DRAM (2WE Method) Connection Example (16-bit Width)
EXWMD
MEMMD1
MEMMD2
DRAMMD1
DRAMMD2
P10MD
P32MD
P4MD
P5MD
MN1021617/F1617
Chapter Interface
Example DRAM Connection (8-bit Width)
MN1021617
DRAM
MN41V4800 (512 k*8bit) D7-0 Row=10 Colum=9
D7-0
(P54) (P55) (P52) (P50)
MN1021617/F1617 cannot connect DRAM PSRAM simultaneously.
Figure 2-1-7 DRAM Connection Example (8-bit Width)
EXWMD
MEMMD1
MEMMD2
DRAMMD1
DRAMMD2
P10MD
P32MD
P4MD
P5MD
MN1021617/F1617
Chapter Interface
2-1-4
Access External Memory
MN1021617/F1617 access external memory. external memory divided into four areas. When MN1021617/F1617 accesses each area, chip select signal output from corresponded (n=0 addition, number wait cycles width each area.
clock output from BOSC base clock external access. address signals, data signals each control signal output synchronizing with BOSC. frequency BOSC clock same with frequency oscillation clock input from OSCI pin. example, BOSC frequency becomes with external oscillator. (However, clock input from OSCI BOSC clock have phase difference. BIBT2 clock BIBT1 clock internal clock synchronizing with BOSC clock indicate memory access cycles. During memory access, BIBT2 clock becomes high then BIBT1 clock becomes high. When wait cycle inserted, high level length BIBT1 clock extended. When wait cycle set, high level cycle BIBT2 BIBT1 BOSC cycle. cycle needed access BOSC cycles.
BOSC BIBT2 BIBT1 Access cycle
Figure 2-1-8 External Access wait)
When wait cycle (the valid range cycle cycles), high level cycle BIBT1 extened BOSC clock cycle each wait cycle. When wait cycle set, cycle needed access BOSC cycles.
BOSC BIBT2 BIBT1 Access cycle
Figure 2-1-9 External Access (0.5 wait cycle)
MN1021617/F1617
Chapter Interface
Table 2-1-3 Address/Data Multiplex Mode (16-bit Data Access)
length wait cycle 0.5-cycle units.
Wait
BOSC
Wait
Base Clock
BIBT2 BIBT1 A23-A16
A23-A16 A15-A0 A23-A16 A15-A0 D15-D0 A23-A16 A15-A0 A23-A16 A15-A0 A15-A0 A23-A16 D15-D0 A23-A16 A15-A0
16-bit Data Read
(The selects necessary data H-side L-side under 8-bit width.)
AD15-AD0
A23-A16 AD15-AD0
A23-A16 A15-A0 A23-A16 A15-A0 D15-D0 A23-A16 A15-A0 A23-A16 A15-A0 A15-A0 A23-A16 D15-D0 A23-A16 A15-A0
16-bit Data Write
A23-A16 AD15-AD0
A23-A16 A15-A0 A23-A16 A15-A0 D15-D0 A23-A16 A15-A0 A23-A16 A15-A0 A15-A0 A23-A16 D15-D0 D15-D8 Valid Output A23-A16 A15-A0
8-bit H-side Data Write
A23-A16 AD15-AD0
A23-A16 A15-A0
D15-D8 Valid Output
A23-A16
A23-A16
A23-A16 A15-A0 A15-A0
A23-A16 D15-D0 D7-D0 Valid Output
A23-A16 A15-A0
8-bit L-side Data Write
A23-A16 AD15-AD0
A23-A16 A15-A0
A15-A0 D15-D0 A15-A0 D7-D0 Valid Output
Hold last output address
A23-A16 A15-A0
Hold last output address
Access
external access, internal access, internal access) (Internal peripheral register access)
External Wait
EXTDK
next don't care Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z wait wait next don't care
A23-A16 AD15-AD0
A23-A16 A15-A0
A23-A16 A15-A0
Request
BREQ BRACK
MN1021617/F1617
Chapter Interface
Table 2-1-4 Address/Data Multiplex Mode (8-bit Data Access)
length wait cycle 0.5-cycle units.
Wait BOSC Base Clock BIBT2 BIBT1 A23-A8 8-bit Data Read AD7-AD0 A23-A8 AD7-AD0 8-bit Data Write general-purpose port 8-bit width mode.
A23-A8 A7-A0 A23-A8 A7-A0 D7-D0 A23-A8 A7-A0 A23-A8 A7-A0 A7-A0 A23-A8 A7-A0 A23-A8 A7-A0 D7-D0 A23-A8 A7-A0 A23-A8 A7-A0 A7-A0
Wait
A23-A8 D7-D0
A23-A8 A7-A0
A23-A8 D7-D0
A23-8 A7-0
8-bit H-side Data Write
(N/A)
(N/A)
8-bit L-side Data Write
(N/A)
(N/A)
A23-A8 A7-A0 Hold last output address. A23-A8 A7-A0 Hold last output address.
A23-A8 AD7-AD0 Access
external access, internal access, internal access) (Internal peripheral register access)
External Wait
EXTDK
next don't care Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z wait wait next don't care
A23-A8 AD7-AD0 Request BREQ BRACK
A23-A8 A7-A0
A23-A8 A7-A0
MN1021617/F1617
Chapter Interface
Table 2-1-5 Address/Data Separate Mode (16-bit Data Access)
length wait cycle 0.5-cycle units.
Wait BOSC BIBT2 BIBT1 CS3-CS0 16-bit Data Read
(The selects necessary data H-side L-side
Wait
Base Clock
A21-A0 D15-D0 CS3-CS0 A21-A0
A21-A0
A21-A0 D15-D0
A21-A0
A21-A0
A21-A0 D15-D0
A21-A0
under 8-bit width.)
A21-A0
A21-A0 D15-D0
A21-A0
A21-A0
A21-A0 D15-D0
A21-A0
16-bit Data Write
D15-D0 CS3-CS0 A21-A0
A21-A0
A21-A0 D15-D8
A21-A0
A21-A0
A21-A0 D15-D8
A21-A0
8-bit H-side Data Write
D15-D0 CS3-CS0 A21-A0
A21-A0
A21-A0 D7-D0
A21-A0
A21-A0
A21-A0 D7-D0
A21-A0
8-bit L-side Data Write
D15-D0 CS3-CS0 A21-A0 D15-D0
A21-A0
Hold last output address.
Hold last output address.
Access
external access, internal access, internal access) (Internal peripheral register access)
External Wait
EXTDK
next don't care Hi-Z
A21-A0
wait
wait
next
don't care
CS3-CS0 A21-A0 D15-D0 Request BREQ BRACK
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
A21-A0
MN1021617/F1617
Chapter Interface
Table 2-1-6 Address/Data Separate Mode (8-bit Data Access)
length wait cycle 0.5-cycle units.
Wait BOSC BIBT2 BIBT1 CS3-CS0 A21-A0 8-bit Data Read D7-D0 CS3-CS0 A21-A0 8-bit Data Write D7-D0
general-purpose port 8-bit width mode.
A21-A0 A21-A0 D7-D0 A21-A0 A21-A0 A21-A0 A21-A0 D7-D0 A21-A0 A21-A0
Wait
Base Clock
A21-A0 D7-D0
A21-0
A21-A0 D7-D0
A21-A0
(N/A)
(N/A)
(N/A)
(N/A)
CS3-CS0 A21-A0 D7-D0 Access
external access, internal access, internal access) (Internal peripheral register access) A21-A0 Hold last output address. Hold last output address.
External Wait
EXTDK
next don't care Hi-Z
A21-A0
wait
wait
next
don't care
CS3-CS0 A21-A0 D7-D0 Request BREQ BRACK
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
A21-A0
MN1021617/F1617
Chapter Interface
Table 2-1-7 Address/Data Separate Mode (16-bit PSRAM)
length wait cycle 0.5-cycle units.
Wait BOSC BIBT2 BIBT1 CS(P55) 16-bit Data Read
(The selects necessary data H-side L-side
Waits
Base Clock
A21-A0 D15-D0 RFSH (P54) CS(P55)
A21-A0
A21-A0 D15-D0
A21-A0
A21-A0 D15-D0
under 8-bit width.)
16-bit Data Write
(The outputs necessary signal H-side L-side under 8-bit width.)
A21-A0 D15-D0 RFSH (P54)
A21-A0
A21-A0 D15-D0
A21-A0
A21-A0 D15-D0
number wait cycles falling timing BOSC unit setting register.
Wait BOSC BIBT2 BIBT1 CS(P55) A21-A0 D15-D0 Access RFSH (P54)
external access, internal access, internal access) A21-A0
Wait
Base Clock
A21-A0
(Internal peripheral register access)
CS(P55) A21-A0 D15-D0 Refresh Request RFSH BREQ BRACK
A21-A0
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Undefined Undefined Undefined A21-A0 A21-A0
Refresh)
MN1021617/F1617
Chapter Interface
Table 2-1-8 Address/Data Separate Mode (8-bit PSRAM)
length wait cycle 0.5-cycle units.
Wait BOSC Base Clock BIBT2 BIBT1 CS(P55) A21-A0 D15-D0 8-bit Data Read RFSH (P54) CS(P55) A21-A0 D15-D0 8-bit Data Write RFSH (P54)
A21-A0 A21-A0 D7-D0 A21-A0 A21-A0 D7-D0 A21-A0
Waits
A21-A0 D7-D0
A21-A0
A21-A0 D7-D0
number wait cycles falling timing BOSC unit setting register.
Wait BOSC BIBT2 BIBT1 CS(P55) A21-A0 D15-D0 Access RFSH (P54)
external access, internal access, internal access) A21-A0
Wait
Base Clock
A21-A0
(Internal peripheral register access)
CS(P55) A21-A0 D7-D0 Refresh Request RFSH BREQ BRACK
A21-A0
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Undefined Undefined Undefined A21-A0 A21-A0
Refresh)
MN1021617/F1617
Chapter Interface
Table 2-1-9 Address/Data Separate Mode (16-bit DRAM)
length wait cycle 0.5-cycle units.
Wait BOSC BIBT2 BIBT1 A22-A8 16-bit Data Read
(The selects necessary data H-side L-side COLUMN D15-D0
Waits
Base Clock
COLUMN D15-D0
D15-D0 OE(RE)
under 8-bit width.)
A22-A8 16-bit Data Write
(The outputs necessary signal H-side L-side under 8-bit width.)
COLUMN D15-D0
COLUMN D15-D0
D15-D0 OE(RE)
number wait cycles, falling timing CAS, timing Address switch BOSC unit setting register.
Wait BOSC BIBT2 BIBT1 A22-A8 D15-D0 Access OE(RE)
external access, internal access, internal access)
Wait
Base Clock
A22-A8
A22-A8
(Internal peripheral register access)
A22-A8 D15-D0 Refresh Request OE(RE) BREQ BRACK
A22-A8
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
A22-A8
A22-A8
A22-A8
A22-A8
Undefined Undefined Undefined
Auto Refresh)
cycle needed delayexternally hold setup time COLUMN address.
MN1021617/F1617
Chapter Interface
Table 2-1-10 Address/Data Separate Mode (8-bit DRAM)
length wait cycle 0.5-cycle units.
Wait BOSC Base Clock BIBT2 BIBT1 A22-A8 D7-D0 8-bit Data Read OE(RE)
COLUMN D7-D0
Waits
COLUMN D7-D0
A22-A8 D7-D0 8-bit Data Write OE(RE)
COLUMN D7-D0
COLUMN D7-D0
number wait cycles, falling timing CAS, timing Address switch BOSC unit setting register.
Wait BOSC BIBT2 BIBT1 A22-A8 D7-D0 Access OE(RE)
external access, internal access, internal access)
Wait
Base Clock
A22-A8
A22-8
(Internal peripheral register access)
A22-A8 D7-D0 Refresh Request OE(RE) BREQ BRACK
A22-A8
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
A22-A8
A22-A8
A22-A8
A22-8
Undefined Undefined Undefined
Auto Refresh)
cycle needed delayexternally hold setup time COLUMN address.
MN1021617/F1617
Chapter Interface
2-1-5
Each Mode Activation Sequence
This section describes activation sequence state singlechip mode, memory expansion mode processor mode after power turns activation sequences states mask version (MN1021617) same those flash version (MN102F1617).
Single-chip Mode
State
Undefined
External oscillation clock cycle more Wait Oscillation Stability
ports input
Power
Self-excited Oscillation Start external oscillation starts supplying clock from external device CPU.
level
high level
Fetch instruction x'80000' Internal ROM.
Hereafter, execute programs
Memory Expansion Mode
State
Undefined
External oscillation clock cycle more
ports input
Wait Oscillation Stability
Valid address pins, data pins control signal pins (Note)
Power
Self-excited Oscillation Start level external oscillation starts supplying clock from external device CPU.
high level
Fetch instruction x'80000' Internal ROM.
Switch address pins, data pins control signal pins needed using program.
Hereafter, execute programs
Processor Mode
Valid address pins, data pins control signal pins (Note) Other ports undefined
External oscillation clock cycle more
State
ports except address pins, data pins control signal pins input
Wait Oscillation Stability
Power
Self-excited Oscillation Start level external oscillation starts supplying clock from external device CPU.
Hereafter, execute programs
high level
Fetch instruction x'80000' External ROM.
(Note) pin, pin, high level. initial values address pins data pins undefined.
Figure 2-1-10 Each Mode Activation Sequence
MN1021617/F1617
Chapter Interface
MN1021617/F1617
Chapter Interrupts
Chapter Interrupts
3-1-1
Interrupt Groups
Overview
most important factor real time control fast program moves interrupt handler processing. MN1021617/ F1617 improves interrupt response aborting instructions, including multiply divide instruction, which require multiple clock cycles. aborted instruction executed once again after returned from interrupt service routine.
This section describes overview interrupt system. MN1021617/F1617 contains interrupt groups. Each interrupt group controls interrupts. interrupt generated speedily because interrupt vector assigned each interrupt group. Interrupt groups classified into classes, which interrupt level. interrupts from peripheral circuits (such timers) external pins, except reset interrupts, registered into interrupt group controller. Once interrupts registered, interrupt requests sent according interrupt priority level (level interrupt group controller. Groups interrupts system. Table 3-1-1 shows comparison between this series previous 16-bit series.
Table 3-1-1 Comparison MN1021617/F1617 MN102B00/MN102L00
Parameters Interrupt Groups (IAGR group numbers) Interrupt Response Time Interrupt Level Setup Software Compatibility MN102B00/MN102L00 vectors group (separated interrupt service routine) Good vectors level MN102H55D/55G/F55G vector group (Generated group number each interrupt) Excellent vectors level Easily modified
MN1021617/F1617 five external interrupt pins eight interrupt pins. EXTMD register, KIMD register KICTR register interrupt conditions (positive edge, negative edge, both edges level).
MN1021617/F1617
Chapter Interrupts
KIMD Edge/Level Edge/Level Edge/Level MASK MASK MASK
KICTR Interrupt Interrupt Arbitration
EXTMD IRQ0 IRQ1 IRQ7 Internal Interrupt Edge/Level Edge/Level Edge/Level
Figure 3-1-1 Interrupt Controller Block Diagram
MN1021617/F1617
Chapter Interrupts
Table 3-1-2 Interrupt Vector Class Assignment
Register Address 00FC40[R/W] 00FC42[R/W] 00FC44[R/W] 00FC46[R/W] 00FC48[R/W] 00FC4A[R/W] 00FC4C[R/W] 00FC4E[R/W] 00FC50[R/W] 00FC52[R/W] 00FC54[R/W] 00FC56[R/W] 00FC58[R/W] 00FC5A[R/W] 00FC5C[R/W] 00FC5E[R/W] 00FC60[R/W] 00FC62[R/W] 00FC64[R/W] 00FC66[R/W] 00FC68[R/W] 00FC6A[R/W] 00FC6C[R/W] 00FC6E[R/W] 00FC70[R/W] 00FC72[R/W] 00FC74[R/W] 00FC76[R/W] 00FC78[R/W] 00FC7A[R/W] 00FC7C[R/W] 00FC7E[R/W] 00FC80[R/W] 00FC82[R/W] 00FC84[R/W] 00FC86[R/W] 00FC88[R/W] 00FC8A[R/W] 00FC8C[R/W] 00FC8E[R/W] 00FC90[R/W] 00FC92[R/W] 00FC94[R/W] 00FC96[R/W] 00FC98[R/W] 00FC9A[R/W] 00FC9C[R/W] 00FC9E[R/W] 00FCA0[R/W] 00FCA2[R/W] 00FCA4[R/W] 00FCA6[R/W] 00FCA8[R/W] 00FCAA[R/W] 00FCAC[R/W] 00FCAE[R/W]
Group GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP GROUP
Interrupt Vector mascable Watchdog Undefined instruction Error interrupt External Interrupt External Interrupt Timer underflow Timer interrupt External interrupt External interrupt Timer underflow Timer underflow External interrupt External interrupt Serial transmission Serial reception External interrupt Timer interrupt Timer interrupt Timer interrupt External interrupt Timer interrupt Timer interrupt Timer interrupt External interrupt Timer underflow Timer interrupt Timer interrupt Serial transmission Serial reception Serial transmission Serial reception conversion Timer underflow Serial transmission Serial reception ATC0 transfer ATC1 transfer ATC2 transfer ATC3 transfer Timer underflow Timer underflow Timer underflow Timer underflow Timer underflow Timer underflow Timer interrupt Timer interrupt Timer underflow Timer underflow Timer interrupt Timer interrupt Timer interrupt Timer interrupt Timer interrupt Timer interrupt
Class
MN102H00 Core
CLASS
Level
CLASS
CLASS
CLASS
CLASS
CLASS
CLASS
CLASS
CLASS
CLASS
CLASS
CLASS
CLASS
CLASS
MN1021617/F1617
Chapter Interrupts
Program
Interrupt
Address 80008
Handler (preprocessing)
max. cycles
cycles
machine cycles
Interrupt service beginning routine (included cycle shown left)
Release interrupt request
Handler cles) (postprocessing)
Table 3-1-3 Handler Preprocessing
Sequence Push register movx Assembler (A3) (FC0E), BASE, (D0, A0), (A0) Byte Cycle
register
Figure 3-1-2 Interrupt Servicing Time
Read group number
Generate first address interrupt service routine
Branch
Total
Table 3-1-4 Handler Postprocessing Sequence register movx Assembler (A3), A3), Byte Cycle
Total
MN1021617/F1617
Chapter Interrupts
3-1-2
Control Registers
These registers control interrupt function: interrupt accept group register (IAGR), interrupt condition setup register (EXTMD), external interrupt condition setup register (KIMD), external interrupt enable register (KICTR).
CLASS (System Interrupt)
Nonmaskable interrupt Watchdog overflow Undefined instruction
NMICR WDICR UNICR EIICR
Interrupt detect flag Interrupt undetected Interrupt detected
CLASS 1~13
Interrupt arbitriation (error interrupt)
XnICH
External interrupt
Timer interrupt Serial interrupt transfer interrupt conversion interrupt interrupt
Interrupt priority level LV[2:0]
Interrupt enable flag (IE) Disable Enable
XnICL
Some registers have flags. These bits read
Interrupt detect flag (ID) Interrupt request flag (IR) Interrupt undetected interrupt requested Interrupt detected Interrupt requested
following example setting interrupt level (LV) interrupt enable (IE) interrupt control register (XnICH). Interrupts must disabled during this routine. 0xf7ff,psw (XnICH) 0x0800, Clear flag Inserted ensure that XnICH accessible after clearing flag completely Write LV/IE flag
MN1021617/F1617
Chapter Interrupts
program does need clear flag disable interrupts during interrupt servicing, since unless flag set. instructions instructions except those which write flag flags XnICH register. instructions inserted example keep minimum number cycles change flag. More than instructions inserted.
IAGR: x'00FC0E'
Reset
Group number
EXTMD: x'00FCF8
Reset
IQ0TG[1:0] Interrupt trigger condition IRQ0 IQ1TG[1:0] Interrupt trigger condition IRQ1 IQ2TG[1:0] Interrupt trigger condition IRQ2 IQ3TG[1:0] Interrupt trigger condition IRQ3 IQ4TG[1:0] Interrupt trigger condition IRQ4 IQ5TG[1:0] Interrupt trigger condition IRQ5 IQ6TG[1:0] Interrupt trigger condition IRQ6 IQ7TG[1:0] Interrupt trigger condition IRQ7 level Both edges Negative edge Positive edge
KIMD: x'00FCFA'
Reset
KI0TG[1:0] Interrupt trigger condition KI1TG[1:0] Interrupt trigger condition KI2TG[1:0] Interrupt trigger condition KI3TG[1:0] Interrupt trigger condition KI4TG[1:0] Interrupt trigger condition KI5TG[1:0] Interrupt trigger condition KI6TG[1:0] Interrupt trigger condition KI7TG[1:0] Interrupt trigger condition level Both edges Negative edge Positive edge
MN1021617/F1617
Chapter Interrupts
KEYCTR: x'00FCB4'
Reset
KI0EN KI1EN KI2EN KI3EN KI4EN KI5EN KI6EN KI7EN
interrupt trigger condition interrupt trigger condition interrupt trigger condition interrupt trigger condition interrupt trigger condition interrupt trigger condition interrupt trigger condition interrupt trigger condition
Table 3-1-5 List Interrupt Control Registers
Register IARG NMICR WDICR UNICR EIICR EXTMD IQ0ICL IQ0ICH IQ1ICL IQ1ICH IQ2ICL IQ2ICH IQ3ICL IQ3ICH IQ4ICL IQ4ICH IQ5ICL IQ5ICH IQ6ICL IQ6ICH IQ7ICL IQ7ICH TM4ICL TM4ICH TM5ICL TM5ICH TM6ICL TM6ICH TM7ICL TM7ICH Address x'00FC0E' x'00FC40' x'00FC42' x'00FC44' x'00FC46' x'00FCF8' x'00FC48' x'00FC49' x'00FC4A' x'00FC4B' x'00FC50' x'00FC51' x'00FC52' x'00FC53' x'00FC58' x'00FC59' x'00FC5A' x'00FC5B' x'00FC60' x'00FC61' x'00FC68' x'00FC69' x'00FC54' x'00FC55' x'00FC56' x'00FC57' x'00FC72' x'00FC73' x'00FC82' x'00FC83' Function Interrupt Accepted Group Number Register Nonmaskable Interrupt Control Register Watchdog Interrupt Control Register Undefined Instruction Interrupt Control Register Error Interrupt Control Register External Interrupt Condition Setup Register External Interrupt Control Register External Interrupt Control Register External Interrupt Control Register External Interrupt Control Register External Interrupt Control Register External Interrupt Control Register External Interrupt Control Register External Interrupt Control Register External Interrupt Control Register External Interrupt Control Register External Interrupt Control Register External Interrupt Control Register External Interrupt Control Register External Interrupt Control Register External Interrupt Control Register External Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register
MN1021617/F1617
Chapter Interrupts
TM8ICL TM8ICH TM9ICL TM9ICH TM10ICL TM10ICH TM11ICL TM11ICH TM12ICL TM12ICH TM13ICL TM13ICH TM14ICL TM14ICH TM15ICL TM15ICH TM16UICL TM16UICH TM16AICL TM16AICH TM16BICL TM16BICH TM17UICL TM171UICH TM17AICL TM17AICH TM17BICL TM17BICH TM18AICL TM18AICH TM18BICL TM18BICH TM19AICL TM19AICH TM19BICL TM19BICH TM20AICL TM20AICH TM20BICL TM20BICH TM21AICL TM21AICH TM21BICL TM21BICH TM21DICL TM21DICH
x'00FC90' x'00FC91' x'00FC92' x'00FC93' x'00FC94' x'00FC95' x'00FC96' x'00FC97' x'00FC98' x'00FC99' x'00FC9A' x'00FC9B' x'00FCA0' x'00FCA1' x'00FCA2' x'00FCA3' x'00FC62' x'00FC63' x'00FC64' x'00FC65' x'00FC66' x'00FC67' x'00FC6A' x'00FC6B' x'00FC6C' x'00FC6D' x'00FC6E' x'00FC6F' x'00FC74' x'00FC75' x'00FC76' x'00FC77' x'00FC9C' x'00FC9D' x'00FC9E' x'00FC9F' x'00FCA4' x'00FCA5' x'00FCA6' x'00FCA7' x'00FCA8' x'00FCA9' x'00FCAA' x'00FCAB' x'00FCAC' x'00FCAD'
Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Underflow Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register
MN1021617/F1617
Chapter Interrupts
TM21EICL TM21EICH TM21FICL TM21FICH TM21UICL TM21UICH SC0TICL SC0TICH SC0RICL SC0RICH SC1TICL SC1TICH SC1RICL SC1RICH SC2TICL SC2TICH SC2RICL SC2RICH SC3TICL SC3TICH SC3RICL SC3RICH AT0ICL AT0ICH AT1ICL AT1ICH AT2ICL AT2ICH AT3ICL AT3ICH ADICL ADICH KIICL KIICH KIMD KICTR
x'00FCAE' x'00FCAF' x'00FC4E' x'00FC4F' x'00FC4C' x'00FC4D' x'00FC78' x'00FC79' x'00FC7A' x'00FC7B' x'00FC7C' x'00FC7D' x'00FC7E' x'00FC7F' x'00FC84' x'00FC85' x'00FC86' x'00FC87' x'00FC5C' x'00FC5D' x'00FC5E' x'00FC5F' x'00FC88' x'00FC89' x'00FC8A' x'00FC8B' x'00FC8C' x'00FC8D' x'00FC8E' x'00FC8F' x'00FC80' x'00FC81' x'00FC70' x'00FC71' x'00FCFA' x'00FCFC'
Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Timer Interrupt Control Register Serial Transmission Interrupt Control Register Serial Transmission Interrupt Control Register Serial Reception Interrupt Control Register Serial Reception Interrupt Control Register Serial Transmission Interrupt Control Register Serial Transmission Interrupt Control Register Serial Reception Interrupt Control Register Serial Reception Interrupt Control Register Serial Transmission Interrupt Control Register Serial Transmission Interrupt Control Register Serial Reception Interrupt Control Register Serial Reception Interrupt Control Register Serial Transmission Interrupt Control Register Serial Transmission Interrupt Control Register Serial Reception Interrupt Control Register Serial Reception Interrupt Control Register Transfer Interrupt Control Register Transfer Interrupt Control Register Transfer Interrupt Control Register Transfer Interrupt Control Register Transfer Interrupt Control Register Transfer Interrupt Control Register Transfer Interrupt Control Register Transfer Interrupt Control Register Conversion Interrupt Control Register Conversion Interrupt Control Register External Interrupt Control Register External Interrupt Control Register External Interrupt Condition Setup Register External Interrupt Enable Register
error interrupt control register does exist hardware. writes IAGR register indicate that detected error interrupt interrupt cannot matched. registers except IAGR, NMICR, WDICR, UNICR, EIICR, EXTMD, KIMD KICTR allow only byte-accesses. MOVB instruction data.
MN1021617/F1617
Chapter Interrupts
3-2-1
Interrupt Setup Examples
External Interrupt Setup Examples
this example, interrupt occurs negative edge from external interrupt IRQ0 (P60).
reset, bits external interrupt condition setup register (EXTMD) IRQ0IR flag external interrupt control register (IQ0ICL)
IRQ0
CORE Interrupt Timer Timer Timer Timer Timer
ROM, Control Serial Converter
Figure 3-2-1 External Interrupt Block Diagram
Interrupt Enable Setting interrupt conditions IRQ0 (P60) pin. this example, IQ0TG[1:0] EXTMD register (bit setting: 10).
EXTMD: x'00FCF8'
Enable interrupts after clearing prior interrupt requests. this, IQ0IR flag external interrupt control register (IQ0ICL) IQ0LV[2:0] flags external interrupt control register (IQ0ICH) interrupt level IQ0IE flag '1'.
IQ0ICL: x'00FC48' IQ0ICH: x'00FC49'
interrupt level this example.
MN1021617/F1617
Chapter Interrupts
Enable interrupts writing flag flag (bit setting: 111). Thereafter, interrupt occurs negative edge IRQ0 (P60) pin. program branches x'080008' when interrupt accepted.
Interrupt Service Routine
Generate interrupt service routine start address then branch that address using program after program branches x'080008'.
Specify interrupt group reading IAGR register during interrupt preprocessing. Execute interrupt service routine. Clear IQ0IR flag IQ0ICL register. Return main program with instruction after interrupt service routine ends.
During interrupt service routine, disable interrupt setting flag register interrupt level flag addition, other interrupts except nonmaskable interrupts accepted unless register set.
(IRQ0) EXTMD IQ0IE IQ0IR Level Negative Edge
Interrupt Servicing Register [R/W] EXTMD(W) IQ0ICH(W) IQ0ICL(W) (2)(3) IQ0ICL(W) (4)(5)(6)(7) IQ0ICL(W) (4)(5)(6)(7)
Figure 3-2-2 External Interrupt Timing
MN1021617/F1617
Chapter Interrupts
3-2-2
Input Interrupt Setup Examples
External pins (KI3 KI0) generates input interrupts. interrupt signal generated whenever level.
After reset released, external interrupt condition setup register (KIMD) sets level KIIR flag external interrupt control register (KIICL) becomes
CORE Interrupt Timer Timer Timer Timer Timer
ROM, Control Serial Converter
Figure 3-2-3 Input Interrupt Block Diagram
interrupt
Figure 3-2-4 Matrix Example
MN1021617/F1617
Chapter Interrupts
Interrupt Enable Setting port input/output control register (P2DIR) direction. pins output level. pins selected input.
P2DIR: x'00FFE2'
DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
pins pull-up port pull-up control register (P2PUL) generate interrupt when pushed. pins output generate interrupt when keys pushed. Generate interrupt signal when pins becomes keys pushed.
P2PUL: x'00FFB2' P2OUT: x'00FFC2'
PLU7 PLU6 PLU5 PLU4 PLU3 PLU2 PLU1 PLU0
OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0
input KIMD register. Enable interrupts KICTR register.
KIMD: x'00FCFA'
KICTR: x'00FCFC'
Enable interrupts after clearing prior interrupt requests. this, KIIR flag external interrupt control register (KIICL) KILV[2:0] flags external interrupt control register (KIICH) interrupt level KIIE flag '1'.
MN1021617/F1617
Chapter Interrupts
Enable interrupts writing flag flag (bit setting: 111). Thereafter, interrupt occurs when keys pushed.
When applying remote controller, moves STOP mode reduce power consumption. When interrupt occurs during STOP mode, waits oscillation stabilization. waits 3.2768 with 40-MHz oscillator. After that, program branches x'080008.
Interrupt Service Routine Specify interrupt group reading IAGR register during interrupt preprocessing. Execute interrupt service routine. Clear KIIR flag KIICL register. Execute determination routine. (10) Return main program with instruction after interrupt service routine ends.
Generate interrupt service routine start address then branch that address using program after program branches x'080008'.
During interrupt service routine, disable interrupt setting flag register interrupt level flag addition, other interrupts except nonmaskable interrupts accepted unless register set.
Determination Routine (11) Write x'E0' port output register (P2OUT). (bit setting: 11100000 (set only P24)). (12) corresponding port input register (P2IN) becomes keys Check with test instruction (BTST). (13) Write x'D0' P2OUT register. (bit setting: 11010000, only P25) (14) corresponding port input register (P2IN) becomes keys Check with test instruction (BTST). (15) Write x'B0' P2OUT register. (bit setting: 10110000, only P26) (16) corresponding port input register (P2IN) becomes keys Check with test instruction (BTST).
determination performed reading port input register (P2IN).
MN1021617/F1617
Chapter Interrupts
(17) Write x'70' P2OUT register. (bit setting: 01110000, only P27) (18) corresponding port input register (P2IN) becomes keys Check with test instruction (BTST).
following figure shows timing input interrupt.
STOP mode KIMD KIIR KIIE CPUM Interrupt Servicing Normal mode Oscillation STOP mode stability wait Normal mode level
Figure 3-2-5 Input Interrupt Timing
MN1021617/F1617
Chapter Interrupts
3-2-3
Watchdog Timer Interrupt Setup Examples
interrupt occurs using watchdog timer.
watchdog timer starts setting WDRST flag mode control register (CPUM) enable ('0') after reset. When watchdog timer overflows, nonmaskable interrupt occurs. This requires clear watchdog timer main program.
CORE Interrupt Timer Timer Timer Timer Timer
ROM, Control Serial Converter
Figure 3-2-6 Watchdog Timer Interrupt Block Diagram
Interrupt Enable Setting Enable interrupts writing flag flag (bit setting: 111). Clear WDRST flag CPUM register. This starts watchdog timer. addition, flags time error detection function.
CPUM: x'00FC00' WDM1 WDM0 watchdog interrupt occurs when watchdog timer counts BOSC cycles (3.2768 with 40-MHz oscillator). following setting. BOSC cycles BOSC cycles BOSC cycles BOSC cycles
STOP HALT OSC1 OSC0
Clearing Watchdog Timer WDRST flag CPUM register then immediately clear watchdog timer clears when WDRST flag
Normally, clear watchdog timer before interrupt occurs. watchdog interrupt used detect errors. cannot return previous operation before watchdog interrupt occurred after interrupt service routine executed. Therefore, must reset after watchdog interrupt occurred.
MN1021617/F1617
Chapter Interrupts
Interrupt Service Routine When interrupt generated accepted, program branches x'080008'.
Generate interrupt service routine start address then branch that address using program after program branches x'080008'.
Specify interrupt group reading IAGR register during interrupt preprocessing. Verify watchdog interrupt reading watchdog interrupt control register (WDICR). Check WDID flag with test instruction (BTST). WDID flag execute interrupt service routine. Clear WDID flag WDICR register. Return main program with instruction after interrupt service routine ends. watchdog timer shares oscillation stabilization wait counter. WDID flag cleared when program moves STOP mode, because watchdog timer operates oscillation stabilization wait counter when program returns from STOP mode. WDID flag cleared again after moving normal mode. ["2-6 Standby Function" MN10200 Series Linear Addressing Highspeed Version User Manual]
Overflow Watchdog Count NWDEN(CPUM) WDIF(WDICR) Interrupt Servicing Registers [R/W] CPUM(W) CPUM(W) Clear CPUM(W) CPUM(W) (3)(4)(5)(6)
During interrupt service routine, other interrupts accepted because becomes highest level.
Figure 3-2-7 Watchdog Timer Interrupt Timing
Watchdog Timer STOP Mode When watchdog timer enabled switches STOP mode, watchdog timer starts counting after operates oscillation stabilization wait counter returns previous mode (either NORMAL mode SLOW mode) from STOP mode interrupt. MN102F1617 Flash EEPROM version), must selected watchdog interrupt cycle (WDM0='0', WDM1='0') when moves STOP mode.
MN1021617/F1617
Chapter Timers
Chapter Timers
4-1-1
Summary 8-bit Timer Functions
Overview
MN1021617/F1617 contains sixteen 8-bit down counters that serve interval timers, event counters, clock outputs (underflow divided base clocks serial interface, start timing conversion. internal clocks (oscillation frequency (BOSC)/2) external clocks (less than BOSC/4) selected clock sources. Interrupts generated when timers underflow.
eight 8-bit timers cascade. example, cascading timers forms 16-bit timer, while cascading timers forms 32-bit timer. Timers function prescalars. They supply timers clock sources. This allows low-speed frequency generation synchronization between timers easily. addition, they supply 16-bit timers clock sources.
MN1021617/F1617
Chapter Timers
TM0IR TM1IR TM2IR
Serial
16-bit Timer 16-bit Timer TMIO TMIA TMIB TMIC TMID TMIA TMIB TMIC TMID TMIA TMIB TMIC TMID TMIA TMIB TMIC TMID TMIA TMIB TMIC TMID TMIA TMIB TMIC TMID TMIA TMIB TMIC TMID TMIA TMIB TMIC TMID TMIA TMIB TMIC TMID TMIA TMIB TMIC TMID TMIA TMIB TMIC TMID TMIA TMIB TMIC TMID TMIA TMIB TMIC TMID TMIA TMIB TMIC TMID
BOSC/2
TM3IR
Serial
TMIO
TMIO
TMIA TMIB TMIC TMID
TM3I
TMIO
TM4IR
Converter Activate
TMIO
TM4O TM5IR
Serial
TMIA TMIB TMIC TMID
TMIO
TM6IR TM6O TM7IR
TMIO
TM6I
TMIO
TM7I
TM8IR TM8O TM9IR
Serial
TMIO
TM8I
TMIO
TM10IR TM10O TM11IR TM11O TM12IR TM12O TM13IR TM13O TM14IR
TMIO
TM10
TM10I
TMIO
TM11
TM11I
TMIO
TM12
External Interrupt
TMIO
TM13
TMIO
TM14
External Interrupt
TM15IR TM15O
TMIO
TM15
External Interrupt
Figure 4-1-1 8-bit Timer Block Diagram
MN1021617/F1617
Chapter Timers
Table 4-1-1 8-bit Timer Functions
Timer Interrupt Request Interrupt Source Interval Timer Event Counter Clock Source 16-bit Timer Timer Output Clock Source Serial Interface Conversion Trigger Clock Sources BOSC/2 Reserved Reserved underflow BOSC/2 underflow Cascade Reserved BOSC/2 underflow Cascade Reserved BOSC/2 underflow Cascade TM3I BOSC/2 underflow Reserved underflow BOSC/2 underflow Cascade underflow BOSC/2 underflow Cascade TM6I BOSC/2 underflow Cascade TM7I Timer Timer Timer Timer TM4ICL (TM4IR) Timer underflow TM4O Timer TM5ICL (TM5IR) Timer underflow Timer TM6ICL (TM6IR) Timer underflow TM6O Timer TM7ICL (TM7IR) Timer underflow
Cascade
Timer Interrupt Request Interrupt Source Interval Timer Event Counter Clock Source 16-bit Timer Timer Output Clock Source Serial Interface Conversion Trigger Clock Sources BOSC/2 underflow TM8I underflow TM8ICL (TM8IR) Timer underflow TM8O
Timer TM9ICL (TM9IR) Timer underflow BOSC/2 underflow Cascade underflow
Timer TM10ICL (TM10IR) Timer underflow TM10O BOSC/2 underflow Cascade TM10I
Timer TM11ICL (TM11IR) Timer underflow TM11O BOSC/2 underflow Cascade TM11I
Timer TM12ICL (TM12IR) Timer underflow TM12O BOSC/2 underflow IRQ1 underflow
Timer TM13ICL (TM13IR) Timer underflow TM13O BOSC/2 underflow Cascade underflow
Timer TM14ICL (TM14IR) Timer underflow BOSC/2 underflow Cascade IRQ5
Timer TM15ICL (TM15IR) Timer underflow TM15O BOSC/2 underflow Cascade IRQ6
Cascade
MN1021617/F1617
Chapter Timers
Cascading 8-bit Timer Configuration Examples 16-bit 8-bit 8-bit 8-bit 8-bit 8-bit 16-bit
Cascading 8-bit counters forms 16-bit timer, 24-bit timer, 32-bit timer, 40-bit timer, 48-bit timer, 56-bit timer, 64-bit timer.
Timer Output
Interval Synchronous UART Event Event Timer Transfer Transfer Counter Counter Clock Clock
Event Counter
Figure 4-1-2 Timer Configuration
Value Load Value
Time
TMnI Input
(n=3,6 8,10,11)
Figure 4-1-3 8-bit Event Counter Input Timing
Value Load Value
Time Interrupts
TMnO Output TMnO Output
(n=4,6,8,10-13,15)
Figure 4-1-4 8-bit Timer Output Interval Timer Timing
MN1021617/F1617
Chapter Timers
4-1-2
8-bit Timer Control Registers
timer binary counters (TMnBC), timer base registers (TMnBR) timer mode registers (TMnMD) control timer/counter functions. (n=0
Reset
TMnBC
Reset
TMnBR [R/W]
Reset
TMnMD [R/W]
TMnS[1:0] Clock Source Selection BOSC divided Timer underflow (Reserved when Timer selected.) Cascading, BOSC input, Timer underflow, BOSC Read TMnBR value TMnBC operation Read TMnBR value TMnBC Reset divisor circuit timer output Timer Counting Operation Counting stop Count operation
Since settings differ depending timers, check each register explanation Appendix Section.
TMnLD
TMnEN
MN1021617/F1617
Chapter Timers
Table 4-1-2 List 8-bit Timer Control Registers
Register Timer TM0BC TM0BR TM0MD TM1BC TM1BR TM1MD TM2BC TM2BR TM2MD TM3BC TM3BR TM3MD TM4BC TM4BR TM4MD TM5BC TM5BR TM5MD TM6BC TM6BR TM6MD TM7BC TM7BR TM7MD TM8BC TM8BR TM8MD TM9BC TM9BR TM9MD TM10BC TM10BR TM10MD TM11BC TM11BR TM11MD TM12BC TM12BR TM12MD TM13BC TM13BR TM13MD TM14BC TM14BR TM14MD TM15BC TM15BR TM15MD Address x'00FE00' x'00FE10' x'00FE20' x'00FE01' x'00FE11' x'00FE21'' x'00FE02' x'00FE12' x'00FE22' x'00FE03' x'00FE13' x'00FE23' x'00FE04' x'00FE14' x'00FE24' x'00FE05' x'00FE15' x'00FE25' x'00FE06' x'00FE16' x'00FE26' x'00FE07' x'00FE17' x'00FE27' x'00FE08' x'00FE18' x'00FE28' x'00FE09' x'00FE19' x'00FE29' x'00FE0A' x'00FE1A' x'00FE2A' x'00FE0B' x'00FE1B' x'00FE2B' x'00FE0C' x'00FE1C' x'00FE2C' x'00FE0D' x'00FE1D' x'00FE2D' x'00FE0E' x'00FE1E' x'00FE2E' x'00FE0F' x'00FE1F' x'00FE2F' Function Timer Binary Counter Timer Base Register Timer Mode Register Timer Binary Counter Timer Base Register Timer Mode Register Timer Binary Counter Timer Base Register Timer Mode Register Timer Binary Counter Timer Base Register Timer Mode Register Timer Binary Counter Timer Base Register Timer Mode Register Timer Binary Counter Timer Base Register Timer Mode Register Timer Binary Counter Timer Base Register Timer Mode Register Timer Binary Counter Timer Base Register Timer Mode Register Timer Binary Counter Timer Base Register Timer Mode Register Timer Binary Counter Timer Base Register Timer Mode Register Timer Binary Counter Timer Base Register Timer Mode Register Timer Binary Counter Timer Base Register Timer Mode Register Timer Binary Counter Timer Base Register Timer Mode Register Timer Binary Counter Timer Base Register Timer Mode Register Timer Binary Counter Timer Base Register Timer Mode Register Timer Binary Counter Timer Base Register Timer Mode Register
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
MN1021617/F1617
Chapter Timers
4-1-3 8-bit Timer Block Diagrams
Data
(FE10)
Timer base register TM0BR Load
(FE20)
TM0EN
TM1EN
Reload
(FE00)
Timer underflow
Timer underflow Timer cascade Reserved
TM0LD
TM0S1
TM0S0
Timer binary counter TM0BC Count
Timer underflow interrupt Underflow
TM0MD
BOSC/2 Reserved Reserved
Multiplex
Figure 4-1-5 Timer Block Diagram
Data
(FE11)
Timer base register TM1BR Load
(FE21)
Reload
(FE01)
TM1LD
TM1S1
TM1S0
Timer binary counter TM1BC Underflow Count
Timer underflow interrupt
TM1MD
BOSC/2
Multiplex
Figure 4-1-6 Timer Block Diagram
MN1021617/F1617
Chapter Timers
Data
(FE12)
Timer base register TM2BR Load
(FE22)
Reload
(FE02)
Timer underflow Timer cascade Reserved
TM2EN TM3EN
Timer underflow Timer cascade TM3I input
TM2LD
TM2S1
TM2S0
Timer binary counter TM2BC Underflow Count
Timer underflow interrupt
TM2MD
BOSC/2
Multiplex
Figure 4-1-7 Timer Block Diagram
Data
(FE13)
Timer base register TM3BR Load
(FE23)
Reload
(FE03)
TM3LD
TM3S1
TM3S0
Timer binary counter TM3BC Count Underflow
Timer underflow interrupt
TM3MD
BOSC/2
Mutliplex
Figure 4-1-8 Timer Block Diagram
MN1021617/F1617
Chapter Timers
Data
(FE14)
Timer base register TM4BR Load
(FE24) TM4EN TM4LD TM4S1 TM4S0
Reload
(FE04)
Timer binary counter TM4BC Count Underflow
Timer underflow interrupt
TM4MD
Reset BOSC/2 Timer underflow Reserved Timer underflow Multiplex
TM4O output PCMD0, PCDIR0
Figure 4-1-9 Timer Block Diagram
Data
(FE15)
Timer base register TM5BR Load
(FE25)
Reload
(FE05)
Timer underflow Timer cascade Timer underflow
TM5EN
TM5LD
TM5S1
TM5S0
Timer binary counter TM5BC Count Underflow
Timer underflow interrupt
TM5MD
BOSC/2
Mutliplex
Figure 4-1-10 Timer Block Diagram
MN1021617/F1617
Chapter Timers
Data
(FE16)
Timer base register TM6BR Load
(FE26) TM6EN
TM7EN
Reload
(FE06)
Timer underflow Timer cascade TM6I input
Timer underflow Timer cascade TM7I input
TM6LD
TM6S1
TM6S0
Timer binary counter TM6BC Count Underflow
Timer underflow interrupt
TM6MD
Reset BOSC/2 Multiplex
TM6O output PCMD1, PCDIR1
Figure 4-1-11 Timer Block Diagram
Data
(FE17)
Timer base register TM7BR Load
(FE27)
Reload
(FE07)
TM7LD
TM7S1
TM7S0
Timer binary counter TM7BC Count Underflow
Timer underflow interrupt
TM7MD
BOSC/2
Mutliplex
Figure 4-1-12 Timer Block Diagram
MN1021617/F1617
Chapter Timers
Data
(FE18)
Timer base register TM8BR Load
(FE28) TM8EN TM8LD TM8S1 TM8S0
Reload
(FE08)
Timer binary counter TM8BC Count Underflow
Timer underflow interrupt
TM8MD
Reset BOSC/2 Timer underflow TM8I input Timer underflow Multiplex
TM8O output PCMD2, PCDIR2
Figure 4-1-13 Timer Block Diagram
Data
(FE19)
Timer base register TM9BR Load
(FE29)
Reload
(FE09)
Timer underflow Timer cascade Timer underflow
TM9EN
TM9LD
TM9S1
TM9S0
Timer binary counter TM9BC Count Underflow
Timer underflow interrupt
TM9MD
BOSC/2
Mutliplex
Figure 4-1-14 Timer Block Diagram
MN1021617/F1617
Chapter Timers
Data
(FE1A)
Timer base register TM10BR Load
(FE2A)
TM10EN
TM11EN
Reload
(FE0A)
Timer underflow Timer cascade TM10I input
Timer underflow Timer cascade TM11I input
TM10LD
TM10S1
TM10S0
Timer binary counter TM10BC Count Underflow
Timer underflow interrupt
TM10MD
Reset BOSC/2 Multiplex
TM10O output PCMD3, PCDIR3
Figure 4-1-15 Timer Block Diagram
Data
(FE1B)
Timer base register TM11BR Load
(FE2B)
TM11LD TM11S1 TM11S0
Reload
(FE0B)
Timer binary counter TM11BC Count Underflow
Timer underflow interrupt
TM11MD
Reset BOSC/2 Multiplex
TM11O output PCMD4, PCDIR4
Figure 4-1-16 Timer Block Diagram
MN1021617/F1617
Chapter Timers
Data
(FE1C)
Timer base register TM12BR Load
(FE2C)
Reload
(FE0C)
Timer underflow External Interrupt Timer underflow
Timer underflow Timer cascade Timer underflow
TM12EN TM13EN
TM12LD
TM12S1
TM12S0
Timer binary counter TM12BC Count Underflow
Timer underflow interrupt
TM12MD
Reset BOSC/2 Multiplex
TM12O output PCMD4, PCDIR4
Figure 4-1-17 Timer Block Diagram
Data
(FE1D)
Timer base register TM13BR Load
(FE2D)
Reload
(FE0D)
TM13LD
TM13S1
TM13S0
Timer binary counter TM13BC Count Underflow
Timer underflow interrupt
TM13MD
Reset BOSC/2 Multiplex
TM13O output PCMD5, PCDIR5
Figure 4-1-18 Timer Block Diagram
MN1021617/F1617
Chapter Timers
Data
(FE1E)
Timer base register TM14BR Load
(FE2E)
TM14EN TM15EN TM14LD TM14S1 TM14S0
Reload
(FE0E)
Timer binary counter TM14BC Count Underflow
Timer underflow interrupt
TM14MD
BOSC/2 Timer underflow Timer cascade External Interrupt
Mutliplex
Figure 4-1-19 Timer Block Diagram
Data
(FE1F)
Timer base register TM15BR Load
(FE2F)
TM15LD TM15S1 TM15S0
Reload
(FE0F)
Timer binary counter TM15BC Count Underflow
Timer underflow interrupt
TM15MD
Reset BOSC/2 Timer underflow Timer cascade External Interrupt Mutliplex
TM15O output P9MD6, P9DIR
Figure 4-1-20 Timer Block Diagram
MN1021617/F1617
Chapter Timers
4-2-1
8-bit Timer Setup Examples
Event Counter Using 8-bit Timer
Timer divides TM6I input generates underflow interrupt.
Event counter operates even while stops. event counter samples TMnI input BOSC when operates. other hand, event counter counts when TMnI input changes during stop. transfers normal mode after oscillation stability wait when interrupt generated. this point, event counter counts TMnI input change timing until oscillation stability wait completed. event counter, however, starts counting TMnI input timing event counter samples BOSC.
When pulse output event counter, change timing quantized (synchronized with BOSC).
TM6I
CORE Interrupt Timer Timer Timer Timer Timer
ROM, Control Serial Converter
Figure 4-2-1 Event Counter Block Diagram
interrupt enable flag (IE) processor status word (PSW) Verify that timer counting stopped with timer mode register (TM6MD).
TM6MD: x'00FE26'
This verification unnecessary after reset.
MN1021617/F1617
Chapter Timers
Enable interrupts after clearing existing interrupt requests. this, KILV[2:0] external interrupt control register (KIICH) interrupt level 0-6, TM6IR TM6IE Thereafter, interrupt will generated whenever timer underflows.
KIICH/TM6ICL/TM6ICH only byte access. MOVB instruction.
KIICH: x'00FC71'
KIICH sets timer interrupt level. "3-1 Interrupt Group"] interrupt level this example.
TM6ICL: x'00FC72'
TM6ICH: x'00FC73'
timer divisor. Since timer divides TM6I timer base register (TM6BR) (The valid range TM6BR 255.)
TM6BR: x'00FE16'
Load TM6BR value timer binary counter (TM6BC). same time, select TM6I input clock source.
TM6MD: x'00FE26'
Setting TM6EN TM6LD required between bank address version linear address version, this setting required linear address high-speed version.
MN1021617/F1617
Chapter Timers
TM6LD TM6EN This starts timer. Counting begins start next cycle.
change clock source once have selected Selecting clock source while setting count operation control will corrupt value binary counter.
When binary counter reaches loads value from base register next count, timer underflow interrupt request will sent CPU.
Interrupt Enable TM6BR TM6BC
Timer Underflow Interrupt
TM6I KILV(W) TM6MD(W) TM6MD(W) TM6BR(W)
Figure 4-2-2 Event Counter Timing (8-bit Timer)
MN1021617/F1617
Chapter Timers
4-2-2 Clock Output Using 8-bit Timer
Timer timer outp
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