significant number digital systems must deal with inputs synchronized

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significant number digital systems must deal with inputs synchronized

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Metastability MACH Devices
significant number digital systems must deal with inputs synchronized their internal clocks. These asynchronous signals arise from various asynchronous protocols which often used designs; they result from sharing signals from systems with different clocks; they response system user course, synchronized with system. result metastability, problem that plague unwary designers. newly discovered phenomenon, normally dealt with somewhat qualitatively, and, unfortunately, usually ignored much possible.
Causes Metastability
flip-flop setup time parameter that most often root metastability. setup time requirement that data made available input flip-flop before clock signal arrives. data must only there, must also stable. PLD, array data adds setup time. data passes through array flip-flop (Figure clock signal, other hand, goes directly from clock flip-flop. path much shorter than data path. setup time requirement that data signal must given more time flip-flop before clock signal. published setup time satisfied, data arrives flip-flop well before clock, output flip-flop will change desired (Figure setup time violated, guarantee made about what output will output could normal, since published setup time worst-case number. However, timing between clock data just right, output will unstable some time before settles into state. Neither time output remains unstable final state predictable (Figure This condition metastability. Figure Clock Data Paths
Array Buffer
Buffer
Figure Output Responses
Data Clock
Data Clock tMET
Outputs
Outputs
Output Response when Setup Time Satisfied
Possible Output Response when Setup Time Violated
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an8060_01
Lattice Semiconductor
Metastability MACH Devices
Calculating Metastability
probability metastable event occurring design calculated based five parameters. probability given terms Mean Time Between Failure (MTBF) metastable events happening. formula used calculate MTBF
CLOCK DATA
MTBF
parameters that specific process technology architecture will similar different devices same architecture technology. They determined taking empirical data. Values MACH MACH families devices given Table Table Metastability Constants
Family MACH MACH 1.01139 10-16 5.417 10-25 2.391 1010 1.07 1010
time takes register stabilize known value once metastable event occurred referred tMET. register does necessarily stabilize correct value, does stabilize logic logic `0.' This shown Figure clock data frequencies also affect probability that metastable event will occur. asynchronous design, these frequencies always known have estimated. Using formula listed above, logarithmic curves MTBF calculated. Figure shows curves using fDATA 1MHz fCLOCK 10MHz. Figure Metastability Curves MACH MACH
LN(MTBF) tMET (ns)
MACH MACH
calculate stabilization time based MTBF: MTBF CLOCK DATA
values should calculated terms seconds Hertz.
Lattice Semiconductor
Metastability MACH Devices
Solutions Metastability
most common solution metastability synchronize inputs with extra flip-flop (Figure Ideally, first flip-flop goes metastable, delay between clock pulses will allow ringing subside before clocking into next flip-flop. This improves chances having good data second flip-flop. Figure Dual Synchronizer
Note that each extra stage flip-flop means extra clock delay data must absorbed system. This method foolproof. possibility metastability reduced, eliminated. flip-flop metastable preceding stage does recover quickly enough. best avoid metastability avoid synchronization when possible. Many applications, such arbitration schemes, synchronization because synchronization itself necessary, because provides only convenient store data. This, unfortunately, requires system that inherently asynchronous adds some synchronizing elements middle.
Summary
Metastability occur number asynchronous systems, usually inability guarantee that setup time flip-flops will satisfied. standard synchronous systems where setup time (and other timing requirements) specifically designed metastability will never problem. some situations, metastability caused need interface systems with different clocks. this case, will never possible completely eliminate possibility metastability. Instead, designer must take steps reduce probability system failure metastability.
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