HB54R5128KN-A75B/B75B/10B (64M words bits, Banks) HB54R5128KN Dou

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HB54R5128KN-A75B/B75B/10B (64M words bits, Banks) HB54R5128KN Dou

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512MB SDRAM S.O.DIMM
HB54R5128KN-A75B/B75B/10B (64M words bits, Banks)
HB54R5128KN Double Data Rate (DDR) SDRAM Module, mounted 256M bits SDRAM (HM5425801BTB) sealed package, piece serial EEPROM bits EEPROM) Presence Detect (PD). HB54R5128KN organized banks mounted pieces 256M bits SDRAM. Read write operations performed cross points /CK. This highspeed data transfer realized bits prefetchpipelined architecture. Data strobe (DQS) both read write available high speed reliable data design. setting extended mode register, on-chip Delay Locked Loop (DLL) enable disable. outline products 200-pin socket type package (dual lead out). Therefore, makes high density mounting possible without surface mount technology. provides common data inputs outputs. Decoupling capacitors mounted beside each module board. Note: push cover drop modules order protect from mechanical defects, which would electrical defects.
Features
200-pin socket type package (dual lead out) Outline: 67.6mm (Length) 31.75mm (Height) 3.80mm (Thickness) Lead pitch: 0.6mm 2.5V power supply (VCC) SSTL-2 interface inputs outputs Clock frequency: (max) (-A75B/B75B) (max) (-10B) Data inputs, outputs synchronized with banks operate simultaneously independently (Component) Burst read/write operation Programmable burst length: Burst read stop capability Programmable burst sequence Sequential Interleave Start addressing capability Even Programmable /CAS latency (CL): 8192 refresh cycles: 7.8µs (8192row/64ms) variations refresh Auto refresh Self refresh
Document E0189H30 (Ver. 3.0) Date Published April 2002 Japan URL: http://www.elpida.com Elpida Memory, Inc. 2001-2002 Elpida Memory, Inc. joint venture DRAM company Corporation Hitachi, Ltd.
HB54R5128KN-A75B/B75B/10B
Ordering Information
Part number HB54R5128KN-A75B*1 HB54R5128KN-B75B*2 HB54R5128KN-10B*3 Clock frequency (max.) /CAS latency Package Contact
200-pin dual lead socket Gold type
Notes: operation /CAS latency 2.5. operation /CAS latency 2.0. operation /CAS latency 2.5.
Configurations
Front side
Back side
name VREF DQS0 DQS1 DQ10 DQ11 /CK0 DQ16 DQ17 DQS2 DQ18
name DQ19 DQ24 DQ25 DQS3 DQ26 DQ27 /CK2 CKE1
name VREF DQ12 DQ13 DQ14 DQ15 DQ20 DQ21 DQ22
name DQ23 DQ28 DQ29 DQ30 DQ31 CKE0
Preliminary Data Sheet E0189H30 (Ver. 3.0)
HB54R5128KN-A75B/B75B/10B
name A10/AP DQ32 DQ33 DQS4 DQ34 DQ35 DQ40 DQ41 DQS5 name DQ42 DQ43 DQ48 DQ49 DQS6 DQ50 DQ51 DQ56 DQ57 DQS7 DQ58 DQ59 VCCSPD VCCID name /RAS /CAS DQ36 DQ37 DQ38 DQ39 DQ44 DQ45 name DQ46 DQ47 /CK1 DQ52 DQ53 DQ54 DQ55 DQ60 DQ61 DQ62 DQ63
Preliminary Data Sheet E0189H30 (Ver. 3.0)
HB54R5128KN-A75B/B75B/10B
name BA0, DQ63 /RAS /CAS /S0, CKE0, CKE1 /CK0 /CK2 DQS0 DQS7 VCCSPD VREF VCCID Function Address input address Column address Data input/output address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input output data strobe Input mask Clock input serial Data input/output serial Serial address input Power internal circuit Power serial EEPROM Input reference voltage Ground identification flag connection
Bank select address
Preliminary Data Sheet E0189H30 (Ver. 3.0)
HB54R5128KN-A75B/B75B/10B
Serial Matrix*
Byte
Function described Number bytes utilized module manufacturer Total number bytes serial device Memory type Number address Number column address Number DIMM banks Module data width Module data width continuation SDRAM cycle time, -A75B -B75B -10B SDRAM access from clock (tAC) -A75B/B75B -10B DIMM configuration type Refresh rate/type Primary SDRAM width Error checking SDRAM width SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number banks SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: latency SDRAM device attributes: latency SDRAM module attributes SDRAM device attributes: General Minimum clock cycle time -A75B -B75B/10B
Bit7
Bit6
Bit5 Bit4
Bit3
Bit2
Bit1 Bit0
value
Comments byte SDRAM bits SSTL 2.5V 2.5*5
Voltage interface level this assembly
0.7ns*5 0.8ns*5 None Self refresh used Unbuffered 0.2V
Maximum data access time (tAC) from clock -A75B/B75B -10B Minimum clock cycle time Maximum data access time (tAC) from clock Minimum precharge time (tRP)
0.7ns*5 0.8ns*5
20ns
Preliminary Data Sheet E0189H30 (Ver. 3.0)
HB54R5128KN-A75B/B75B/10B
Byte Function described Minimum active active delay (tRRD) Minimum /RAS /CAS delay (tRCD) Minimum active precharge time (tRAS) -A75B/B75B -10B Module bank density Address command setup time before clock (tIS) -A75B/B75B -10B Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value (ASCII-8bit code) Comments 15ns 20ns 45ns 50ns banks 256MB 1.1ns*5 1.2ns*5 1.1ns*5 1.2ns*5 0.5ns*5 0.6ns*5 0.5ns*5 0.6ns*5 Future 65ns*5 70ns*5 75ns*5 80ns*5 15ns*5 500ps*5 600ps*5 750ps*5 1000ps*5 Future Initial HITACHI
Address command hold time after clock (tIH) -A75B/B75B -10B Data input setup time before clock (tDS) -A75B/B75B -10B Data input hold time after clock (tDH) -A75B/B75B -10B Superset information Active command period (tRC) -A75B/B75B -10B Auto refresh active/ Auto refresh command cycle (tRFC) -A75B/B75B -10B SDRAM cycle max. (tCK max.) Dout skew -A75B/B75B -10B Data hold skew (tQHS) -A75B/B75B -10B Superset information revision Checksum bytes -A75B -B75B -10B
Manufacturer's JEDEC code Manufacturer's JEDEC code Manufacturing location Module part number Module part number Module part number
Preliminary Data Sheet E0189H30 (Ver. 3.0)
HB54R5128KN-A75B/B75B/10B
Byte
Function described Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number -A75B -B75B -10B Module part number -A75B/B75B -10B Module part number -A75B/B75B -10B Module part number -A75B/B75B -10B Module part number Revision code Revision code Manufacturing date Manufacturing date Module serial number Manufacturer specific data
Bit7
Bit6
Bit5 Bit4
Bit3
Bit2
Bit1 Bit0
value
Comments (Space) (Space) Initial (Space) Year code (BCD) Week code (BCD)
Notes: serial data protected. Serial data, "driven Low", Serial data, "driven High" These based JEDEC Committee Ballot JC-42.5-99-129. Byte72 manufacturing location code. (ex: case Japan, byte72 4AH. shows ASCII code.) Bytes through assembly serial number. bits through defined ("1" "0"). These specifications defined based component specification, module.
Preliminary Data Sheet E0189H30 (Ver. 3.0)
HB54R5128KN-A75B/B75B/10B
Block Diagram
DQS0 DQS1 DQ15 DQS5 DQ40 DQ47 I/O0 I/O7 I/O0 I/O7 DQ32 DQ39 DQS4 I/O0 I/O7 I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
DQS2 DQ16 DQ23 DQS3 DQ24 DQ31
DQS6 DQ48 DQ55 DQS7 DQ56 DQ63
I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
Serial /RAS /CAS CKE0 CKE1 VCCSPD VREF SDRAMs D15) SDRAMs D15) SDRAMs D15) SDRAMs D15) SDRAMs D15) SDRAMs SDRAMs D15) SDRAMs D15) SDRAMs D15), VCCQ Notes VCCID Open 256M bits SDRAM EEPROM SDRAMs D15), SDRAMs D15), wiring differ from that described this drawing; however DQ/DM/DQS relationships maintained shown. VCCID strap connections: (for memory device VCC, VCCQ) Strap (open): VCCQ Strap (closed): VCCQ pull-up registor reguired open-drain/open-collector output. pull-up registor recommended, because normal lime inactive "high" state. /CK0 /CK1 /CK2 loads loads loads
Preliminary Data Sheet E0189H30 (Ver. 3.0)
HB54R5128KN-A75B/B75B/10B
Logical Clock Structure
8DRAM loads DRAM1 DRAM5
DIMM connector
DRAM2 DRAM6
DRAM3 DRAM7
DRAM4 DRAM8
Preliminary Data Sheet E0189H30 (Ver. 3.0)
HB54R5128KN-A75B/B75B/10B
Functions
(CLK), (/CLK) (input pin): master clock inputs. inputs except DMs, DQSs referred cross point rising edge VREF level. When read operation, DQSs referred cross point /CK. When write operation, referred cross point VREF level. DQSs write operation referred cross point /CK. (/CS) (input pin): When Low, commands data input. When High, inputs ignored. However, internal operations (bank active, burst operations, etc.) held. /RAS, /CAS, (input pins): These pins define operating commands (read, write, etc.) depending combinations their voltage levels. "Command operation". (input pins): address (AX0 AX12) determined level cross point rising edge VREF level bank active command cycle. Column address (AY0 AY9) loaded cross point rising edge VREF level read write command cycle. This column address becomes starting address burst operation. (AP) (input pin): defines precharge mode when precharge command, read command write command issued. High when precharge command issued, banks precharged. when precharge command issued, only bank that selected BA1, precharged. High when read write command, auto-precharge function enabled. While Low, auto-precharge function disabled. BA0, (input pin): BA0/BA1 bank select signals. memory array divided into bank bank bank bank Low, bank selected. High Low, bank selected. High, bank selected. High High, bank selected. (input pin): controls power down self-refresh. power down self-refresh commands entered when driven exited when resumes High. level must kept cycle LCKEPW) least, that changes cross point rising edge VREF level with proper setup time tIS, next rising edge level must kept with proper hold time tIH.
Functions
(input output pins): Data input output from these pins. (input output pin): provide read data strobes output) write data strobes input). (input pins): reference signal data input mask function. sampled cross point VREF VCCQ (power supply pins): 2.5V applied. (VCC internal circuit VCCQ output buffer.) VCCSPD (power supply pin): 2.5V applied (For serial EEPROM). (power supply pin): Ground connected.
Detailed Operation Part, Characteristics Timing Waveforms
Refer Series datasheet (E0086H).
Preliminary Data Sheet E0189H30 (Ver. 3.0)
HB54R5128KN-A75B/B75B/10B
Electrical Specifications
Absolute Maximum Ratings
Parameter Voltage relative Supply voltage relative Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VCC, VCCQ IOUT Topr Tstg Value -1.0 +4.6 -1.0 +4.6 +100 Unit Note
Notes: Respect VSS. Operating Conditions +65°C)
Parameter Supply voltage Symbol VCC, VCCQ Input reference voltage Termination voltage Input high voltage Input voltage Input signal voltage differential input voltage Ambient illuminance VREF (dc) min. 1.15 VREF 0.04 VREF 0.18 -0.3 -0.3 1.25 VREF max. 1.35 VREF 0.04 VCCQ VREF 0.18 VCCQ VCCQ Unit Notes
VSWING (dc) 0.36
Notes:
parameters referred VSS, when measured. VCCQ must lower than equal VCC. allowed exceed 4.6V period shorter than equal 5ns. allowed outreach below down -1.0V period shorter than equal 5ns. (dc) specifies allowable execution each differential input. VSWING (dc) specifies input differential voltage required switching.
Preliminary Data Sheet E0189H30 (Ver. 3.0)
HB54R5128KN-A75B/B75B/10B
Characteristics 65°C, VCC, VCCQ 2.5V 0.2V,
Parameter Operating current (ACTV-PRE) Symbol ICC0 Grade -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B max. 1200 1120 1640 1520 1360 2200 2080 1960 2040 1920 1800 2040 1960 1760 Unit Test condition VIH, min. VIH, 2.5, min. Notes
Operating current (ACTV-READ-PRE)
ICC1
Idle power down standby current
ICC2P
Idle standby current
ICC2N
VIH,
Active power down standby current
ICC3P
VIH, tRAS max. VIH, VIH, tRFC min., Input Input 0.2V Input 0.2V.
Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto refresh current Self refresh current
ICC3N
ICC4R
ICC4W
ICC5 ICC6
Notes.
These data measured under condition that pins connected. bank operation. bank active. banks idle. Command/Address transition once cycle. Data/Data mask transition twice cycle. data this table measured with regard min. general.
Characteristics2 65°C, VCC, VCCQ 2.5V 0.2V,
Parameter Input leakage current Output leakage current Output high voltage Output voltage Symbol min. 0.76 max. 0.76 Unit Test condition VOUT (max.) -15.2mA (min.) 15.2mA Notes
Preliminary Data Sheet E0189H30 (Ver. 3.0)
HB54R5128KN-A75B/B75B/10B
Capacitance 25°C, VCC, VCCQ 2.5V 0.2V)
Parameter Input capacitance Input capacitance Data input/output capacitance Symbol Pins Address, /RAS, /CAS, CKE, DQS, min. max. Unit Notes
Notes: These parameters measured conditions: 100MHz, VOUT VCCQ/2, VOUT 0.2V. Dout circuits disabled. Timing Parameter Measured Clock Cycle Unbuffered DIMM
Number clock cycle Parameter Write pre-charge command delay (same bank) Read pre-charge command delay (same bank) Write read command delay input data) Burst stop command write command delay 2.5) Burst stop command High-Z 2.5) Read command write command delay output data) 2.5) Pre-charge command High-Z 2.5) Write command data latency Write recovery data latency Register command active register command Self refresh exit non-read command Self refresh exit read command Power down entry Power down exit command input minimum pulse width Symbol tWPD tRPD tWRD tBSTW tBSTW tBSTZ tBSTZ tRWD tRWD tHZP tHZP tWCD tDMD tMRD tSNR tSRD tPDEN tPDEX tCKEPW min. BL/2 BL/2 BL/2 BL/2 BL/2 max.
Preliminary Data Sheet E0189H30 (Ver. 3.0)
HB54R5128KN-A75B/B75B/10B
Physical Outline
Unit: 67.60 63.60 11.55 18.45 3.80 (DATUM -A-)
Full
Component area (Front)
20.0 4.00
31.75 6.00
2.15
11.40 4.20
47.40
2.45 1.00 0.10
4.20 1.50 2.45
11.40
47.40
2.15 R0.50 0.20
R0.50 0.20
1.80
Component area (Back)
4.00 0.10
(DATUM -A-)
2.00 Min.
Detail
(DATUM -A-) FULL
4.00 0.10
Detail
0.60 1.80 1.00 0.10 0.45 0.03
ECA-TS2-0019-01
Preliminary Data Sheet E0189H30 (Ver. 3.0)
0.25
2.55
HB54R5128KN-A75B/B75B/10B
CAUTION HANDLING MEMORY MODULES
When handling inserting memory modules, sure touch components modules, such memory ICs, chip capacitors chip resistors. necessary avoid undue mechanical stress these components prevent damaging them. particular, push module cover drop modules order protect from mechanical defects, which would electrical defects. When re-packing memory modules, sure modules touching each other. Modules contact with other modules cause excessive mechanical stress, which damage modules.
MDE0202
NOTES CMOS DEVICES
PRECAUTION AGAINST DEVICES
Exposing devices strong electric field cause destruction gate oxide ultimately degrade devices operation. Steps must taken stop generation static electricity much possible, quickly dissipate when once occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS DEVICES
connection CMOS devices input pins cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. unused pins must handled accordance with related specifications.
STATUS BEFORE INITIALIZATION DEVICES
Power-on does necessarily define initial status devices. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee output levels, settings contents registers. devices initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
CME0107
Preliminary Data Sheet E0189H30 (Ver. 3.0)
HB54R5128KN-A75B/B75B/10B
information this document subject change without notice. Before using this document, confirm that this latest version.
part this document copied reproduced form means without prior written consent Elpida Memory, Inc. Elpida Memory, Inc. does assume liability infringement intellectual property rights (including limited patents, copyrights, circuit layout licenses) Elpida Memory, Inc. third parties arising from products information listed this document. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights Elpida Memory, Inc. others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. Elpida Memory, Inc. assumes responsibility losses incurred customers third parties arising from these circuits, software information. [Product applications] Elpida Memory, Inc. makes every attempt ensure that products high quality reliability. However, users instructed contact Elpida Memory's sales office before using product aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment life support, other such application which especially high quality reliability demanded where failure malfunction directly threaten human life cause risk bodily injury. [Product usage] Design your application that product used within ranges conditions guaranteed Elpida Memory, Inc., including maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions other related characteristics. Elpida Memory, Inc. bears responsibility failure damage when product used beyond guaranteed ranges conditions. Even within guaranteed ranges conditions, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Elpida Memory, Inc. products does cause bodily injury, fire other consequential damage operation Elpida Memory, Inc. product. [Usage environment] This product designed resistant electromagnetic waves radiation. This product must used non-condensing environment. export products technology described this document that controlled Foreign Exchange Foreign Trade Japan, must follow necessary procedures accordance with relevant laws regulations Japan. Also, export products/technology controlled U.S. export control regulations, another country's export control laws regulations, must follow necessary procedures accordance with such laws regulations. these products/technology sold, leased, transferred third party, third party granted license these products, that third party must made aware that they responsible compliance with relevant laws regulations.
M01E0107
Preliminary Data Sheet E0189H30 (Ver. 3.0)

HB54R5128KN-A75B/B75B/10B (64M words bits, Banks) HB54R5128KN Dou

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