Simulation Guide Windows UNIX® Environments Actel Corporatio

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Simulation Guide Windows UNIX® Environments Actel Corporatio

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Verilog®
Simulation Guide
Windows UNIX® Environments
Actel Corporation, Sunnyvale, 94086
2000 Actel Corporation. rights reserved. Printed United States America Part Number: 5579005-4 Release: July 2000 part this document copied reproduced form means without prior written consent Actel. Actel makes warranties with respect this documentation disclaims implied warranties merchantability fitness particular purpose. Information this document subject change without notice. Actel assumes responsibility errors that appear this document. This document contains confidential proprietary information that disclosed unauthorized person without prior written consent Actel Corporation.
Trademarks
Actel Actel logotype registered trademarks Actel Corporation. Adobe Acrobat Reader registered trademarks Adobe Systems, Inc. Cadence registered trademark Cadence Design Systems, Inc. Mentor Graphics registered trademark Mentor Graphics, Inc. Synopsys registered trademark Synopsys, Inc. Verilog registered trademark Open Verilog International. Viewlogic, ViewSim, ViewDraw registered trademarks MOTIVE SpeedWave trademarks Viewlogic Systems, Inc. Windows registered trademark Windows trademark Microsoft Corporation U.S. other countries. other products brand names mentioned trademarks registered trademarks their respective holders.
Table Contents
Table Contents
Introduction
Document Organization Document Assumptions Document Conventions Actel Manuals Online Help.
Setup
Software Requirements Verilog Libraries Compiling Verilog Libraries
Design Flow
Actel-Verilog Design Flow Illustrated Actel-Verilog Design Flow Overview
Generating Netlists
Generating EDIF Netlist Generating Structural Verilog Netlist
Interpreted Simulation
Example Testbench Example Command File Behavioral Simulation Structural Simulation Timing Simulation Verilog Switches.
Simulation with V-System ModelSim
Table Contents
Behavioral Simulation Structural Simulation Timing simulation
Simulation with Mentor Graphics QuickHDL
Behavioral Simulation Structural Simulation Timing simulation
Product Support
Actel U.S. Toll-Free Line Customer Service Customer Applications Center Guru Automated Technical Support Site Site. Contacting Customer Applications Center Worldwide Sales Offices
Index
Introduction
Verilog Simulation Guide contains information about interfacing Designer Series FPGA development software with Verilog simulation tools. Refer Designer User's Guide additional information about using Designer software. Refer documentation included with your Verilog simulation tool information about performing simulation.
Document Organization
Verilog Simulation Guide contains following chapters: Chapter Setup contains information about setting Verilog libraries simulating Actel designs. Chapter Design Flow illustrates describes design flow simulating Actel designs using Verilog Simulation tools. Chapter Generating Netlists contains information generating EDIF structural Verilog netlists. Chapter Interpreted Simulation describes procedures performing functional (behavioral structural) timing simulation Actel design using tools that either interpret library design files, compile them on-the-fly. Chapter Simulation with V-System ModelSim describes procedures performing functional (behavioral structural) timing simulation Actel design using commands Model Technology V-System ModelSim simulator. Chapter Simulation with Mentor Graphics QuickHDL describes procedures performing functional (behavioral structural) timing simulation Actel design using commands Mentor Graphics QuickHDL simulator. Appendix Product Support provides information about contacting Actel customer technical support.
Introduction
Document Assumptions
This document assumes following: using have installed Designer Series software "c:\actel" directory. have installed Verilog simulator. familiar with UNIX workstations operating systems. familiar with Windows operating environments. familiar with FPGA architecture FPGA design software.
Document Conventions
This document uses following conventions: Information input user follows this format:
keyboard input
contents file follows this format:
file contents
Messages displayed screen appear follows:
Screen Message
This document uses following variables: Actel FPGA family libraries shown <act_fam>. Substitute desired Actel FPGA family ACT1, ACT2 (for 1200XL devices), ACT3, 3200DX, 40MX, 42MX, 54SX, 54SX-A, needed. example:
edn2vlog fam:<act_fam> <design_name>
Compiled Verilog libraries shown <vlog_fam>. Substitute <vhd_fam> desired VHDL family ACT1, ACT2 (for 1200XL devices), ACT3, A3200DX, A40MX, A42MX, A54SX, A54SX-A,
Introduction
needed. VHDL language requires that library names begin with alpha character.
Actel Manuals
Designer Series software includes printed online manuals. online manuals format CD-ROM "/manuals" directory. These manuals also installed onto your system when install Designer software. view online manuals, must install Adobe® Acrobat Reader® from CD-ROM. Designer Series includes following manuals, which provide additional information designing Actel FPGAs: Getting Started User's Guide. This manual describes design flow user interface Actel Designer Series software, including information about using ACTgen Macro Builder. Designer User's Guide. This manual provides introduction Designer series software well explanation tools features. PinEdit User's Guide. This guide provides detailed description PinEdit tool Designer. includes cross-platform explanations PinEdit features. ChipEdit User's Guide. This guide provides detailed description ChipEdit tool Designer. includes detailed explanation ChipEdit functionality. Timer User's Guide. This guide provides detailed description Timer tool Designer. includes detailed explanation Timer functionality. Actel Coding Style Guide. This guide provides preferred coding styles Actel architecture information about optimizing your code Actel devices. Silicon Expert User's Guide. This guide contains information assist Actel's Silicon Expert tool. DeskTOP Interface Guide. This guide contains information about using integrated VeriBest® Synplicity®CAE software tools with
Introduction
Actel Designer Series FPGA development tools create designs Actel Devices. Cadence Interface Guide. This guide contains information assist design Actel devices using Cadence software Designer Series software. Mentor Graphics Interface Guide. This guide contains information assist design Actel devices using Mentor Graphics software Designer Series software. Synopsys®Synthesis Methodology Guide. This guide contains preferred coding styles information assist design Actel devices using Synopsys software Designer Series software. Innoveda® eProduct Designer Interface Guide. This guide contains information assist design Actel devices using eProduct Designer software Designer Series software. Viewlogic® Powerview Interface Guide. This guide contains information procedures assist design Actel devices using Powerview software Designer Series software. Viewlogic® Workview Office® Interface Guide. This guide contains information procedures assist design Actel devices using Workview Office software Designer Series software. VHDL Vital Simulation Guide. This guide contains information assist simulating Actel designs using Vital compliant VHDL simulator. Verilog Simulation Guide. This guide contains information assist simulating Actel designs using Verilog simulator. Activator Programming System Installation User's Guide. This guide contains information about program debug Actel devices, including information about using Silicon Explorer diagnostic tool system verification. Silicon Sculptor User's Guide. This guide contains information about program Actel devices using Silicon Sculptor software device programmer.
viii
Introduction
Silicon Explorer Quick Start. This guide contains information about connecting Silicon Explorer diagnostic tool using perform system verification. Actel FPGA Data Book. This guide contains detailed specifications Actel device families. Information such propagation delays, device package pinout, derating factors, power calculations found this guide. Macro Library Guide. This guide provides descriptions Actel library elements Actel device families. Symbols, truth tables, module count included macros. Guide ACTgen Macros. This Guide provides descriptions macros that generated using Actel ACTgen Macro Builder software.
Online Help
Designer Series software comes with online help. Online help specific each software tool available Designer, ACTgen, Silicon Expert, Silicon Explorer, Silicon Sculptor, APSW. Online help also available within Veribest software tools Synplicity Synplify® software.
Setup
This chapter contains information about directory structure Verilog libraries setting Verilog libraries simulating Actel designs. Refer documentation included with your Verilog simulator information about setting your simulation tool.
Software Requirements
information this guide applies Actel Designer Series software release R1-2000 later IEEE-1364-compliant Verilog simulators. Additionally, this guides contains information about using UNIX V-System ModelSim simulators UNIX Mentor Graphics QuickHDL simulator. specific information about which versions this release supports, Guru automated technical support system Actel site (http://www.actel.com/guru) type following Keyword box:
third party
using HP-UX, must also following variable:
setenv SHLIB_PATH $ALSDIR/lib
Refer Designer User's Guide documentation included with your simulation tool additional information about setting environment variables.
Verilog Libraries
Actel Verilog libraries contain Verilog models each Actel macro Actel families. Verilog libraries installed directories.
Migration Libraries
addition standard Actel libraries, Actel provides migration libraries. These libraries contain macros supported 3.1.1u1
Chapter Setup
earlier versions Designer Series software macros possibly needed retarget designs from different Actel family. Actel does recommend using migration libraries designs. Verilog migration libraries installed directories.
Compiling Verilog Libraries
Before simulating design with V-System, ModelSim, Mentor Graphics QuickHDL Verilog simulator, must compile Actel Verilog libraries. This section describes procedures. Refer documentation included with your simulation tool additional information about compiling libraries.
ModelSim V-System
following procedure compile Verilog libraries ModelSim V-System simulators. Type UNIX commands UNIX prompt. Type commands command line Transcript window. commands below make commands work UNIX, forward slashes instead back slashes. Create directory called "mti" "$ALSDIR\lib\vlog" directory. Invoke simulator only). Change "$ALSDIR\lib\vlog\mti" directory. Type following command:
$ALSDIR\lib\vlog\mti
Create <act_fam> family library directory simulator. Type following command:
vlib <act_fam>
Compile Actel library. Type following command:
vlog -work <act_fam> $ALSDIR\lib\vlog\<act_fam>\*.v
Compiling Verilog Libraries
(Optional) Compile Migration library. Only perform this step using migration library. Type following command:
vlog -work <act_fam>
Mentor Graphics QuickHDL Simulator
following procedure compile Verilog libraries Mentor Graphics QuickHDL simulator. Create directory called "qhdl" "$ALSDIR/lib/vlog" directory. Change "$ALSDIR/lib/vlog/qhdl" directory. Type following command:
$ALSDIR/lib/vlog/qhdl
Create <act_fam> family library directory simulator. Type following command:
qhlib <act_fam>
Compile Actel family models. Type following command:
qvlcom -work <act_fam> $ALSDIR/lib/vlog/<act_fam>/*.v
(Optional) Compile Migration library. Only perform this step using migration library. Type following command:
qvlcom -work <act_fam>
Design Flow
This chapter describes design flow creating Actel designs using Verilog simulation Designer Series software.
Actel-Verilog Design Flow Illustrated
Figure shows design flow Actel device using software, Verilog simulation tool, Designer Series software1.
Design Creation/Verification Behavioral Verilog
Verilog Libraries
Standard Verilog Test Bench
ACTgen
Macro Builder
Verilog Synthesis Tool/ Schematic Capture Tool
Netlist Translation (Optional) EDIF Netlist
Verilog Simulator
Functional/Structural/Timing Simulation
edn2vlog
Structural Verilog Netlist Timing File
Design Implementation
Export Command File Menu
Compile
Layout
Fuse
User Tools
PinEdit ChipEdit Timer Back Annotate
Programming
Fuse File
Software Activator 2/2s Programmer Silicon Sculptor
Actel Device System Verification
Sprint Data
System General Microsystems
Silicon Explorer
Figure 2-1. Actel-Verilog Design Flow
grey boxes Figure denote Actel-specific utilities/tools.
Chapter Design Flow
Actel-Verilog Design Flow Overview
Actel-Verilog design flow four main steps: Design Creation/Verification Design Implementation Programming System Verification
following sections describe these steps.
Design Creation/ Verification
During design creation/verification, design captured schematic RTL-level (behavioral) Verilog source file. your design Verilog source file, perform behavioral simulation verify that code correct. code then synthesized into Actel gate-level (structural) Verilog netlist. After synthesis, perform structural simulation design. Finally, generate EDIF netlist Designer structural Verilog netlist structural timing simulation. your design schematic, generate EDIF netlist Designer structural Verilog netlist structural timing simulation. perform behavioral simulation synthesis. Design Capture Enter your schematic using third-party schematic-capture tool create your Verilog source file using text editor contextsensitive editor. Your Verilog design source contain RTLlevel constructs, well instantiations structural elements, such ACTgen macros. Refer documentation included with your design-capture tool information about design capture. Behavioral Simulation Perform behavioral simulation your design before synthesis. Behavioral simulation verifies functionality your Verilog code. standard Verilog testbench drive simulation. Refer "Behavioral Simulation" page
Actel-Verilog Design Flow Overview
documentation included with your simulation tool information about performing functional simulation. Synthesis After have created your Verilog source file, must synthesize before placing-and-routing Designer. Synthesis transforms Verilog source file into gate-level netlist optimizes design target technology. Refer documentation included with your synthesis tool information about performing design synthesis. EDIF Netlist Generation After have created, synthesized your design source file), verified your design, must generate EDIF netlist place-and-route Designer. your design Verilog source file, EDIF netlist generate structural Verilog netlist. Refer "Generating EDIF Netlist" page documentation included with your schematic-capture synthesis tool information about generating EDIF netlist. Structural Verilog Netlist Generation Generate structural Verilog netlist from your EDIF netlist structural timing simulation either exporting from Designer using Actel "edn2vlog" program. Refer "Generating Structural Verilog Netlist" page information about generating structural netlist. Structural Simulation Perform structural simulation your design before placing-androuting Structural simulation verifies functionality your structural Verilog netlist. default unit delays included Verilog libraries every gate. Refer "Structural Simulation" page documentation included with your simulation tool information about performing structural simulation.
Design Implementation
During design implementation, place-and-route design using Designer. Additionally, perfrom static-timing analysis
Chapter Design Flow
design Designer with Timer tool. After place-and-route, perform postlayout (timing) simulation with Verilog simulator. Place-and-Route Designer place-and-route your design. Make sure specify Verilog Naming Style when importing EDIF netlist into Designer. Refer Designer User's Guide information about using Designer. Static-Timing Analysis Timer tool Designer perform static-timing analysis your design. Refer Timer User's Guide information about using Timer. Timing Simulation Perform timing simulation your design after placing-and-routing Timing simulation requires information extracted from Designer, which overrides default unit delays Actel Verilog libraries. Refer "Timing Simulation" page documentation included with your simulation tool information about performing timing simulation.
Programming
Program device with programming software hardware from Actel supported third-party programming system. Refer Designer User's Guide Activator Programming System Installation User's Guide Silicon Sculptor User's Guide information about programming Actel device.
System Verification
perform system verification programmed device using Actel Silicon Explorer diagnostic tool. Refer Activator Programming System Installation User's Guide Silicon Explorer Quick Start information about using Silicon Explorer.
Generating Netlists
This chapter describes procedures generating EDIF structural Verilog netlists.
Generating EDIF Netlist
After capturing your schematic synthesizing your design, generate EDIF netlist from your schematic-capture synthesis tool. EDIF netlist place-and-route Designer. Refer documentation included with your schematic-capture synthesis tool information about generating EDIF netlist. Make sure specify Verilog naming style when importing EDIF netlist into Designer.
Generating Structural Verilog Netlist
generate structural Verilog netlist using Designer "edn2vlog" program. structural Verilog netlist structural timing simulation. generate structural Verilog netlist using Designer, Invoke Designer. Import EDIF netlist. Choose Import Netlist File command from File menu. Import Netlist dialog displayed. Specify EDIF Netlist Type, GENERIC Edif flavor, Verilog Naming Style. Type full path name your EDIF netlist Browse button select your design. Click Export structural Verilog netlist. Choose Export command from File menu then choose Netlist. Export Netlist File dialog displayed. pull-down menu, click Verilog Files (*.v) enter name Verilog file want save.
Chapter Generating Netlists
generate structural netlist using edn2vlog, Change directory that contains EDIF netlist. Type following command UNIX prompt:
edn2vlog FAM:{<act_fam>} VLGOUT:<Verilog_File> <design_name>
"EDNIN" option specifies EDIF input file(s). specify multiple files with delimiter between file names. default EDIF input file <design_name>.edn. "VLOGOUT" option specifies Verilog output file names. default Verilog output file <design_name>.v. "SIMTEMP" option instructs program generate Verilog stimulus template file. specify this option, program does generate stimulus file.
Interpreted Simulation
This chapter describes procedures performing functional (behavioral structural) timing simulation Actel design using tools that either interpret library design files compile them on-the-fly. Cadence Verilog-XL, Simucad SilosIII, Synopsys simulators this category. This chapter includes information about creating testbench information about creating command file simulation batch mode. Also, this chapter includes description some common Verilog simulation switches. Refer documentation included with your simulation tool additional information about testbenches, command files, switches, simulation.
Example Testbench
testbench apply test vectors patterns design during simulation compare input output patterns. file instantiate top-level design, using Verilog-predefined command, such "$readmemb," "$monitor," "$display." testbench, must current project directory. following example testbench:
'timescale 1ns/100ps module test; //Inputs outputs declaration wire //Instantiate module your design test module <top_module> <instance_name> (.Pin List.); //stimulus patterns initial begin endmodule
Chapter Interpreted Simulation
Example Command File
command file batch simulation. Your command file should include command variables Verilog switches want during simulation. following example command file:
<test_bench>.v <design_name>.v <verilog_switch_1> <verilog_switch_n>
<design_name>.v variable Verilog top-level design that includes design sublevels. This variable represent behavioral Verilog design function simulation gate-level Verilog design structural timing simulation. <verilog_switch_1> <verilog_switch_n> variables represent Verilog switches that your command line during simulation. Refer "Verilog Switches" page information about available Verilog switches.
Behavioral Simulation
following procedure perform behavioral simulation design. Refer documentation included with your simulation tool additional information about performing behavioral simulation. Create modify testbench. Make sure your testbench timescale definition added following example timescale definition:
'timescale 1ns/100ps
Refer "Example Testbench" page information about creating testbenches. Create modify command file. command file only necessary running batch simulation. Refer "Example Command File" page information.
Structural Simulation
Simulate design. your design Verilog design, make sure that simulate your behavioral Verilog source file. Invoke Verilog simulator typing following command:
<verilog_executable> <test_bench>.v <design_name>.v $ALSDIR/lib/vlog/<act_fam> +libext+.v
using migrations libraries, type following command:
<verilog_executable> <test_bench>.v <design_name>.v $ALSDIR/lib/vlog/<act_fam> $ALSDIR/lib/vlog/<act_fam>_mig +libext+.v
"-y" "+libtext+" options Verilog switches that your command line during simulation. Refer "Verilog Switches" page information. simulate design using command file, invoke Verilog simulator typing following command:
<verilog_executable> <command_file>
"-f" switch necessary using command file simulate design.
Structural Simulation
following procedure perform structural simulation design. Refer documentation included with your simulation tool additional information about performing structural simulation. Create modify testbench. Make sure your testbench timescale definition added following example timescale definition:
'timescale 1ns/100ps
Refer "Example Testbench" page information about creating testbenches.
Chapter Interpreted Simulation
Create modify command file. command file only necessary running batch simulation. Refer "Example Command File" page information. Simulate design. your design Verilog design, make sure that simulate structural Verilog netlist that generated using Designer "edn2vlog" program. Invoke Verilog simulator typing following command:
<verilog_executable> <test_bench>.v <design_name>.v $ALSDIR/lib/vlog/<act_fam> +libext+.v
using migrations libraries, type following command:
<verilog_executable> <test_bench>.v <design_name>.v $ALSDIR/lib/vlog/<act_fam> $ALSDIR/lib/vlog/<act_fam>_mig +libext+.v
"-y" "+libtext+" options Verilog switches that your command line during simulation. Refer "Verilog Switches" page information. simulate design using command file, invoke Verilog simulator typing following command:
<verilog_executable> <command_file>
"-f" switch necessary using command file simulate design.
Timing Simulation
following procedure perform timing simulation design. Refer documentation included with your simulation tool additional information about performing timing simulation. Place-and-route your design Designer. Refer Designer User's Guide information about placing-and-routing design using Designer.
Timing Simulation
Extract timing information your design from Designer. From File menu, click Export. Then, click Timing Files. Choose click Save click Back Annotate). Back Annotate dialog displayed. Create <design_name>.sdf file specifying type. Click Create modify testbench. Make sure your testbench "sdf_annotate" construct following example testbench with construct line:
'timescale 1ns/100ps module test; //Inputs outputs declaration wire //Instantiate module your design test module <top_module> <instance_name> (.Pin List.); //stimulus patterns initial begin //Invoke routine back annotate initial endmodule
"<instance_name>" variable top-level instance name. Refer "Example Testbench" page information about creating testbenches. Create modify command file. command file only necessary running batch simulation. Refer "Example Command File" page information about creating command files. (VCS Only) Create table. table text file that contains commands VCS. following example
Chapter Interpreted Simulation
table called "sdf.tab" that uses module "test" testbench example step
$sdf_annotate call=sdf_annotate_call acc+=tchk,mp,mip,prx:test+
Refer documentation information about creating table. Simulate design. your design Verilog design, make sure that simulate structural Verilog netlist that generated using Designer "edn2vlog" program. Invoke Verilog simulator typing following command (for VCS):
<test_bench>.v <design_name>.v $ALSDIR/lib/vlog/ <act_fam> +libext+.v sdf.tab
using migrations libraries, type following command:
<test_bench>.v <design_name>.v $ALSDIR/lib/vlog/ <act_fam> $ALSDIR/lib/vlog/<act_fam>_mig +libext+.v sdf.tab
other simulators:
<verilog_executable> <test_bench>.v <design_name>.v $ALSDIR/lib/vlog/<act_fam> +libext+.v
using migrations libraries, type following command:
<verilog_executable> <test_bench>.v <design_name>.v $ALSDIR/lib/vlog/<act_fam> $ALSDIR/lib/vlog/<act_fam>_mig +libext+.v
"-y" "+libtext+" options Verilog switches that your command line during simulation. Refer "Verilog Switches" page information. simulate design using command file, invoke Verilog simulator typing following command:
Verilog Switches
<verilog_executable> <command_file>
"-f" switch necessary using command file simulate design.
Verilog Switches
This section defines gives usage examples some common Verilog switches simulators that interpret design files compile files on-the-fly. Refer documentation included with your Verilog simulation tool additional information about using switches during simulation.
Minus Switches
Table defines gives usage examples Verilog minus switches. Table 4-1. Minus Switches Switch
Definition
Stop option; initiates entry into interactive mode after successful design compilation. Accelerated option; directs accelerated, declared elements simulate accelerated mode (Verilog-XL only). Compile only option; compiles text code data file exits simulation mode. Decompile option; retargets data files into existing text files. Command argument file option; reads invocation command from text file. file option. Library directory option; specifies target library directory.
Chapter Interpreted Simulation
Plus Switches
Table defines gives usage examples Verilog plus switches. Table 4-2. Plus Switches Switch
+libext+ +delay_mode_path +delay_mode_unit +delay_mode_zero +mindelays +maxdelays +typdelays Used with switch. Specifies path delay model simulation. Specifies unit delay model simulation. Functional simulation option; specifies zero delay model simulation. Back-annotation option; selects minimum delay simulation. Back-annotation option; selects maximum delay simulation. Back-annotation option; selects typical delay simulation.
Definition
Simulation with V-System ModelSim
This chapter describes procedures performing functional (behavioral structural) timing simulation Actel design using commands Model Technology V-System ModelSim simulator. Refer documentation included with your simulation tool information about simulating design using graphical user interface.
Behavioral Simulation
following procedure perform behavioral simulation design using V-System ModelSim simulator. Type UNIX commands UNIX prompt. Type commands command line Transcript window. commands below make commands work UNIX, forward slashes instead back slashes. Invoke simulator only). Change directory your project directory. This directory must include your Verilog design files testbench. Type following command:
<project_dir>
Create "work" directory. Type following command:
vlib work
Compile your design source testbench file(s). Before simulating your design, must compile source files testbench. hierarchical designs, compile lower-level design blocks before higher-level design blocks. Type following commands:
vlog <behavioral_design_file>.v vlog <test_bench>.v
Chapter Simulation with V-System ModelSim
Simulate your design. Type following command:
vsim <topmost_module_name>
example:
vsim test_adder_behave
module test_adder_behave testbench will simulated. Actel macros instantiated your Verilog source, following command simulate your design with compiled Actel Verilog library.
vsim $ALSDIR\lib\vlog\mti\<act_fam> <topmost_module_name>
Structural Simulation
following procedure perform structural simulation design using V-System ModelSim simulator. Type UNIX commands UNIX prompt. Type commands command line Transcript window. commands below make commands work UNIX, forward slashes instead back slashes. Invoke simulator only). Change directory your project directory. This directory must include your Verilog design files testbench. Type following command:
<project_dir>
Create "work" directory. only need create work directory using different project directory than used behavioral simulation. Type following command:
vlib work
Compile structural netlist testbench. have already generated structural Verilog netlist, "Generating
Timing simulation
Structural Verilog Netlist" page procedure. Type following commands:
vlog <structural_netlist>.v vlog <test_bench>.v
Simulate your design. Type following commands:
vsim $ALSDIR\lib\vlog\mti\<act_fam> <topmost_module_name>
example:
vsim $ALSDIR\lib\vlog\mti\42mx test_adder_structure
module test_adder_structure testbench will simulated using compiled 42MX Verilog library.
Timing simulation
following procedure perform timing simulation design using V-System ModelSim simulator. Type UNIX commands UNIX prompt. Type commands command line Transcript window. commands below make commands work UNIX, forward slashes instead back slashes. Place-and-route your design Designer. Refer Designer User's Guide information about placing-and-routing design using Designer. Extract timing information your design from Designer. Choose Export command from File menu click Back Annotate. Extract dialog displayed. Create <design_name>.sdf file choosing option from pull-down menu. Click Invoke simulator only). Change directory your project directory. This directory must include your Verilog design files testbench. Type following command:
<project_dir>
Chapter Simulation with V-System ModelSim
Create "work" directory. only need create work directory using different project directory than used behavioral structural simulation. Type following command:
vlib work
Compile structural netlist testbench. have already generated structural Verilog netlist, "Generating Structural Verilog Netlist" page procedure. Type following commands:
vlog <structural_netlist>.v vlog <test_bench>.v
Simulate your design using timing information contained file. Type following command:
vsim $ALSDIR\lib\vlog\mti\<act_fam> -sdf[max|typ|min] /<region>=<design name>.sdf <topmost_module_name>
<region> option specifies region path) instance design where back annotation begins. specify particular FPGA instance larger system design testbench that wish back annotate. example:
vsim $ALSDIR\lib\vlog\mti\42mx -sdfmax /uut=adder.sdf test_adder_structural
this example, module "adder" been instantiated instance "uut" testbench. module named "test_adder_structural" testbench will simulated using maximum delays specified file.
Simulation with Mentor Graphics QuickHDL
This chapter describes procedures performing functional (behavioral structural) timing simulation Actel design using commands Mentor Graphics QuickHDL simulator. Refer documentation included with your simulation tool information about simulating design using graphical user interface.
Behavioral Simulation
following procedure perform behavioral simulation design using Mentor Graphics QuickHDL simulator. Change directory your project directory. This directory must include your Verilog design files testbench. Type following command:
<project_dir>
Create "work" directory. Type following command:
qhlib work
Compile your design source testbench file(s). Before simulating your design, must compile source files testbench. hierarchical designs, compile lower-level design blocks before higher-level design blocks. Type following commands:
qvlcom <behavioral_design_file>.v qvlcom <test_bench>.v
Simulate your design. Type following command:
qhsim <topmost_module_name>
example:
qhsim test_adder_behave
module test_adder_behave testbench will simulated.
Chapter Simulation with Mentor Graphics QuickHDL
Actel macros instantiated your Verilog source, following command simulate your design with compiled Actel Verilog library.
qhsim $ALSDIR/lib/vlog/qhdl/<act_fam> <topmost_module_name>
Structural Simulation
following procedure perform structural simulation design using Mentor Graphics QuickHDL simulator. Change directory your project directory. This directory must include your Verilog design files testbench. Type following command:
<project_dir>
Create "work" directory. only need create work directory using different project directory than used behavioral simulation. Type following command:
qhlib work
Compile structural netlist testbench. have already generated structural Verilog netlist, "Generating Structural Verilog Netlist" page procedure. Type following commands:
qvlcom <structural_netlist>.v qvlcom <test_bench>.v
Simulate your design. Type following commands:
qhsim $ALSDIR/lib/vlog/qhdl/<act_fam> <topmost_module_name>
example:
qhsim $ALSDIR/lib/vlog/qhdl/42mx test_adder_structure
module test_adder_structure testbench will simulated using compiled 42MX Verilog library.
Timing simulation
Timing simulation
following procedure perform timing simulation design using Mentor Graphics QuickHDL simulator. Place-and-route your design Designer. Refer Designer User's Guide information about placing-and-routing design using Designer. Extract timing information your design from Designer. From File menu, click Export. Then, click Timing Files. Choose click Save click Back Annotate). Back Annotate dialog displayed. Create <design_name>.sdf file specifying type. Click Change directory your project directory. This directory must include your Verilog design files testbench. Type following command:
<project_dir>
Create "work" directory. only need create work directory using different project directory than used behavioral structural simulation. Type following command:
qhlib work
Compile structural netlist testbench. have already generated structural Verilog netlist, "Generating Structural Verilog Netlist" page procedure. Type following commands:
qvlcom <structural_netlist>.v qvlcom <test_bench>.v
Simulate your design using timing information contained file. Type following command:
qhsim $ALSDIR\lib\vlog\qhdl\<act_fam> -sdf[max|typ|min] /<region>=<design name>.sdf <topmost_module_name>
Chapter Simulation with Mentor Graphics QuickHDL
<region> option specifies region path) instance design where back annotation begins. specify particular FPGA instance larger system design testbench that wish back annotate. example:
qhsim $ALSDIR\lib\vlog\qhdl\42mx -sdfmax /uut=adder.sdf test_adder_structural
this example, module "adder" been instantiated instance "uut" testbench. module named "test_adder_structural" testbench will simulated using maximum delays specified file.
Product Support
Actel backs products with various support services including Customer Service, Customer Applications Center, site, site, electronic mail, worldwide sales offices. This appendix contains information about contacting Actel using these support services.
Actel U.S. Toll-Free Line
Actel toll-free line contact Actel sales information, technical support, requests literature about Actel Actel products, Customer Service, investor information, using Action Facts service. Actel toll-free line (888) 99-ACTEL.
Customer Service
Contact Customer Service nontechnical product support, such product pricing, product upgrades, update information, order status, authorization. From Northeast North Central U.S.A., call (408) 522-4480. From Southeast Southwest U.S.A., call (408) 522-4480. From South Central U.S.A., call (408) 522-4434. From Northwest U.S.A., call (408) 522-4434. From Canada, call (408) 522-4480. From Europe, call (408) 522-4252 1256 305600. From Japan, call (408) 522-4743. From rest world, call (408) 522-4743. Fax, from anywhere world (408) 522-8044.
Appendix Product Support
Customer Applications Center
Actel staffs Customer Applications Center with highly skilled engineers help answer your hardware, software, design questions. Applications Center spends great deal time creating application notes answers FAQs. before contact please visit online resources. very likely have already answered your question(s).
Guru Automated Technical Support
Guru web-based automated technical support system accessible through Actel home page (http://www.actel.com/guru/). Guru provides answers technical questions about Actel products. Many answers include diagrams, illustrations, links other resources Actel site. Guru available hours day, seven days week.
Site
Actel World Wide home page where browse variety technical nontechnical information. browser (Netscape recommended) access Actel's home page. http://www.actel.com. welcome share resources provided Internet. sure visit "Actel User Area" site, which contains information regarding products, technical services, current manuals, release notes.
Site
Actel anonymous site located ftp://ftp.actel.com. Here obtain library updates, software patches, design files, data sheets.
Contacting Customer Applications Center
Contacting Customer Applications Center
Highly skilled engineers staff Customer Applications Center from 7:30 A.M. 5:00 P.M., Pacific Time, Monday through Friday. Several ways contacting Center follow:
Electronic Mail
communicate your technical questions e-mail address receive answers back e-mail, fax, phone. Also, have design problems, e-mail your design files receive assistance. constantly monitor e-mail account throughout day. When sending your request please sure include your full name, company name, your contact information efficient processing your request. technical support e-mail address tech@actel.com.
Telephone
Technical Message Center answers calls. center retrieves information, such your name, company name, phone number your question, then issues case number. Center then forwards information queue where first available application engineer receives data returns your call. phone hours from 7:30 A.M. 5:00 A.M., Pacific Time, Monday through Friday. Customer Applications Center number (800) 262-1060. European customers call 1256 305600.
Appendix Product Support
Worldwide Sales Offices
Headquarters
Actel Corporation East Arques Avenue Sunnyvale, California 94086 Toll Free: 888.99.ACTEL Tel: 408.739.1010 Fax: 408.739.1540
Sales Offices
California Area Tel: 408.328.2200 Fax: 408.328.2358 Irvine Tel: 949.727.0470 Fax: 949.727.0476 Diego Tel: 619.938.9860 Fax: 619.938.9887 Thousand Oaks Tel: 805.375.5769 Fax: 805.375.5749 Colorado Tel: 303.420.4335 Fax: 303.420.4336 Florida Tel: 407.677.6661 Fax: 407.677.1030 Georgia Tel: 770.831.9090 Fax: 770.831.0055 Illinois Tel: 847.259.1501 Fax: 847.259.1572 Maryland Tel: 410.381.3289 Fax: 410.290.3291 Massachusetts Tel: 978.244.3800 Fax: 978.244.3820 Minnesota Tel: 612.854.8162 Fax: 612.854.8120 North Carolina Tel: 919.376.5419 Fax: 919.376.5421 Pennsylvania Tel: 215.830.1458 Fax: 215.706.0680 Texas Tel: 972.235.8944 Fax: 972.235.965
International Sales Offices
Canada Suite Michael Cowpland Kanata, Ontario Tel: 613.591.2074 Fax: 613.591.0348 France Avenue General Gaulle 92147 Clamart Cedex Tel: (0)1.40.83.11.00 Fax: (0)1.40.94.11.04 Germany Bahnhofstrasse 85375 Neufahrn Tel: (0)8165.9584.0 Fax: (0)8165.9584.1 Hong Kong Suite 2206, Parkside Pacific Place, Queensway Tel: +011.852.2877.6226 Fax: +011.852.2918.9693 Italy Giovanni Udine 20156 Milano Tel: (0)2.3809.3259 Fax: (0)2.3809.3260 Japan EXOS Ebisu Building 1-24-14 Ebisu Shibuya-ku Tokyo Tel: (0)3.3445.7671 Fax: (0)3.3445.7668 Korea 135-090, 18th Floor, Kyoung Building 157-27 Samsung-dong Kangnam-ku, Seoul Tel: (0)2.555.7425 Fax: (0)2.555.5779 Taiwan 4F-3, Sec. Hsin-Tai-Wu Road, Hsi-chih, Taipei, Tel: +886 (0)2.698.2525 Fax: +886 (0)2.698.2548 United Kingdom Daneshill House, Lutyens Close Basingstoke, Hampshire RG24 Tel: (0)1256.305600 Fax: (0)1256.355420
Index
Accessing Migration Libraries Verilog Libraries Actel Site Manuals Site Web-Based Technical Support Assumptions Design Creation/Verification Behavioral Simulation Design Capture EDIF Netlist Generation Structural Netlist Generation Structural Simulation Synthesis Design Flow Programming System Verification Design Implementation Place-and-Route Timing Simulation Design Layout Design Synthesis Designer EDIF Option Extracting Timing Information GENERIC Option Place-and-Route Software Installation Directory Structural Netlist Generation Verilog Option Device Programming Verification Document Assumptions Organization Document Conventions
Back-Annotating Delays Behavioral Simulation
Capturing Design Command File Compiling Verilog Libraries Contacting Actel Customer Service Electronic Mail Technical Support Toll-Free Web-Based Technical Support Conventions Document Creating Command File File 15-22 Stimulus File Creating Testbench Customer Service
EDIF Netlist Generation EDIF Option edn2vlog Electronic Mail
Delays
Index
Example Testbench page Extracting Timing Information 15-22
Netlist Generation EDIF Gate-Level Structural
File Command Stimulus Functional Simulation
Online Help
Gate-Level Netlist Generating EDIF Netlist Gate-Level Netlist Structural Netlist GENERIC Option
Place-and-Route Plus Switches Product Support 27-30 Customer Applications Center Customer Service Electronic Mail Site Technical Support Toll-Free Line Site Programming Device
Installation Directory Designer Migration Libraries Verilog Libraries
Related Manuals Required Software
Libraries Compiling Migration Verilog
Schematic Capture file 15-22 sdf_annotate Setup Procedures User Setup Simulation Behavioral Functional Mentor Graphics 23-26
Migration Library Installation Directory Minus Switches
Index
Model Technology 19-22 SilosIII 11-17 Structural Synthesis-Based Timing 11-17 Verilog-XL 11-17 Software Requirements Stimulus File Structural Netlist Generation Designer EDIF Option edn2vlog GENERIC Option Structural Simulation Mentor Graphics Model Technology V-System Simulator Verilog Switches 17-18 Minus Plus Synthesis System Requirements System Verification Silicon Explorer
Unit Delays User Setup
Verilog Back-Annotating Delays Behavioral Simulation Libraries Option Option Designer Structural Simulation Switches 17-18 Timing Simulation Verilog Design Flow Design Implementation Programming Verilog Source Entry Verilog Libraries Compiling Verilog Library Installation Directory
Web-Based Technical Support
Technical Support Testbench Timescale Definition Timing Information 15-22 File 15-22 Timing Simulation Toll-Free Line

Simulation Guide Windows UNIX® Environments Actel Corporatio

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