Reliability Handbook FOREWORD Analog Devices, Inc. would lik
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Reliability Handbook
Reliability Handbook
FOREWORD
Analog Devices, Inc. would like thank customers making leading supplier highquality LSI, VLSI, ULSI integrated circuits choosing products their design solutions. While products innovative leading-edge from design perspective, they also, based reliability data, exceptionally robust meet industry standards their high reliability. broad range applications integrated circuit technology driven customers' quality reliability requirements extremely high levels these challenges. With extensive variety programs ensure high quality reliability, meets customers' existing emerging needs true spirit Total Quality Management (TQM). This Reliability Handbook introduces customers potential customers research, technological developments, quality/reliability philosophy, programs employed Analog Devices. hope readers find informative that manual becomes standard reference they will find helpful should they wish similar procedures. reserves right modify manual time. This handbook published reference guide interpreted guarantee that certain products meet criteria defined here. specific information regarding dedicated products, please refer applicable data specification sheet.
INTRODUCTION Purpose
purpose this page focus activities criteria that uses produce very reliable high-quality products that meet customers' requirements. site also designed convey embedded philosophies quality reliability that embodied every step manufacturing process personnel. Also discussed ADI's commitment customers' needs quest excellence through continuous improvement levels design, manufacturing, support areas company.
Reliability Charter
always placed highest emphasis delivering products that meet customer's total requirements and, result, generate complete customer satisfaction-critical success survival today's integrated circuit industry. This achieved incorporating quality reliability checks only realms product process design, manufacturing process well. This achieved through careful planning design phases development equipment introduction into facilities utilizing communication teamwork. strongly believes necessity cross-functional teams contributions individuals attain excellence quality reliability. employees committed quality reliability goals company continually improving quality reliability Analog's processes services global basis. Consequently, ADI's policy statement quality placed meeting rooms prominent positions throughout plant remind employees that quest total customer satisfaction continual every employee responsibility ensuring quality objectives Analog Devices.
Quality Policy Statement
"Analog Devices committed establishment continuous improvement world class systems processes aimed satisfying customers' evolving needs. embrace total quality philosophy with emphasis prevention rather than detection. focus technology, quality, reliability, service costs order make innovative solutions available customers minimized total cost."
Reliability Handbook
From this statement comes reliability goal:
"The charter reliability groups consistently strive ensure that reliability production, products processes developed meet exceed industry reliability requirements. This achieved working teams with development groups such wafer fabrication, product design, packaging focusing aspects product/process design, incorporating combined knowledge team with classical bathtub curve reliability statistics used describe reliability." addition introducing quality systems that full accordance with ISO9000 QS9000 procedures, continually seeking methodologies improve quality reliability through variety in-house internationally developed techniques. With customer satisfaction goal, continually focuses efforts meeting this objective. This handbook been developed keeping with this goal. Analog Devices leading manufacturer precision high-performance integrated circuits used analog digital signal processing applications. company organized into product lines with product line management structures each market segment. These product lines design manufacturing resources from number design manufacturing locations around world. These sites have exceptionally close linkages supported kept informed very capable worldwide sales force with office locations major population industrial centers. With design centers worldwide, corporate headquarters Analog Devices North America: Analog Devices, Inc. Three Technology Norwood, 02062 U.S.A. ADI's other major U.S. manufacturing locations: Woburn Street Wilmington Massachusetts 01187-3462 Woburn Street Wilmington Massachusetts 01187-4601 Willow Street North Andover Massachusetts 01845 ADI's major overseas manufacturing locations: KM-14, Edision Avenue South Expressway, Paranque Metro Manila Philippines 9-1, Kung, Road Wu-Ku Industrial Park Hsin Chung City Taipei Hsien Taiwan, R.O.C Osborn Street Cambridge Massachusetts 02139-3556 7910 Triad Centre Drive Greensboro North Carolina 27409-9605 1500 Space Park Drive P.O. 58020 Santa Clara, California 95052-8020 Raheen Industrial Estate Limerick Ireland
2000 Analog Devices, Inc., Norwood 02062 RIGHTS RESERVED Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices infringement patents other rights third parties that result from use. license granted implication otherwise under patent rights Analog Devices.
Reliability Handbook
Analog Devices also contracts with other wafer fabrication packaging facilities ongoing basis, needed. Consequently, maintains active program with vendors strives ensure that highest standards quality reliability achieved. this end, every vendor must comply with certification, qualification, predefined audit program part ADI's vendor assurance program. believes that excellence product process reliability comes from people design manufacture products processes. Upon joining company, Analog Devices employees undergo extensive training their particular functions, followed ongoing external/internal professional development.
PRODUCT PHILOSOPHY Introduction
achieved leadership position marketplace releasing innovative products that meet latent needs electronic industry. turn, these leading-edge products have become market leaders, setting standards future products. Produced various locations around world, these products serve illustrate strong teamwork that hallmark Analog Devices.
Table Examples ADI's Leading-Edge Products
Model AD7541 AD7816 AD7572 AD7008 AD5300 ADV7152 AD7714 ADG508F AD7723 AD7891 AD7472 ADG7xx AD7705/AD7706 ADSP-21160 SHARC® ADSP-21065 SHARC AD9054A AD9483 AD9772 AD9856 AD1881A/AD1885 AD6523/AD6524 AD8361 AD8016 AD8051/AD8052/AD8054 Leadership Position World's First 12-Bit CMOS Lowest-Power Temperature Control Converter Industry-Standard, 12-Bit, A-to-D Converter World's First Single-Chip Direct Digital Synthesizer World's First SOT-23 World's First True Color Computer Display RAMDAC Low-Power, 24-Bit Sigma Delta 8-Channel, Overvoltage, Fault-Protected Multiplexer Bandwidth, 16-Bit, Sigma-Delta World's Fastest Multiplexed 12-Bit Lowest-Power, 12-Bit IMSPS Lowest-Leakage, Lowest-RON Family Switches Lowest-Power, 16-Bit, Sigma-Delta Single-Instruction, Multiple Data Architecture Single-Instruction, Single Data Architecture 8-Bit, MSPS Triple 8-Bit, MSPS 14-Bit, MSPS TxDAC+with Interpolation Filter CMOS Quadrature Digital Upconverter AC'97 SoundMAX® Codec Direct Conversion Radio Chipset (OthelloTM) TruPwrDetector Low-Power, High-Output Current xDSL Line Driver Low-Cost, High-Speed, Rail-to-Rail Amplifiers
ADI's leadership position been realized through effective cross-functional teamwork product introduction policy that extremely proactive. This policy incorporates aspects product development cycle, culminating creation, agreement, execution qualification plan.
Reliability Handbook
Specific development teams design, introduction, qualification, release each product. During product development cycle, support group works with development teams ensure adherence continuous improvement procedures across aspects release process; provide centralized link between development areas manufacturing sites.
PROCESS PHASES MILESTONES
PSD0 REVIEW FEASIBILITY DESIGN START IMPLEMENTATION TAPE WAFER SILICON PACKAGING PACKAGING DETAILS PSD2 SIGN PSD1 SIGN
SAMPLES VALIDATION FINAL TAPE
FINAL SILICON RELEASE RELEASE PSD3 SIGN
PSD4
Figure Product Development Process There basically seven milestones release product within starting with design initiation ending with release product. process which each these milestones divided into five distinct phases: Feasibility Implementation Wafer Fabrication Packaging Validation Release step process deemed applicable development product, development team responsible documenting reasons. These phases outlined Figure Step development PSD0. This document review critical factors highlighting strengths weaknesses project. development team uses create high-quality PSD1.
Feasibility
feasibility study begins with product definition that come from number sources, such marketing, engineering, directly from customers. Once agreement been reached product definition feasibility, product lines then allocate generic model number accordance with corporate policy. upper management team sponsor appointed design team formed consisting limited Design, CAD, Manufacturing, Test, Quality, Reliability. During feasibility phase, design engineers assess meet market requirements, various architectures package options explored. manufacturing process selected, size estimates made, time frames established development release. This work allows product start document (PSD1) completed.
Reliability Handbook
During this stage various resources allocated project decisions made. in-depth architecture review conducted among project designers other design engineers outside project group secure balanced perspective proposed architecture. product team also convenes during this period decide characterization plan product allocate responsibilities. designer will supply high-level product simulation enable test engineer gain good understanding part will perform investigate Design Test (DFT) strategies. Prior completing product start document, design engineer will discuss with relevant assembly engineer issues related assembly. requirements also reviewed resources allocated this time. Once this step completed, PSD1 signed off. PSD1 controlled document signifies formal start project. outlines roles responsibilities team sponsor, leader, members. completing PSD, product release team must generate schedule development release product outlining resources required. test feasibility phase begins once assigned test engineer receives controlled copy data sheet. During this phase test engineer considers technical risks involved where possible effort made eliminate these risks. test engineer provides inputs design engineer give maximum coverage probe final test stages.
Implementation
Prior commencing detailed design, development team generates list simulations planned during design phase. These simulations become basis design review this point detailed design completed schematics produced. design engineer calls design review meeting which engineer shows that desired product performance achieved providing simulation data. changes required, design proceeds while characterization plans reviewed updated needed. layout begins accordance with specified design rules, additional simulations done achieve full-chip simulation. Also during this phase, burn-in, HAST (Highly Accelerated Stress Testing), (Temperature Humidity Bias) diagrams generated current density calculations electromigration completed. layout engineer then calls meeting review layout versus schematic, results automated checking procedure analyzed. test implementation phase occurs conjunction with design development. During this phase test plan (Device Under Test) board schematics generated sort final test. Using agreed-upon test plan, test engineer generates test code test boards. Following test review meeting, boards ordered test program completed. this point sign-off given stress test diagrams qualification plan generated product line along with appropriate reliability engineering group. manufacturing review then conducted manufacturing review checklist completed. issues arise, finishing completed masks generated.
Wafer Fabrication Phase
While wafers being fabricated, test wafer sort programs hardware being prepared along with stress test boards that required qualification. also during this phase that design engineer develops functionality testing capability while test engineer ports vectors onto target test system performs required test simulations. While wafers target wafer fabrication facility, their progress tracked monitored products coordinator.
Reliability Handbook
Design Validation
validation phase consists design test validation using very stringent criteria. receipt silicon from wafer fabrication group, responsibility design engineering group evaluate level functionality silicon, issue results regularly, generate functionality report. receipt report product development team will review performance decide appropriate course action. design evaluation been completed design engineer working with design evaluation group evaluates parameters decided characterization review meeting. this point design evaluation engineer issues design evaluation report which, conjunction with test engineering report, provides basis continuing with qualification redesigning product. Concurrently, latch-up also evaluated give indication product performance.
Test Validation Phase
During this phase test programs hardware debugged modifications made. hardware software stress testing during qualification also analyzed debugged. Simultaneously, samples collated reliability qualification testing agreed qualification plan designed part implementation phase. During test validation further program modification occurs yield analysis report generated review.
Release Phase
Assuming that criteria date achieved, product moves into release phase. formal latch-up qualification test performed well complete qualification testing dictated qualification plan. release inventory tested dispositioned release certificate generated signed. PSD4 document, which market survey product's performance versus expectations, produced approximately months after release. results from this survey back into product development process allowing continuous improvement. While above snapshot product process, other major milestones such provision samples data sheet generation also underway. major items receiving significant attention product schedule product qualification. This final hurdle overcome before product release Analog Devices very proactive qualification procedure based customer market requirements. Where applicable, customers provide input qualification plans that reflect their individual needs.
Qualification Planning
Analog Devices defined corporate qualification procedure that customer-driven. recognizes different market segments together with performance capabilities manufacturing processes they mature [1-8]. certified processes, qualified product design layout tools, continuous improvement standard. context process development, process change evaluation, evaluation products, approach philosophy prevent failure. certification work failure-mechanism driven, encourages qualified design rules software tools product development underscore this approach. development both characterization qualification plans significant process changes, processes, products team effort with relevant parties forming technical review board. board comprised vested parties well reliability engineers. This ADI's standard qualification plan development procedure; incorporated into product process just dedicated reliability engineer involved phases product development.
Reliability Handbook
table known potential failure mechanisms developed from which qualification plan generated based substitution data. This approach summarized Figure Once failure mechanisms identified, appropriate stress tests defined evaluated against suitable substitution data. deciding whether data applicable substitution, some items consider include: When Data Generated Sizes Used Package Types Used Details Layout Elements Introduced Passivation Type Laser Trim, etc. Design Rule Violations Process Developments Changes Once preceding questions answered, table failure mechanisms versus test methods generated similarity review conducted investigate applicability substitution data. This table then linked with process product change reliability test criteria matrix final qualification plan developed. qualification test list then feeds into another table that indicates appropriate package types used well test sequence Burn-In, Temperature Cycle, etc. Finally, detailed description each test supplied outlined Figure
TYPE CHANGE/NEW PRODUCT
EVALUATION FAILURE MECHANISMS
QUALIFICATION TEST LIST
REVIEW EQUIVALENT DATA
DEVELOP APPROVE QUALIFICATION PLAN USING SIMILARITY RULES
QUALIFICATION REVISED PRODUCT PROCESS FAILURE MECHANISM SIMILARITY REVIEW QUALIFICATION TEST LIST TEST GROUP TEST GROUP TEST GROUP TEST METHOD TEST METHOD TEST METHOD
TEST METHOD
Figure Qualification Philosophy
Reliability Handbook
Test Generation Method
This qualification planning methodology allows high-quality reliability decisions made about qualification process reliability criteria team project engineers who, nature their involvement, exceptionally knowledgeable these issues. Input aspects design, quality, process, reliability, manufacturing leads well-informed decision agreement from departments. ensures successful completion qualification adherence standards highest quality reliability. Once qualification been completed product released, product reliability report generated. This available upon request.
PRODUCT RELIABILITY MONITORING PREDICTION Introduction
Analog Devices maintains very active reliability monitoring program. operates state-of-the-art reliability testing laboratories major production facilities; smaller reliability test locations strategically located around world. monitoring program's objective provide assurance that product shipped highest quality. acknowledges that only snapshot production monitored. true reliability products cannot gauged reliability tests alone. Reliability tests restricted sample sizes test capacity. Other factors, such process control, total quality management, employee training education, design reliability building reliability programs all-important factors true evaluation reliability. However, because strongly believes that true reliability built designed company developed active monitoring programs targeted these areas.
Product/Process Reliability
question often asked reliability engineers "What makes reliable process know yours reliable?" answer often quite complex. facet reliability process that makes process product reliable, vast combination items such good product design methodology, good process development process control, consistency manufacturing. this chapter reliability prediction monitoring philosophy explained. founded giving customer utmost confidence reliability processes, based historical data conjunction with philosophies such Design Reliability, Building Reliability, well tight statistical process control processes materials.
Reliability Goals
reliability goals industry generally discussed conjunction with traditional bathtub curve shown Figure This curve shows failure rate products with respect time made three individual curves related constant failure rate, quality defects, wear-out.
BATHTUB CURVE EARLY LIFE FAILS
QUALITY FAILURES
USEFUL LIFE
STRESS-RELATED FAILURES
WEAROUT
WEAROUT FAILURES
TIME
Figure Classic Bathtub Curve
Reliability Handbook
Figure shows that curve follows classic bathtub shape (although this generalization). curve consists three distinct regions: Early Life, Useful Life, Wear-out. Each region characterized separately with potential failures classified quality failures, random failures, wear-out failures, respectively. early life failures process related, such defect-induced, would characterized decreasing failure rate. wear-out failures, other hand, inherent process limitations generally well characterized before process release. These failures would oxide wear-out, electromigration, electron effects, which limit life product. They generally have increasing failure rate. Random failures occur variety reasons usually account only very small number failures. They characterized constant failure rate. ideal shape curve have very long useful life period amount quality defects.
Product Reliability Stressing
integrated circuit potentially undergo number stresses during life, reliability stress tests have been designed evaluate effects these stresses over time. device shipped Analog Devices customer will assembled onto printed circuit board using thermal stresses into system automotive, military, commercial environments where will complete useful life. During lifetime, device will likely endure thermal, humidity, electrical stresses. Therefore, reliability testing must encompass types reliability stresses device will operate under order test meaningful evaluate product's ability resist such stresses. Stated another way, this implies that function reliability stress testing evaluate product will perform when used machines, systems, environments which manufactured. This evaluation reliability begins when device planning stage. works with customers study understand application environment which product will used establish appropriate levels quality reliability. These then built into product design manufacturing flows verified qualification stage product cycle. Because different types failures that occur, many different reliability stress tests applied product. Generally, they separated into electrical-, thermal-, moisture-related tests that have been developed refined over period time. Various models exist extrapolate accelerated test conditions useful life.
Reliability Testing Analog Devices
Analog Devices conducts major classes reliability tests each processes. These tests conducted conjunction with design stage extend levels production enable devices meet customer quality reliability requirements. process design product design stages, reliability issues such electromigration, TDDB, electrons characterized process level checked/verified product design phase provide robust product. tests discussed this section primarily product-related stress tests; process-related stress testing used identify verify wear-out mechanisms discussed section process reliability. product stress testing, main emphasis useful life section bathtub curve. test methodology used predict useful life period usually steady-state life test. This generally done under static dynamic bias steady-state temperature 125°C, 135°C, 150°C maximum specified voltage product. duration these temperatures 1,000, 750, hours, respectively. Analog Devices uses state-of-the-art microprocessor-based equipment. some instances equipment been designed engineers conjunction with vendors provide maximum versatility based operational needs product test. Accelerated tests performed products these results then extrapolated standard operating conditions.
Reliability Handbook
Since Analog uses these tests determine product failure rates, important understand these tests related standard operating conditions accelerated test conditions. quite common both temperature voltage acceleration. Before explaining why, important understand underlying statistical distribution [9-11] which exponential distribution well some related terms. basic reliability terms are: Unreliability F(t): expresses percentage population that will fail during time F(t) where number failing items total population Reliability R(t): expresses percentage population that will good during time R(t) (n-r)/n Failure Density f(t): expresses percentage population that will have failed unit time during time (t). f(t, Failure Rate (t): expresses percentage population that good until time will fail during next unit time. r/(n-r) Other terms include Mean Time Failure (MTTF MTBF) useful life. MTTF time period over which meaningful portion population will have failed. case exponential distribution with constant failure rate, around population will have failed MTTF exponential distribution applied constant failure rate determined alone, where failure rate. Mathematically simple deal with expresses useful life period bathtub curve with constant failure rate. result, used failure rate distribution failure rate sampling tests. also most fundamental distribution field reliability where: Probability Distribution Function f(t) Cumulative Distribution Function F(t) Failure Rate These distributions shown graphically Figure
Figure Exponential Distribution
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Device Testing
practical effective conducting long-term reliability testing generate long-term failure rates expose devices accelerated conditions voltage temperature periods time. Long-term reliability testing done microprocessor-controlled ovens ADI. These systems software-controlled with very accurate temperature voltage control. schematics also controlled coded into controllers. major advantage that systems fully operatorcontrolled; testing operations performed person, thus eliminating sources error these critical tests. test results generated these high conditions then extrapolated conditions. this extrapolation valid, requirements must met: accelerated test conditions should introduce failure mechanisms. accelerated test conditions, i.e., temperature and/or voltage, should generate failure mechanisms that would encountered under normal operating conditions. Extrapolation from accelerated conditions conditions must possible.
Temperature Acceleration
This acceleration factor, calculated using Arrhenius equation. Equation relates use/ application temperature part actual stress condition using activation energy (Ea). t1/t2 Exp. Ea/k (1/TTEST 1/TUSE)] where Mean Time Failure (MTTF) TTEST TUSE TTEST TUSE Test Acceleration Temperatures Kelvin Boltzmann's Constant 8.617 eV/K Thermal Activation Energy Specific Failure Mechanism (eV) Because nature test, variety products being tested, Analog Devices applies generic activation energy calculation based process characterization knowledge processes. uses average activation energy This quite conservative activation energy when looks Table below, which lists some typical failure mechanisms that could occur steady-state period their activation energies. Table Failure Mechanism Oxide Contamination Silicon Junction Defects (eV)
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Reliability Handbook
1000000 100000
FAILURE RATE
10000
1000
JUNCTION TEMPERATURE
Figure Failure Rate Junction Temperature equation also predicts reliability will degraded (increased failure rate) higher temperatures indicated Figure
Voltage Acceleration
Voltage-accelerated stress test results also translated nominal voltage conditions manner similar temperature conditions outlined above applying voltage acceleration factor (VAF). acceleration factor voltage stress approximated following exponential relationship: Exp. VU)] where stress voltage, respectively, volts constant value derived experimentally. rarely uses voltage acceleration; used, voltage acceleration constant derived from Time Dependent Dielectric Breakdown testing which equal
1.0E+07
1.0E+06 1.0E+05
ACC. FACTOR
1.0E+04 1.0E+03 1.0E+02 1.0E+01
1.0E+00
TEMPERATURE
Figure Acceleration Factor Temperature normally applies temperature acceleration only. This factor dependency temperature several activation energies shown Figure graph normalized hour testing 225°C.
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Reliability Handbook
Sample Failure Rate Calculation
There commonly used failure rate calculations: instantaneous average. average failure rate applied constant portion bathtub curve. device hours calculated based time products being life tested. appropriate junction temperatures acceleration factors calculated. Since majority products manufactured low-power CMOS ovens cater variety products, ambient temperature primarily used these calculations. Rather than calculate lifetimes each failure mechanism, uses standard activation failure rate calculation; each calculation Analog reports results upper confidence limits using squared tables. data generated generally reported FITs (Failures Time) which number failures device hours that then translated MTTF. Using this calculation methodology, infant mortality commonly reported simply proportion failures compared quantity tested. following example used illustrate calculation additional reliability data processes. found Table sample data collected CMOS process 125°C 135°C over 2000-, 1000-, 750-hour life test. Table III. Data Sampling Sample Size Hrs. Hrs. Hrs. Hrs. 1000 Hrs. 2000 Hrs.
Generic Model AD1845 AD1845 AD1845 AD6421 AD6421 AD6421 AD7015 AD7015 AD7015 AD7302
Test Temp
failure rate operating temperature T°C. expressed Nf/Ndt where Number Failures number device hours test temperature T°C. where number devices tested number hours testing acceleration factor between test use/application temperature.
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Reliability Handbook
Arrhenius equation Exp. {Ea/k (1/TTEST 1/TUSE)} applied find acceleration factors where measured acceleration factors 135°C 125°C 55°C (408 respectively, (assuming ambient temperature 55°C): 135°C 55°C 125°C 55°C voltage acceleration used, total acceleration factor (ATOT) found multiplying factors give ATOT VAF.) Applying these acceleration factors data above, equivalent device hours 55°C calculated 125°C 135°C. Table Test Temp 135°C 125°C Number Device Hrs. Test Temp 434750 211000 Temp 55°C 55°C Equivalent Device Hrs. 55648000 16247000 71895000
Total Equivalent Device Hrs.
failure rate expressed number ways: (Failures Time) Failure Rate reject 1000 Hrs.) MTTF (Mean Time Failure) 1/Fr failure rate essentially expected frequency failures while MTTF interval period between failures. calculation failure rate mentioned previously (Nf/Ndt) gives average expected failure rate meaning results confidence level parts will this rate better. However, because limitations test fact that small random samples chosen, statistical effects significant squared distribution used confidence intervals results. confidence intervals normally used 90%, respectively. Using squared table [12] failure rate calculated Failure Rate (Fr) v)/2 where Square Value times device hours 55°C squared value based particular type distribution found table where C.L.) where C.L. confidence level where number rejects
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Reliability Handbook
Using equivalent device hours generated above with zero failures calculation Failure Rate (Fr) v)/2Ndt C.I. Value 1.83 C.I. Value 4.61 C.I. 1.27 10-8 C.I. 10-8 Using these figures MTTF, rates calculated Table MTTF 78740157 (Hrs.) 30303030 (Hrs.)
Using data generated process from which above sample taken, actual rates MTTF figures Table MTTF MTTF 171212156 (Hrs.) 68132030 (Hrs.)
quick glance Annual Reliability Reports read/2ndpage1.html indicates type data collected from steady-state life testing conducted ADI. When doing MTTF failure calculations applying results system reliability, various issues must understood, especially when comparing vendor data. vendors using standard activation energy, this should realistic same activation energy should applied both calculations have significant impact thermal acceleration factor. important know sample sizes involved. sample sizes used small, equivalent device hours small resulting failure rate artificially high. also very important know use/application temperature product temperature which vendor derated again, this considerable impact calculated acceleration factor resultant failure rate. other predominant mathematical distributions associated with reliability engineering Weibull, Normal, Log-normal.
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Weibull Distribution
Weibull distribution [9-11] minimum value asymptotic distribution. used express distribution material breakdown strength very useful analysis lifetime data where failure time dependent weakest-link phenomena. this situation failure weakest component causes part system fail. Weibull used express wear-out period random failure period bathtub curve. distribution three basic parameters associated with shaping parameter scaling parameter location parameter equations, which describe Weibull distribution, follows: f(t) {[(t-)/]m-1} Exp. -(t-)/]m} F(t) Exp. -(t-)/]m} [(t-)/]m-1
Normal Distribution
normal distribution [9-11] basic statistical distribution primarily used analyze characteristic distributions variations either their initial design after defined period time. This distribution normally associated with statistical process control determined mean, standard deviation, equations, which define normal distribution, follows f(t) [1/(2)-0.5] Exp. {-0.5 [(t-µ)/]2} F(t) [1/(2)-0.5] Exp. {-0.5 [(t- )/]2}
normal distribution called standard distribution when mean variance this case f(t) F(t) follows: f(t) [1/(2)-0.5] Exp. (-0.5 F(t) (2)-0.5
Exp. (-0.5
Log-Normal Distribution
Once variable converted logarithm logarithmic distribution [9-11] generated. This follows normal distribution. measuring reliability used distribution lifetime maintenance time. distribution defined mean value standard deviation follows: f(t) [1/(2 -0.5 Exp. -0.5 (t-µ)/]2} F(t) [1/(2) -0.5] (1/x) Exp. {-0.5 [(ln (x-µ)/]2}
Which distribution given reliability situation defined data obtained goodness obtained data. Therefore, given failure mechanism, different models applied, depending process data obtained.
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Figure Bank Life Test Ovens addition long-term steady dynamic life testing, performs continuous short-term monitoring processes. This establish infant mortality (IM) early-life failure rate (ELFR). This achieved burning products short durations (<168 Hr.) 125°C. sample sizes these tests statistically chosen products picked random from high-volume fabrication processes package families. equipment doing these tests microprocessor-controlled schematics stimulating product during burn-in life test stored program facilitate ease prevent wrong programs being loaded. typical oven types used vary from location location over wide range temperatures. typical oven configuration shown Figure Other tests [13-18] performed include combined moisture thermal testing; equally important from package assembly wafer fabrication process perspective. These tests performed part qualification processes outlined earlier part standard reliability monitoring program.
Autoclave
autoclave test, sometimes referred "pressure cooker" "steam bomb" test, performed purpose evaluating moisture resistance nonhermetic packaged integrated circuits. employs severe conditions pressure, humidity, temperature, typical actual operating environments, that accelerate penetration moisture through protective material (molding compound), along interface between external protective material metallic conductors passing through When moisture reaches surface die, contaminants other constituent reactive agents that present from manufacture corrode metallization, affecting parametric performance eventually causing device failure. Other die-related failure mechanisms activated this method including various temperature- moisture-related phenomena. devices placed chamber pressurized psia (206 absolute) with continuous saturated conditions (100% relative humidity). temperature held 121°C test duration hours. Upon completion, devices fully electrically tested failures analyzed.
Test Conditions (JEDEC-STD-22 METHOD A102)
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Prediction Methodology Autoclave Testing
views this testing rough evaluation reliability performance products. saturated test models available extrapolation conditions. result, chooses publish data reliability reports.
Temperature Humidity Bias C/85 R/H)
Temperature Humidity Bias 85/85) life test performed purpose evaluating reliability nonhermetic packaged solid state devices humid environments. employs severe conditions temperature, humidity, bias, which accelerates penetration moisture through external protective material (molding compound) along interface between external material metallic conductors passing through While test less accelerated than Autoclave testing, takes longer complete, thought provide more realistic results with regard field reliability device relative device performance. When moisture reaches surface die, applied potential forms electrolytic cell that corrode aluminum, affecting parameters through conduction possibly causing failure opening metal. presence contaminants greatly accelerates this reaction.
Test Conditions (JEDEC-STD-22 METHOD A101)
test conducted 1000 hours with interval readouts hours hours controlled environment 85°C relative humidity. bias potential applied continuously manner that maximizes formation electrolytic cells, minimizes device power dissipation. Before beginning stress test, devices fully tested receive appropriate precondition JEDEC specifications simulate printed circuit board manufacture. completion stress testing, devices fully electrically tested failures analyzed determine root cause. When conducting this test, care must taken minimize junction temperature allow moisture reach surface.
Reliability Prediction Methodology Temperature Humidity Bias Testing
This most established humidity test. methods prediction based Eyring equation because stresses involved. accelerating factors temperature humidity. acceleration factor given following equation, developed D.S. Peck [13], where relative humidities test conditions expressed fraction test temperatures. other values constants derived from testing while Boltzmann's constant. (H2/H1)n Exp. [Ea/k(1/T1 1/T2)] Using this equation time failure calculated values known. These values derived Peck equal 2.66 0.76, respectively, electrolytic corrosion. When using these equations care must taken derive correct values particular failure mechanism being evaluated.
Highly Accelerated Stress Testing
HAST uses pressurized environment produce extremely severe temperature, humidity, bias conditions. HAST accelerates same failure mechanisms much shorter time. this test, unlike autoclave test, devices being tested biased. Care taken keep power dissipation minimum enable moisture progress surface. Using HAST technique devices operated temperatures that exceed boiling point water while avoiding unrelated factors introduced condensation.
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Reliability Handbook
Test Conditions
test performed temperature 130°C relative humidity with pressure 33.3 psia kPa. bias potential applied manner that maximizes formation electrolytic cells minimizes device power dissipation. equipment schematics again microprocessor-controlled. Stringent cleaning procedures followed cleanliness exceptionally important this type testing. equipment shown Figure
Figure Typical HAST Test System
Reliability Prediction Methodology HAST Testing
HAST testing accelerated form 85/85 testing outlined above. There three accelerating factors: pressure, temperature, moisture. pressure temperature humidity settings. acceleration factors generated relative those 85/85 testing formulae used similar those 85/85 lifetime prediction. Using Peck's [13] paper activation energies, following acceleration factors calculated relative 85/85: 85/85 120/85 130/85 140/85
Temperature Cycle
Temperature Cycle testing conducted determine resistance solid state devices alternate exposures extremes high temperatures. Permanent changes electrical characteristics physical damage produced during temperature cycling result, principally from mechanical stress caused thermal expansion contraction. Effects temperature cycling include cracking delamination packages internal structures, changes electrical characteristics resulting from mechanical damage.
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Figure Typical Temperature Cycle Test Chambers
Test Conditions (MIL-STD-883 Method 1010 Condition
devices placed chamber there substantial obstruction flow circulating across each unit. devices then cycled between temperature extremes required number cycles. temperature extremes -65°C +150°C. time temperature shall greater than minutes devices under test must reach temperature less than minutes. transfer time from cold from cold must exceed minute. Some types equipment available within shown Figure While conditions mentioned above maximum that Analog Devices employs, from time time less stringent conditions (e.g., -40°C +125°C), depending technology being qualified
Thermal Shock
purpose thermal shock testing determine ability solid state devices withstand exposure extreme changes temperature thermally stressing device. Thermal shock effects include cracking delamination package, changes electrical characteristics. Such conditions could encountered equipment intermittently used areas cold temperature.
Test Conditions (MIL-STD-883 Method 1011 Condition
devices under test alternately immersed cold liquid. temperature liquids maintained +150°C -65°C. devices must reach temperature five minutes. Transfer time between baths seconds less. Again, depending technology combinations being monitored qualified, other test conditions based 883B JEDEC specifications.
Prediction Methodology Thermal Cycling Tests
There various methods predicting lifetimes from thermal tests [19] based Coffin Manson laws. such method outlined below. Because various prediction methodologies, Analog Devices prefers provide data rather than lifetime predictions.
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N1/N2 (T1/T2) where failed cycle counts operating test temperature range derived from experimentation acceleration coefficient device lifetime years then given A)/365 where number days failure.
High Temperature Storage
purpose this test determine effect solid state electronic devices storage elevated temperature without electrical stress applied.
Test Conditions
device shall subjected continuous storage +150°C (-0, 1000 (-0, +72) hours, except returned room ambient conditions interim electrical measurements.
Prediction Methodology High Temperature Storage Tests
uses Arrhenius equation prediction required from this test conditions.
Reliability Monitoring Program
Reliability Monitoring Program (RMP) employed corporate-wide program driven corporate manufacturing teams. centrally driven avoid duplication effort free this valuable reliability resource qualification engineering functions. program viewed isolation; must remembered that only gives snapshot time reliability product being produced. statistical process control, reduction variability, yield monitoring, improvement among additional factors that must considered when reviewing RMP. intended generate reliability data most recently manufactured material continuous basis. intended identify major life-limiting failure mechanisms, detect long-term process shifts, reduce unnecessary end-of-line testing, provide customers with data continuous support reliability efforts. also strives ensure that in-line controls used assembly wafer fabrication effective. procedure generated live document that continually updated corporate level. procedure governs package families, fabrication processes, manufacturing locations. product selection plan based volume production reliability sensitivity. Part types selected based moderate consistently high production volumes, susceptibility stress, ease failure analysis, availability.
Wafer Fabrication Process Families
ADI's wafer fabrication processes grouped into families according similarities. processes must have same production design rules, features, fabrication facilities, reliability characteristics similar. more products within these wafer fabrication process families selected monitor vehicles. Wherever possible, differnt part types rotated into monitor progam giving best possible product-to-process mix, thus ensuring that stress sensitivities attended
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Reliability Handbook
Assembly Package Families
package characteristics assembly locations primary considerations when grouping packages into package families. main packaging families Hermetic Plastic which then further subdivided based lead counts, cavity/lead-frame size, die-attach method, etc. result, package family consist group 14-lead 20-lead SOIC packages manufactured particular manufacturing location.
Sample Plans
Based expected production volumes, forecast given three months advance each manufacturing site world wide manufacturing group. This forecast will detail each location agreed-upon wafer fabrication processes foundry, package families/foundries monitored upcoming quarterly monitor period. based production volumes, also applies subcontractors used manufacture products. example breakdown lots production volume shown Table VII. Table VII. Total Volume 0-2.5% >20% Lots Table VIII. Early Life Failure Rate High Temperature Operating Life Test Temperature Humidity Bias HAST Autoclave Solderability Thermal Shock Temperature Cycle Solder Heat Resistance tests based international standards include following tests (see Table VIII). devised gives much real-time monitor, recognizes that only snapshot time selected lots, reliability monitors. ADI's only monitor reliability; company maintains very active rigorous Statistical Process Control Program well Risk Management Program, both which early detection reliability issues significantly improve end-of-line reliability. Coupled with these programs corporate-wide production management information system database (PROMIS) that provides manufacturing instructions collects engineering data associated with production lots. This system allows immediate location containment potentially discrepant material, pending problem resolution and/or corrective actions. Sample Size 45/77 45/77 45/77
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failures generated from reliability monitor plan failure analyzed root cause; results reported appropriate wafer manufacturing facilities where corrective actions established. data generated published annually World Wide available review
PROCESS RELIABILITY Introduction
reliability product depends product test, design, assembly, wafer fabrication processes. There strict design rules each these stages. function these rules allow introduction products without introducing reliability concerns. reliability engineering group's function that wafer fabrication assembly technologies meet existing reliability requirements, provide strong platform future products process development. philosophy product process reliability based premise that reliability must designed/built-in cannot tested-in later stage. result, reliability system based three fundamental activities: independent verification, certification, qualification wafer fabrication processes package technologies extremities known design parameters. statistical process control stages manufacturing drive continuous improvement improve reliability processes rigorous design tools checkers identify potential reliability issues very early design phase before committing silicon. This system focuses process development, control, design rules, produces highly reliable products.
Fabrication Process Reliability
holds belief that process reliable reliability must built [20-33] foundation level very difficult costly change modify process once production. process reliability groups work tandem with process development manufacturing engineers when they developing technologies. They strive ensure that defect densities reduced sufficient levels allow product manufactured without significant yield losses reliability risks. They also characterize lifetimes products thorough characterization wearout failure mechanisms performing accelerated tests specifically designed test chips. main activities related process reliability modeling wearout failure mechanisms, detection reduction latent defects, elimination contamination. Process reliability also includes determination reliability related design rules, e.g., electromigration carrier effects, qualification process using leading technology products.
Time-Dependent Dielectric Breakdown
There various test methods used predict oxide quality reliability. Analog Devices uses TimeDependent Dielectric Breakdown testing, commonly known TDDB [34-48] testing, characterize oxide from reliability perspective. Other methods such also used; uses both ongoing monitors within wafer fabrication facilities determine ongoing quality oxide.
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TDDB testing done constant electric field voltage fixed temperature. test methodology dictates that constant voltage placed capacitors current continuously monitored until predefined value reached. When predefined value reached device under test considered failure time recorded each failure. failure criterion generally microamps preselected from Fowler-Nordheim breakdown curves generated devices under test. Figure indicates Fowler-Nordheim curve capacitor type substrate 0.6µm DPDM CMOS process.
10mA
CURRENT DEC/DIV
10fA
VOLTS
Figure Dielectric Breakdown Curve
Test Structures/Devices
TDDB testing performed gate dielectric used transistors give measure reliability specific structure tested. generally done either transistors themselves capacitor structures that have gate oxide thickness equivalent structure. Capacitors generally used these typically small, flat structures with oxide grown either substrate well; testing done accumulation, i.e., substrate capacitor negative bias applied polysilicon plate.
Equipment
testing equipment either purchased built within company. however, specifically built wearout-type testing. equipment generally consists microprocessor, controlled mainframe containing voltage supply, current-measuring units. devices under test placed ovens printed circuit boards. ovens capable running 300°C maximum temperature limited 250°C material constraints circuit boards.
Test Conditions
test conditions used vary, depending results required. process monitors, generally voltage (12.5 temperature (225°C) used. process characterization, matrix voltages, temperatures, capacitor sizes used. These allow calculation voltage acceleration factor, thermal activation energy, area dependency time failure different area sizes, which necessary accurately predict product reliability. sample sizes chosen should statistically significant allow determination intrinsic extrinsic present) distributions.
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Data Analysis/Modeling
data generated from testing form times failure. This analyzed using normal statistics give time cumulative failure various test conditions order calculate Thermal Activation Energy Field Acceleration factor. data shown Figure generated Angstrom micron dual polysilicon, dual metal process.
DATA
99.9 MV/cm
CUMULATIVE FAILURE
MV/cm
MV/cm
MV/cm
MV/cm
0.01 TIME Hours 1000
Figure TDDB Test Results Angstrom Gate Dielectric above data extrinsic intrinsic distributions separated. intrinsic distribution characterized small sigma value (<0.4) related inherent robustness process. extrinsic distribution reasonably large sigma (>0.5) results from flaws defects process. collection data sets such these allows calculation field acceleration thermal activation energies. oxide lifetime predicted using appropriate model. Linear model used predict oxide reliability. basic equation shown Equation This been shown equation that adequately fits data derived processes. Care must taken when analyzing TDDB data that capacitors used same size that distributions being analyzed calculate acceleration parameters intrinsic distributions. Exp. [-Ea/k (1/TTEST 1/TUSE)] Exp. (VTEST VUSE) test where test test times failure e.g. 0.1% Cumulative Failure TUSE TTEST test temperatures Thermal Activation Energy (eV) Boltzmann's Constant 8.63 eV/K Voltage Acceleration Factor VTEST VUSE test voltages mentioned above, important same size capacitor calculate field thermal acceleration factors. reason this that large area capacitors have shorter failure time than smaller ones, even though field thermal acceleration factors similar. result, lifetime larger transistors capacitors less than would expected smaller ones. Figure shows time failure different area capacitors under constant voltage stressing 225°C; difference T50% failure appreciated. Figure shows time failure versus inverse temperature SEMI plot several groups capacitors. thermal activation energy calculated from slopes lines fitted data.
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1.20E-07 0.00004
T50% HOURS
0.0025 0.0005 -0.5 0.01 -1.0 -1.5 -2.0
FIELD MV/cm
Figure T50% Failure Time Electric Field
1000
0.01
T50% HOURS
0.00001 0.001
0.00000012 0.0025
0.01 0.0015
0.002
0.0025
0.003
Figure T50% Failure Time (1/T(K))
Electromigration
Electromigration mass material transportation through diffusion, under driving force electron wind. This occurs when current flows metal interconnect, electron wind generated, electron wind applies force aluminum atoms resulting diffusion direction electron flow. This movement material will result voids hillock growth, Figure which will eventually result failure open circuit, shorting adjacent tracks, simply change line resistance. Although electromigration been widely recognized failure mode many years [49-54], concern increased over probability occurrence toward useful life. This heightened concern coincides with reduction feature sizes into submicron regime, with multiple levels metallization. These technology trends result increased interconnect current densities device operating temperatures, both which exacerbate electromigration. complexity assuring electromigration reliability significant, requiring much more than generation design rules limit current densities. Many aspects manufacturing process ranging from metal quality, dielectric processing, topography severity, circuit density, influence electromigration failure.
Testing Methodology
Dedicated electromigration test structures tested accelerated test conditions temperature (180°C 225°C) current densities mA/µm2). time failures recorded from these tests translated typical end-user conditions 70°C, mA/µm2. This translation accelerated test end-user conditions achieved using Black's equation (Equation
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(Ea/kT)
where time failure (hours) process dependent parameter current density (mA/mm current density exponent activation energy (eV) Boltzmann's constant (eV/k) temperature dedicated electromigration test structures consist metal lines flat topography substrate with various widths designed ASF-1259 design rules. contact chains also used determine reliability these structures. varying topography under chains, dielectric thickness between interconnect changes, resulting variation step coverage via, i.e., variation depth via.
Process Monitor Results
Once process characterized, finalized with design rules place, sample material from dedicated, specifically designed test chips tested monthly basis results back wafer fabrication manufacturing groups. example typical results plotted Figure using Black's equation translate from accelerated test conditions conditions, control lines process obtained process. Control lines established using minimum time test sample fail corresponding sigma value, required give <0.1% cumulative failure years 70°C from electromigration test conditions, Equation below: (test50%) Exp. (93.08 sigma) Yrs. (AJD current temperature acceleration factors from test conditions; they calculated similar fashion those TDDB testing previously outlined. sigma value dispersion distribution.
Figure Electromigration Failures
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1000
2.5mA/ LIMITS LIMITS LIMITS TOPOG FLAT SHALLOW
Tf50
4.2mA/ VIA, 1.68mA/VIA
UNACCEPTABLE DATA (BELOW LIMIT LINE) SIGMA
Figure Selection Electromigration Monitor Results from DPDM Process units subjected testing analyzed completion test verify that failures found indeed true electromigration failures. Figure indicates position voids (gaps from which metal migrated) hillocks (areas where metal been deposited) with respect current flow.
Carrier Injection
effects carrier degradation [55-59] important issue device scaling outpaced reduction supply voltages resulting increased electric fields silicon gate oxide. carriers generated channel large electric field drain region shown Figure This lateral electric field occurs result high doping levels shorter channel lengths. carriers created electrons channel gaining energy from field faster than they lose lattice. result they longer thermal equilibrium with lattice. Impact ionization these high-energy electrons causes generation electron/hole pairs. From these pairs holes flow substrate current electrons can, they gain sufficient energy, surmount energy barrier tunnel into oxide. These electrons become trapped oxide create interface states. these interface states that result changes parameters such IDS, (transconductance).
Figure Electron Injection
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carrier testing NMOS nominal Leff devices used, (20/0.6 20/0.5 µm). stress applied bias room temperature. Typically total sample size used with eight devices each following stress conditions (depending process): (0.6 (0.5 (0.5 maximum substrate current Fail criteria shift
10000
Test Method
1000
REVERSE (nA)
SERIES1 POWER (SERIES1) 0.001 -4.9509 0.9977
0.01
T0.1 (HRS)
Figure Typical Time Failure (IBS/IDS) Curve Carrier Injection
Lifetime Prediction
Lifetime predictions made using Berkeley model. Cx-m
where time 0.1% failure, process-dependent parameter obtained from Figure axis intercept, IBS/IDS, indicates hole electron injection, obtained from Figure slope line. time degradation each device plotted cumulative probability plot. extrapolated time 0.1% failure obtained from this graph each stress level. 0.1% versus IBS/IDS plotted log/log scale each stress level, Figure trend line fitted data using power resulting equation represents model used lifetime prediction. Using equation from Step lifetime worst-case operating conditions calculated. This results lifetime. lifetime value calculated using following conversion factor. 170/2.2 where conversion factor room temperature -55°C conversion factor. There thermal acceleration factor (Ea) equation; room temperature conversion factor used because failure mechanism more pronounced cold temperatures result lattice stability.
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Bipolar Carriers Description
major reliability issue high-performance bipolar transistors reduction forward current gain (hfe) resulting from carrier (HC) generation during reverse bias operation emitter-base junction [60-61]. Bipolar HC-induced degradation strongly dependant device size. overall objective develop reliability-driven rules that used reduce degradation improve transistor reliability. vertical lateral dimensions scaled down increase device performance, doping levels must increased maintain optimal performance. Because high doping densities emitter base, very large electric field exists along periphery emitter. When emitterbase junction reverse-biased, large electric field create carriers that degrade oxide around emitter edge, causing increase forward-bias recombination current. collector current remains same. result decrease current gain which, turn, limit performance bipolar circuit.
Test Method
methods accelerating HC-induced degradation available: reverse voltage stressing reverse current stressing. Constant current stressing used ADI. This method provides more consistent results than constant voltage stressing because reverse current more sensitive function electric field than reverse voltage. test system used force currents between stress devices. Three measurements taken decade stress time starting 0.01 hours. fail criterion time degrade 10%.
Bipolar Lifetime Calculation
cumulative probability plot times degradation drawn each current time 0.1% failure determined.
100%
0.1%
0.01% 100mHrs 1Hrs 10Hrs 100Hrs 1KHrs
Figure Graph Gain Degradation Axis) Stress Time Axis) When bipolar transistors stressed gain transistor shifts, shown Figure gain shifts appreciably during lifetime transistor will longer operate specified causing circuit failure and, result, become long-term reliability hazard. gain (hfe) simply ratio These parameters vary with (Gummel plot) and, result, gain varies with shown Figures Figure Gummel plot values upper curve while values lower one. gain also varies with shown Figure
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10mA 100nA 10nA 100pA 10pA 0.3V
0.4V
0.5V
0.6V
0.7V
0.8V
0.9V
1.0V
Figure Gummel Plot (Upper Curve) (Lower Curve) Voltage
10nA
100nA
10mA
Figure Plot Gain Axis) Axis) Once degradation gain been achieved, times degradation each device under test calculated. These plotted shown Figure time 0.1% cumulative failure each sample population extrapolated assuming normal distribution.
99.9%
0.1%
0.001Hrs 0.01Hrs 0.1Hrs 1Hrs 10Hrs 100Hrs 1KHrs 10KHrs 100KHrs
Figure Cumulative Failure Gain Shift Time Failure (Hrs.) Once time 0.1% failure been calculated each stress condition, these values then plotted against reverse (nA) Figure
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1000
REVERSE
305.54x-0.1302 0.8461 SERIES1 POWER (SERIES1)
0.001
0.01 T0.1
Figure Lifetime Reverse Bias time failure voltage calculated specific that translated into voltage with curve. measurement made virgin devices, allowing equivalent current specified voltage calculated.
Random Fails
failure mechanisms discussed previously, while related wafer fabrication process, lifelimiting wearout failure mechanisms. These failure mechanisms effect area right bathtub curve stringent design rules checks apply these failure mechanisms.
Figure Visual Defect There are, however, other failure mechanisms [62-65] that affect infant mortality portion bathtub curve. These generally related contamination defects, which exist wafer fabrication process. Figure indicates visual defect that resulted metal metal short. This occurred during stress test caused product fail. particle identified, results reported wafer fabrication group, corrective action implemented. defect Figure visible under microscope identified with certain failure signature such high IDD.
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Figure Light Emission However, failures visible eye, even under very high magnification, necessary specially designed failure analysis tools. such tool light emission microscope. enables location sublayer defects detection faint light levels emitted from silicon device structures. These faint light levels arise from recombinant radiation emitted from junctions well from oxides. Figure shows visually unseen defect located using this system. defect observed cause circuit failure reported wafer fabrication facility corrective action. other instances, possible identify exact cause failure utilizing visual system light spot detection using either light emission liquid crystal techniques. these cases, while location failure evident, very detailed cross-sectional analysis required determine cause failure. uses focused beam (FIB) milling this. This technique discussed another section. results shown Figures Figure shows cross-section failing contact from metal substrate, which caused device failure. Junction spiking identified light spot emission verified cross-sectional analysis.
Figure Junction Spiking
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Reliability Handbook
Figure Metal Metal Short Figure again shows benefit combining failure analysis techniques where metal metal short submicron process been verified using focused beam milling technique. importance this occasion cannot overestimated allowed accurate precise identification particle causing short particle kept intact identification using SIMS techniques. Once type particle been identified, makes corrective action process easier aids successful elimination problem. These pictures show damage input device during simulation testing. damage seen visually (Figure under medium-power microscope. increased magnification power enhances this even more (Figure 28), again showing benefits combining failure analysis equipment techniques produce high-quality analysis. Figure circles point damage that occurred positions, worst which beside ball bond. This area enhanced Figure where explosive damage caused simulated pulse very visible.
Figure Visual Defects
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Reliability Handbook
Figure Shot Simulated Defects
PACKAGE RELIABILITY Introduction
reliability assembly process exceptionally important regards life product. packaging process provides first-level protection active circuitry against harsh printed circuit board manufacturing techniques. mentioned previously, products manufactured fall into categories: hermetic plastic. Thanks today's assembly processes, issues that dogged plastic packaging process past, such corrosion purple plague, have been eliminated improved processing techniques controls. Today majority integrated circuits produced plastic packages. always easy determine whether failure mechanism package, design, wafer fabrication issue, since there strong interdependence areas once assembled, tested, placed printed circuit board. Figure below indicates this interdependence role environmental stress testing.
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WAFER PROCESS DESIGN
ASSEMBLY PROCESS
CUSTOMER BOARD DESIGN
PACKAGE DESIGN BOARD MOUNTING PROCESS
FAILURE MECHANISM
FAILURE MODE
ENVIRONMENTAL STRESS TESTING
Figure Process Interaction Failure Mechanisms easy understand design, wafer fabrication process, etc., could affect performance product this interaction could lead specific failure mechanisms. However, discussed earlier, other stresses, such temperature, humidity, mechanical electrical, also affect device reliability. These stresses normal service life product. These stress conditions accelerated controlled environment thermal, mechanical, electrical, humidity stimuli that result failure used generate reliability data. However, running devices these tests alone sufficient. Today manufacturers' processes extend their customers; manufacturer must include precondition appropriate thermal moisture data simulate printed circuit board production order generate accurate reliability figures products produced.
Thermal Issues
reliability integrated circuits very dependent environmental conditions. Considering factors that influence package reliability, thermal stress most significant impact. integrated circuits dissipate some power while operating. This turn will cause temperature integrated circuit rise. temperature rise integrated circuit complex function part construction, electrical operating conditions, part placement printed circuit board, airflow around part (laminar turbulent). producer controls some these while user environment which parts operate control others. result thermal characteristics integrated circuits major concern both users producers ICs. increase temperature junction temperature (TJ) rise components adversely effect long-term reliability product.
Reliability Implications
bathtub curve shown Figure long been used represent reliability integrated circuits. curve represents cumulative failure rate over time three distinct sections: early life failure rate (infant mortality), useful life period, wearout stage.
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BATHTUB CURVE EARLY LIFE FAILS
QUALITY FAILURES
USEFUL LIFE
STRESS-RELATED FAILURES
WEAROUT
WEAROUT FAILURES
TIME
Figure Classical Bathtub Curve infant mortality early life period typically first months circuit operation characterized decreasing failure rate above). types failures found this period quality failures induced manufacturing process generally found board level test. Most reputable manufacturers have programs place reduce infant mortality provide Early Life Failure rate data Outgoing Quality figures. useful life period characterized constant failure rate from time above, where failure rate number devices that will expected fail given period time, e.g., failures 1000 hours. This then translated into Mean Time Failure (MTTF) which time interval between failures. This simply inverse failure rate. Both failure rate MTTF primary units measure device reliability. useful life period normally quite long integrated circuits, extending decades before going into wearout stage where life-limiting failure mechanisms such oxide wearout electromigration come into play. Many factors affect length useful life period product, including pressure, humidity, electrical stress. However, most critical common factor most failure mechanisms temperature. temperature which devices operate shortens useful life period product, increases failure rate useful life period, shortens time wearout. result temperature plays significant role operating reliability product. relationship between integrated circuit failure rates temperature very well established represented Arrhenius Model. Exp. (Ea/kT) where Failure Rate, Constant, Activation Energy Particular Failure Mechanism 5-1.2 Range) Boltzmann's Constant (8.63 eV/K) Temperature Kelvin failure rate exponential function temperature stress: higher stress higher failure rate components. Most manufacturers conduct reliability testing elevated temperatures demonstrate reliability their products. temperature relationship between these tests actual conditions derived from above equation follows: Acc. Factor Exp. [-Ea/k (1/T2 1/T1)] where Test Temperature Failure Rates Test Temperature
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Based above equation, normalized graph Figure drawn indicate affect junction temperature failure rate.
1000000
100000
FAILURE RATE
10000
1000
JUNCTION TEMPERATURE
Figure Failure Rate Temperature graph normalized, gives good indication failure rate vary with junction temperature. graph indicates that reducing junction temperature will increase reliability. Table indicates effect reducing junction temperature from 105°C 75°C application different activation energies.
Table
Activation Energy
Improvement
illustrated, reliability improvement depends activation energy. Significant reliability improvements improvement being possible made reducing device junction temperature [66-69] application. thermal resistance between points space temperature difference needed drive heat rate watt from point other. used measure easy remove heat from center package exterior surface, into ambient surroundings package. high value Thermal Resistance means that more difficult remove heat. Thermal resistance measured between points more usually, between planes. example, thermal resistance stated being from from Junction Case. Thermal Resistance from Junction Case defined temperature gradient required drive heat rate watt from diode junction circuit hottest point surface package. practice this temperature gradient from anywhere surface chip point surface package, directly underneath center chip. latter location, often found more convenient point surface package directly above center chip. Another term used this parameter Theta J-C, often written There detailed standard methods defined carrying measurements determine value Theta J-C. example, SEMI Standard Methods G38-87 G43-87, 883C, Method 1012.
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Thermal Resistance from Junction Ambient defined temperature gradient required drive heat rate watt from junction circuit other surroundings package. practice this measured temperature gradient from anywhere surface chip point one-half inch away from package, inch "upstream" from package. Another term used this parameter Theta J-A, often written Again, there detailed standards explaining these measurements taken. example, SEMI Standard Method G38-87, SEMI Standard Specification G42-88.
Derating Factor
Derating term used specify power dissipated device must reduced when temperature ambient environment above particular level. such circumstances, there concern that maximum Junction Temperature device exceeded because package able transfer heat from chip warm environment.
1000
AMBIENT TEMPERATURE
Figure Power Dissipation (mW) Junction Temperature Ambient Temperature Figure device dissipates power (illustrated dotted line). junctionto-ambient thermal resistance device 67°C watt. temperature junction will rise 67°C watt power dissipated. junction temperature exceeded. this example been determined that junction temperature should exceed 120°C. This means that maximum allowable junction temperature reached device ambient 80°C, dissipating only which device operated ambient above 80°C reduce power dissipation. derating power dissipation each degree Centigrade rise ambient temperature above 80°C, junction temperature will remain 120°C. This result derating factor, 0.015 which actually inverse Junction Ambient Thermal Resistance, 67°C/W. some devices such power controllers, power dissipation almost totally dependent application. Such device example above theoretically operated ambient 119°C, where maximum junction yemperature exceeded. some instances manufacturers choose derating begin ambient temperature that even lower than typical application environments. example, manufacturer specify device capable dissipating 1700 with derating required conditions above 25°C. package derated degree Centigrade. such case, environment 70°C, device would limited
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Enhancing Heat Dissipation
There generalized construction types assemblies. first, chip enclosed hermetic space, with base chip attached over full area inner surface package. other part chip contact with package. second type, chip encapsulated center solid plastic molding that also supports leads which package mounted onto printed circuit board. hermetic package, portion package which chip attached becomes almost chip heat then conducted remainder package body. heat removed from package conduction through leads into printed circuit board, from surfaces package body convection into surrounding environment. surface package body usually coolest, having longest thermal path chip, poor dissipating heat into ambient. Typically most heat conducted away, through leads, into printed circuit board. However, where package constructed die-down configuration, upper surface package hottest, suitable mounting supplementary heat sinks. These offer substantial amount increased surface area ambient environment. this way, thermal resistance package greatly reduced, especially where there significant flow cooling air. Heat sink manufacturers supply data thermal performance their products specifying thermal resistance from mounting face ambient. heat sink mounted hottest point package, full thermal resistance assembly (i.e., from junction ambient) estimated from package plus thermal resistance heat sink. plastic encapsulated packages (PEP) chip mounted onto metal (usually copper) paddle. plastic encloses chip paddle faces, heat thus conducted directions away from chip. plastic poor conductor heat, because heat flow directions, overall performance typical plastic packages least good their hermetic equivalents. Thermal performance enhanced plastic encapsulated devices Incorporating metal heat spreader internally package; mounting chip onto thick copper slug instead paddle with opposite face copper slug extending surface package; directly connecting some leads paddle which mounted; arranging layout leads paddle maximize flow heat from paddle leads. External heat sinks very effective when mounted directly onto slug face package with thick copper slug, otherwise seldom used with plastic encapsulated packages. High-thermal conductivity plastics occasionally used improve thermal performance. There major disadvantages terms manufacturability package reliability almost such compounds, they avoided possible.
Similarities Between Manufacturers
most cases, manufacturers same package materials same method construction packages that visually similar. Therefore, devices packages identical outline will have virtually identical thermal performances-if measured under identical conditions. There are, however, significant differences thermal performance quoted data sheets different manufacturers. Even identical packages, these products sometimes, fact, produced same factory from same materials, perhaps same day, with only difference being details circuit chip. such cases, difference between quoted thermal performances rests solely circumstances under which measurements were made.
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Effect Component Mounting Thermal Resistance
primary routes thermal dissipation from integrated circuit radiation from package (and heat sink, used) ambient air, conduction circuit board. Ultimately, dissipated heat will find ambient environment. thermal resistance figures published Analog Devices' products generated standard SEMI boards. SEMI standard board double-sided board, with each side covered with ounce/sq. copper. This provides conservative measure junction ambient thermal resistance. important that component users understand factors under their control that affect junction temperature die.
Socket Versus Board Mounting
thermal data published Analog Devices' parts based direct mounting component board, with leads soldered. Sockets provide less efficient heat sink than direct board attach, will increase junction temperature component. Where sockets used high power dissipation products, recommended that thermal resistance measurements made that component/socket combination.
Thermal Fillers
Where thermal resistance board individual component needs lowered, option thermal filler material. These compliant, electrically nonconductive, elastomer-filled sheets that size, placed over component(s) question, used fill between component, enclosure surface above, which acts heat sink. Because their compliance, they usually accommodate height differences between various components, also provide reduced thermal contact resistance, their ability conform surface irregularities. filler usually highly thermally conductive ceramic, such boron nitride aluminum oxide. suitable applications, these materials provide cost-effective solution power dissipation problems.
Component Selection
option consider when dealing with thermal resistance problem select same product different package outline, space permits. Table shows example 20-lead component mounted SEMI standard board still air. part, dissipating required operate ambient 80°C without exceeding maximum permitted junction temperature 125°C, changing from SSOP SOIC outline will provide solution, without additional heat sinking. Table 0.150" SOIC 119.5 SSOP TSSOP °C/W Junction Temperature (°C) while Dissipating 80°C Ambient.
Forced Cooling Heat Sinks
Unless otherwise stated, thermal data provided Analog Devices based still conditions specified SEMI G42-88. applications where ambient temperature high cannot easily reduced, option forced cooling, with without heat sink. Figure below shows effect forced cooling component, with without heat sink.
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THETA C/WATT
THETA C/WA. HEATSINK
THETA C/WA. HEATSINK DIAMETER INCH, DISKS
VELOCITY Ft/Min
Figure Airflow When selecting heat sink, important consider heat sink manufacturer generated thermal resistance data. Some manufacturers attach insulating block base plate heat sink, thus preventing heat loss from this surface, while others suspend heat sink air, allowing heat dissipation from surfaces. first method better representation heat sinks used practice. Where heat sink used, power dissipated expressed follows: TA)/(JC JHA) where Power dissipated watts Silicon junction temperature (°C) Temperature (°C) Junction case resistance (°C/W) Case heat sink resistance (°C/W) Heat sink ambient resistance (°C/W) airflow repeatability manufacturing process must also considered. optimum board position vertical this facilitates natural convection giving reduction thermal resistance 8%-10% over horizontally positioned boards. Board vertical length also have effect, greater this length more been heated lower components before passes upper ones. This principle also applicable forced cooling, shortest board side should parallel airflow.
Board Construction Mounting
normal still conditions, primary heat dissipation path component leads into PCB. critical factor thermal resistance board. This lowered maximizing planes heat sinks, also optimizing means which heat dissipated, e.g., conduction into board mounting chassis maximizing potential natural convection cooling. greater percent copper board, lower thermal resistance. Thermal modeling 8-lead SOIC shown that doubling conductivity board (W/M reduced component junction temperature from 130°C 98°C. wide tracks thermal vias ground plane will also have significant effect.
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Placing critical components close where edge board attached chassis provide additional cooling without heat sinks forced air. best results advisable avoid close spacing high-power devices, allowing heat dissipated over maximum possible area. result ongoing trend towards miniaturization packages that thermal resistance packages increases with reduction size. more important than ever that user semiconductor packages understands only issues arising from increase thermal resistance, also importance correct component selection mounting techniques. Possibly most important point bear mind when comparing thermal data, whether semiconductor package, heat sink filler, understand test methodology used. test method clearly described, values must treated with caution.
Moisture Effects
advent plastic surface-mount component (PSMC) enabled printed circuit board (PCB) designers obtain greater packing density components boards utilize both sides boards component placement. This progression considerably increased PSMC. Unfortunately, this progression necessitated increase temperatures used place components boards. Modern surface-mount techniques expose surface-mount components temperatures 260°C. This placed additional stress components highlighted failure mechanisms [70-82]. result mechanisms such popcorning delamination have occurred. plastic molding compound used PSMCs hydrophilic absorbs moisture from surrounding air, reaching saturation level dependent surrounding ambient. quantity moisture absorbed depends quantity moisture surrounding atmosphere, while rate which moisture absorbed depends temperature which component sitting. higher temperature higher absorption rate faster package will reach equilibrium with surrounding air. graphs Figures illustrate this effect.
INCREASE
PLCC PLCC PLCC SOIC SOIC (150mil)
TIME Weeks
Figure 34a. Moisture Absorption Graph Various Packages 85°C
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INCREASE
TIME Weeks
Figure 34b. Moisture Absorption Graphs PLCC Package Various Conditions this particular package quantity absorbed moisture been measured after exposure controlled environment various times. selection packages identified weighed time zero, after bake initialize moisture content packages. packages then underwent exposure various conditions temperature humidity predefined times graphs plotted. From graphs evident that units saturate, i.e., they take more moisture, level that depends humidity. moisture congregate package body areas indicated Figure
Figure Cross-Section Typical Package
Reflow
Temperature (Deg.
Pre-heat
Temp. Stabilization
Time
Figure Typical Solder Profile
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moisture relatively benign effect reliability product unless brought some impurities into body package. However, subsequent printed circuit board manufacturing process subjects board extremely high temperatures infrared profile Figure indicates. manufacture printed circuit board components reach temperatures 260°C seconds. This rapid rise temperature vaporizes moisture present packages causes expand. This expansion vapor, particularly areas attach leadframe, cause separation molding compound from surface (popcorning) leadframe. This separation will then create gaps back leadframe which have detrimental effect reliability product. separation back leadframe paddle degrade thermal performance product, surface, provides where moisture contaminants from printed circuit board process congregate cause device failure. quantity moisture absorbed very large, exposure extreme humidity levels, damage more significant. Cracks propagate from hard surfaces such paddle outside surfaces package shown Figure These cracks significantly degrade moisture resistance package shear bond wires leading device failure. Figure delamination shown fixed surfaces while cracks propagating from stress points shown yellow. cracks generally tend start immovable surfaces such leadframe propagate outside package. some instances cracks sever bond wires thus breaking connection between outside world leading device malfunction.
Figure Package Cross-Section Showing Delamination (Red) Cracking (Yellow) manufacturer measure resistance failure mechanisms, such those outlined above, conducting specific reliability tests. These tests include acoustic microscope view extent delamination cracking result exposure simulated soldering process after exposure various temperature humidity conditions. Figure shows acoustic microscope image 44-lead PLCC package after exposure high conditions temperature humidity.
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Figure Acoustic Microscope Micrograph Delaminated PLCC areas figure indicate delamination surface; gray areas indicate that there still adhesion between surface plastic molding compound. Research several companies have found influencing factors that contribute package cracking delamination are: Peak temperature reached during solder reflow. Dimensions paddle. Percentage moisture absorbed molding compound. Adhesion molding compound leadframe. Thickness molding compound under paddle. Fukuzawa have tied together above factors simple model. steam pressure under paddle Figure causes molding compound expand from paddle form dome (popcorn). crack occurs when maximum bending stress plastic, SMAX exceeds fracture stress characteristic molding compound being used elevated soldering temperature. Therefore cracking occurs SMAX SCRIT (TSOLDER) maximum bending stress first reached center long side given SMAX (a/t) where dimensionless stress concentration factor which depends aspect ration paddle length short side paddle thickness moulding compound under paddle water pressure cavity Based above equation packages with large paddles thin layers molding compound under paddle more prone package cracking. Fukuzawa found that (a/t) ratio less than five, package cracking occur.
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order predict cracking sensitivity function moisture saturation dryout, model required Equation above. This been derived PSAT (TSOLDER) (10) where relative humidity saturation ambient prior solder shock water vapor pressure cavity, which varies with peak solder temperature second failure mechanism associated with moisture absorption cratering. this type failure sudden evaporation moisture high reflow temperatures conjunction with quantity silicon modules aluminum cause gold ball bonds lift result excessive moisture pressure. Figure graphic example what occurs.
WIRE
THERMAL EXPANSION FORCE MOLDING COMPOUND MOISTURE VAPORIZATION
MOISTURE VAPORIZED FORCE
NODULES A1-SI METAL
INSULATOR
SILICON CRACK DAMAGE
CRATERING
Figure Bond Cratering nodules formed insulator from silicon added aluminum deposited Al-Si metallization. wire bonding, excessive bonding force cause silicon nodules damage insulator during bonding process accompanying ultrasonic vibration exaggerate damage causing microcracks insulator under ball bond. Once molding occurs, package absorbs moisture that penetrates surface. very high temperatures experienced during reflow soldering causes moisture vaporize, creating very high pressure vicinity ball bond. underlying insulator weakened microcracks. This, conjunction with thermal expansion force molding compound moisture-vaporized force, cause ball bond lift leaving behind crater silicon shown Figure
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Figure Bond after Cratering Occurred much same that devices absorb moisture, this same moisture expelled from package baking products prior circuit board manufacture. This shown Figure which packages that been soaked moisture until saturation occurred have been dried baking.
-0.05 PLCC PLCC 20PLCC -0.15 -0.2 -0.25 -0.3 -0.35 TIME 20SOIC 16SOIC (150 MIL)
WEIGHT DECREASE
-0.1
Figure Bake-Out Various Packages Analog Devices developed strong understanding this reliability concern. development in-house reliability tests procedures evaluate reliability products postsolder simulation. larger packages, procedure that involves baking components expel moisture then sealing them with desiccant humidity indicators moisture barrier bags. These units should used within predefined timeframe should rebaked only once. full details ADI's procedure available request.
Additional Moisture-Related Failure Mechanisms
Popcorning delamination only failure mechanisms associated with moisture intrusion plastic packages. Other failure mechanisms such corrosion also occur, although these prevalent today they were more than decade ago. order have moisture-related failure mechanisms plastic packages, four prerequisites must occur: There must path moisture. There must moisture. There must voltage. There must contaminant.
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four these present some degree plastic packages goal minimize them reduce moisture-related failure rate products. previously discussed, plastic package hydrophilic, absorbing moisture from surrounding ambient until reaches equilibrium with that ambient. Therefore, most important issue whether there path contamination impurities. path impurities along interfaces, such leadframe/package interface, which formed part package construction. These paths could result unintentionally introduced cracks, voids, gaps during manufacture. Figure below shows interfaces that occur inherently package these provide paths impurities reach surface. Figure shows results once these contaminants reach surface. been shown that corrosion types failure, highest density failures occur pins with shortest path surface.
LEAD CORROSION MIGRATION
MOISTURE
MICROGAP
Figure 42a. Ingression Paths
Figure 42b. Corroded Bond analytical evidence suggests that impurities diffuse along interfaces between epoxy leadframe onto bond wires where they make their down surfaces, aiding corrosion process. corrosion process regenerative following equations aluminum corrosion presence chlorine show. result, minute quantities contaminant cause significant amounts corrosion.
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aluminum reacts with following fashion: (Cl)- (Cl)- will then react with available water following reaction: (Cl)- (OH)3 8Cl- From this reaction, always available continue further corrosion. This known regenerative process. resultant product aluminum hydroxide (OH)3 whose volume expansion sufficient crack passivation layer. paths moisture contaminants provided cracks that occur: During mold ejection. deflash, trim, form poor tooling. thermal shock. reflow soldering. test process manufacture. Once moisture impurities reach die, path active circuitry provided Pinholes passivation. Poor passivation step coverage over aluminum steps where passivation cracked. Cracks passivation thermo-mechanical type stresses. Inadequate gettering passivation. Poor step coverage bond pads surface. contaminants reach active circuitry these paths they introduced poor contamination control during wafer fabrication assembly processes. When these accelerated temperature, humidity, bias, failure mechanisms that occur either aluminum corrosion, which causes gross circuit malfunction, more subtle type failure such shift which could cause parametric failure. aluminum metal corrosion failure mechanism well understood occurs ways: Moisture combines with phosphorous form phosphoric acid. phosphorous integral part fabrication process contained phosphosilicate glass (PSG) process. This cause corrosion either with without bias. Under bias, corrosion occur cathode phosphorous detected analytical techniques such SIMS. exposed moisture cracked passivation misaligned openings passivation; most efficient catalysts anodic aluminum corrosion ionic chlorine. outlined above example this regenerative. main sources chlorine chemical deflash, generation molding compounds, handling, oxide strippers, etc. More subtle failure mechanisms occur result sodium, such localized shifts resulting very subtle failures. This type failure occur result poor handling techniques fabrication assembly process. Metal corrosion longer significant failure mechanism plastic packaging. phosphoric content glass exposed moisture carefully controlled. addition, chlorine other ionic components such iron sodium have been greatly reduced newer generation molding compounds processing materials. Also stringent contamination controls monitors have
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been introduced eliminate contamination manufacturing processes. elimination aluminum corrosion other associated failure mechanisms evidenced decreasing failure rates these mechanisms. Evidence this found referencing annually published reliability data well papers published over past decade HAST other related testing methodologies. Other failure mechanisms related lead finish trim, form, deflash process result from moisture humidity. These failure mechanisms exceptionally rare require discussion.
Stress Migration
metal lines become thinner (i.e., failures occur high temperature heat cycling. metal interconnect lines open circuit result stress. This called stress migration. this failure mechanism, unlike electromigration corrosion, bias applied. stress migration generated thermal mismatch between aluminum interconnects passivation film interlayer insulating film. aluminum atoms migrate relieve this stress. aluminum atoms migrate from boundary continue relieving stress, thus widening voids boundary eventually creating open circuit. line does completely open circuit, this migration reduces effective width metal lines increases probability electromigration failures occurring. resistance stress migration increased aluminum alloys, TiN, TiW, metal layer structure.
Thermal-Induced Gold Wire Failure
wire bonding process also potential cause failure process. dissimilar metals that easily interdiffuse form intermetallic phases such purple plague (AuAl2). Characterized distinctive purple-like color bond pad, purple plague generally caused excessive bonding temperatures assembly process. imbalances atomic fluxes balanced vacancy flux. These vacancy fluxes coalesce form what called Kirkendall voids intermetallic producing weakening intermetallic. This results lower than optimum bond strength that cause bond break during subsequent thermal cycling. Most molding compounds contain flame retardant that bromine small amounts chlorine. bromine released molding compound high temperatures activated chlorine, which also released from molding compound, form attacks intermetallic formed between gold aluminum, degrading integrity bond causing failure. Cross sections good bond degraded elongated life testing excessively high temperatures shown Figure below. flame retardant, which required international specifications, released above 150°C life-limiting effect bond. This critical high-temperature electronics when conducting extended life tests junction temperatures 150°C greater.
43a.
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43b. Figure 43b. Good Thermally Degraded Ball Bond presence contaminants bond pads also affect reliability ball bond. Silicon dust from sawing process inadequate cleans accelerate AuAl interdiffusion. Other issues such residual passivation stained bond pads, have detrimental effect reliability ball bond. today's processes thermal degradation wire bonds major issue because lower processing temperatures. This been brought about introduction thermosonic bonding where ultrasonic energy results much lower bonding temperature. This effect lowering temperatures from approximately 350°C somewhere region 260°C.
Package Cracking
Interconnect miniaturization chip size enlargement advances occurring rapidly chip sizes become larger. result these advances there increased risk aluminum slide shear stress damage metallization. Thermal stress from sealing resins different expansion coefficients individual components enhance probability these failure mechanisms occurring. Table shows typical expansion coefficients components. They matched easy understand internal stress occur. Table Component Silicon Molding Compound Leadframe Alloy42 ppm/°C ppm/°C ppm/°C ppm/°C
equilibrium assembly processing temperatures where zero stress occurs around 170°C epoxy adhesive attach. this temperature zero stress established differentials cause increasing stress temperature lowered. Once values processing temperatures known, stress conditions modeled using finite element techniques (FEM). analysis will show that attach leads bending moment that places under tensile stress bottom under compressive stress. magnitude tensile stress varies with thickness thickness should optimized process. molding process superimposes compressive stress die. This places molding compound under tension and, result, cracks propagate molding compound. discussed earlier, these cracks provide paths contaminants degrade reliability product.
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Once cracks molding compound, temperature cycling enlarge them. Nishimura studied this mechanism crack growth found that rate crack propagation given da/dN (K)m where crack length number cycles stress intensity factor range constants package cracking controlled several ways Down-setting below plane leads that there almost equal thickness molding compound above below paddle. Modifying molding compound control crack propagation characteristics. This includes modifying filler particle coating controlling size quantity filler particles. Providing in-line monitors controls minimize occurrence voids.
Thin Film Cracking Wire Bond Failures
Package cracking only failure mechanism concern plastic molded parts. molding compound completely encases and, discussed above, induces many different stresses package die. adhesion between molding compound great that forms exact replica molding compound shown Figure This picture shows section molding compound after mechanically removed from package. This implies that molding compound transmits force bond wires, these forces cause bond wire die-related failures during thermal temperature cycle testing. different aspects consider are: Package cracking propagation. bond wires respond internal package stressing. order understand these issues, forces package must understood.
Figure Imprints Plastic Molding Compound after Processing
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Nature Forces
forces acting surface shown Figure zero stress point around 170°C where attach molding processes occur. thermal tests from around +150°C -65°C -45°C. These temperatures represent range operation most products. Figure represents nonzero stress condition. There components force acting die. There shear force directed towards center that vanishes toward center, compressive normal force that almost constant along surface, which highly compressive. result, crack initiates corner die, will redistribute forces acting surface. crack will increase shear stress acting near edge stress change from compressive tensile. shear force represented graphically shown Figure
CRACK
CENTER
EDGE
SHEAR STRESS
TENSILE STRESS
COMPRESSIVE STRESS
COMPRESSIVE STRESS
DISTANCE FROM CENTER CHIP EDGE CENTER
Figure Stresses
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Reliability Handbook
SHEAR STRESS
SURFACE CORNER CENTER
Figure Shear Stress
Wire Bond Damage
Figure shows make-up ball bond wire package. shows position wire relative potential crack package. crack could induced combination moisture ingression reflow solder, initiated propagated during temperature cycling thermal shock testing. crack intersected wire cracked normal shear stresses ball enhanced delamination between plastic; ball bonds shear depending stress experienced. Even bond does shear there sufficient stress cause wire sever neck ball bond. This happens because gold wire will move with plastic while ball bond firmly attached die. wire neck ball bond particularly susceptible damage since been annealed during formation ball bond. This annealing generally leaves neck wire ball bond thinner than wire and, result, more susceptible breaking.
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SHEARED WIRE
TENSILE STRESS
SHEAR STRESS PACKAGE
CRACK
SUBSTRATE DELAMINATION
Figure Bond Wire Shearing Result Microcracks This type damage also compounded additional damage such cratering, discussed previously. Figure shows shot bond where cratering occurred during extensive thermal cycling testing. Figure shows ball bonds that have cratered while visible under ball bond.
Figure Bond after Lifted Bonds during Extended Temperature Cycle Figure shows ball bonds this test chip lifted during extended temperature cycling test. decapsulation, ball bond moved bond leaving crater exposed picture. Figure shows underside bonds silicon visible under lower bond.
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Figure Lifted Ball Bonds after Extended Temperature Cycle
Thin Film Cracking
shearing force exerted package damage thin film structures, particularly those situated edge where stress highest. This especially true large area packages such PLCCs. Most shear stress that applied aluminum interconnect through passivation directly aluminum. passivation cracks when applied force exceeds yield strength, aluminum deforms when applied force through passivation exceeds yield strength. failure mechanism shown Figure
STRESS PASSIVATION
METAL
METAL
Figure Metal Deformation Shear Stress metal slides direction shear stress resulting substantial deformation, bending metal tracks, also deformation bond periphery metal. Figure shows resultant damage that occurred specifically designed test chip after extended temperature cycling.
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Figure Metal Deformation Result Shear Stress deformation lines clearly seen bowing bond periphery edge die. aluminum damage occurs more readily when there very thick metal lines edge because stress lines greater. Localized aluminum deformation also occur result filler particles molding compound. This occurs when compressive stress from resin shear stress component applied local area through filler particles molding compound. This type metal deformation particularly dependent location within chip. Figure shows failure mechanism.
LOCAL DEFORMATION COMPRESSIVE STRESS
SHEAR STRESS
PASSIVATION FILM
ALUMINUM
Figure Metal Deformation Filler Particles Local aluminum deformation depends grain size filler. This concern ability cause small, geometric metal lines open-circuit, resulting device failure. Below various factors that affect both types thin film cracking: Size. Molding Compound Filler Size Used. Type Molding Compound Used. Width Aluminum Tacks, i.e., Design Rules. Overcoats Thermal Range Thermal Cycle Thermal Shock Based failure kinetics, place comprehensive range programs practices aimed preventing these failure mechanisms from being translated customers' applications. Analog Devices also supports comprehensive quality reliability control procedures that strive ensure these failure mechanisms occur qualified packages. Reliability test chips specifically designed with these other potential failure mechanisms used characterize newer packages before qualification begins. These test chips used only characterize newer packages also evaluate make changes existing processes packaging, assembly, wafer fabrication.
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PRODUCT ANALYSIS Introduction
Product analysis failure analysis contributor ADI's overall quality improvement. order maintain success, it's imperative that customers have high level confidence ADI's competency supplier. Part in-built product analysis philosophy emphasize concept continuous quality improvement with realization that product analysis significant contributor quality reliability products. Through feedback problems identified during product analysis pinpointing precise areas process improvement, contributions product analysis groups ADI's excellence quality reliability invaluable. product analysis groups dedicated providing customers with uncompromising support- whatever issue. demands that product analysis techniques flawless that analyst teams comprised highly trained skilled professionals. engineering group under direction Quality Assurance Department, members required versatile their problem management techniques. product analysis requests filter from external internal sources, analysts exposed wide range problems. ability cope with such diversity clients issues that makes product analysis group unique insight into stages semiconductor manufacturing process. There five product analysis centers regional customer support centers within that provide technical assistance customers form failure analysis centers located Limerick, Ireland; Taiwan; Philippines; Santa Clara, Wilmington, Offering highly professional engineering support services, advanced product analysis techniques, customer advocacy programs, measured customer response times with continuous focus prompt timely failure analysis, these centers structured reflect ADI's policy total quality management. following section outlines responsibilities that face product analysis engineering groups meeting ADI's quality objectives.
Definitions
following product analysis definitions that will used throughout upcoming section: Product Analysis Failure Analysis (FA): This general definition given activity that follows when integrated circuit fails perform expected specification. combines advanced analytical techniques from physics, electrical measurement, materials analysis, chemistry identify cause failure. Failure Mode: reported characteristics failure, e.g., "open circuit" "IDD." Failure Mechanism: physical mechanism conditions that have created observed failure, e.g., "gate oxide breakdown" "lifted bond." Failure Site: exact physical location package that resulted failure. Corrective Action: This list more actions taken eliminate avoid reoccurrence failure mechanism.
Sources Failure
product analysis requests originate from wide variety customers there need clear breakdown. requests generated external customer, i.e., customer return, generated internally from Reliability Evaluations/New Product Qualifications/Fab Process Yield Issues.
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Customer Returns Procedure
These suspected failures that returned customer. These failures come from: Incoming inspections Failures that occur during customer's manufacturing process. Customer field failures Failures generated from customer evaluations When customer identifies problem with product, following course action generally taken. most cases customer relevant representative completes Failure Analysis Initiation Request (FAIR) Form detailing information associated with potential
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