August 1997 Revised 2000 High Speed CMOS Logic Decimal Decoder

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August 1997 Revised 2000 High Speed CMOS Logic Decimal Decoder

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CD54/74HC42, CD74HCT42
August 1997 Revised 2000
High Speed CMOS Logic Decimal Decoder
Description
'HC42 CD74HCT42 BCD-to-Decimal Decoders utilize silicon-gate CMOS technology achieve operating speeds similar LSTTL decoders with power consumption standard CMOS integrated circuits. These devices have capability driving LSTLL loads compatible with standard logic family. outputs (low select) selected accordance with input. Non-valid inputs result none outputs being selected (all outputs high).
Features
Buffered Inputs Outputs Typical Propagation Delay: 12ns 15pF, 25oC Fanout (Over Temperature Range) Standard Outputs LSTTL Loads Driver Outputs LSTTL Loads Wide Operating Temperature Range -55oC 125oC Balanced Propagation Delay Transition Times Significant Power Reduction Compared LSTTL Logic Types Operation High Noise Immunity: 30%, Types 4.5V 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), (Min) CMOS Input Compatibility, VOL,
/Title (CD74H C42, CD74H CT42) /Subject (High Speed CMOS Logic Deci-
Ordering Information
PART NUMBER CD54HC42F3A CD74HC42E CD74HC42M CD74HCT42E NOTES: When ordering, entire part number. suffix obtain variant tape reel. this part number available which meets electrical specifications. Please contact your local sales office customer service ordering information. TEMP. RANGE (oC) PACKAGE CERDIP SOIC SOIC PDIP
Pinout
CD54HC42 (CERDIP) CD74HC42, CD74HCT42 (PDIP, SOIC) VIEW
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
2000 Texas Instruments Incorporated.
CD54/74HC42, CD74HCT42 Functional Diagram
TRUTH TABLE INPUTS OUTPUTS
NOTE: High Voltage Level, Voltage Level
CD54/74HC42, CD74HCT42
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±20mA Output Source Sink Current Output Pin, -0.5V 0.5V .±25mA Ground Current, IGND .±50mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) PDIP Package SOIC Package Maximum Junction Temperature 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range (TA) -55oC 125oC Supply Voltage Range, Types Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Time 1000ns (Max) 4.5V. 500ns (Max) 400ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current -0.02 -0.02 -0.02 -5.2 0.02 0.02 0.02 3.15 3.98 5.48 1.35 0.26 0.26 ±0.1 3.15 3.84 5.34 1.35 0.33 0.33 3.15 1.35 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD54/74HC42, CD74HCT42
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Input Pin: Unit Load -2.1 -0.02 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
3.98
3.84
0.02
0.26
0.33
±0.1
NOTE: dual-supply systems theoretical worst case 2.4V, 5.5V) specification 1.8mA.
Input Loading Table
INPUT UNIT LOADS
NOTE: Unit Load limit specified Electrical Table, e.g. 360µA 25oC.
Switching Specifications Input
TEST CONDITIONS 25oC -40oC 85oC -55oC 125oC UNITS
PARAMETER TYPES Propagation Delay, Input (Figure
SYMBOL
tPLH, tPHL
50pF
Input Output Transition Time (Figure
tPLH, tPHL tTLH, tTHL
15pF 50pF
Input Capacitance
CD54/74HC42, CD74HCT42
Switching Specifications Input
(Continued) 25oC -40oC 85oC -55oC 125oC UNITS
PARAMETER Power Dissipation Capacitance (Notes TYPES Propagation Delay, Input (Figure Input Output Transition Time (Figure Input Capacitance Power Dissipation Capacitance (Notes NOTES:
SYMBOL
TEST CONDITIONS
tPLH, tPHL tPLH, tPHL tTLH, tTHL
50pF 15pF 50pF
used determine dynamic power consumption, package. VCC2 (CPD where: Input Frequency, Output Load Capacitance, Supply Voltage.
Test Circuits Waveforms
INPUT tTLH tPHL tPLH INPUT tTHL 2.7V 1.3V 0.3V tTLH INVERTING OUTPUT tPHL tPLH 1.3V
tTHL
INVERTING OUTPUT
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Customers responsible their applications using components. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 2000, Texas Instruments Incorporated

August 1997 Revised 2000 High Speed CMOS Logic Decimal Decoder

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