FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR FEATURES di

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR FEATURES di

Datasheet Thumbnail

Top Searches for this datasheet

ICS843252-04
FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
FEATURES
differential 3.3V LVPECL output Crystal oscillator interface designed 18pF parallel resonant crystals Crystal input frequency range: 19.33MHz 30MHz Output frequency range: 145MHz 187.5MHz frequency range: 580MHz 750MHz phase jitter 156.25MHz (1.875MHz 20MHz): 0.39ps (typical) 3.3V operating supply 70°C ambient operating temperature Industrial temperature information available upon request Available both standard lead-free compliant packages
GENERAL DESCRIPTION
ICS843252-04 10Gb/12Gb Ethernet Clock Generator member HiPerClockSHiPerClocks family high perfor mance devices from ICS. ICS843252-04 synthesize Gigabit Ethernet Gigabit Ethernet with 25MHz crystal. also generate SATA 10Gb Fibre Channel reference clock frequencies with appropriate choice crystals. ICS843252-04 excellent phase jitter performance packaged small 16-pin TSSOP, making ideal systems with limited board space.
CONFIGURATION TABLE
Crystal Frequency (MHz)
WITH
25MHZ CRYSTAL
Inputs Frequency (MHz)
Feedback Divide
WITH
Output Divide
Output Frequency (MHz) 187.5 156.25
Application Gigabit Ethernet Gigabit Ethernet
CONFIGURATION TABLE
Crystal Frequency (MHz) 21.25 25.5
SELECTABLE CRYSTALS
Output Divide Output Frequency (MHz) 159.375 159.375 187.5 Application SATA Gigabit Fibre Channel SATA Gigabit Fibre Channel Gigabit Ethernet
Inputs Feedback Frequency Divide (MHz) 637.5 637.5
BLOCK DIAGRAM
nPLL_SEL REF_CLK
Pullup Pulldown
ASSIGNMENT
VCCO nPLL_SEL VCCO XTAL_IN XTAL_OUT REF_CLK CLK_SEL VCCA FREQ_SEL
Pulldown
XTAL_IN
XTAL_OUT CLK_SEL
Pulldown
Phase Detector
580MHz-750MHz
DIV.
ICS843252-04
16-Lead TSSOP 4.4mm 5.0mm 0.92mm package body Package View
(default)
FREQ_SEL
Pulldown
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice. 843252AG-04 REV. JANUARY 2006
ICS843252-04
FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Type Description Differential clock outputs. LVPECL interface levels. Output supply pins. Output enable. When HIGH, clock outputs follow clock input. When LOW, outputs forced low, outputs forced high. Pullup LVCMOS/LVTTL interface levels. Selects between reference clock input divider. Pulldown When Low, selects PLL. When High, selects reference clock. LVCMOS/LVTTL interface levels. Differential clock outputs. LVPECL interface levels. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. Analog supply pin. Core supply pin. Clock select input. When Low, selects ystal inputs. When High, Pulldown selects REF_CLK. LVCMOS/LVTTL interface levels. Pulldown Reference clock input. LVCMOS/LVTTL interface levels.
TABLE DESCRIPTIONS
Number Name nQ1, VCCO Power Input Output
nPLL_SEL FREQ_SEL VCCA CLK_SEL REF_CLK
Input Output Input Power Power Input Input
Power Negative supply pin. ystal oscillator interface. XTAL_IN input, XTAL_OUT, Input XTAL_OUT output. XTAL_IN NOTE: Pullup Pulldown refer internal input resistors. Table Characterristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
843252AG-04
REV. JANUARY 2006
ICS843252-04
FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
4.6V -0.5V 0.5V 50mA 100mA -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Continuous Current Surge Current Storage Temperature, TSTG
Package Thermal Impedance, 89°C/W lfpm)
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VCCA ICCA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Power Supply Current Test Conditions Minimum 3.135 3.135 Typical Maximum 3.465 3.465 Units
TABLE LVCMOS/LVTTL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input High Voltage Input Voltage REF_CLK, FREQ_SEL, nPLL_SEL REF_CLK, FREQ_SEL, nPLL_SEL 3.465V 3.465V 3.465V, 3.465V, -150 Test Conditions Minimum -0.3 Typical Maximum Units
Input High Current
Input Current
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO Units
NOTE Outputs terminated with VCCO
843252AG-04
REV. JANUARY 2006
ICS843252-04
FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Test Conditions Minimum 19.33 Typical Fundamental Maximum Units
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol fOUT Parameter Output Frequency 156.25MHz Integration Range: 1.875MHz 20MHz 159.375MHz Integration Range: 1.875MHz 20MHz 187.5MHz Integration Range: 1.875MHz 20MHz Test Conditions Minimum 0.39 0.38 0.38 Typical Maximum 187.5 Units
Phase Jitter (Random); NOTE
tsk(o)
Output Skew; NOTE Output Rise/Fall Time
Output Duty Cycle NOTE Please refer Phase Noise Plots following this section. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured VCCO/2. NOTE These parameters guaranteed characterization. tested production.
843252AG-04
REV. JANUARY 2006
ICS843252-04
FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
Phase Noise Plot
LVPECL
Noise Power
VCC, VCCA, VCCO
SCOPE
Phase Noise Mask
Offset Frequency
-1.3V 0.165V
Jitter Area Under Masked Phase Noise Plot
3.3V OUTPUT LOAD TEST CIRCUIT
PHASE JITTER
Clock Outputs
tsk(o)
OUTPUT SKEW
OUTPUT RISE/FALL TIME
nQ0,
PERIOD
PERIOD
100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
843252AG-04
REV. JANUARY 2006
ICS843252-04
FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS843252-04 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with .01F bypass capacitor should connected each VCCA pin. resistor also replaced ferrite bead.
3.3V .01F
.01F
FIGURE POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
ICS843252-04 been characterized with 18pF parallel resonant crystals. capacitor values, shown Figure below were determined using 25MHz, 18pF parallel resonant crystal were chosen minimize error. optimum values slightly adjusted different board layouts.
XTAL_OUT 18pF Parallel Crystal XTAL_IN
Figure CRYSTAL INPUt INTERFACE
843252AG-04
REV. JANUARY 2006
ICS843252-04
FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
RECOMMENDATIONS UNUSED INPUT OUTPUT PINS INPUTS: OUTPUTS:
CRYSTAL INPUT: applications requiring crystal oscillator input, both XTAL_IN XTAL_OUT left floating. Though required, additional protection, resistor tied from XTAL_IN ground. REF_CLK INPUT: applications requiring reference clock, left floating. Though required, additional protection, resistor tied from REF_CLK ground. LVCMOS CONTROL PINS: control pins have internal pull-ups pull-downs; additional resistance required added additional protection. resistor used. LVPECL OUTPUT unused LVPECL outputs left floating. recommend that there trace attached. Both sides differential output pair should either left floating terminated.
TERMINATION 3.3V LVPECL OUTPUT
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
3.3V
FOUT
FOUT
((VOH VOL) (VCC
FIGURE LVPECL OUTPUT TERMINATION
FIGURE LVPECL OUTPUT TERMINATION
843252AG-04
REV. JANUARY 2006
ICS843252-04
FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS843051. Equations example calculations also provided. Power Dissipation. total power dissipation ICS843051 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 80mA 277.2mW Power (outputs)MAX 30mW/Loaded Output pair outputs loaded, total power 30mW 60mW
Total Power_MAX (3.465V, with outputs switching) 277.2mW 60mW 337.2mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C. equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow meter second multi-layer board, appropriate value 81.8°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 0.337W 81.8°C/W 97.6°C. This well below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE LEAD TSSOP, FORCED CONVECTION
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 89.0°C/W
118.2°C/W 81.8°C/W
106.8°C/W 78.1°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
843252AG-04
REV. JANUARY 2006
Calculations Equations. purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
ICS843252-04
FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
VOUT
FIGURE LVPECL DRIVER CIRCUIT TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT
CCO_MAX
OH_MAX
CC_MAX
0.9V
OH_MAX
0.9V 1.7V
logic low, VOUT
CCO_MAX
OL_MAX
CC_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H
OH_MAX
CC_MAX
2V))/R
CC_MAX
OH_MAX
[(2V
CC_MAX
OH_MAX
))/R
CC_MAX
OH_MAX
[(2V 0.9V)/50] 0.9V 19.8mW
Pd_L
OL_MAX
CC_MAX
2V))/R
CC_MAX
OL_MAX
[(2V
CC_MAX
OL_MAX
))/R
CC_MAX
OL_MAX
[(2V 1.7V)/50] 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30mW
843252AG-04
REV. JANUARY 2006
ICS843252-04
FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE LEAD TSSOP
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 89.0°C/W
118.2°C/W 81.8°C/W
106.8°C/W 78.1°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS843252-04 2210
843252AG-04
REV. JANUARY 2006
ICS843252-04
FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
PACKAGE OUTLINE SUFFIX LEAD TSSOP
TABLE PACKAGE DIMENSIONS
SYMBOL 0.45 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 0.10 Millimeters Minimum 1.20 0.15 1.05 0.30 0.20 5.10 Maximum
Reference Document: JEDEC Publication MO-153
843252AG-04
REV. JANUARY 2006
ICS843252-04
FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
Marking 43252A04 43252A04 3252A04L 3252A04L Package Lead TSSOP Lead TSSOP Lead "Lead-Free" TSSOP Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape reel tube 2500 tape reel Temperature 70°C 70°C 70°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS843252AG-04 ICS843252AG-04T ICS843252AG-04LF ICS843252AG-04LFT
NOTE: that ordered with "LF" suffix number Pb-Free configuration RoHS compliant.
aforementioned trademarks, HiPerClockS FemtoClocks trademarks Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 843252AG-04
REV. JANUARY 2006

FEMTOCLOCKSCRYSTAL-TO3.3V LVPECL CLOCK GENERATOR FEATURES di

Top Searches for this datasheet

Other recent searches