EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Ioff Supp

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Ioff Supp

Datasheet Thumbnail

Top Searches for this datasheet

SN74LVC2G125 DUAL BUFFER GATE WITH 3-STATE OUTPUTS
EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Ioff Supports Partial-Power-Down Mode Operation Supports Operation Package Options Include Plastic Thin Shrink Small-Outline (DCT, DCU) Packages
PACKAGE (TOP VIEW)
description
This dual buffer gate designed 1.65-V 5.5-V operation. SN74LVC2G125 features dual line drivers with 3-state outputs. outputs disabled when associated output-enable (OE) input high. ensure high-impedance state during power power down, should tied through pullup resistor; minimum value resistor determined current-sinking capability driver. This device fully specified partial-power-down applications using Ioff. Ioff circuitry disables outputs, preventing damaging current backflow through device when powered down. SN74LVC2G125 characterized operation from -40°C 85°C.
FUNCTION TABLE (each buffer) INPUTS OUTPUT
logic symbol
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. EPIC trademark Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
Copyright 2000, Texas Instruments Incorporated
POST OFFICE 655303
DALLAS, TEXAS 75265
PRODUCT PREVIEW
SN74LVC2G125 DUAL BUFFER GATE WITH 3-STATE OUTPUTS
logic diagram (positive logic)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Output voltage range, (see Notes -0.5 Input clamp current, Output clamp current, Continuous output current, Continuous current through ±100 Package thermal impedance, (see Note package 296°C/W package 329°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input negative-voltage output voltage ratings exceeded input output current ratings observed. value provided recommended operating conditions table. package thermal impedance calculated accordance with JESD
PRODUCT PREVIEW
POST OFFICE 655303
DALLAS, TEXAS 75265
SN74LVC2G125 DUAL BUFFER GATE WITH 3-STATE OUTPUTS
recommended operating conditions (see Note
Supply voltage Operating Data retention only 1.65 1.95 1.65 1.95 1.65 High-level output current 1.65 Low-level output current 0.15 Input transition rise fall rate 1.65 0.65 0.35 ns/V UNIT
High-level High level input voltage
Low-level level input voltage
Input voltage Output voltage
Operating free-air temperature NOTE unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004.
POST OFFICE 655303
DALLAS, TEXAS 75265
PRODUCT PREVIEW
SN74LVC2G125 DUAL BUFFER GATE WITH 3-STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER -100 inputs GND, input TEST CONDITIONS 1.65 1.65 1.65 1.65 Other inputs 1.65 VCC-0.1 0.45 0.55 0.55 UNIT
PRODUCT PREVIEW
Ioff
typical values 25°C.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures through
PARAMETER tdis FROM (INPUT) (OUTPUT) 0.15 UNIT
operating characteristics, 25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN74LVC2G125 DUAL BUFFER GATE WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION 0.15
From Output Under Test (see Note Open TEST tPLZ/tPZL tPHZ/tPZH Open
LOAD CIRCUIT Timing Input Data Input VCC/2 VCC/2 VCC/2 VOLTAGE WAVEFORMS SETUP HOLD TIMES Output Waveform (see Note tPZH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 Output Waveform (see Note Output Control tPZL Input VCC/2 tPLH VCC/2 tPHL VCC/2 VCC/2 tPLZ VCC/2 0.15 tPHZ 0.15 VOLTAGE WAVEFORMS ENABLE DISABLE TIMES Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2
VCC/2
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
PRODUCT PREVIEW
SN74LVC2G125 DUAL BUFFER GATE WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
From Output Under Test (see Note Open TEST tPLZ/tPZL tPHZ/tPZH Open
LOAD CIRCUIT Timing Input VCC/2 VCC/2 VCC/2 VOLTAGE WAVEFORMS SETUP HOLD TIMES Output Waveform (see Note tPZH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 Output Waveform (see Note Output Control tPZL Input VCC/2 tPLH VCC/2 tPHL VCC/2 VCC/2 tPLZ VCC/2 0.15 tPHZ 0.15 VOLTAGE WAVEFORMS ENABLE DISABLE TIMES Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2
PRODUCT PREVIEW
Data Input
VCC/2
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
SN74LVC2G125 DUAL BUFFER GATE WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
Open TEST tPLZ/tPZL tPHZ/tPZH Open
From Output Under Test (see Note
LOAD CIRCUIT
Timing Input Data Input
VOLTAGE WAVEFORMS SETUP HOLD TIMES
Input
VOLTAGE WAVEFORMS PULSE DURATION
Output Control tPZL Output Waveform (see Note tPZH Output Waveform (see Note tPLZ tPHZ VOLTAGE WAVEFORMS ENABLE DISABLE TIMES
Input tPLH
tPHL
Output
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
PRODUCT PREVIEW
SN74LVC2G125 DUAL BUFFER GATE WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
Open
From Output Under Test (see Note
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
Open
LOAD CIRCUIT
Timing Input
VCC/2 VCC/2 VOLTAGE WAVEFORMS SETUP HOLD TIMES VCC/2
Input VCC/2 VCC/2 Data Input
PRODUCT PREVIEW
VOLTAGE WAVEFORMS PULSE DURATION
Input tPLH Output tPHL VCC/2 VCC/2 VCC/2 VCC/2 tPHL VCC/2 tPLH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS
Output Control tPZL
VCC/2 VCC/2 tPLZ VCC/2 tPZH tPHZ VCC/2
Output Waveform (see Note Output Waveform (see Note
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 2000, Texas Instruments Incorporated

EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Ioff Supp

Top Searches for this datasheet

Other recent searches