16COM/80SEG Controller/Driver FEB. 2005 Version other rights

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16COM/80SEG Controller/Driver FEB. 2005 Version other rights

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SPLC782A
16COM/80SEG Controller/Driver
FEB. 2005 Version
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SPLC782A
Table Contents
PAGE
GENERAL DESCRIPTION FEATURES BLOCK DIAGRAM SIGNAL DESCRIPTIONS. FUNCTIONAL DESCRIPTIONS. 5.1. OSCILLATOR 5.2. CONTROL DISPLAY INSTRUCTIONS 5.3. INSTRUCTION TABLE.
5.4. 8-BIT OPERATION 16-DIGIT 1-LINE DISPLAY (USING INTERNAL RESET). 5.5. 4-BIT OPERATION 16-DIGIT 1-LINE DISPLAY (USING INTERNAL RESET). 5.6. 8-BIT OPERATION 16-DIGIT 2-LINE DISPLAY (USING INTERNAL RESET). 5.7. RESET FUNCTION 5.8. DISPLAY DATA RAM). 5.9. TIMING GENERATION CIRCUIT. 5.10. DRIVER CIRCUIT 5.11. CHARACTER GENERATOR ROM). 5.12. CHARACTER GENERATOR RAM). 5.13. CURSOR/BLINK CONTROL CIRCUIT 5.14. INTERFACING MPU. 5.15. SUPPLY VOLTAGE DRIVE. 5.16. REGISTER (INSTRUCTION REGISTER) (DATA REGISTER) 5.17. BUSY FLAG (BF) 5.18. ADDRESS COUNTER (AC). 5.19. SEGMENT DATA DIRECTION 5.20. COMMON DATA DIRECTION 5.21. PORT CONFIGURATION ELECTRICAL SPECIFICATIONS 6.1. ABSOLUTE MAXIMUM RATINGS 6.2. CHARACTERISTICS (VDD 2.4V 4.5V, +75) 6.3. CHARACTERISTICS (VDD 4.5V 5.5V, +75) 6.4. CHARACTERISTICS (VDD 4.5V 5.5V, +75) 6.5. CHARACTERISTICS (VDD 2.4V 4.5V, +75) 6.6. WRITE MODE TIMING DIAGRAM (WRITING DATA FROM SPLC782A). 6.7. READ MODE TIMING DIAGRAM (READING DATA FROM SPLC782A MPU). 6.8. FOLLOWING GRAPS SHOW RELATIONSHIP BETWEEN FOSC TEMPERATURE APPLICATION CIRCUITS 7.1. INTERFACE MPU. 7.2. APPLICATIONS CHARACTER GENERATOR 8.1. SPLC782A 8.2. SPLC782A
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PACKAGE/PAD LOCATIONS 9.1. ASSIGNMENT LOCATIONS 9.2. ORDERING INFORMATION DISCLAIMER. REVISION HISTORY
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16COM/80SEG CONTROLLER/DRIVER
GENERAL DESCRIPTION
SPLC782A, dot-matrix controller driver, low-power CMOS integrated circuit. designing low-cost products. SPLC782A capable connecting with application easily used Provide connecting 4-bit 8-bit Direct driver LCD: COMs SEGs 80-channel Bi-Direction segment driver 16-channel Bi-direction common driver Duty factor (selected program): duty: line dots
FEATURES
Character generator ROM: 10880 bits Character font dots: characters Character font dots: characters type CGROM mode, Max. characters used. Character generator RAM: bits Character font dots: characters
1/11 duty: line dots
1/16 duty: lines dots line
type-A, type-B waveform selected. Built-in power automatic reset circuit Built-in Bias resistor Built-in oscillator circuit (with internal resistor)
Character font dots: characters
BLOCK DIAGRAM
OSC1 MOD0 MOD1 DB0-DB3 DB4-DB7
Support external clock operation Package form: bump chip
Timing Generation Circuit Parallel Serial Data Conversion Circuit Character Generator Character Generator Busy Flag Cursor Blink Control Circuit 80-bit Bi-Direction Shift Register Data Register Latch Circuit Buffer Instruction Register Instruction Decorder Display Data Bytes 16-bit Shift Register Driver Address Counter
Figure 3-1: Block Diagram
Segments Commons
TYPE DIRC COM1COM16
SEG1SEG80
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SIGNAL DESCRIPTIONS
Mnemonic Type Logic Power input Ground Voltage; VLCD Bias Voltage Control. Open Bias, Short Bias start signal read data write data. signal select read write. Read, Write. signal select register. Data register (for read write) Instruction register (for write), SEG80 SEG1 Low-order data bits Description
COM16 COM9 COM8 COM1 TYPE
DIRC
MOD1 MOD0
OSC1
High-order data bits Segment signals LCD. Common signals LCD. Common signals LCD. Alternate Signals. TYPE Type-A TYPE Type-B Common Scan Direction DIRC COM1 COM2 Segment Shift Direction COM15 COM16 COM2 COM1 DIRC COM16 COM15 SEG1 SEG2 SEG79 SEG80 SEG80 SEG79 SEG2 SEG1 CGROM CGRAM Mode Select
MOD1 MOD0 Function CGRAM CGRAM, CGROM CGRAM, CGROM CGROM
Busy flag address counter (for read).
internal clock operation, leave this open.
external clock operation, clock input OSC1. Test Mode Clock Output; Open normally use. Test Mode Data Output; Open normally use.
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FUNCTIONAL DESCRIPTIONS
5.1. Oscillator
built-in oscillator generates suitable clock SPLC782A operation. I/D=1 I/D=0 shifts display left shifts display right
5.2. Control Display Instructions
Control display instructions shown follows:
Figure 5-4: Shift Direction Patterns According Bits
5.2.4. Display ON/OFF control
Code
5.2.1. Clear display
Code
Figure 5-5: Display ON/OFF Control Instruction Code
Figure 5-1: Clear Display Instruction Code
Display Display Cursor Cursor Blinks Blinks
clears whole display sets display data RAMs address address counter.
5.2.2. Return home
Code
Figure 5-2: Return Home Instruction Code
care
sets display data RAMs address address counter display returns original position. cursor blink goes left edge display line lines displayed). content Display Data does change.
5.2.3. Entry mode
shifts display.
Code
During writing reading data, sets cursor move direction
Figure 5-3: Entry Mode Instruction Code
character font line
Cursor
character font
11th line
Blink display alternately
Figure 5-6: Cursor Blinking
5.2.5. Cursor display shift
display.
Without changing RAMs data, move cursor shift
Code
Figure 5-7: Cursor Display Shift Instruction Code
Increment, Decrement. display shift, display does shift.
Shift cursor left Shift cursor right Shift display left. Shift display right.
Description
Address Counter
Cursor follows display shift Cursor follows display shift
Figure 5-8: Shift Patterns According Bits
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5.2.6. Function
Code
Display data read write after this setting. one-line display
Figure 5-9: Function Instruction Code
(aaaaaaa)2: (00)16 (4F)16. two-line display (aaaaaaa)2: (00)16 (27)16 first line, (aaaaaaa)2: (40)16 (67)16 second line.
care sets interface data length. Datas transferred with 8-bit lengths (DB0 DB7). Datas transferred with 4-bit lengths (DB4 DB7). requires times transfer data) sets number display line. One-line display. Two-line display. sets character font. dots character font.
5.2.9. Read busy flag address
Code
dots character font.
Display Lines Character Font Duty Factor dots
Figure 5-10: Function Description
cannot display lines with character font.
5.2.7. character generator address
Code
Figure 5-11: CGRAM address Instruction Code
sets character generator address (aaaaaa)2 address counter. Character generator data read write after this setting.
dots dots
Figure 5-13: Read busy flag address Instruction Code
When indicates that system busy now; will accept instruction until busy same time, address counter contents (aaaaaaa)2 read out.
5.2.10. Write data character generator display data
Code
Figure 5-14: Write Data CGRAM/DDRAM Instruction Code
writes data (dddddddd)2 character generator display
data RAM.
5.2.11. Read data from character generator display data
Code
Figure 5-15: Read Data from CGRAM/DDRAM Instruction Code
5.2.8. display data address
Code
reads data (dddddddd)2 from character generator display data RAM. correct data readout shown belows: address character generator display data shift cursor instruction. Send "Read" instruction.
Figure 5-12: DDRAM address Instruction Code
sets display data address (aaaaaaa)2 address counter.
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5.3. Instruction Table
Instruction Instruction Code Description Write "20H" DDRAM Clear Display DDRAM address "00H" from DDRAM address "00H" Return Home return from cursor 4.1ms Max. Execution time (Temp +75)
original position shifted. contents DDRAM changed. Assign cursor
Entry Mode
direction enable shift entire display display
Display Control
Cursor Display Shift
Function
CGRAM Address DDRAM Address
Read Busy Flag Address Counter
(D), cursor(C), blinking cursor(B) on/off control bit. cursor moving display shift control bit, direction, without changing data. DDRAM interface data length (DL: 8-bit/4-bit), numbers display line 2-line/1-line) and, display font type (F:5x10 dots/5x8 dots) CGRAM address address counter. address counter DDRAM address Whether during internal operation contents address counter read. also known reading Write data into internal (DDRAM/CGRAM). Read data from internal (DDRAM/CGRAM).
Figure 5-16: Instruction Table
moving
4.1ms
100s
100s
100s
100s
100s 100s
Write Data Read Data from
Note: don't care
100s 100s
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5.4. 8-Bit Operation 16-Digit 1-Line Display (Using Internal Reset)
Instruction Display Power reset. display. 8-bit operation select 1-line display line character font.
Operation
Power (SPLC782A starts initializing) Function
Display control
Display Cursor appear. Increase address one.
Entry mode
will shift cursor right when writing RAM/CG RAM. display shift. Write
Write data
cursor incremented shifted right. Write
Write data
Write data
Entry mode
Write data
Write data
Write data
Cursor display shift
Cursor display shift
Write data
cursor incremented shifted right.
WELCOME
Write
cursor incremented shifted right. mode display shift when writing
WELCOME
ELCOME
Write
"(space).
cursor incremented shifted right.
LCOME
Write
cursor incremented shifted right.
COMPAMY
Write
cursor incremented shifted right. Only shift cursor's position left (Y).
COMPAMY
COMPAMY
Only shift cursor's position left (M).
COMPANY
Write
display moves left.
Cursor display shift
COMPANY
Shift display cursor's position right.
Cursor display shift
COMPANY
Shift display cursor's position right.
Write data
COMPANY
Write
(space).
cursor incremented shifted right.
Return home
WELCOME
Both display cursor return original position (address
Figure 5-17: 8-Bit Operation 16-Digit 1-Line Display
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5.5. 4-Bit Operation 16-Digit 1-Line Display (Using Internal Reset)
Power initializing) Function
Instruction (SPLC782A starts
Display Power reset. display. 4-bit operation.
Operation
Function
4-bit operation select 1-line display line character font.
Display control
Display
Cursor appears.
Entry mode
Write data
5.6. 8-Bit Operation 16-Digit 2-Line Display (Using Internal Reset)
Instruction Display
Power (SPLC782A starts initializing) Function
Display control
Entry mode
Write data
Increase address one.
will shift cursor right when writing RAM/CG RAM. display shift. Write
cursor incremented shifted right.
Figure 5-18: 4-Bit Operation 16-Digit 1-Line Display
Operation
Power reset. display.
8-bit operation select 2-line display line character font. Display
Cursor appear.
Increase address one.
will shift cursor right when writing RAM/CG RAM. display shift. Write
cursor incremented shifted right.
Write data
WELCOME_
Write cursor incremented shifted right.
address
WELCOME
sets RAM's address. cursor moved beginning position line. Write cursor incremented shifted right.
Write data
WELCOME
Write data
WELCOME PART_
Write cursor incremented shifted right.
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Instruction Write data
Display
WELCOME PART_
Operation Write cursor incremented shifted right. When writing, sets mode display shift.
Entry mode
WELCOME PART_ ELCOME PARTY_
Write data
Write cursor incremented shifted right.
Return home
WELCOME PARTY
Both display cursor return original position (address
Figure 5-19: 8-Bit Operation 16-Digit 2-Line Display
5.7. Reset Function
power starts internal auto-reset circuit executes initial instructions.
Power
Wait time after 4.5V
Wait time
Wait time
8-Bit Interface Wait time 40ms After 2.7V cannot checked before this instruction Function Interface bits length cannot checked before this instruction Function Interface bits length cannot checked before this instruction Function Interface bits length checked after following instructions
There initial procedures shown belows:
Function Interface bits length Specify number display lines character font number display lines character font cannot changed afterwards Display
Display clear Entry mode
Figure 5-20: Reset Function (8-bit Interface)
Initialization Ends
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4-Bit Interface Power Wait time after 4.5V Wait time Wait time cannot checked before this instruction Function Interface bits length Wait time 40ms After 2.7V cannot checked before this instruction Function Interface bits length
cannot checked before this instruction Function Interface bits length checked after following instructions
Initialization Ends
Function interface bits length) Interface bits length Function Interface bits length Specify number display lines character font Display Display clear Entry mode
Figure 5-21: Reset Function (4-bit Interface)
number display lines character font cannot changed afterwards
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5.8. Display Data RAM)
stores display data size bytes. area that used display used general data RAM. address address counter. There relations between display data RAMs address LCDs position shown belows.
1-line display display characters
Display position Display data address
Example 1-line display display characters
Display position Display data address
When display shift operation performed display data RAM's address moves Left shift Right shift
5.9. Timing Generation Circuit
internal circuits. generated.
timing generation circuit generate needed timing signals
access timing access timing separately
5.10. Driver Circuit
There commons segments signal drivers
driver circuit. When program specifies character fonts
line numbers, corresponding common signals will output drive waveforms others still output unselected waveforms.
Figure 5-22: Relations Between Display Data Ram's Address LCD's Position
also
5.11. Character Generator ROM)
Using 8-bit character code, character generator generates character patterns. character patterns. generate character patterns
prevent internal timing interface,
5.12. Character Generator RAM)
Using programs, users easily change character patterns character generator RAM. character patterns. written with dots, character patterns written with dots,
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Here SPLC782As character patterns shown belows: Correspondence between Character Codes Character Patterns.
Figure 5-23: Character Code Character Patterns
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relations between character generator addresses, character generator data (character patterns) character codes shown belows:
5.12.1. character patterns
Character Code Data
Address
Character Patterns Data
Note1: Note2:
means that bit0~2 character code correspond bit3~5 address. These areas used display, used general data RAM.
Note3: When bit4-7 character code character patterns selected. Note4: Selected, selected care display character. with cursor.
Note5: example (1), character code b7-b4 display Note6: bits character code character pattern line position.
Figure 5-24: Character Patterns
Character Pattern Example
Cursor Position
Character Pattern Example
That means character code (00) 16,and (08)
line cursor position display formed logical
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5.12.2. character patterns
Character Code Data
Address
Character Patterns Data Character Pattern Example
Note1: Note2:
means that bit1~2 character code correspond bit4~5 address.
These areas used display, used general data RAM.
Note3: When bit4-7 character code character patterns selected. Note4: Selected, selected, care (08) 16,and (09) display character. with cursor.
Note5: example (1), character code b7-b4 display That means character codes (00) (01) Note6: bits character code character pattern line position. 11th line cursor position display formed logical
Figure 5-25: Character Patterns
Cursor Position
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5.13. Cursor/Blink Control Circuit
generate cursor blink cursor blink control circuit. address address counter. When address counter (07) cursor's position shown follows: cursor blink appears digit display data
1-line display digit 2-line display digit line line Display position
Display data address Hexadecimal
cursor position
Display position cursor position
Figure 5-26: Cursor/Blink Control
Display data address Hexadecimal
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5.14. Interfacing
There types data operations: 4-bit operation 8-bit operation. Using 4-bit MPU, interfacing 4-bit data Using 4-bit transferred lines (for 8-bit operation, DB4). lines used. interface 8-bit data needs times. transferred 4-busline (for 8-bit operation, DB4). Secondly, lower 4-bit data transferred lines (for 8-bit operation, DB0). Using 8-bit MPU, interfacing 8-bit data transferred lines (DB0 DB7).
First, higher 4-bit data
Internal operation
Functioning Busy busy Instruction Write Busy flag check Busy flag check
Figure 5-27: Example 4-bit Data Transfer Timing Sequence
Data Write
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Internal operation
Functioning
Busy
Busy
Busy
Instruction Write Busy flag check Busy flag check Busy flag check
Data Write
Figure 5-28: Example 8-bit Data Transfer Timing Sequence
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5.15. Supply Voltage Drive
bias selected open/short pins. Duty Factor Supply Voltage 1/8, 1/11 Short 1/16 Open
Bias (1/8, 1/11 Duty) Bias (1/16 Duty) SPLC782A SPLC782A
short
open
Figure 5-29: Supply Voltage Drive
5.15.1. relations between frames frequency oscillators frequency
(Assume oscillation frequency 250KHz, clock cycle time 4.0s)
5.15.2. Duty, type-A waveform
COM1
frame 12800 12.8 Frame frequency 78.1 (Hz) 12.8 (ms)
5.15.3. 1/11 Duty, type-A waveform
COM1
frame 17600 17.6 Frame frequency 56.8 (Hz) 17.6 (ms)
clocks
V2(V3) frame
Figure 5-30: Duty type-A waveform
clocks
V2(V3)
frame
Figure 5-31: 1/11 Duty type-A waveform
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5.15.4. 1/16 Duty, type-A waveform
clocks
COM1 frame frame 12800 12.8 78.1 (Hz) Frame frequency 12.8 (ms)
Figure 5-32: 1/16 Duty type-A waveform
5.15.5. Duty, type-B waveform
COM1 V2(V3)
5.15.6. 1/11 Duty, type-B waveform
clocks Frame Frame frame 4(s) 12800(s) 12.8ms Framefrequ ency 78.1(Hz) 12.8(ms)
Figure 5-33: Duty type-B waveform
clocks
COM1 V2(V3)
Frame frame 4(s) 17600(s) 17.6ms Framefrequency 17.6(ms) 56.8(Hz)
Frame
Figure 5-34: 1/11 Duty type-B waveform
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5.15.7. 1/16 Duty, type-B waveform
clocks COM1 Frame frame 4(s) 12800(s) 12.8ms Framefrequ ency 78.1(Hz) 12.8(ms)
Figure 5-35: 1/16 Duty type-B waveform
Frame
5.16. Register (Instruction Register) (Data Register)
SPLC782A 8-bit registers (instruction register) (data register). followings, combinations select
write (Display clear, etc.) (DB0 DB6)
Read busy flag (DB7) address counter
write Display data Character generator RAM)
read (Display data Character generator
5.17. Busy Flag (BF)
When busy flag output DB7. instructions until busy flag
busy flag SPLC782A busy state does accept
5.19. Segment Data Direction 5.20. Common Data Direction
Operation VDD.
segment data shift direction control pin. data shifted from SEG1 SEG80 connecting VSS, reversed connecting VDD.
DIRC common data shift direction control pin.
common scan sequence from COM1 COM16
connecting DIRC VSS, reversed connecting DIRC
5.21. Port Configuration 5.21.1. Input port:
PMOS
NMOS
Figure 5-36: Input port: Configuration
5.18. Address Counter (AC)
address counter assigns addresses display data character generator RAM. When instruction address After
PMOS PMOS
5.21.2. Input port: R/W,
written address information sent from
writing into reading from)display data character generator RAM, automatically incremented decremented -1). contents output when
NMOS
Figure 5-37: Input port: Configuration
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5.21.3. Output port: CL2,
PMOS
NMOS
Figure 5-38: Output port: CL2, Configuration
5.21.4. Input Output port:
PMOS PMOS NMOS
Figure 5-39: Input/Output port: DB0-DB7 Configuration
Enable
Data
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ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics Operating Voltage Driver Supply Voltage Input Voltage Range Operating Temperature Storage Temperature
conditions AC/DC Electrical Characteristics.
Symbol TSTO
Ratings -0.3V +7.0V -0.3V +7.0V -0.3V +0.3V +125
Note: Stresses beyond those given Absolute Maximum Rating table cause operational errors damage device.
6.2. Characteristics (VDD 2.4V 4.5V, +75)
Characteristics Operating Voltage Symbol IDD1 IDD2 Limit Min. Typ. Max.
Unit
Operating Current
Input High Voltage Input Voltage
Input High Current Input Current
Output High Voltage Output Voltage Voltage Drop
Operating Current Voltage
Note1: Typ. condition 3.0V Max. condition 4.5V Note2: Typ. condition 6.0V Max. condition 6.0V
0.15 0.18 0.25 0.48 VIH1 VIL1 0.7VDD -0.3 0.55 -5.0 -100 VOH1 VOL1 0.75VDD 0.2VDD VDCOM VDSEG 0.35 0.45
normal operational
Test Condition
access from (Note1)
Access operation from (FCYC 500KHz)(Note1) Pins:(E, R/W, DB7)
Pins: (RS, R/W, DB7)
0.1mA, Pins: 0.1mA, Pins:
0.1mA, Pins: COM1 COM16 0.1mA, Pins: SEG1 SEG80
6.0V (Note2) bias bias
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6.3. Characteristics (VDD 4.5V 5.5V, +75)
Characteristics Operating Voltage Operating Current Symbol IDD1 IDD2 VIH1 VIL1 VOH1 VOL1 VDCOM VDSEG Limit Min. 0.7VDD -0.3 Typ. 0.25 0.45 Max. 0.35 -150 Unit access from (Note1) Access operation from (FCYC 500KHz)(Note1) Pins:(E, R/W, DB7) Pins: (RS, R/W, DB7) Test Condition
Input High Voltage Input Voltage Input High Current Input Current Output High Voltage (TTL) Output Voltage (TTL) Voltage Drop
Operating Current Voltage
Note1: Typ. condition 5.0V Max. condition 5.5V Note2: Typ. condition 6.0V Max. condition 6.0V
6.4. Characteristics (VDD 4.5V 5.5V, +75)
6.4.1. Internal clock operation oscillator frequency chart reference Figure 6-3)
Characteristics Frequency Symbol FOSC1 Limit Typ. Unit
6.4.2. bias resistor
Characteristics Bias Resistor
6.4.3. Write mode (Writing data from SPLC782A)
Characteristics Cycle Time Pulse Width Rise/Fall Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Symbol
0.35 0.45 Min. Max. Symbol Limit Typ. Min. Max. Limit Min. Typ. Max. Unit tSP1 tHD1 tSP2 tHD2
0.1mA, Pins:
0.1mA, Pins:
0.1mA, Pins: COM1 COM16 0.1mA, Pins: SEG1 SEG80 bias bias
6.0V (Note2)
Unit K-ohm
Test Condition
Pins: R/W, Pins: R/W, Pins: Pins:
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6.4.4. Read mode (Reading Data from SPLC782A MPU)
Characteristics Cycle Time Pulse Width Rise/Fall Time Address Setup Time Address Hold Time Data Output Delay Time Data hold time Symbol tSP1 tHD1 tHD2 Limit Min. Typ. Max. Unit Test Condition Pins: R/W, Pins: R/W,
6.5. Characteristics (VDD 2.4V 4.5V, +75)
6.5.1. Internal clock operation oscillator frequency chart reference Figure 6-3)
Characteristics Frequency
6.5.2. bias resistor
Characteristics Bias Resistor
6.5.3. Write mode (Writing data from SPLC782A)
Characteristics Cycle Time Symbol
Pulse Width
Rise/Fall Time
Address Setup Time Address Hold Time Data Setup Time Data Hold Time
6.5.4. Read mode (Reading data from SPLC782A MPU)
Characteristics Cycle Time Pulse Width Rise/Fall Time Address Setup Time Address Hold Time Data Output Delay Time Data hold time Symbol tSP1 tHD1 tHD2
Symbol FOSC1 Limit Typ. Min. Max. Symbol Limit Typ. Min. Max. Limit Min. Typ. Max. Unit 1250 tSP1 tHD1 tSP2 tHD2 Limit Typ. Min. 1250 Max. Unit
Pins: Pins:
Unit Unit
K-ohm
Test Condition
Pins: R/W, Pins: R/W, Pins:
Pins:
Test Condition Pins: R/W, Pins: R/W, Pins:
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6.6. Write Mode Timing Diagram (Writing Data from SPLC782A)
tSP1 tSP2 tHD1 tHD1
tHD2
Valid Data
Figure 6-1: Write Mode Timing Diagram
6.7. Read Mode Timing Diagram (Reading Data from SPLC782A MPU)
VIH1 VIL1 tSP1 VIH1 VIL1
6.8. Following Graps Show Relationship Between FOSC Temperature
SPLC782A Fosc Frequency (VDD 2.4V 5.5V)
tHD1 VIH1 VIH1 VIH1 VIL1 VIH1 VIL1 tHD1 VIL1 VIH1 VIL1 tHD2 Valid Data VIH1 VIL1
Figure 6-2: Read Mode Timing Diagram
Min. Typ. Max.
Temp
FOSC (Max.) 515KHz 5.5V, Temp FOSC (Min.) 114KHz 2.4V, Temp Figure 6-3: Relationship Between Fosc Temperature
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APPLICATION CIRCUITS
7.1. Interface 7.1.1. Interface 8-bit (6805)
6805
COM1 COM16 SEG1 SEG80
PANEL COMMONS
SPLC782A
SEGMENTS
7.1.2. Interface 8-bit (Z80)
Figure 7-1: Interface 8-bit (6805)
COM1 COM16
PANEL
SPLC782A
COMMONS
IORQ
SEG1 SEG80
SEGMENTS
Figure 7-2: Interface 8-bit (Z80)
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7.2. Applications 7.2.1. Chip bottom lower view (DIRC "0", "0")
Panel characters line
COM8 COM1
SPLC782A BOTTOM VIEW
DIRC
Example dots characters line Bias Duty
Figure 7-3: Chip Bottom Lower View (Example
Example dots characters line Bias Duty
Figure 7-4: Chip Bottom Lower View (Example
Panel SEG80 SEG1 COM8 COM1
SEG80
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SEG1
DIRC
characters line
SPLC782A BOTTOM VIEW
COM11 COM9
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Panel characters line
COM8 COM1
SPLC782A BOTTOM VIEW
DIRC
COM16 COM9
7.2.2. Chip bottom upper view (DIRC "1", "1")
Panel
characters line
Example dots characters lines Bias Duty
Figure 7-5: Chip Bottom Lower View (Example
SEG80
Example dots characters line Bias Duty
Figure 7-6: Chip Bottom Upper View (Example
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SEG1
SEG1
SEG80
DIRC
COM1 COM8
SPLC782A BOTTOM VIEW
FEB. 2005 Version:
SPLC782A
COM1 COM8 SEG1
COM9 COM11 SEG80
DIRC
SPLC782A BOTTOM VIEW
Panel characters line
characters line
Example dots characters line Bias Duty
Figure 7-7: Chip Bottom Upper View (Example
COM9
DIRC
COM1 COM8 SEG1
COM16
Panel
Example dots characters lines Bias Duty
Figure 7-8: Chip Bottom Upper View (Example
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SEG80
SPLC782A BOTTOM VIEW
FEB. 2005 Version:
SPLC782A
7.2.3. Chip lower view (DIRC "0", "1")
Panel characters line
Panel characters line
Example dots characters line Bias Duty
Figure 7-9: Chip Lower View (Example
SEG80
SEG80 COM11 COM9
SPLC782A VIEW
DIRC
COM8 COM1
SEG1
SEG1
SPLC782A VIEW
COM8 COM1
DIRC
Example dots characters line Bias Duty
Figure 7-10: Chip Lower View (Example
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Panel characters line
COM16 COM9
SPLC782A VIEW
7.2.4. Chip upper view (DIRC "1", "0")
Figure 7-11: Chip Lower View (Example
DIRC
COM8 COM1 SEG1
Example dots characters lines Bias Duty
COM1 COM8
DIRC
SEG80
SPLC782A VIEW
SEG80
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SEG1
Panel
characters line
Example dots characters line Bias Duty
Figure 7-12: Chip Upper View (Example
FEB. 2005 Version:
SPLC782A
COM1 COM8 SEG1
COM1 COM8 SEG1 DIRC
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DIRC
COM9 COM11 SEG80
SPLC782A VIEW
Example dots characters line Bias Duty
Figure 7-13: Chip Upper View (Example
Panel
characters line
COM9
SPLC782A VIEW
COM16
Example dots characters lines Bias Duty
Figure 7-14: Chip Upper View (Example
SEG80
Panel
characters line
FEB. 2005 Version:
SPLC782A
CHARACTER GENERATOR
8.1. SPLC782A
Figure 8-1: CGROM (SPLC782A-016)
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SPLC782A
8.2. SPLC782A
Figure 8-2: CGROM (SPLC782A-022)
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PACKAGE/PAD LOCATIONS
9.1. Assignment Locations
Please contact Sunplus sales representatives more information.
9.2. Ordering Information
Product Number SPLC782A-NnnnV-C
Note1: Code number assigned customer. Note2: Code number 999); version
Package Type Chip form with gold bump
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DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication FURTHER, SUNPLUS MAKES WARRANTY SUNPLUS reserves right halt production alter specifications regarding freedom described chip(s) from patent infringement. MERCHANTABILITY FITNESS PURPOSE. prices time without notice. publication current before placing orders.
Accordingly, reader cautioned verify that data sheets other information this Products described herein intended normal commercial applications.
Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. Please note that application circuits illustrated this document reference purposes only.
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REVISION HISTORY
Date FEB. 2005 Revision Description Modify from TYPE DIRC section 5.20 Common data Direction description(TA=25) section 6.5.1 6.5.2 Correct description Figure Correct code 5.2.9 Read busy flag address Modify execution time Instruction table Remove note Figure 5-16 Correct display 14~21 Figure 5-17 Insert display Figure 5-19 Modify Driver Supply voltage absolute maximum ratings Characteristics Page
Modify operation current IDD1 IDD2 Characteristics
DEC. 2004
APR. 2004
APR. 2004
JUN. 2003
MAY. 2002
description max. min. Fosc Figure figure number figure Modify max. Value -100uA Modify max. Value -150uA Modify VIH1 min. Value 0.7VDD Modify DC/AC Characteristics TA=-20 Modify 6.5.3 6.5.4 Cycle time 1250ns Modify 6.5.3 6.5.4 Pulse Width 600ns Modify description: "Execution time" "Execution time (Temp 25)" Modify Note2: from 2.3ms 4.1ms min. max. value Instruction Table 8-bit/4-bit data transfer timing sequence example Note2 Instruction Table "8.3 SPLC782A Remove PACKAGE/PAD LOCATIONS" Correct error pin: pin: pin: pin: MOD1 pin: MOD0 pin: Correct size: character patterns 5*10 5*10 character patterns Modify pins "CL2" description: "normal mode" "normally use" SIGNAL DESCRIPTIONS" Modify OSC1 description SIGNAL DESCRIPTIONS" Modify Characteristics ELECTRICAL SPECIFICATIONS"
operation current Characteristics Characteristics
24-25 24-25
"6.8 Following Graps Show Relationship Between FOSC Temperature"
NOV. 2001
Modify "MODE1" "MOD1", "MODE2" "MOD0" SIGNAL DESCRIPTIONS"
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Date JUL. 2001 Revision Delete "PRELIMINARY" "with gold bump" "9.3 Ordering Information" Renew document format MAY. 2001 Original Description Page
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16COM/80SEG Controller/Driver FEB. 2005 Version other rights

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