Source Driver Features Output: output channels 6-bit resolution g
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NT3967
Source Driver
Features Output: output channels 6-bit resolution gray scales inversion with polarity control adjusting Gamma correction Power analog circuit: Output dynamic range: AVDD-0.1V Power consumption analog circuit: General Description NT3967 data driver color panel, SVGA(800*600) UXGA(1600*1200) applications. better performance, inversion wide range voltage output designed this chip reducing EMI, data inversion control used. This chip supplies sections voltage-reference Gamma correction. Power interface circuit: 2.5~3.6V Operating frequency: 65MHz Output deviation: 20mV Data inversion reducing Cascade function with bi-direction shift control CMOS silicon gate p-type substrate package
Block diagram
OUT1 OUT2 OUT3 OUT402 OUT401
Driver Buffer channels
Digit Analog Converter
REV1
Level Shift
Decoder
Decoder
Line Latch bits
REV2 DIO1
67-bit Shift Register
DIO2
AVDD
AVSS
Version
,2001
NT3967 Source Driver
NT3967 configuration (Face up): This figure does specify package.
DIO2 AVDD AVSS REV1 REV2 DIO1
OUT402 OUT401 OUT400 OUT399 OUT398
NT3967
OUT206 Dummy pads Dummy OUT205
OUT5 OUT4 OUT3 OUT2 OUT1
Version
7,2001
NT3967 Source Driver
Description Designation REV1 REV2 OUT1 OUT402 Description Data input. 6-bit data,2 pixels, color data MSB;
Controls whether data D00~D25 inverted not. When "REV1"=1 these data will inverted. "00" 3F", 38", "2A", Controls whether data D30~D55 inverted not, same REV1. Clock input; latching data onto line latches rising edge. Gamma correction reference voltage. voltage these pins must AVSS< V10< V8<V7<V6; V5<V4<V3<V2<V1< AVDD Output drive signals;
DIO1 DIO2
AVDD AVSS Dummy
Selects left right shift; SHL="1" DIO1 DIO2 SHL="0" OUT397,398,399,400,401,402DIO2 DIO1 DIO2 SHIFT Input Output Right Output Input Left Start pulse signal input/output When applied high (SHL="1"), start high-pulse DIO1 latched rising edge CLK. Then data latched serially onto internal latches rising edge CLK. After line latches filled with data, clocks, pulse shifted through DIO2 rising edge CLK. This function cascade more devices dot-size expansion. normal applications, DIO2 signal first device connected DIO1 second stage, DIO2 second connected DIO1 third, like daisy chain. contrast, when applied low, start pulse inputs DIO2, pulse outputs through DIO1. *Remark: input pulse-width DIO1/2 exceed clock-cycle. Latches polarity outputs switches data outputs. rising edge, latches "POL" signal control polarity outputs. also controls switch line registers that switches incoming data outputs. *Remark: switch data outputs anytime even line data completely full. Polarity selector dot-inversion control. Available rising edge "POL" value latched rising edge "LD" control polarity even outputs. "POL=1" indicates that even outputs positive polarity with voltage range from V1~V5, outputs negative polarity with voltage range from V10. other hand, receives level "POL", even outputs negative polarity outputs positive polarity. POL=1: Even outputs range from outputs range from POL=0: Even outputs range from outputs range from Power supply analog circuit Ground analog circuit Power supply digital circuit Ground digital circuit Dummy pads
Version
7,2001
NT3967 Source Driver
Power on/off sequence:
This high-voltage driver, damaged large current flow when incorrect power sequence used. recommend power on/off sequence first connect logical power, then drive power, AVDD&AVSS with V1~V10 When shutting power, first shut drive power then logic system, turn power simultaneously. Relationship between order input data output channels SHL="1", Start pulse from DIO1, shift right Output OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 Order First data Data D05~D00 D15~D10 D25~D20 D35~D30 D45~D40 D55~D50 SHL="0", Start pulse from DIO2, shift left Output OUT397 OUT398 OUT399 OUT400 OUT401 OUT402 Order First data Data D05~D00 D15~D10 D25~D20 D35~D30 D45~D40 D55~D50 -OUT402 Last data D55~D50 OUT6 Last data D55~D50
Relationship between input data output voltage figure below shows relationship between input data output voltage with polarity. range V1~V5 positive polarity, negative polarity. Please refer following page relative sistor value voltage calculation method.
Gamma correction diagram Vout AVDD
Vcom Negative polarity Positive polarity
AVSS Input Data
Remark: AVDD-0.1 >AVSS+0.1V
Version
7,2001
NT3967 Source Driver
Gamma correction resistor
Name
Resistor
Name
Resistor
1.6K
8.05K
2.75K
3.45K
Total impedance, Rn=R0 R62, equals 15.85K
Version
7,2001
NT3967 Source Driver
Output Voltage Input Data Data Output Voltage Positive polarity 7250/8050 6500/8050 5800/8050 5150/8050 4550/8050 4000/8050 3450/8050 2950/8050 2450/8050 2050/8050 1650/8050 1300/8050 950/8050 600/8050 300/8050 X2450/2750 2200/2750 1950/2750 1700/2750 1500/2750 1300/2750 1100/2750 950/2750 800/2750 650/2750 500/2750 400/2750 300/2750 200/2750 100/2750 1500/1600 1400/1600 1300/1600 1200/1600 1100/1600 1000/1600 900/1600 800/1600 700/1600 600/1600 500/1600 /1600 300/1600 200/1600 100/1600 Version Output Voltage Negative polarity
V10) 800/8050 V10) 1550/8050 V10) 2250/8050 V10) 2900/8050 V10) 3500/8050 V10) 4050/8050 V10) 4600/8050 V10) 5100/8050 V10) 5600/8050 V10) 6000/8050 V10) 6400/8050 V10) 6750/8050 V10) 7100/8050 V10) 7450/8050 V10) 7750/8050 300/2750 550/2750 800/2750 1050/2750 1250/2750 1450/2750 1650/2750 1800/2750 1950/2750 2100/2750 2250/2750 2350/2750 2450/2750 2550/2750 2650/2750 100/1600 200/1600 300/1600 400/1600 500/1600 600/1600 700/1600 800/1600 900/1600 1000/1600 1100/1600 1200/1600 1300/1600 1400/1600 1500/1600
7,2001
NT3967 Source Driver
Output Voltage Input Data (continued) Data Output Voltage Positive polarity
3350/3450 3250/3450 3150/3450 3050/3450 2950/3450 2800/3450 2650/3450 2500/3450 2300/3450 2100/3450 1850/3450 1600/3450 1300/3450 800/3450
Output Voltage Negative polarity
100/3450 200/3450 300/3450 400/3450 500/3450 650/3450 800/3450 950/3450 1150/3450 1350/3450 1600/3450 1850/3450 2150/3450 2650/3450
Version
7,2001
NT3967 Source Driver
Absolute Maximum Ratings*
Digital supply voltage, -0.5V Analog supply voltage, AVDD -0.5V +11V Supply voltage, -0.3 ~AVDD+0.3 Digital input voltage -0.5V Vcc+0.5V Output voltage, DIO1 DIO2 -0.5V Vcc+0.5V Output voltage,OUT1~OUT420 -0.5V DD+0.5V Storage temperature Operating temperature
*Comments
Stresses above those listed under "Absolu Maximum Ratings" cause permanent damage device. These stress ratings only. Functional operation this device these under other conditions above those indicated operational sections this specification implied exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics =2.5~3.6V DD=6.5~10V, AVSS=GND=0V, =-10~75)
(For digital circuit)
Parameter Supply Voltage Level Input Voltage High Level Input Voltage High Level Output Voltage Level Output Voltage Input Leakage Current Digital Stand-by current Digital Operating Current Symbol Min. 0.7xVcc Vcc-0.3V Typ. Max. Unit 0.3xVcc GND+0.3V Conditions Digital power digital circuit digital circuit DIO1/2, Ioh=500uA DIO1/2, Iol=-500uA digital circuit stopped, DIO1/2 load Fclk=40 MHz, FLD=50KHz
(For analog circuit)
Parameter Supply Voltage Input level Input level Voltage Output Deviation Voltage Output Offset Dynamic Range Output Sinking Current outputs Driving Current outputs Impedance Gamma Correction Analog Operating Current Symbol Min. AVDD Vref 0.4AVDD Vref Typ. -180 Max. AVDD-0.1 0.6AVDD AVDD-0.1 1.3*Rn Unit Conditions analog circuit power Gamma correction voltage Gamma correction voltage Vo=0.1V 1.5V AVDD-1.5 AVDD0.1V Vo=1.5V AVDD-1.5V OUT1 OUT402 OUT1 OUT402; Vo=0.1V 1.1V OUT1 OUT402; Vo=9.9V 8.9V Rn=15850 ohm, from V6~V10 load, Fclk=33MHz, FLD=50KHz
-150 0.8*Rn
Version
7,2001
NT3967 Source Driver
Electrical Characteristics (Vcc =3.0~3.6V AVDD=6.5~10V, AVSS=GND=0V, -10~75) Parameter frequency period cycle pulse width Data set-up time Data hold time Propagation delay DIO2/1 Time that last data Pulse width Time that DIO1/2 set-up time hold time Output stable time Output loading Symbol Fclk Tcph Tphl Twld Tlds Tpsu Tphd Min. Typ. Max. Unit Tcph Tcph Tcph Conditions
D55, REVx DIO1/2 D55, REVx DIO1/2 CL=25pF Output
final value below with 30mV precision CL=75pF, R=5K OUT1 OUT402
Electrical Characteristics (Vcc =2.5~3.0V DD=6.5~10V, AVSS=GND=0V, -10~75) Parameter frequency period cycle pulse width Data set-up time Data hold time Propagation delay DIO2/1 Time that last data Pulse width Time that DIO1/2 set-up time hold time Output stable time Output loading Symbol Fclk Tcph Tphl Twld Tlds Tpsu Tphd Min. Typ. Max. Unit Tcph Tcph Tcph Conditions
D55, REVx DIO1/2 D55, REVx DIO1/2 CL=25pF Output
final value below with 30mV precision CL=75pF, R=5K OUT1 OUT402
Version
7,2001
NT3967 Source Driver
Timing Diagram
Tcph DIO1/2 Input Data, REVx Second data Tphl DIO1/2 Output Last data Tphl
First data
Last Twld Tlds
DIO1/2 Input
Tpsu Tpdh
outputs
High-Z
Positive
High-Z
Even outputs
High-Z
Negative
Output load condition Output
Vcom
Version
7,2001
NT3967 Source Driver
Function operation
DIO1/2 Input
1CLK min.) 2CLK min.)
1CLK
Data, REVx
Last Data
First Data
Outputs
Vcom
~V10
Even Outputs
~V10
Version
7,2001
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