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16COM/80SEG Controller/Driver MAR. 2005 Version patent other


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SPLC783A
16COM/80SEG Controller/Driver
MAR. 2005 Version
patent other rights third parties which result from use. addition, Sunplus products authorized critical components life support devices/ systems aviation devices/systems, where malfunction failure product reasonably expected result significant injury user, without express written approval Sunplus.
SPLC783A
Table Contents
PAGE
GENERAL DESCRIPTION BLOCK DIAGRAM FEATURES SIGNAL DESCRIPTIONS. 4.1. FUNCTIONAL DESCRIPTIONS. 5.1. OSCILLATOR 5.2. CONTROL DISPLAY INSTRUCTIONS 5.3. INSTRUCTION TABLE. 5.4. 8-BIT OPERATION 8-DIGIT 1-LINE DISPLAY (USING INTERNAL RESET).
5.5. 4-BIT OPERATION 8-DIGIT 1-LINE DISPLAY (USING INTERNAL RESET).11 5.6. 8-BIT OPERATION 8-DIGIT 2-LINE DISPLAY (USING INTERNAL RESET).11 5.7. RESET FUNCTION. 5.8. DISPLAY DATA RAM). 5.9. TIMING GENERATION CIRCUIT. 5.10. DRIVER CIRCUIT 5.11. CHARACTER GENERATOR ROM). 5.12. CHARACTER GENERATOR RAM). 5.13. CURSOR/BLINK CONTROL CIRCUIT 5.14. INTERFACING MPU. 5.15. SUPPLY VOLTAGE DRIVE. 5.16. REGISTER (INSTRUCTION REGISTER) (DATA REGISTER) 5.17. BUSY FLAG (BF) 5.18. ADDRESS COUNTER (AC). 5.19. PORT CONFIGURATION ELECTRICAL SPECIFICATIONS 6.1. ABSOLUTE MAXIMUM RATINGS 6.2. CHARACTERISTICS (VDD 2.7V 4.5V, 6.3. CHARACTERISTICS (VDD 2.7V 4.5V, 6.4. CHARACTERISTICS (VDD 4.5V 5.5V, 25). 6.5. CHARACTERISTICS (VDD 4.5V 5.5V, APPLICATION CIRCUITS 7.1. R-OSCILLATOR 7.2. INTERFACE MPU. 7.3. SPLC783A APPLICATION CIRCUIT 7.4. APPLICATIONS CHARACTER GENERATOR 8.1. SPLC783A 8.2. SPLC783A
Sunplus Technology Co., Ltd. Proprietary Confidential
MAR. 2005 Version:
SPLC783A
PACKAGE/PAD LOCATIONS 9.1. ASSIGNMENT LOCATIONS 9.2. PACKAGE INFORMATION 9.3. ORDERING INFORMATION 9.4. STORAGE CONDITION PERIOD PACKAGE 9.5. RECOMMENDED TEMPERATURE PROFILE. DISCLAIMER. REVISION HISTORY
Sunplus Technology Co., Ltd. Proprietary Confidential
MAR. 2005 Version:
SPLC783A
16COM/80SEG CONTROLLER/DRIVER
GENERAL DESCRIPTION
SPLC783A, dot-matrix controller driver from SUNPLUS, unique design displaying alpha-numeric, Japanese-Kana characters symbols. SPLC783A single provides types interfaces MPU: 4-bit 8-bit interfaces. transferring speed 8-bit twice faster than 4-bit. SPLC783A able display 16-character lines. extended. rank.
FEATURES
Character generator ROM: 10880 bits Character font dots: characters Character font dots: characters Character generator RAM: bits Character font dots: characters Character font dots: characters 4-bit 8-bit interfaces
cascading with SPLC100 SPLC063, display capability CMOS technology ensures power saves most efficient performance keeps highest
Direct driver LCD: COMs SEGs Duty factor (selected program): duty: line dots 1/11 duty: line dots
BLOCK DIAGRAM
OSC1 OSC2
Timing Generation Circuit
Parallel Serial Data Conversion Circuit Busy Flag Character Generator Character Generator
DB0-DB3 DB4-DB7 Power Supply Drive (V1-V5) Buffer
Data Register
Instruction Register
1/16 duty: lines dots line Built-in power automatic reset circuit Support external clock operation Power Consumption
CLK1, CLK2 80-bit Cursor Blink Control Circuit Shift Register
Built-in oscillator circuit (with external resistor)
Package form: bare chip available
Latch Circuit
Display Data Bytes
16-bit Shift
Segments Commons Driver
COM1COM16
Instruction Decorder
Register
SEG1SEG80
Address Counter
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SIGNAL DESCRIPTIONS
Mnemonic OSC1 OSC2 Type Power input Ground Both OSC1 OSC2 connected resistor internal oscillator circuit. external clock operation, clock input OSC1. Supply voltage driving. start signal reading writing data. signal selecting read write actions. Read, Write. signal selecting registers. Data Register (for read write) Instruction Register (for write), CLK1 CLK2 SEG1 SEG33 4-bit data Description
SEG34 SEG80 COM1 COM16 TEST
High 4-bit data Clock latch serial data Clock shift serial data Switch signal convert waveform Selection, Non-selection. Segment signals LCD. Common signals LCD. TEST pin. This must fixed open.
Busy flag Address Counter (for read).
Sends character pattern data corresponding each common signal serially.
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4.1.
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 OSC2 OSC1
SEG60 SEG61 SEG62 SEG63
SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1
SEG64
TEST
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CLK1
CLK2
MAR. 2005 Version:
SPLC783A
FUNCTIONAL DESCRIPTIONS
5.1. Oscillator
SPLC783A oscillator supports only internal oscillator operation, also external clock operation. I/D=1 I/D=0 shifts display left shifts display right
5.2. Control Display Instructions
Control display instructions described details follows:
5.2.4. Display ON/OFF control
5.2.1. Clear display
Code
Code
Display Display Cursor Cursor Blinks Blinks
clears entire display sets Display Data Address Address Counter.
5.2.2. Return home
Code
care
sets Display Data Address Address Counter display returns original position. displayed). change. cursor blink goes most-left side display line lines contents Display Data
5.2.3. Entry mode
shifts display.
Code
During writing reading data, defines cursor moving direction
Increment, Decrement.
character font line Cursor
character font
11th line
5.2.5. Cursor display shift
display.
Without changing data, moves cursor shifts
Code
Blink display alternately
display shift, display does shift.
Shift cursor left Shift cursor right Shift display left. Shift display right.
Description
Address Counter
Cursor follows display shift Cursor follows display shift
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5.2.6. Function
Code
Display data read written after this setting. one-line display (aaaaaaa)2: (00)16 (4F)16. two-line display (aaaaaaa)2: (00)16 (27)16 first line, (aaaaaaa)2: (40)16 (67)16 second line.
care sets interface data length. Data transferred with 8-bit length (DB7 Data transferred with 4-bit length (DB7 requires times accomplish data transferring. sets number display line. One-line display. Two-line display. sets character font. dots character font. dots character font.
Code
5.2.9. Read busy flag address
Display Lines
cannot display lines with dots character font.
5.2.7. character generator address
Code
sets Character Generator Address (aaaaaa)2 Address Counter.
Character Generator data read written after this setting.
5.2.8. display data address
Code
Character Font Duty Factor dots dots dots
When indicates system busy will accept instruction until busy same time, content Address Counter (aaaaaaa)2 read.
5.2.10. Write data character generator display data
Code
writes data (dddddddd)2 character generator display
data RAM.
5.2.11. Read data from character generator display data
Code
reads data (dddddddd)2 from character generator display data RAM.
sets Display Data Address (aaaaaaa)2 Address Counter. read data correctly, following: address Character Generator Display Data shift cursor instruction. Read instruction.
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5.3. Instruction Table
Instruction Code Instruction Description Execution time Fosc= 190KHz Write "20H" DDRAM Clear Display DDRAM address "00H" from DDRAM address "00H" Return Home return from cursor 2.16ms 1.52ms 1.18ms Fosc= 270KHz Fosc= 350KHz
original position shifted. contents DDRAM changed. Assign cursor
Entry Mode
Display Control
Cursor Display Shift
Function
CGRAM Address DDRAM Address
direction enable shift entire display display (D), cursor(C), blinking cursor(B) on/off control bit. cursor moving display shift control bit, direction, without changing data. DDRAM interface data length (DL: 8-bit/4-bit), numbers display line 2-line/1-line) and, display font type (F:5x10 dots/5x8 dots) CGRAM address address counter. address counter DDRAM address Whether during internal operation contents address counter read. also known reading Write data into internal (DDRAM/CGRAM). Read data from internal (DDRAM/CGRAM).
moving
2.16ms
1.52ms
1.18ms
Read Busy Flag Address Counter
Write Data Read Data from
Note: "-": don't care
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5.4. 8-Bit Operation 8-Digit 1-Line Display (Using Internal Reset)
Instruction Power (SPLC783A starts initializing) Function
Display Power reset. display.
Operation
8-bit operation select 1-line display line character font.
Display control
Display Cursor appear. Increase address one.
Entry mode
will shift cursor right when writing RAM/CG RAM. display shift. Write
Write data
cursor incremented shifted right. Write
Write data
Write data
Entry mode
Write data
Write data
Write data
Cursor display shift
Cursor display shift
Write data
Cursor display shift
cursor incremented shifted right.
WELCOME_
Write
cursor incremented shifted right. mode display shift when writing
WELCOME_
ELCOME
Write
"(space).
cursor incremented shifted right. Write
LCOME
cursor incremented shifted right.
COMPAMY_
Write
cursor incremented shifted right. Only shift cursor's position left (Y).
COMPAMY_
COMPAMY_
Only shift cursor's position left (M).
OMPANY_
Write
display moves left.
COMPAMY_
Shift display cursor's position right.
Cursor display shift
OMPANY_
Shift display cursor's position right.
Write data
COMPAMY_
Write
(space).
cursor incremented shifted right. Both display cursor return original position (address
Return home
WELCOME_
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5.5. 4-Bit Operation 8-Digit 1-Line Display (Using Internal Reset)
Power (SPLC783A starts initializing) Function
Instruction
Display Power reset. display. 4-bit operation.
Operation
4-bit operation select 1-line display line character font.
Display Cursor appears. Increase address one.
will shift cursor right when writing RAM. display shift. Write
5.6. 8-Bit Operation 8-Digit 2-Line Display (Using Internal Reset)
Power Function
(SPLC783A starts initializing)
Display control
Entry mode
Write data
Write data
cursor incremented shifted right.
Instruction
Display
Operation
Power reset. display.
8-bit operation select 2-line display line
character font. Display
Cursor appear.
Increase address one. RAM.
will shift cursor right when writing display shift. Write
cursor incremented shifted right.
WELCOME_
Write
cursor incremented shifted right.
WELCOME
address
sets RAM's address. cursor moved beginning position line. Write cursor incremented shifted right. Write cursor incremented shifted right.
Write data
WELCOME
Write data
WELCOME PART_
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SPLC783A
Entry mode
Instruction
Display
WELCOME PART_
Operation When writing, sets mode display shift.
Write data
ELCOME PARTY_
Write cursor incremented shifted right. Both display cursor return original position (address
Return home
WELCOME PARTY
5.7. RESET Function
follows:
power SPLC783A starts internal auto-reset circuit executes initial instructions. initial procedures shown
8-Bit Interface Power time after 4.5V
time 40ms After 2.7V
cannot checked before this instruction Function Interface bits length
time
cannot checked before this instruction Function Interface bits length
time
cannot checked before this instruction Function Interface bits length
checked after following instructions
Function Interface bits length Specify number display lines character font number display lines character font cannot changed afterwards Display Display clear
Initialization Ends
Entry mode
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4-Bit Interface Power
time after 4.5V
time 40ms After 2.7V
cannot checked before this instruction Function Interface bits length
time
cannot checked before this instruction Function Interface bits length
Function Interface bits length checked after following instructions Function Interface bits length Specify number display lines character font number display lines character font cannot changed afterwards Display Display clear Initialization Ends Entry mode
time
cannot checked before this instruction
Function interface bits length) Interface bits length
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5.8. Display Data RAM)
80-bit normally used storing display data. Those used display data used general data RAM. address configured Address Counter. relationships between Display Data Address LCDs position depicted follows.
1-line display display characters
Display position Display data address
Example 1-line display display characters
Display position Display data address
When display shift operation performed display data RAM's address moves Left shift Right shift
5.9. Timing Generation Circuit
internal circuits.
timing generating circuit able generate timing signals
interface, access timing access timing generated independently.
5.10. Driver Circuit
driver circuit.
Total commons segments signal drivers valid When program specifies character fonts line numbers, corresponding common signals output drive-waveforms others still output unselected waveforms.
order prevent internal timing dots character patterns. generator through program.
also
5.11. Character Generator ROM)
Using 8-bit character code, character generator generates dots dots character patterns. generate 192's dots character patterns 64's
5.12. Character Generator RAM)
Users easily change character patterns character written dots, 8-character patterns dots 4-character patterns.
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following diagram shows SPLC783A character patterns: Correspondence between Character Codes Character Patterns.
Higher 4-bit Character Code (Hexadecimal)
Lower 4-bit Character Code (Hexadecimal)
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relationships between Character Generator Addresses, Character Generator Data (character patterns), Character Codes depicted follows: character patterns
Character Code Data
Address
Character Patterns Data
Note1: Note2:
means that bit0~2 character code correspond bit3~5 address. These areas used display, used general data RAM.
Note3: When bit4-7 character code character patterns selected. Note4: Selected selected care display character. with cursor.
Note5: example (1), character code b7-b4 display That means character code (00) 16,and (08) Note6: bits character code character pattern line position. line cursor position display formed logical
Character Pattern Example
Cursor Position
Character Pattern Example
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character patterns
Character Code Data
Address
Character Patterns Data Character Pattern Example
Note1: Note2:
means that bit1~2 character code correspond bit4~5 address. These areas used display, used general data RAM.
Note3: When bit4-7 character code character patterns selected. Note4: Selected, selected, care (08) 16,and (09) display character. with cursor.
Note5: example (1), character code b7-b4 display That means character codes (00) (01) Note6: bits character code character pattern line position. 11th line cursor position display formed logical
Cursor Position
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5.13. Cursor/Blink Control Circuit
This circuit generates cursor blink cursor blink control circuit. cursor blink appears digit Display Data Address defined Address Counter. When Address Counter (07) cursor position shown belows:
1-line display digit
Display position
2-line display digit line line
Display position Hexadecimal cursor position
cursor position
Display data address Hexadecimal
Display data address
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5.14. Interfacing
There types data operations: 4-bit 8-bit operations. Using 4-bit MPU, interfacing 4-bit data transferred 4-busline (DB4 DB7). used. transferring. Thus, lines Using 4-bit interface 8-bit data requires times First, higher 4-bit data transferred 4-busline (for 8-bit operation, DB4). DB0). Secondly, lower 4-bit data transferred 4-busline (for 8-bit operation, 8-bit MPU, 8-bit data transferred 8-buslines (DB0 DB7).
Example 4-bit Data Transfer Timing Sequence
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5.15. Supply Voltage Drive
Different voltages supplied SPLC783A's pins obtaining drive-waveform. factor supply voltages shown belows:
Supply Voltage
Example 8-bit Data Transfer Timing Sequence
relationships between bias, duty
Duty Factor
1/8, 1/11
1/16
VLCD VLCD VLCD VLCD VLCD
VLCD VLCD VLCD VLCD VLCD
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5.15.1. power connections (1/4 Bias, Bias) shown belows:
+5.0V +5.0V
bypass-capacitor improves display quality.
Bias Bias (1/8,1/11 Duty) (1/16 Duty)
+5.0V
+5.0V
Bias (1/8,1/11 Duty) Bias (1/16 Duty)
bias voltage must have following relations:
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5.15.2. relationship between frames frequency oscillators frequency.
(Assume oscillation frequency 250KHz, clock cycle time 4.0s)
5.15.2.1. duty, TYPE-B waveform
clocks COM1 V2(V3) Frame Frame
5.15.2.2. 1/11 duty, TYPE-B waveform
5.15.2.3. 1/16 duty, TYPE-B waveform
clocks COM1 V2(V3) Frame Frame frame 4(s) 17600(s) 17.6ms Frame frequency 17.6(ms) .8(Hz)
frame 4(s) 12800(s) 12.8ms Frame frequency 78.1(Hz) 12.8(ms)
clocks
COM1
Frame frame 4(s) 12800(s) 12.8ms Frame frequency 78.1(Hz) 12.8(ms)
Frame
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5.16. REGISTER (Instruction Register) (Data Register)
SPLC783A contains 8-bit registers: Instruction Register (IR) Data Register (DR). Using combinations selects below:
5.19. Port Configuration 5.19.1. Input port:
PMOS
Operation write (Display clear, etc.) Read busy flag (DB7) Address Counter (DB0 DB6) write Display data Character generator RAM) read (Display data Character generator
NMOS
5.19.2. Input port:
written MPU, cannot read MPU.
5.17. Busy Flag (BF)
When busy flag output DB7. instruction until busy flag
busy flag SPLC783A busy state does accept
5.18. Address Counter (AC)
Character Generator RAM.
Address Counter assigns addresses Display Data
written address information sent from Generator RAM, automatically incremented decremented one). when
After writing to/reading from Display Data Character contents output
PMOS
PMOS
PMOS
NMOS
5.19.3. Output port: CLK1, CLK2,
When instruction address
NMOS
5.19.4. Input Output port:
Enable
PMOS
PMOS
NMOS
Data
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ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics Operating Voltage Driver Supply Voltage Input Voltage Range Operating Temperature Storage Temperature
conditions AC/DC Electrical Characteristics.
Symbol VLCD TSTO
Ratings -0.3V +7.0V 0.3V -0.3V 0.3V +125
Note: Stresses beyond those given Absolute Maximum Rating table cause operational errors damage device.
6.2. Characteristics (VDD 2.7V 4.5V,
Characteristics Operating Current Symbol Limit Min. Typ. Max.
Input High Voltage Input Voltage
Input High Voltage Input Voltage
Input High Current Input Current Output High Voltage (TTL) Output Voltage (TTL) Output High Output
Voltage (CMOS) Voltage (CMOS) (COM) (SEG) Voltage
Driver Resistance Driver Resistance
Note: FOSC 270KHz, 3.0V, "L", R/W, open, outputs loads.
VIH1 VIL1 0.7VDD -0.3 VIH2 VIL2 0.7VDD -0.2 0.2VDD OSC1 -1.0 -5.0 VOH1 VOL1 0.2VDD VOH2 VOL2 0.8VDD 0.2VDD RCOM RSEG VLCD
Unit
normal operational
Test Condition
External clock (Note) Pins:(E, R/W, DB7)
Pins: (RS, R/W, DB7) 3.0V 0.1mA 0.1mA 40A, 40A, Pins: ±50A, VLCD 4.0V
Pins: Pins:
Pins: CLK1, CLK2, CLK1, CLK2, Pins: COM1 COM16 Pins: SEG1 SEG80 VDD-V5, bias bias
±50A, VLCD 4.0V
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6.3. Characteristics (VDD 2.7V 4.5V, 6.3.1. Internal clock operation
Characteristics Frequency Symbol FOSC1 Limit Min. Typ. Max. Unit Test Condition 3.0V, 75K±2%
6.3.2. External clock operation
Characteristics External Frequency Duty Cycle Rise/Fall Time Symbol FOSC2 Limit Min. Typ. Max. Unit
6.3.3. Write mode (Writing data from SPLC783A)
Characteristics Cycle Time Pulse Width Symbol
Rise/Fall Time
Address Setup Time Address Hold Time Data Setup Time Data Hold Time
6.3.4. Read mode (Reading data from SPLC783A MPU)
Characteristics Cycle Time Pulse Width Symbol
Rise/Fall Time
Address Setup Time Address Hold Time
Data Output Delay Time Data hold time
Limit Typ. Min. Max. Unit 1400 tSP1 tHD1 tSP2 tHD2 Limit Typ. Min. Max. Unit 1400 tSP1 tHD1 tHD2
Test Condition
Test Condition
Pins: R/W, Pins: R/W,
Pins: Pins:
Test Condition
Pins: R/W, Pins: R/W,
Pins:
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6.4. Characteristics (VDD 4.5V 5.5V,
Characteristics Operating Current Input High Voltage Input Voltage Input High Voltage Input Voltage Input High Current Input Current Output High Voltage (TTL) Output Voltage (TTL) Output High Output Symbol VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 Limit Min. -0.3 VDD-1 -0.2 -1.0 Typ. Max. -100 Unit OSC1 OSC1 Pins: (RS, R/W, DB7) 5.0V Test Condition External clock (Note) Pins:(E, R/W, DB7)
Voltage (CMOS) Voltage (CMOS) (COM) (SEG) Voltage
Driver Resistance Driver Resistance
Note: FOSC 270KHz, 5.0V, "L", R/W, open, outputs loads.
6.5. Characteristics (VDD 4.5V 5.5V, 6.5.1. Internal clock operation
Characteristics Frequency
6.5.2. External clock operation
Characteristics External Frequency Duty Cycle Rise/Fall Time
VOH2 VOL2 0.9VDD -40A, 0.1VDD RCOM RSEG VLCD Symbol FOSC1 Limit Typ. Min. Max. Unit Symbol FOSC2 Limit Typ. Min. Max. Unit
-0.205mA
Pins: 1.2mA Pins:
Pins: CLK1, CLK2, 40A, Pins: CLK1, CLK2,
±50A, VLCD 4.0V Pins: COM1 COM16 Pins: SEG1 SEG80
±50A, VLCD 4.0V
VDD-V5, bias bias
Test Condition
5.0V, 91K±2%
Test Condition
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6.5.3. Write mode (Writing Data from SPLC783A)
Characteristics Cycle Time Pulse Width Rise/Fall Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Symbol tSP1 tHD1 tSP2 tHD2 Limit Min. Typ. Max. Unit Pins: R/W, Pins: R/W, Pins: Pins: Test Condition
6.5.4. Read mode (Reading Data from SPLC783A MPU)
Characteristics Cycle Time Pulse Width Symbol Limit Min. Typ. Max.
Rise/Fall Time
Address Setup Time Address Hold Time
Data Output Delay Time Data hold time
6.5.5. Interface mode with Driver (SPLC100A1)
Characteristics Symbol tPWH tPWL tCSP
Clock pulse width high Clock pulse width Clock setup time Data setup time Data hold time delay time
tSP1 tHD1 tHD2 Limit Typ. Min. Max. Unit tDSP Pins: Pins: -1000 1000 Pins:
Unit
Test Condition
Pins: R/W, Pins: R/W,
Pins:
Test Condition
Pins: CLK1, CLK2 Pins: CLK1, CLK2 Pins: CLK1, CLK2
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6.5.6. Write mode timing diagram (Writing Data from SPLC783A)
Valid Data
6.5.7. Read mode timing diagram (Reading Data from SPLC783A MPU)
6.5.8. Interface mode with SPLC100A1 timing diagram
0.9VDD
Valid Data
tPWH
0.9VDD
tPWH
0.1VDD 0.1VDD
0.9VDD
tPWL
0.9VDD 0.1VDD 0.9VDD 0.1VDD
0.1VDD
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APPLICATION CIRCUITS
7.1. R-Oscillator
oscillation resistor used only internal oscillaotr operation mode.
OSC1 when 3.0V) when 5.0V) Since oscillation frequency varies depending OSC1 OSC2 capacitance, wiring length these pins should minimized.
OSC2
Fosc
Fosc
7.2. Interface
7.2.1. Interface 8-bit (6805)
7.2.2. Interface 8-bit (Z80)
Rosc Kohms Rosc Kohms
3.0V
5.0V
COM1 COM16
PANEL
6805
SPLC783A
COMMONS
SEG1 SEG80
SEGMENTS
PANEL
SPLC783A
ENTS
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7.3. SPLC783A Application Circuit
MATRIX PANEL
COM16 (COM8) COM1
SEG80 SEG1
Y1-Y40 SHL1 SHL2
SPLC100A1
CLK1 CLK2 SHL1 SHL2
Y1-Y40
SPLC100A1
CLK1 CLK2 SHL1 SHL2
Y1-Y40
SPLC100A1
CLK1 CLK2
SPLC783A
+5.0V
7.4. Applications
SPLC783A COM1
Example dots characters line Bias Duty
CLK1 CLK2
Panel
COM8 SEG1
characters line
SEG80
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SPLC783A COM1 Panel characters line COM11 SEG1
SEG80 Example dots characters line Bias Duty
SPLC783A COM1
COM8 COM9
COM16 SEG1
SEG80
SPLC783A COM1
COM8 SEG1
SEG80 COM9
Example dots characters lines Bias Duty
Panel
characters lines
COM16 Example dots characters line Bias Duty
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SPLC783A
SEG1 SEG40 COM1 Panel COM8
SEG41 SEG80
Example dots characters lines Bias Duty
characters lines
Sunplus Technology Co., Ltd. Proprietary Confidential
MAR. 2005 Version:
SPLC783A
CHARACTER GENERATOR
8.1. SPLC783A
Sunplus Technology Co., Ltd. Proprietary Confidential
MAR. 2005 Version:
SPLC783A
8.2. SPLC783A
Sunplus Technology Co., Ltd. Proprietary Confidential
MAR. 2005 Version:
SPLC783A
PACKAGE/PAD LOCATIONS
9.1. Assignment Locations
Please contact Sunplus sales representatives more information.
9.2. Package Information
Symbol
Unit: Millimeter
Min.
Nom.
Max.
1.60 0.15 1.45 22.10 20.10 16.10 14.10 0.27 0.20
0.05 1.35
1.40
21.90 15.90 13.90 0.17 0.09
22.00 16.00 14.00 0.22
19.90
20.00
0.50 BSC.
1.00
9.3. Ordering Information
Product Number SPLC783A-NnnV-C SPLC783A-NnnV-PL11 SPLC783A-NnnV-HL11
Note1: Code number assigned customer. Note2: Code number 99); version
Package Type Chip form Package form LQFP 128* Green Package form LQFP 128**
Sunplus Technology Co., Ltd. Proprietary Confidential
MAR. 2005 Version:
SPLC783A
9.4. Storage Condition Period Package
Package *LQFP **LQFP Moisture sensitivity level LEVEL LEVEL Max. Reflow temperature +5/-0 +5/-0 Floor life storage condition 168Hrs R.H. 168Hrs R.H. pack
Note1: Please refer IPC/JEDEC standard J-STD-020A JEDEC stand JFSD22-A112 Note2: refer "CAUTION Note" pack bag.
9.5. Recommended Temperature Profile
This "Recommended" temperature profile rough guideline process reference. Most SUNPLUS leadframe base product choice Matte Sn/Bi plating recipe. PPF(Pre-Plated Frame) product with 63/37 solder paste, recommend 240~245 peak temperature.
Sunplus Technology Co., Ltd. Proprietary Confidential
MAR. 2005 Version:
SPLC783A
DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication FURTHER, SUNPLUS MAKES WARRANTY SUNPLUS reserves right halt production alter specifications regarding freedom described chip(s) from patent infringement. MERCHANTABILITY FITNESS PURPOSE. prices time without notice. publication current before placing orders.
Accordingly, reader cautioned verify that data sheets other information this Products described herein intended normal commercial applications. Please note that application circuits
Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. illustrated this document reference purposes only.
Sunplus Technology Co., Ltd. Proprietary Confidential
MAR. 2005 Version:
SPLC783A
REVISION HISTORY
Date MAR. 2005 Revision Description Modify code numbers from digits digits Green Package Product Number sections Correct name: from Page APR. 2004 min. max. value Instruction Table 8-bit/4-bit data transfer timing sequence example NOV. 2003 package information: LQFP Remove PACKAGE/PAD LOCATIONS" SEP. 2002 OCT. 2001 Correct PACKAGE/PAD LOCATIONS" Original
Sunplus Technology Co., Ltd. Proprietary Confidential
MAR. 2005 Version:

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