November 1997 Revised 2000 High Speed CMOS Logic Quad Buffer, Thr

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November 1997 Revised 2000 High Speed CMOS Logic Quad Buffer, Thr

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CD54/74HC125, CD54/74HCT125
November 1997 Revised 2000
High Speed CMOS Logic Quad Buffer, Three-State
Description
'HC125 'HCT125 contain independent three-state buffers, each having output enable input, which when "HIGH" puts output high impedance state.
Features
Three-State Outputs Separate Output Enable Inputs Fanout (Over Temperature Range) Standard Outputs LSTTL Loads Driver Outputs LSTTL Loads Wide Operating Temperature Range -55oC 125oC Balanced Propagation Delay Transition Times Significant Power Reduction Compared LSTTL Logic Types Operation High Noise Immunity: 30%, Types 4.5V 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), (Min) CMOS Input Compatibility, VOL,
/Title (CD74 HC125 CD74 HCT12 /Subject (High Speed CMOS Logic Quad Buffer, ThreeState)
Ordering Information
PART NUMBER CD54HC125F CD54HC125F3A CD74HC125E CD74HC125M CD54HCT125F3A CD74HCT125E CD74HCT125M NOTES: When ordering, entire part number. suffix obtain variant tape reel. Wafer this part number available which meets electrical specifications. Please contact your local sales office customer service ordering information. TEMP. RANGE (oC) PACKAGE CERDIP CERDIP PDIP SOIC CERDIP PDIP SOIC
Pinout
CD54HC125, CD54HCT125 (CERDIP) CD74HC125, CD74HCT125 (PDIP, SOIC) VIEW
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
2000, Texas Instruments Incorporated
CD54/74HC125, CD54/74HCT125 Functional Diagram
TRUTH TABLE INPUTS NOTE: High Voltage Level Voltage Level Don't Care High Impedance, State OUTPUTS
Logic Diagram
CD54/74HC125, CD54/74HCT125
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±20mA Drain Current, Output, -0.5V 0.5V. ±35mA Output Source Sink Current Output Pin, -0.5V 0.5V .±25mA Ground Current, .±70mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) PDIP Package SOIC Package Maximum Junction Temperature 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range (TA) -55oC 125oC Supply Voltage Range, Types Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Time 1000ns (Max) 4.5V. 500ns (Max) 400ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads -0.02 -0.02 -0.02 High Level Output Voltage Loads Level Output Voltage CMOS Loads -7.8 0.02 0.02 0.02 Level Output Voltage Loads Input Leakage Current 3.15 3.98 5.48 1.35 0.26 0.26 ±0.1 3.15 3.84 5.34 1.35 0.33 0.33 3.15 1.35 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD54/74HC125, CD54/74HCT125
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Quiescent Device Current Three-State Leakage Current TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Input Pin: Unit Load (Note Three-State Leakage Current NOTE: dual-supply systems theoretical worst case 2.4V, 5.5V) specification 1.8mA. -2.1 -0.02 SYMBOL (mA) 25oC ±0.5 -40oC 85oC -55oC 125oC UNITS
3.98
3.84
0.02
0.26
0.33
±0.1
±0.5
Input Loading Table
INPUT UNIT LOADS
NOTE: Unit Load limit specified Electrical Specifications table, e.g., 360µA 25oC.
CD54/74HC125, CD54/74HCT125
Switching Specifications
Input TEST CONDITIONS 25oC -40oC 85oC -55oC 125oC UNITS
PARAMETER TYPES Propagation Delay Time
SYMBOL
tPLH, tPHL
50pF
15pF 50pF Enable Delay Time tPZL, tPZH 50pF
15pF 50pF Disable Delay Time tPLZ, tPHZ 50pF 50pF 15pF 50pF Output Transition Time tTLH, tTHL 50pF
Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes TYPES Propagation Delay Time Output Enable Time
tPLH, tPHL
50pF 15pF
tPZL, tPZH
50pF 15pF
Output Disabling Time
tPLZ, tPHZ
50pF 15pF
Output Transition Times Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes NOTES:
tTLH, tTHL
50pF
used determine dynamic power consumption, channel. VCC2 (CPD where Input Frequency, Output Frequency, Output Load Capacitance, Supply Voltage.
CD54/74HC125, CD54/74HCT125 Test Circuits Waveforms
INPUT tTLH tPHL tPLH INPUT tTHL 2.7V 1.3V 0.3V tTLH INVERTING OUTPUT tPHL tPLH 1.3V
tTHL
INVERTING OUTPUT
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
OUTPUT DISABLE tPZL tPHZ OUTPUT HIGH OUTPUTS ENABLED OUTPUTS DISABLED OUTPUTS ENABLED tPZH
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
OUTPUT DISABLE tPLZ OUTPUT tPHZ OUTPUT HIGH OUTPUTS ENABLED tPZL
tPLZ OUTPUT
tPZH
1.3V
1.3V OUTPUTS DISABLED OUTPUTS ENABLED
FIGURE THREE-STATE PROPAGATION DELAY WAVEFORM
FIGURE THREE-STATE PROPAGATION DELAY WAVEFORM
OTHER INPUTS TIED HIGH OUTPUT DISABLE
WITH THREESTATE OUTPUT
OUTPUT 50pF
tPLZ tPZL tPHZ tPZH
NOTE: Open drain waveforms tPLZ tPZL same those three-state shown left. test circuit Output VCC, 50pF. FIGURE THREE-STATE PROPAGATION DELAY TEST CIRCUIT
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Customers responsible their applications using components. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 2000, Texas Instruments Incorporated

November 1997 Revised 2000 High Speed CMOS Logic Quad Buffer, Thr

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