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CD54 / 74HC125, CD54 / 74HCT125

November 1997 - Revised May 2000

CD54 / 74HC125, CD54 / 74HCT125
Data sheet acquired from Harris Semiconductor SCHS143A
November 1997 - Revised May 2000
High Speed CMOS Logic Quad Buffer, Three-State
Description
Features
/ Title (CD74 HC125 , CD74 HCT12 5) / Subject (High Speed CMOS Logic Quad Buffer, ThreeState)
Ordering Information
PART NUMBER CD54HC125F CD54HC125F3A CD74HC125E CD74HC125M CD54HCT125F3A CD74HCT125E CD74HCT125M NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC
Pinout
CD54HC125, CD54HCT125 (CERDIP) CD74HC125, CD74HCT125 (PDIP, SOIC) TOP VIEW
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
CD54 / 74HC125, CD54 / 74HCT125 Functional Diagram
Logic Diagram
CD54 / 74HC125, CD54 / 74HCT125
Absolute Maximum Ratings
Thermal Information
Thermal Resistance (Typical, Note 3) JA (oC / W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
CD54 / 74HC125, CD54 / 74HCT125
DC Electrical Specifications
5.5 5.5 4.5 to 5.5
VIL or VIH
HCT Input Loading Table
INPUT nA, nOE UNIT LOADS 1
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC.
CD54 / 74HC125, CD54 / 74HCT125
Switching Specifications
PARAMETER HC TYPES Propagation Delay Time nA to nY
SYMBOL
tPLH, tPHL
Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes 5, 6) HCT TYPES Propagation Delay Time nA to nY Output Enable Time
CI CO CPD
tPLH, tPHL
tPZL, tPZH
Output Disabling Time
tPLZ, tPHZ
Output Transition Times Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes 5, 6) NOTES:
tTLH, tTHL CI CO CPD
CD54 / 74HC125, CD54 / 74HCT125 Test Circuits and Waveforms
INVERTING OUTPUT
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
tPLZ OUTPUT LOW TO OFF
1.3V OUTPUTS DISABLED OUTPUTS ENABLED
FIGURE 3. HC THREE-STATE PROPAGATION DELAY WAVEFORM
FIGURE 4. HCT THREE-STATE PROPAGATION DELAY WAVEFORM
OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE
IC WITH THREESTATE OUTPUT
VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH