Individual Product Specifications ADE-602-188A Rev. 8/24/00 Hitac
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Individual Product Specifications
ADE-602-188A Rev. 8/24/00 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Main Revisions Additions this Edition
Page Item Whole sections Revisions (See Manual Details) Amendment addition H8S/2319 F-ZTAT, H8S/2315 F-ZTAT, H8S/2316, H8S/2313 product lineup. Table Overview product lineup added. Figure Block Diagram Note amended addition WDTOVF (FWE, EMLE). Figure Arrangement Note amended addition WDTOVF (FWE, EMLE). Figure Arrangement Note amended addition WDTOVF (FWE, EMLE). Functions Each Operating Mode Table Functions Each Operating Mode Functions pins (TFP-100B) flash memory programmer mode amended. Function (TFP-100B) amended Note amended. Functions Table Functions EMLE added. Note added. Product Lineup Memory Each Operating Mode Note added. Figure H8S/2319 F-ZTAT Memory Each Operating Mode added. Figures 2.2, 2.3, Memory Each Operating Mode Note reserved area added. Figure H8S/2316 Memory Each Operating Mode added. Figure H8S/2315 F-ZTAT Memory Each Operating Mode added. Figure H8S/2313 Memory Each Operating Mode added. H8S/2318 Series Operating Modes (F-ZTAT Version) Deleted (see hardware manual).
Overview Block Diagram
Arrangement
Page
Item 3.3.3 Interrupt Exception Vector Table
Revisions (See Manual Details) Table Interrupt Sources, Vector Addresses, Interrupt Priorities Names interrupts RXI0 RXI1 amended. Table Interrupt Response Times Number wait states until execution instruction ends amended. Description H8S/2319, H8S/2316, H8S/2315, H8S/2313 added Table 5.23 Port States Each Processing State LWROD DAOEn added Legend. Figure 5.35(a) Port Block Diagram (Pin PG0) Amended. Amended addition H8S/2319 FZTAT product lineup. Table Conversion Characteristics Nonlinearity error, offset error, full-scale error, quantization error, absolute accuracy amended. Added.
Interrupt Response Times
4.2.5 Control Register (BCRL) 5.13 States
5.14.11 Port 6.11 7.1.4 Conversion Characteristics
Electrical Characteristics Mask Version (H8S/2318, H8S/2317) Low-Voltage Operation Electrical Characteristics F-ZTAT Version (H8S/2318) 7.3.2 Characteristics
Table 7.19 Absolute Maximum Ratings Conditions added. Note amended. Tables 7.20 Characteristics Maximum value input leakage current, typical maximum values current dissipation, typical maximum values analog power supply voltage, typical maximum values reference power supply voltage, equation note amended. Table 7.25 Timing On-Chip Supporting Modules overflow output delay time deleted. Table 7.26 Conversion Characteristics Nonlinearity error, offset error, full-scale error, quantization error, absolute accuracy amended.
7.3.3 Characteristics
7.3.4 Conversion Characteristics
Page
Item 7.3.6 Flash Memory Characteristics Electrical Characteristics F-ZTAT Version (H8S/2315)
Revisions (See Manual Details) Tables 7.28 Flash Memory Characteristics Completely replaced. Added. 7.3.1 Notes when Converting F-ZTAT Application Software Mask-ROM Versions Edition) Deleted (see hardware manual).
List Registers (Address Order)
H'FFC8: FLMCR1 H'FFC9: FLMCR2 H'FFCB: EBR2 Amended. H'FED5: BCRL Description amended. H'FF37: DTVECR Description amended. H'FFC8: FLMCR1 Amended. H'FFC9: FLMCR2 Amended. H'FFCB: EBR2 Amended.
402, 404,
Functions
Organization H8S/2319, H8S/2318 Series following manuals available H8S/2319, H8S/2318 Series. Table
Title H8S/2600 Series, H8S/2000 Series Programming Manual H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series Hardware Manual H8S/2319, H8S/2318 Series, H8S/2319 F-ZTATTM, H8S/2318 F-ZTATTM, H8S/2315 F-ZTAT
Manuals
Document Code ADE-602-083A ADE-602-171A preparation) ADE-602-188A
H8S/2600 Series, H8S/2000 Series Programming Manual gives detailed description architecture instruction H8S/2000 CPU. H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series Hardware Manual describes operation on-chip functions, gives detailed description related registers. H8S/2319, H8S/2318 Series, H8S/2319 F-ZTATTM, H8S/2318 F-ZTATTM, H8S/2315 F-ZTATReference Manual mainly covers information specific H8S/2319, H8S/2318 Series H8S/2318 F-ZTATproducts, including arrangement, ports, operating modes (address maps), interrupt vectors, control, electrical characteristics, also includes brief description registers convenience user. contents H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series Hardware Manual H8S/2319, H8S/2318 Series, H8S/2319 F-ZTATTM, H8S/2318 F-ZTATTM, H8S/2315 F-ZTATReference Manual summarized table
Table
Item
Contents Hardware Manual Hardware Manual Reference Manual (including arrangement)
Overview
operating modes (including address maps) Exception handling Interrupt controller controller controller (DMAC) Data transfer controller (DTC) 16-bit timer pulse unit (TPU) Programmable pulse generator (PPG) 8-bit timers Watchdog timer Serial communication interface (SCI) Smart card interface converter converter (flash memory) Clock pulse generator Power-down modes ports (including port block diagrams) Electrical characteristics Register reference chart address order, with function summary) Instruction Package dimension diagrams
Included Included (with detailed register descriptions) included
following chart shows where find various kinds information different purposes.
product evaluation information, comparative specification information current users Hitachi products product specifications Overview arrangement diagram Block diagrams function modules functions Electrical characteristics Overview Arrangement Section Peripheral Block Diagrams Functions Section Electrical Characteristics
detailed information functions
details operation modules port information Interrupts exception handling Information other modules Section Ports Section Exception Handling Interrupt Controller H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series Hardware Manual Functions
functions
information operating modes List Detailed descriptions Functions Each Operating Mode Section Operating Modes
design material
information registers List find register from address find register information function Setting procedure notes Section registers List Registers (Address Order) List Registers Module) H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series Hardware Manual
information instructions List Operation description notes Program examples H8S/2600 Series, H8S/2000 Series Programming Manual
H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series have on-chip modules shown below Table H8S/2339, H8S/2338, H8S/2329, H8S/2328, H8S/2319, H8S/2318 Series On-Chip Modules
H8S/2339 Series, H8S/2338 Series H8S/2329 Series, H8S/2328 Series H8S/2319 Series, H8S/2318 Series
On-Chip Module controller (BUSC) DRAM controller controller (DMAC) Data transfer controller (DTC) 16-bit timer pulse unit (TPU) Programable pulse generator (PPG) 8-bit timer Watchdog timer Serial communication interface (SCI) converter converter Interrupt controller (INTC) Memory*
channels)
channels)
channels)
channels)
channels)
channels)
channels)
channels)
channels)
channels) channels)
channels) channels)
channels) channels)
Product Code H8S/2339 H8S/2338 H8S/2337 H8S/2332
(kbytes) (kbytes)
Product Code H8S/2329 H8S/2328 H8s/2327 H8S/2324 H8S/2323 H8S/2322R H8S/2320
(kbytes) (kbytes)
Product Code H8S/2319 H8S/2318 H8S/2317 H8S/2316 H8S/2315 H8S/2313 H8S/2312 H8S/2311 H8S/2310
(kbytes) (kbytes)
On-chip on-chip
Note: reference manual each series details.
Contents
Section
Overview Overview Block Diagram Arrangement Functions Each Operating Mode Functions. Product Lineup Package Dimensions Operating Modes Overview 2.1.1 Operating Mode Selection (H8S/2318 F-ZTAT H8S/2315 F-ZTAT Versions). 2.1.2 Operating Mode Selection (Mask ROM, ROMless, H8S/2319 F-ZTAT Versions). 2.1.3 Register Configuration Register Descriptions 2.2.1 Mode Control Register (MDCR) 2.2.2 System Control Register (SYSCR). 2.2.3 System Control Register (SYSCR2) (F-ZTAT Version Only) Operating Mode Descriptions 2.3.1 Modes 2.3.2 Mode (Expanded Mode with On-Chip Disabled) 2.3.3 Mode (Expanded Mode with On-Chip Disabled) 2.3.4 Mode (Expanded Mode with On-Chip Enabled). 2.3.5 Mode (Single-Chip Mode). 2.3.6 Modes (H8S/2318 F-ZTAT H8S/2315 F-ZTAT Versions Only) 2.3.7 Mode (H8S/2318 F-ZTAT H8S/2315 F-ZTAT Versions Only). 2.3.8 Mode (H8S/2318 F-ZTAT H8S/2315 F-ZTAT Versions Only). 2.3.9 Modes (H8S/2318 F-ZTAT H8S/2315 F-ZTAT Versions Only). 2.3.10 Mode (H8S/2318 F-ZTAT H8S/2315 F-ZTAT Versions Only). 2.3.11 Mode (H8S/2318 F-ZTAT H8S/2315 F-ZTAT Versions Only). Functions Each Operating Mode Memory Each Operating Mode
Section
Section
Exception Handling Interrupt Controller
Overview 3.1.1 Exception Handling Types Priority. Interrupt Controller
3.2.1 Interrupt Controller Features. 3.2.2 Configuration Interrupt Sources 3.3.1 External Interrupts. 3.3.2 Internal Interrupts. 3.3.3 Interrupt Exception Vector Table Interrupt Control Modes Interrupt Operation Interrupt Response Times. Activation Interrupt 3.6.1 Overview. 3.6.2 Block Diagram 3.6.3 Operation.
Section
Controller Overview 4.1.1 Features 4.1.2 Block Diagram 4.1.3 Configuration 4.1.4 Register Configuration Register Descriptions 4.2.1 Width Control Register (ABWCR) 4.2.2 Access State Control Register (ASTCR) 4.2.3 Wait Control Registers (WCRH, WCRL) 4.2.4 Control Register (BCRH) 4.2.5 Control Register (BCRL) Overview Control 4.3.1 Area Partitioning. 4.3.2 Specifications. 4.3.3 Memory Interfaces 4.3.4 Advanced Mode 4.3.5 Chip Select Signals Basic Interface. 4.4.1 Overview. 4.4.2 Wait Control. Burst Interface 4.5.1 Overview. 4.5.2 Basic Timing. 4.5.3 Wait Control. Idle Cycle 4.6.1 Operation. 4.6.2 States Idle Cycle Release 4.7.1 Overview.
4.7.2 Operation. 4.7.3 States External-Bus-Released State. 4.7.4 Transition Timing 4.7.5 Usage Note Arbitration. 4.8.1 Overview. 4.8.2 Operation. 4.8.3 Transfer Timing 4.8.4 Note External Release Controller Operation Reset
Section
Ports Overview Port 5.2.1 Overview. 5.2.2 Register Configuration 5.2.3 Functions. Port 5.3.1 Overview. 5.3.2 Register Configuration 5.3.3 Functions. Port 5.4.1 Overview. 5.4.2 Register Configuration 5.4.3 Functions. Port 5.5.1 Overview. 5.5.2 Register Configuration 5.5.3 Functions. Port 5.6.1 Overview. 5.6.2 Register Configuration 5.6.3 Functions. 5.6.4 Input Pull-Up Function. Port 5.7.1 Overview. 5.7.2 Register Configuration 5.7.3 Functions. 5.7.4 Input Pull-Up Function. Port 5.8.1 Overview. 5.8.2 Register Configuration 5.8.3 Functions.
5.10
5.11
5.12
5.13 5.14
5.8.4 Input Pull-Up Function. Port 5.9.1 Overview. 5.9.2 Register Configuration 5.9.3 Functions. 5.9.4 Input Pull-Up Function. Port 5.10.1 Overview. 5.10.2 Register Configuration 5.10.3 Functions. 5.10.4 Input Pull-Up Function. Port 5.11.1 Overview. 5.11.2 Register Configuration 5.11.3 Functions. Port 5.12.1 Overview. 5.12.2 Register Configuration 5.12.3 Functions. States 5.13.1 Port States Each Mode Port Block Diagrams. 5.14.1 Port 5.14.2 Port 5.14.3 Port 5.14.4 Port 5.14.5 Port 5.14.6 Port 5.14.7 Port 5.14.8 Port 5.14.9 Port 5.14.10 Port 5.14.11 Port
Section
Supporting Module Block Diagrams.
Interrupt Controller 6.1.1 Features 6.1.2 Block Diagram 6.1.3 Pins. Data Transfer Controller 6.2.1 Features 6.2.2 Block Diagram 16-Bit Timer Pulse Unit
6.10
6.11
6.12
6.13
6.3.1 Features 6.3.2 Block Diagram 6.3.3 Pins. 8-Bit Timer. 6.4.1 Features 6.4.2 Block Diagram 6.4.3 Pins. Watchdog Timer. 6.5.1 Features 6.5.2 Block Diagram 6.5.3 Pins. Serial Communication Interface. 6.6.1 Features 6.6.2 Block Diagram 6.6.3 Pins. Smart Card Interface 6.7.1 Features 6.7.2 Block Diagram 6.7.3 Pins. Converter Analog Input Channel Version) 6.8.1 Features 6.8.2 Block Diagram 6.8.3 Pins. Converter 6.9.1 Features 6.9.2 Block Diagram 6.9.3 Pins. RAM. 6.10.1 Features 6.10.2 Block Diagram (H8S/2319). 6.11.1 Features 6.11.2 Block Diagrams. ROM. 6.12.1 Features 6.12.2 Block Diagrams. Clock Pulse Generator 6.13.1 Features 6.13.2 Block Diagram
Section
Electrical Characteristics. Electrical Characteristics Mask Version (H8S/2318, H8S/2317, H8S/2316, H8S/2313, H8S/2311) ROMless Version (H8S/2312, H8S/2310)
7.1.1 Absolute Maximum Ratings 7.1.2 Characteristics 7.1.3 Characteristics 7.1.4 Conversion Characteristics 7.1.5 Conversion Characteristics Electrical Characteristics Mask Version (H8S/2318, H8S/2317) Low-Voltage Operation 7.2.1 Absolute Maximum Ratings 7.2.2 Characteristics 7.2.3 Characteristics 7.2.4 Conversion Characteristics 7.2.5 Conversion Characteristics Electrical Characteristics F-ZTAT Version (H8S/2318) 7.3.1 Absolute Maximum Ratings 7.3.2 Characteristics 7.3.3 Characteristics 7.3.4 Conversion Characteristics 7.3.5 Conversion Characteristics 7.3.6 Flash Memory Characteristics Electrical Characteristics F-ZTAT Version (H8S/2315) (Under Development). 7.4.1 Absolute Maximum Ratings 7.4.2 Characteristics 7.4.3 Characteristics 7.4.4 Conversion Characteristics 7.4.5 Conversion Characteristics 7.4.6 Flash Memory Characteristics Usage Note
Section
Registers. List Registers (Address Order) List Registers Module) Functions
Section Overview
Overview
H8S/2319 H8S/2318 Series series microcomputers (MCUs: microcomputer units), built around H8S/2000 CPU, employing Hitachi's proprietary architecture, equipped with peripheral functions on-chip. H8S/2000 internal 32-bit architecture, provided with sixteen 16-bit general registers concise, optimized instruction designed high-speed operation, address 16-Mbyte linear address space. instruction upward-compatible with H8/300 H8/300H instructions object-code level, facilitating migration from H8/300, H8/300L, H8/300H Series. On-chip peripheral functions required system configuration include data transfer controller (DTC) master, memory, 16-bit timer pulse unit (TPU), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), converter, converter, ports. Single-power-supply flash memory (F-ZTATTM*) mask versions available, providing quick flexible response conditions from ramp-up through full-scale volume production, even applications with frequently changing specifications. connected 16-bit data bus, enabling both byte word data accessed state. Instruction fetching thus speeded processing speed increased. features H8S/2319 H8S/2318 Series shown table 1.1. Note: F-ZTAT trademark Hitachi, Ltd.
Table
Item
Overview
Specification General-register machine Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) High-speed operation suitable realtime control Maximum clock rate: High-speed arithmetic operations 8/16/32-bit register-register add/subtract: operation) 16-bit register-register multiply: operation) 16-bit register-register divide: operation) Instruction suitable high-speed operation Sixty-five basic instructions 8/16/32-bit data transfer, arithmetic, logic instructions Unsigned/signed multiply divide instructions Powerful bit-manipulation instructions operating mode Advanced mode: 16-Mbyte address space Address space divided into areas, with specifications settable independently each area Chip select output possible each area Choice 8-bit 16-bit access space each area 2-state 3-state access space designated each area Number program wait states each area Burst directly connectable External release function activated internal interrupt software Multiple transfers multiple types transfer possible activation source Transfer possible repeat mode, block transfer mode, etc. Request sent interrupt that activated
controller Data transfer controller (DTC)
Item 16-bit timer pulse unit (TPU) 8-bit timer, channels Watchdog timer Serial communication interface (SCI), channels converter
Specification 6-channel 16-bit timer on-chip Pulse processing capability pins Automatic 2-phase encoder count capability 8-bit up-counter (external event count capability) time constant registers Two-channel connection possible Watchdog timer interval timer selectable Asynchronous mode synchronous mode selectable Multiprocessor communication function Smart card interface function Resolution: bits Input: channels minimum conversion time operation) Single scan mode selectable Sample-and-hold function conversion activated external trigger timer trigger Resolution: bits Output: channels input/output pins, input-only pins Flash memory mask High-speed static kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes
converter ports Memory
Product Name H8S/2319* H8S/2318 H8S/2317 H8S/2316 H8S/2315* H8S/2313 H8S/2312 H8S/2311 H8S/2310 Note: Under development Interrupt controller
Nine external interrupt pins (NMI, IRQ0 IRQ7) internal interrupt sources Eight priority levels settable
Item Power-down state
Specification Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Variable clock division ratio Eight operating modes (H8S/2318 F-ZTAT, H8S/2315 F-ZTAT) External Data On-Chip Initial Value Maximum Value
Operating modes
Operating Mode Mode Description Advanced User program mode Advanced Boot mode Advanced Expanded mode with on-chip disabled Expanded mode with on-chip enabled Single-chip mode
Disabled bits bits Enabled bits
bits bits bits
Enabled
bits
bits
Enabled
bits
bits
Item Operating modes
Specification Four operating modes (mask version ROMless version H8S/2319 F-ZTAT) Operating Mode External Data Description On-Chip Initial Value Maximum Value
Mode Clock pulse generator Package Product lineup
Advanced
Expanded mode with onchip disabled Expanded mode with onchip disabled Expanded mode with onchip enabled Single-chip mode
Disabled Disabled Enabled Enabled
bits bits bits
bits bits bits
Note: Only modes provided ROMless version. Built-in duty correction circuit 100-pin plastic TQFP (TFP-100B) 100-pin plastic (FP-100A) Condition Operating power supply voltage Operating frequency Model HD64F2319 HD64F2318 HD6432318 HD6432317 HD6432316 HD64F2315 HD6432313 HD6412312 HD6432311 HD6412310 Products current lineup Notes: -40°C 85°C (wide-range specifications) available condition Under development planning stage
Condition
Condition
Block Diagram
PD7/ PD6/ PD5/ PD4/ PD3/ PD2/ PD1/ PD0/ PE7/ PE6/ PE5/ PE4/ PE3/ PE2/ PE1/ PE0/ Port
Port
H8S/2000
Internal address
Internal data
controller
EXTAL XTAL STBY WDTOVF (FWE, EMLE)*1
Clock pulse generator
Port
PA3/A19 PA2/A18 PA1/A17 PA0/A16
Interrupt controller PF7/ PF6/ PF5/ PF4/ PF3/ LWR/ IRQ3 PF2/ WAIT/IRQ2/ DREQO PF1/ BACK/ IRQ1/CS5 PF0/ BREQ/IRQ0/ PG4/ PG3/ CS1/CS7 PG2/ PG1/ CS3/IRQ7/CS6 PG0/ ADTRG/ IRQ6 ROM*2
Port
Peripheral address
Port
Peripheral data
PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/ PB2/A10 PB1/A9 PB0/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 P35/SCK1/IRQ5 P34/SCK0/IRQ4 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0
Port
Port
8-bit timer
Port
converter
converter
Port
Port Vref AVCC AVSS
Port P47/AN7/DA1 P46/AN6/DA0 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0
P10/TIOCA0/A20 P11/TIOCB0/A21 P12/TIOCC0/TCLKA/A22 P13/TIOCD0/TCLKB/A23 P14/TIOCA1 P15/TIOCB1/TCLKC P16/TIOCA2 P17/TIOCB2/TCLKD
Notes: function only available H8S/2318 F-ZTAT H8S/2315 F-ZTAT versions. EMLE function only available H8S/2319 F-ZTAT version. WDTOVF function available F-ZTAT versions. supported ROMless version.
Figure Block Diagram
P20/TIOCA3 P21/TIOCB3 P22/TIOCC3/TMRI0 P23/TIOCD3/TMCI0 P24/TIOCA4/TMRI1 P25/TIOCB4/TMCI1 P26/TIOCA5/TMO0 P27/TIOCB5/TMO1
Arrangement
PF2/WAIT/IRQ2/BREQO WDTOVF (FWE, EMLE)*
PF1/BACK/IRQ1/CS5
P23/TIOCD3/TMCI0
PF3/LWR/IRQ3
P22/TIOCC3/TMRI0
P21/TIOCB3
PF4/HWR
P20/TIOCA3
PA3/A19
PA2/A18
PF5/RD
PF6/AS
PF0/BREQ/IRQ0/CS4 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS P24/TIOCA4/TMRI1 P25/TIOCB4/TMCI1 P26/TIOCA5/TMO0 P27/TIOCB5/TMO1 PG0/ADTRG/IRQ6 PG1/CS3/IRQ7/CS6 PG2/CS2 PG3/CS1/CS7 PG4/CS0 P10/TIOCA0/A20 P11/TIOCB0/A21
PA1/A17
EXTAL
STBY
XTAL
PA0/A16 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11
P12/TIOCC0/TCLKA/A22
P13/TIOCD0/TCLKB/A23
P15/TIOCB1/TCLKC
P17/TIOCB2/TCLKD
P34/SCK0/IRQ4
P35/SCK1/IRQ5
P14/TIOCA1
P16/TIOCA2
P30/TxD0
P31/TxD1
P32/RxD0
P33/RxD1
Note: function only available H8S/2318 F-ZTAT H8S/2315 F-ZTAT versions. EMLE function only available H8S/2319 F-ZTAT version. WDTOVF function available F-ZTAT versions.
Figure Arrangement (TFP-100B: View)
PD2/D10
PD0/D8
PD1/D9
PE4/D4
PE5/D5
PE6/D6
PE0/D0
PE1/D1
PE2/D2
PE3/D3
PE7/D7
Note: function only available H8S/2318 F-ZTAT H8S/2315 F-ZTAT versions. EMLE function only available H8S/2319 F-ZTAT version. WDTOVF function available F-ZTAT versions.
P10/TIOCA0/A20 P11/TIOCB0/A21 P12/TIOCC0/TCLKA/A22 P13/TIOCD0/TCLKB/A23 P14/TIOCA1 P15/TIOCB1/TCLKC P16/TIOCA2 P17/TIOCB2/TCLKD P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/IRQ4 P35/SCK1/IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 PE7/D7 PD0/D8 PD1/D9 PD2/D10 PD3/D11 PD4/D12 PD5/D13
P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS P24/TIOCA4/TMRI1 P25/TIOCB4/TMCI1 P26/TIOCA5/TMO0 P27/TIOCB5/TMO1 PG0/ADTRG/IRQ6 PG1/CS3/IRQ7/CS6 PG2/CS2 PG3/CS1/CS7 PG4/CS0
Vref AVCC PF0/BREQ/IRQ0/CS4 PF1/BACK/IRQ1/CS5 PF2/WAIT/IRQ2/BREQO PF3/LWR/IRQ3 PF4/HWR PF5/RD PF6/AS EXTAL XTAL STBY WDTOVF (FWE, EMLE)* P23/TIOCD3/TMCI0 P22/TIOCC3/TMRI0 P21/TIOCB3 P20/TIOCA3 PA3/A19 PA2/A18 PA1/A17 PA0/A16
PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PD7/D15 PD6/D14
Figure Arrangement (FP-100A: View)
Functions Each Operating Mode
Table shows functions each operating modes. Table
TFP-100B FP-100A Mode P12/TIOCC0/ TCLKA/A22 P13/TIOCD0/ TCLKB/A23 P14/TIOCA1 P15/TIOCB1/ TCLKC P16/TIOCA2 P17/TIOCB2/ TCLKD P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/IRQ4 P35/SCK1/IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 PE7/D7 Mode P12/TIOCC0/ TCLKA/A22 P13/TIOCD0/ TCLKB/A23 P14/TIOCA1 P15/TIOCB1/ TCLKC P16/TIOCA2 P17/TIOCB2/ TCLKD P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/IRQ4 P35/SCK1/IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 PE7/D7 Mode P12/TIOCC0/ TCLKA/A22 P13/TIOCD0/ TCLKB/A23 P14/TIOCA1 P15/TIOCB1/ TCLKC P16/TIOCA2 P17/TIOCB2/ TCLKD P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/IRQ4 P35/SCK1/IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 PE7/D7
Functions Each Operating Mode
Name Mode P12/TIOCC0/ TCLKA P13/TIOCD0/ TCLKB P14/TIOCA1 P15/TIOCB1/ TCLKC P16/TIOCA2 P17/TIOCB2/ TCLKD P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/IRQ4 P35/SCK1/IRQ5 Flash Memory Programmer Mode*
TFP-100B FP-100A Mode P20/TIOCA3 P21/TIOCB3 P22/TIOCC3/ TMRI0 P23/TIOCD3/ TMCI0 WDTOVF (FWE, EMLE)* Mode P20/TIOCA3 P21/TIOCB3 P22/TIOCC3/ TMRI0 P23/TIOCD3/ TMCI0 WDTOVF (FWE, EMLE)* Mode
Name Mode P20/TIOCA3 P21/TIOCB3 P22/TIOCC3/ TMRI0 P23/TIOCD3/ TMCI0 WDTOVF (FWE, EMLE)* Flash Memory Programmer Mode*
PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PA3/A19 P20/TIOCA3 P21/TIOCB3 P22/TIOCC3/ TMRI0 P23/TIOCD3/ TMCI0 WDTOVF (FWE, EMLE)*
TFP-100B FP-100A Mode STBY XTAL EXTAL PF6/AS PF3/LWR/IRQ3 PF2/WAIT/ IRQ2/DREQO PF1/BACK/ IRQ1/CS5 PF0/BREQ/ IRQ0/CS4 AVCC P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS P24/TIOCA4/ TMRI1 P25/TIOCB4/ TMCI1 Mode STBY XTAL EXTAL PF6/AS PF3/LWR/IRQ3 PF2/WAIT/ IRQ2/DREQO PF1/BACK/ IRQ1/CS5 PF0/BREQ/ IRQ0/CS4 AVCC P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS P24/TIOCA4/ TMRI1 P25/TIOCB4/ TMCI1 Mode STBY XTAL
Name Mode STBY XTAL EXTAL PF3/IRQ3 PF2/IRQ2 PF1/IRQ1 PF0/IRQ0 AVCC P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS P24/TIOCA4/ TMRI1 P25/TIOCB4/ TMCI1 Flash Memory Programmer Mode* XTAL EXTAL
EXTAL PF6/AS PF3/LWR/IRQ3 PF2/WAIT/ IRQ2/DREQO PF1/BACK/ IRQ1/CS5 PF0/BREQ/ IRQ0/CS4 AVCC P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS P24/TIOCA4/ TMRI1 P25/TIOCB4/ TMCI1
TFP-100B FP-100A Mode P26/TIOCA5/ TMO0 P27/TIOCB5/ TMO1 PG0/IRQ6/ ADTRG PG1/CS3/ IRQ7/CS6 PG2/CS2 PG3/CS1/CS7 PG4/CS0 P10/TIOCA0/A20 P11/TIOCB0/A21 Mode P26/TIOCA5/ TMO0 P27/TIOCB5/ TMO1 PG0/IRQ6/ ADTRG PG1/CS3/ IRQ7/CS6 PG2/CS2 PG3/CS1/CS7 PG4/CS0 P10/TIOCA0/A20 P11/TIOCB0/A21 Mode
Name Mode P26/TIOCA5/ TMO0 P27/TIOCB5/ TMO1 PG0/IRQ6/ ADTRG PG1/IRQ7 P10/TIOCA0 P11/TIOCB0 Flash Memory Programmer Mode*
P26/TIOCA5/ TMO0 P27/TIOCB5/ TMO1 PG0/IRQ6/ ADTRG PG1/CS3/ IRQ7/CS6 PG2/CS2 PG3/CS1/CS7 PG4/CS0 P10/TIOCA0/A20 P11/TIOCB0/A21
Notes: Only modes available ROMless version. Flash memory programmer mode information preliminary. function only available H8S/2318 F-ZTAT H8S/2315 F-ZTAT versions. EMLE function only available H8S/2319 F-ZTAT version. cannot used WDTOVF F-ZTAT version.
Table
Functions
Functions
Type Power
Symbol
TFP-100B FP-100A Input
Name Function Power supply: connection power supply. pins should connected system power supply. Ground: connection ground pins should connected system power supply Connects crystal oscillator. section Hardware Manual, Clock Pulse Generator, typical connection diagrams crystal oscillator external clock input. Connects crystal oscillator. EXTAL also input external clock. section Hardware Manual, Clock Pulse Generator, typical connection diagrams crystal oscillator external clock input.
Input
Clock
XTAL
Input
EXTAL
Input
Output System clock: Supplies system clock external device.
Type Symbol TFP-100B FP-100A Input Name Function Mode pins: These pins operating mode. relation between settings pins operating mode shown below. These pins should changed while H8S/2318 Series operating. H8S/2318 F-ZTAT, H8S/2315 F-ZTAT versions
Operating mode control
Operating Mode Mode Mode Mode Mode Mode Mode Mode Mode
Type Symbol TFP-100B FP-100A Input Name Function Mask ROMless versions, H8S/2319 F-ZTAT version Operating Mode Mode Mode Mode Mode
Operating mode control
Note: used ROMless version. System control STBY Input Input Reset input: When this driven low, chip reset. Standby: When this driven low, transition made hardware standby mode. request: Used external master issue request H8S/2318 Series.
BREQ
Input
BREQO
Output request output: External request signal used when internal master accesses external space external-bus-released state. Output request acknowledge: Indicates that been released external master. Input Input Flash write enable: Enables disables writing flash memory. Emulator enable: connection ground
BACK
FWE* EMLE
Type Interrupts Symbol TFP-100B FP-100A Input Name Function Nonmaskable interrupt: Requests nonmaskable interrupt. When this used, should fixed high. Interrupt request These pins request maskable interrupt.
IRQ7 IRQ0 Address
100,
Input
Output Address bus: These pins output address.
Data control
Data bus: These pins constitute bidirectional data bus.
Output Chip select: Signals selecting areas Output Address strobe: When this low, indicates that address output address enabled. Output Read: When this low, indicates that external address space read. Output High write: strobe signal that writes external space indicates that upper half (D15 data enabled. Output write: strobe signal that writes external space indicates that lower half data enabled. Input Wait: Requests insertion wait state cycle when accessing external 3-state address space.
WAIT
Type 16-bit timerpulse unit (TPU) Symbol TCLKD TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TFP-100B FP-100A Input Name Function Clock input These pins input external clock. Input capture/ output compare match TGR0A TGR0D input capture input output compare output, output pins. Input capture/ output compare match TGR1A TGR1B input capture input output compare output, output pins. Input capture/ output compare match TGR2A TGR2B input capture input output compare output, output pins. Input capture/ output compare match TGR3A TGR3D input capture input output compare output, output pins. Input capture/ output compare match TGR4A TGR4B input capture input output compare output, output pins. Input capture/ output compare match TGR5A TGR5B input capture input output compare output, output pins.
100,
TIOCA2, TIOCB2
TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4
TIOCA5, TIOCB5
8-bit timer
TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1
Output Compare match output: compare match output pins. Input Counter external clock input: Input pins external clock input counter. Counter external reset input: counter reset input pins.
Input
Watchdog timer (WDT)
WDTOVF*
Output Watchdog timer overflows: counter overflows signal output watchdog timer mode.
Type Serial communication interface (SCI) Smart Card interface Symbol TxD1, TxD0 RxD1, RxD0 SCK1 SCK0 ADTRG TFP-100B FP-100A Name Function
Output Transmit data (channel Data output pins. Input Input Input Receive data (channel Data input pins. Serial clock (channel Clock pins. Analog Analog input pins. conversion external trigger input: input external trigger start conversion.
converter
converter converter converters
DA1, AVCC
Output Analog output: converter analog output pins. Input This power supply converter converter. When converter converter used, this should connected system power supply CC). This ground converter converter. This should connected system power supply This reference voltage input converter converter. When converter converter used, this should connected system power supply CC). Port 8-bit port. Input output designated each means port data direction register (P1DDR). Port 8-bit port. Input output designated each means port data direction register (P2DDR).
AVSS
Input
Vref
Input
ports
100,
Type ports Symbol TFP-100B FP-100A Name Function Port 6-bit port. Input output designated each means port data direction register (P3DDR). Port 8-bit input port. Port 4-bit port. Input output designated each means port data direction register (PADDR). Port 8-bit port. Input output designated each means port data direction register (PBDDR). Port C*4: 8-bit port. Input output designated each means port data direction register (PCDDR). Port D*4: 8-bit port. Input output designated each means port data direction register (PDDDR). Port 8-bit port. Input output designated each means port data direction register (PEDDR). Port 8-bit port. Input output designated each means port data direction register (PFDDR). Port 5-bit port. Input output designated each means port data direction register (PGDDR).
Input
Notes:
Applies H8S/2318 F-ZTAT H8S/2315 F-ZTAT versions only. Applies H8S/2319 F-ZTAT version only. Applies mask ROMless versions only. Cannot used port ROMless versions.
Table
Product Lineup
H8S/2319, H8S/2318 Series Product Lineup
Model F-ZTAT version HD64F2319 Marking Package (Hitachi Package Code)
Product Type H8S/2319*
HD64F2319VTE 100-pin TQFP (TFP-100B) HD64F2319VF 100-pin (FP-100A) 100-pin TQFP (TFP-100B) 100-pin (FP-100A)
H8S/2318
Mask version
HD6432318*
HD6432318TE HD6432318F
F-ZTAT version
HD64F2318
HD64F2318VTE 100-pin TQFP (TFP-100B) HD64F2318VF 100-pin (FP-100A) 100-pin TQFP (TFP-100B) 100-pin (FP-100A) 100-pin TQFP (TFP-100B) 100-pin (FP-100A)
H8S/2317
Mask version
HD6432317*
HD6432317TE HD6432317F
H8S/2316*
Mask version
HD6432316
HD6432316TE HD6432316F
H8S/2315*
F-ZTAT version
HD64F2315
HD64F2315VTE 100-pin TQFP (TFP-100B) HD64F2315VF 100-pin (FP-100A) 100-pin TQFP (TFP-100B) 100-pin (FP-100A) 100-pin TQFP (TFP-100B) 100-pin (FP-100A) 100-pin TQFP (TFP-100B) 100-pin (FP-100A) 100-pin TQFP (TFP-100B) 100-pin (FP-100A)
H8S/2313*
Mask version
HD6432313
HD6432313TE HD6432313F
H8S/2312
ROMless version
HD6412312
HD6412312VTE HD6412312VF
H8S/2311
Mask version
HD6432311
HD6432311TE HD6432311F
H8S/2310
ROMless version
HD6412310
HD6412310VTE HD6412310VF
Notes: Under development HD6432318 HD6432317 include products (low-voltage operation) well details, section Electrical Characteristics.
Package Dimensions
Unit:
16.0
16.0
*0.22 0.05 0.20 0.04 0.08
*0.17 0.05 0.15 0.04
1.20
1.00
0.10
0.10 0.10
*Dimension including plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
TFP-100B Conforms
Figure TFP-100B Package Dimensions
24.8
Unit:
18.8
*0.32 0.08 0.30 0.06
0.13
3.10
0.65
*0.17 0.05 0.15 0.04
0.83
0.58
0.20 +0.10 -0.20
2.70
Hitachi Code JEDEC EIAJ Weight (reference value) FP-100A
0.15
*Dimension including plating thickness Base material dimension
Figure FP-100A Package Dimensions
Section Operating Modes
2.1.1
Overview
Operating Mode Selection (H8S/2318 F-ZTAT H8S/2315 F-ZTAT Versions)
H8S/2318 Series eight operating modes (modes 15). These modes determined mode (MD2 MD0) flash write enable (FWE) settings. operating mode initial width selected shown table 2.1. Table lists operating modes. Table Operating Mode Selection (H8S/2318 F-ZTAT H8S/2315 F-ZTAT Versions)
External Data On-Chip Initial Value Max. Value
Operating Operating Mode Mode Description Advanced User program mode Advanced Boot mode Advanced Expanded mode with on-chip disabled Expanded mode with on-chip enabled Single-chip mode
Disabled bits bits bits Enabled bits bits bits
Enabled bits
bits
Enabled bits
bits
CPU's architecture allows Gbytes address space, H8S/2318 Series actually accesses maximum Mbytes. Modes externally expanded modes that allow access external memory peripheral devices. external expansion modes allow switching between 8-bit 16-bit modes. After program execution starts, 8-bit 16-bit address space each area, depending controller setting. 16-bit access selected area, 16-bit mode set; 8-bit access selected areas, 8-bit mode set. Note that functions each depend operating mode. Modes boot modes user program modes which flash memory programmed erased. details, section ROM, Hardware Manual H8S/2318 Series only used modes This means that flash write enable mode pins must select these modes. change inputs mode pins during operation. 2.1.2 Operating Mode Selection (Mask ROM, ROMless, H8S/2319 F-ZTAT Versions)
H8S/2319 H8S/2318 Series have four operating modes (modes operating mode determined mode pins (MD2 MD0). operating mode, enabling disabling on-chip ROM, initial width setting selected shown table 2.2. Table lists operating modes.
Table
Operating Mode Selection (Mask ROM, ROMless, H8S/2319 F-ZTAT Versions)
External Data On-Chip Initial Value Max. Value
Operating Operating Mode Mode Description
Advanced Expanded mode with Disabled bits on-chip disabled bits Expanded mode with on-chip enabled Single-chip mode Enabled bits
bits bits bits
Note: Only modes provided ROMless version.
CPU's architecture allows Gbytes address space, H8S/2319 H8S/2318 Series actually access maximum Mbytes. Modes externally expanded modes that allow access external memory peripheral devices. external expansion modes allow switching between 8-bit 16-bit modes. After program execution starts, 8-bit 16-bit address space each area, depending controller setting. 16-bit access selected area, 16-bit mode set; 8-bit access selected areas, 8-bit mode set. Note that functions each depend operating mode. H8S/2319 H8S/2318 Series only used modes This means that mode pins must select these modes. However, note that only mode ROMless version. change inputs mode pins during operation. 2.1.3 Register Configuration
H8S/2319 H8S/2318 Series have mode control register (MDCR) that indicates inputs mode pins (MD2 MD0), system control register (SYSCR) system control register (SYSCR2)*2 that control operation chip. Table summarizes these registers.
Table
Name
Registers
Abbreviation MDCR SYSCR
Initial Value Undefined H'01 H'00
Address* H'FF3B H'FF39 H'FF42
Mode control register System control register System control register
SYSCR2
Notes: Lower bits address. SYSCR2 register only used F-ZTAT version. mask ROMless versions this register will return undefined value read, cannot modified.
2.2.1
Register Descriptions
Mode Control Register (MDCR)
MDS2 MDS1 MDS0
Initial value
Note: Determined pins MD0.
MDCR 8-bit read-only register that indicates current operating mode H8S/2318 Series chip. 7-Reserved: This always read cannot modified. Bits 3-Reserved: These bits always read cannot modified. Bits 0-Mode Select (MDS2 MDS0): These bits indicate input levels pins (the current operating mode). Bits MDS2 MDS0 correspond pins MD0. MDS2 MDS0 read-only bits, cannot written mode (MD2 MD0) input levels latched into these bits when MDCR read. These latches canceled reset. 2.2.2
System Control Register (SYSCR)
INTM1 INTM0 NMIEG LWROD RAME
Initial value
7-Reserved: Only should written this bit. 6-Reserved: This always read cannot modified. Bits 4-Interrupt Control Mode (INTM1, INTM0): These bits select control mode interrupt controller. details interrupt control modes, section 3.4.1, Interrupt Control Modes Interrupt Operation, Hardware Manual.
INTM1 INTM0 Interrupt Control Mode Description Control interrupts Setting prohibited Control interrupts bits Setting prohibited (Initial value)
3-NMI Edge Select (NMIEG): Selects valid edge interrupt input.
NMIEG Description interrupt requested falling edge input interrupt requested rising edge input (Initial value)
2-LWR Output Disable (LWROD): Enables disables output.
LWROD Description designated output designated port, does function output (Initial value)
1-Reserved: Only should written this bit. 0-RAM Enable (RAME): Enables disables on-chip RAM. RAME initialized when reset state released. initialized software standby mode.
RAME Description On-chip disabled On-chip enabled (Initial value)
2.2.3
System Control Register (SYSCR2) (F-ZTAT Version Only)
FLSHE
Initial value
SYSCR2 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 initialized H'00 reset, hardware standby mode. Bits 4-Reserved: These bits always read cannot modified. 3-Flash Memory Control Register Enable (FLSHE): Controls access flash memory control registers (FLMCR1, FLMCR2, EBR1, EBR2). details, section ROM, Hardware Manual.
FLSHE Description Flash control registers selected addresses H'FFFFC8 H'FFFFCB (Initial value) Flash control registers selected addresses H'FFFFC8 H'FFFFCB
Bits 0-Reserved: These bits always read cannot modified.
2.3.1
Operating Mode Descriptions
Modes
Modes supported H8S/2319 H8S/2318 Series, must set. 2.3.2 Mode (Expanded Mode with On-Chip Disabled)
access 16-Mbyte address space advanced mode. on-chip disabled. Pins P10, ports function address bus, ports functions data bus, part port carries control signals. Pins function input ports immediately after reset. These pins output addresse setting corresponding data direction register (DDR) bits A23E A20E PFCR1
initial mode after reset bits, with 16-bit access areas. However, note that 8-bit access designated controller areas, mode switches bits. 2.3.3 Mode (Expanded Mode with On-Chip Disabled)
access 16-Mbyte address space advanced mode. on-chip disabled. Pins P10, ports function address bus, port functions data bus, part port carries control signals. Pins function input ports immediately after reset. These pins output addresses setting corresponding data direction register (DDR) bits A23E A20E PFCR1 initial mode after reset bits, with 8-bit access areas. However, note that least area designated 16-bit access controller, mode switches bits port becomes data bus. 2.3.4 Mode (Expanded Mode with On-Chip Enabled)
access 16-Mbyte address space advanced mode. on-chip enabled. Pins P10, ports function input ports immediately after reset. These pins output addresses setting corresponding data direction register (DDR) bits A23E A20E PFCR1 Port functions data bus, part port carries control signals. initial mode after reset bits, with 8-bit access areas. However, note that least area designated 16-bit access controller, mode switches bits port becomes data bus. 2.3.5 Mode (Single-Chip Mode)
access 16-Mbyte address space advanced mode. on-chip enabled, external addresses cannot accessed. ports available input/output ports. 2.3.6 Modes (H8S/2318 F-ZTAT H8S/2315 F-ZTAT Versions Only)
Modes supported H8S/2319 H8S/2318 Series, must set.
2.3.7
Mode (H8S/2318 F-ZTAT H8S/2315 F-ZTAT Versions Only)
This flash memory boot mode. details, section ROM, Hardware Manual. Except fact that flash memory programming erasing performed, operation this mode same advanced expanded mode with on-chip enabled. 2.3.8 Mode (H8S/2318 F-ZTAT H8S/2315 F-ZTAT Versions Only)
This flash memory boot mode. details, section ROM, Hardware Manual. Except fact that flash memory programming erasing performed, operation this mode same advanced single-chip mode. 2.3.9 Modes (H8S/2318 F-ZTAT H8S/2315 F-ZTAT Versions Only)
Modes supported H8S/2319 H8S/2318 Series, must set. 2.3.10 Mode (H8S/2318 F-ZTAT H8S/2315 F-ZTAT Versions Only)
This flash memory user program mode. details, section ROM, Hardware Manual. Except fact that flash memory programming erasing performed, operation this mode same advanced expanded mode with on-chip enabled. 2.3.11 Mode (H8S/2318 F-ZTAT H8S/2315 F-ZTAT Versions Only)
This flash memory user program mode. details, section ROM, Hardware Manual. Except fact that flash memory programming erasing performed, operation this mode same advanced single-chip mode.
Functions Each Operating Mode
functions ports vary depending operating mode. Table shows their functions each operating mode. Table Functions Each Mode
Mode Mode Mode 1/T/A
Port Port Port Port Port Port Port Port PF6, PF5,
Mode /T/A P/D* P/C*
Mode 1/T/A P/C*
Mode Mode Mode
P/C*
P/C*
P/C*
P/C*
Legend port Timer Address output Data Control signals, clock Notes: After reset used ROMless version. Applies H8S/2318 F-ZTAT H8S/2315 F-ZTAT versions only.
Memory Each Operating Mode
Figures show memory maps each operating modes. address space Mbytes. address space divided into eight areas.
Modes (advanced expanded modes with on-chip disabled) H'000000
Mode (advanced expanded mode with on-chip enabled) H'000000 On-chip H'010000
Mode (advanced single-chip mode) H'000000 On-chip H'010000
External address space
On-chip ROM/ external address space*1
On-chip ROM/ reserved area*2,*5
H'080000 External address space H'FF7400 H'FFDC00 Reserved area*4 On-chip RAM*3
H'080000 External address space H'FF7400 H'FFDC00 H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF Reserved area*4 On-chip RAM*3,*6 External address space Internal registers External address space Internal registers
H'07FFFF
H'FF7400 H'FFDC00 H'FFFBFF H'FFFE50 H'FFFF07
Reserved area*4 On-chip RAM*6
H'FFFC00 External address space H'FFFE50 Internal registers H'FFFF08 External address space H'FFFF28 Internal registers H'FFFFFF
Internal registers
H'FFFF28 H'FFFFFF
Internal registers
Notes:
External addresses when BCRL; on-chip when Reserved area when BCRL; on-chip when External addresses accessed clearing RAME SYSCR access reserved area addresses H'FF7400 H'FFDBFF. access reserved areas. When writing flash memory, clear RAME SYSCR because on-chip used writing procedure.
Figure H8S/2319 F-ZTAT Memory Each Operating Mode
Modes (advanced expanded modes with on-chip disabled) H'000000
Mode (advanced expanded mode with on-chip enabled) H'000000
Mode (advanced single-chip mode) H'000000
On-chip
On-chip
External address space
H'010000
H'010000
On-chip ROM/ external address space*2
On-chip ROM/ reserved area*3,*5
H'03FFFF H'040000 H'FFDC00 On-chip
External address space H'FFDC00 On-chip
H'FFDC00
On-chip H'FFFBFF
H'FFFC00 External address space H'FFFE50 Internal registers H'FFFF08 External address space H'FFFF28 Internal registers H'FFFFFF
H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF
External address space Internal registers External address space Internal registers
H'FFFE50 H'FFFF07
Internal registers
H'FFFF28 H'FFFFFF
Internal registers
Notes:
Only modes provided ROMless version (H8S/2312). External addresses when BCRL; on-chip when Reserved area when BCRL; on-chip when External addresses accessed clearing RAME SYSCR access reserved areas.
Figure H8S/2318 H8S/2312 Memory Each Operating Mode
Mode Boot Mode (advanced expanded mode with on-chip enabled) H'000000
Mode Boot Mode (advanced single-chip mode) H'000000
On-chip
On-chip
H'010000
H'010000
On-chip ROM/ external address space*1
On-chip ROM/ reserved area*2,*4
H'03FFFF H'040000 H'FFDC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal registers H'FFFF08 External address space H'FFFF28 Internal registers H'FFFFFF External address space H'FFDC00 On-chip RAM*3
H'FFFE50 H'FFFF07
Internal registers
H'FFFF28 H'FFFFFF
Internal registers
Notes: External addresses when BCRL; on-chip when Reserved area when BCRL; on-chip when On-chip used flash memory programming. clear RAME SYSCR access reserved areas.
Figure H8S/2318 Memory Each Operating Mode (F-ZTAT Version Only)
Mode User Program Mode (advanced expanded mode with on-chip enabled) H'000000
Mode User Program Mode (advanced single-chip mode) H'000000
On-chip
On-chip
H'010000
H'010000
On-chip ROM/ external address space*1
On-chip ROM/ reserved area*2,*4
H'03FFFF H'040000 H'FFDC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal registers H'FFFF08 External address space H'FFFF28 Internal registers H'FFFFFF External address space H'FFDC00 On-chip RAM*3
H'FFFE50 H'FFFF07
Internal registers
H'FFFF28 H'FFFFFF
Internal registers
Notes: External addresses when BCRL; on-chip when Reserved area when BCRL; on-chip when On-chip used flash memory programming. clear RAME SYSCR access reserved areas.
Figure H8S/2318 Memory Each Operating Mode (F-ZTAT Version Only)
Modes (advanced expanded modes with on-chip disabled) H'000000
Mode (advanced expanded mode with on-chip enabled) H'000000
Mode (advanced single-chip mode) H'000000
On-chip
On-chip
External address space
H'010000 On-chip ROM/ external address space*1
H'010000 On-chip ROM/ reserved area*2,*4
H'020000 Reserved area*4/external address space*1
H'020000 Reserved area*4 H'03FFFF
H'040000 H'FFDC00 On-chip RAM*3 H'FFFC00 External address space H'FFFE50 Internal registers H'FFFF08 External address space H'FFFF28 Internal registers H'FFFFFF H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF H'FFDC00
External address space H'FFDC00 On-chip RAM*3 H'FFFBFF External address space Internal registers External address space Internal registers On-chip
H'FFFE50 H'FFFF07
Internal registers
H'FFFF28 H'FFFFFF
Internal registers
Notes:
External addresses when BCRL; on-chip reserved area when Reserved area when BCRL; on-chip External addresses accessed clearing RAME SYSCR access reserved areas.
Figure H8S/2317 Memory Each Operating Mode
Modes (advanced expanded modes with on-chip disabled) H'000000
Mode (advanced expanded mode with on-chip enabled) H'000000
Mode (advanced single-chip mode) H'000000
On-chip
On-chip
External address space
H'010000
H'010000
Reserved area*3/ external address space*1
Reserved area*3
H'03FFFF H'040000 H'FFDC00 On-chip
External address space H'FFDC00 On-chip
H'FFDC00
On-chip H'FFFBFF
H'FFFC00 External address space H'FFFE50 Internal registers H'FFFF08 External address space H'FFFF28 Internal registers H'FFFFFF
H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF
External address space Internal registers External address space Internal registers
H'FFFE50 H'FFFF07
Internal registers
H'FFFF28 H'FFFFFF
Internal registers
Notes: External addresses when BCRL; reserved area when External addresses accessed clearing RAME SYSCR access reserved areas.
Figure H8S/2316 Memory Each Operating Mode
Modes (advanced expanded modes with on-chip disabled) H'000000
Mode (advanced expanded mode with on-chip enabled) H'000000 On-chip H'010000
Mode (advanced single-chip mode) H'000000 On-chip H'010000
External address space
On-chip ROM/ external address space*1
On-chip ROM/ reserved area*2,*5
H'060000 H'080000
Reserved area*4
H'060000 H'080000
Reserved area*4
H'060000 H'07FFFF
Reserved area*4
External address space
External address space
H'FFDC00
On-chip RAM*3
H'FFDC00 H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF
On-chip RAM*3 External address space Internal registers External address space Internal registers
H'FFDC00 H'FFFBFF H'FFFE50 H'FFFF07
On-chip
H'FFFC00 External address space H'FFFE50 Internal registers H'FFFF08 External address space H'FFFF28 Internal registers H'FFFFFF
Internal registers
H'FFFF28 H'FFFFFF
Internal registers
Notes:
External addresses when BCRL; on-chip when Reserved area when BCRL; on-chip when External addresses accessed clearing RAME SYSCR access reserved area addresses H'060000 H'07FFFF. access reserved areas.
Figure H8S/2315 F-ZTAT Memory Each Operating Mode
Mode Boot Mode (advanced expanded mode with on-chip enabled) H'000000 On-chip H'010000
Mode Boot Mode (advanced single-chip mode) H'000000 On-chip H'010000
On-chip ROM/ external address space*1
On-chip ROM/ reserved area*2,*5
H'060000 H'080000
Reserved area*4
H'060000 H'07FFFF
Reserved area*4
External address space
H'FFDC00
On-chip RAM*3
H'FFDC00 H'FFFBFF H'FFFE50 H'FFFF07
On-chip RAM*3
H'FFFC00 External address space H'FFFE50 Internal registers H'FFFF08 External address space H'FFFF28 Internal registers H'FFFFFF
Internal registers
H'FFFF28 H'FFFFFF
Internal registers
Notes:
External addresses when BCRL; on-chip when Reserved area when BCRL; on-chip when External addresses accessed clearing RAME SYSCR access reserved area addresses H'060000 H'07FFFF. access reserved areas.
Figure H8S/2315 F-ZTAT Memory Each Operating Mode
Mode User Program Mode (advanced expanded mode with on-chip enabled) H'000000 On-chip H'010000
Mode User Program Mode (advanced single-chip mode) H'000000 On-chip H'010000
On-chip ROM/ external address space*1
On-chip ROM/ reserved area*2,*5
H'060000 H'080000
Reserved area*4
H'060000 H'07FFFF
Reserved area*4
External address space
H'FFDC00
On-chip RAM*3
H'FFDC00 H'FFFBFF H'FFFE50 H'FFFF07
On-chip RAM*3
H'FFFC00 External address space H'FFFE50 Internal registers H'FFFF08 External address space H'FFFF28 Internal registers H'FFFFFF
Internal registers
H'FFFF28 H'FFFFFF
Internal registers
Notes:
External addresses when BCRL; on-chip when Reserved area when BCRL; on-chip when External addresses accessed clearing RAME SYSCR access reserved area addresses H'060000 H'07FFFF. access reserved areas.
Figure H8S/2315 F-ZTAT Memory Each Operating Mode
Modes (advanced expanded modes with on-chip disabled) H'000000
Mode (advanced expanded mode with on-chip enabled) H'000000
Mode (advanced single-chip mode) H'000000
On-chip
On-chip
External address space
H'010000
H'010000
Reserved area*3/ external address space*1
Reserved area*3
H'03FFFF H'040000 H'FFDC00 H'FFF400 On-chip RAM*2 H'FFFC00 External address space H'FFFE50 Internal registers H'FFFF08 External address space H'FFFF28 Internal registers H'FFFFFF H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF H'FFDC00 H'FFF400 On-chip RAM*2 External address space Internal registers External address space Internal registers External address space Reserved area*3 H'FFDC00 H'FFF400 H'FFFBFF On-chip Reserved area*3
Reserved area*3
H'FFFE50 H'FFFF07
Internal registers
H'FFFF28 H'FFFFFF
Internal registers
Notes: External addresses when BCRL; reserved area when External addresses accessed clearing RAME SYSCR access reserved areas.
Figure H8S/2313 Memory Each Operating Mode
Modes (advanced expanded modes with on-chip disabled) H'000000
Mode (advanced expanded mode with on-chip enabled) H'000000
Mode (advanced single-chip mode) H'000000
On-chip
On-chip
H'008000 Reserved area*4
H'008000 Reserved area*4
External address space
H'010000
H'010000
Reserved area*4/ external address space*2
Reserved area*4
H'03FFFF H'040000 H'FFDC00 H'FFF400 On-chip RAM*3 H'FFFC00 External address space H'FFFE50 Internal registers H'FFFF08 External address space H'FFFF28 Internal registers H'FFFFFF H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF H'FFDC00 H'FFF400 On-chip RAM*3 External address space Internal registers External address space Internal registers External address space Reserved area*4 H'FFDC00 H'FFF400 H'FFFBFF On-chip Reserved area*4
Reserved area*4
H'FFFE50 H'FFFF07
Internal registers
H'FFFF28 H'FFFFFF
Internal registers
Notes:
Only modes provided ROMless version (H8S/2310). External addresses when BCRL; reserved area when External addresses accessed clearing RAME SYSCR access reserved areas.
Figure H8S/2311 H8S/2310 Memory Each Operating Mode
Section Exception Handling Interrupt Controller
3.1.1
Overview
Exception Handling Types Priority
table indicates, exception handling caused reset, trap instruction, interrupt. Exception handling prioritized shown table 3.1. more exceptions occur simultaneously, they accepted processed order priority. Trap instruction exceptions accepted times program execution state. Exception handling sources, stack structure, operation vary depending interrupt control mode INTM0 INTM1 bits SYSCR. details exception handling interrupt controller, section Exception Handling, section Interrupt Controller, Hardware Manual. Table
Priority High
Exception Types Priority
Exception Type Reset Trace* Interrupt Trap instruction* (TRAPA) Start Exception Handling Starts after low-to-high transition pin, when watchdog timer overflows Starts when execution current instruction exception handling ends, trace Starts when execution current instruction exception handling ends, interrupt request been issued* Started execution trap instruction (TRAPA)
Notes: Traces enabled only interrupt control mode Trace exception handling executed after execution instruction. Interrupt detection performed completion ANDC, ORC, XORC, instruction execution, completion reset exception handling. Trap instruction exception handling requests accepted times program execution state.
3.2.1
Interrupt Controller
Interrupt Controller Features
interrupt control modes Either interrupt control modes means INTM1 INTM0 bits system control register (SYSCR). Priorities settable with IPRs Interrupt priority registers (IPRs) provided setting interrupt priorities. Eight priority levels each module interrupts except NMI. assigned highest priority level accepted times. Independent vector addresses interrupt sources assigned independent vector addresses, making unnecessary source identified interrupt handling routine. Nine external interrupt pins highest-priority interrupt, accepted times. Rising edge falling edge selected NMI. Falling edge, rising edge, both edge detection, level sensing, selected independently IRQ7 IRQ0. control activation controlled means interrupts. 3.2.2 Table
Name Nonmaskable interrupt
Configuration Interrupt Controller Pins
Symbol Input Function Nonmaskable external interrupt; rising falling edge selected Maskable external interrupts; rising, falling, both edges, level sensing, selected
External interrupt requests
IRQ7 IRQ0
Input
Interrupt Sources
Interrupt sources comprise external interrupts (NMI IRQ7 IRQ0) internal interrupts sources). 3.3.1 External Interrupts
There nine external interrupts: IRQ7 IRQ0. IRQ7 IRQ0 used restore chip from software standby mode. (IRQ7 IRQ3 used software standby mode clearing sources setting IRQ37S SBYCR Interrupt: highest-priority interrupt, always accepted regardless status interrupt mask bits. NMIEG SYSCR used select whether interrupt requested rising edge falling edge pin. vector number interrupt exception handling Interrupts IRQ7 IRQ0: Interrupts IRQ7 IRQ0 requested input signal pins IRQ7 IRQ0. Interrupts IRQ7 IRQ0 have following features: Using ISCR, possible select whether interrupt generated level, falling edge, rising edge, both edges, pins IRQ7 IRQ0. Enabling disabling interrupt requests IRQ7 IRQ0 selected with IER. interrupt priority level with registers. status interrupt requests IRQ7 IRQ0 indicated ISR. flags cleared software. block diagram interrupts IRQ7 IRQ0 shown figure 3.1.
IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit Clear signal Note:
IRQnE
IRQn interrupt request
IRQn input
Figure Block Diagram Interrupts IRQ7 IRQ0
Figure shows timing IRQnF setting.
IRQn input
IRQnF
Figure Timing IRQnF Setting vector numbers IRQ7 IRQ0 interrupt exception handling Detection IRQ7 IRQ0 interrupts does depend whether relevant been input output. When used external interrupt input pin, clear corresponding another function. 3.3.2 Internal Interrupts
There sources internal interrupts from on-chip supporting modules. each on-chip supporting module there flags that indicate interrupt request status, enable bits that select enabling disabling these interrupts. these interrupt request issued interrupt controller. interrupt priority level means registers. activated TPU, SCI, other interrupt request. When activated interrupt, interrupt control mode interrupt mask bits have effect. 3.3.3 Interrupt Exception Vector Table
Table shows interrupt sources, vector addresses, interrupt priorities. default priorities, lower vector number, higher priority. activated interrupt request. Priorities among modules means registers. situation when more modules same priority, priorities within module, fixed shown table 3.3.
Table
Interrupt Sources, Vector Addresses, Interrupt Priorities
Origin Interrupt Source Vector Number Vector Address* H'0000 H'0004 H'0008 H'000C H'0010 H'0014 H'0018 H'001C H'0020 H'0024 H'0028 H'002C H'0030 H'0034 H'0038 H'003C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C IPRC6 IPRC4 IPRB2 IPRB0 IPRA6 IPRA4 IPRA2 IPRA0 IPRB6 IPRB4 Priority Activation High
Interrupt Source Power-on reset Reserved Reserved system
Trace Reserved system Trap instruction sources) External
Reserved system
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
External
Interrupt Source
Origin Interrupt Source
Vector Number
Vector Address* H'0060
Priority Activation
SWDTEND (software- activated data transfer end) WOVI (interval timer) Reserved Reserved (A/D conversion end) Reserved
IPRC2 High IPRC0 IPRD6 IPRD4 IPRD2 IPRD0 IPRE6 IPRE4 IPRE2 IPRE0
Watchdog timer
H'0064 H'0068 H'006C H'0070 H'0074 H'0078 H'007C H'0080
TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TCI0V (overflow Reserved
channel
IPRF6 IPRF4
H'0084
H'0088
H'008C
H'0090 H'0094 H'0098 H'009C
Interrupt Source TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow
Origin Interrupt Source channel
Vector Number
Vector Address* H'00A0
IPRF2 IPRF0
Priority Activation High
H'00A4
H'00A8
TCI1U (underflow TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow TCI2U (underflow TGI3A (TGR3A input capture/compare match) TGI3B (TGR3B input capture/compare match) TGI3C (TGR3C input capture/compare match) TGI3D (TGR3D input capture/compare match) TCI3V (overflow Reserved channel channel
H'00AC H'00B0 IPRG6 IPRG4
H'00B4
H'00B8 H'00BC H'00C0 IPRG2 IPRG0
H'00C4
H'00C8
H'00CC
H'00D0 H'00D4 H'00D8 H'00DC
Interrupt Source TGI4A (TGR4A input capture/compare match) TGI4B (TGR4B input capture/compare match) TCI4V (overflow TCI4U (underflow TGI5A (TGR5A input capture/compare match) TGI5B (TGR5B input capture/compare match) TCI5V (overflow TCI5U (underflow CMIA0 (compare match CMIB0 (compare match OVI0 (overflow Reserved CMIA1 (compare match CMIB1 (compare match OVI1 (overflow Reserved
Origin Interrupt Source channel
Vector Number
Vector Address* H'00E0
Priority Activation
IPRH6 High IPRH4
H'00E4
channel
H'00E8 H'00EC H'00F0 IPRH2 IPRH0
H'00F4
8-bit timer channel 8-bit timer channel
H'00F8 H'00FC H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C IPRI2 IPRI0 IPRI6 IPRI4
Interrupt Source Reserved
Origin Interrupt Source
Vector Number
Vector Address* H'0120 H'0124 H'0128
IPRJ6 IPRJ4
Priority Activation High
ERI0 (receive error RXI0 (receive-data-full TXI0 (transmit-dataempty TEI0 (transmit ERI1 (receive error RXI1 (receive-data-full TXI1 (transmit-dataempty TEI1 (transmit Reserved channel channel Note: Lower bits start address.
H'012C H'0130 H'0134 H'0138 H'013C H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C IPRK2 IPRK0 IPRK6 IPRK4 IPRJ2 IPRJ0
Interrupt Control Modes Interrupt Operation
Interrupt operations H8S/2319 H8S/2318 Series differ depending interrupt control mode. interrupts accepted times except reset state hardware standby state. case interrupts on-chip supporting module interrupts, enable provided each interrupt. Clearing enable disables corresponding interrupt request. Interrupt sources which enable controlled interrupt controller. interrupt control modes shown table 3.4, interrupts selected each interrupt control mode tables 3.6, operations control signal functions each interrupt control mode table 3.7. interrupt controller performs interrupt control according interrupt control mode INTM1 INTM0 bits SYSCR, priorities registers, masking state indicated CPU's bits EXR. Table
Interrupt Control Mode
Interrupt Control Modes
Priority Setting Interrupt Registers Mask Bits Description Interrupt mask control performed bit. Setting prohibited 8-level interrupt mask control performed bits priority levels with IPR.
INTM1
INTM0
Setting prohibited
Table
Interrupts Selected Each Interrupt Control Mode
Interrupt Mask Bits Selected Interrupts interrupts interrupts interrupts
Interrupt Control Mode
Don't care
Table
Interrupts Selected Each Interrupt Control Mode
Selected Interrupts interrupts Highest-priority-level (IPR) interrupt with priority level greater than mask level (IPR
Interrupt Control Mode
Table
Operations Control Signal Functions Each Interrupt Control Mode
Interrupt Acceptance Control
Interrupt Control Mode
Settings INTM1 INTM0
8-Level Control
Default Priority Determination (Trace)
Legend Interrupt operation control performed operation (all interrupts enabled) Used interrupt mask Sets priority used Notes: when interrupt accepted. Keep initial setting.
Interrupt Response Times
H8S/2319 H8S/2318 Series capable fast word access on-chip memory, program area provided on-chip stack area on-chip RAM, enabling highspeed processing. Table shows interrupt response times-the interval between generation interrupt request execution first instruction interrupt handling routine. execution phase symbols used table explained table 3.9. Table Interrupt Response Times
Advanced Mode Execution Phase Interrupt priority determination*
INTM1
INTM1
Number wait states until executing instruction ends* CCR, stacking Vector fetch Instruction fetch*
Internal processing*
Total (when using on-chip memory) Notes:
states case internal interrupt. Refers MULXS DIVXS instructions. Prefetch after interrupt acceptance interrupt handling routine prefetch. Internal processing after interrupt acceptance internal processing after vector fetch.
Table
Number States Interrupt Handling Routine Execution Phases
Access External Device 8-Bit 16-Bit 2-State Access 3-State Access
Symbol Instruction fetch Branch address read Stack manipulation
Internal Memory
2-State Access
3-State Access
Legend Number wait states external device access
3.6.1
Activation Interrupt
Overview
H8S/2319 H8S/2318 Series, activated interrupt. this case, following options available: Interrupt request Activation request Selection number above table interrupt requests that used activate DTC. details, section Data Transfer Controller, Hardware Manual. 3.6.2 Block Diagram
Figure shows block diagram interrupt controller.
interrupt
Interrupt request Selection circuit Select signal Clear signal DTCER
activation request vector number
Control logic Clear signal
On-chip supporting module
Interrupt source clear signal
DTVECR SWDTE clear signal
interrupt request vector number Priority determination
Interrupt controller
Figure Interrupt Control
3.6.3
Operation
interrupt controller three main functions control, described below. Selection Interrupt Source: interrupt sources, possible select activation request interrupt request with DTCE registers DTCERA DTCERE. After data transfer, DTCE cleared interrupt request sent accordance with specification DISEL DTC's register. When performed specified number data transfers transfer counter value DTCE cleared after data transfer interrupt request sent CPU. Determination Priority: activation source selected accordance with default priority order, affected mask priority levels. table 3.10, Interrupt Sources, Vector Addresses, Corresponding DTCEs, respective priorities.
Table 3.10 Interrupt Sources, Vector Addresses, Corresponding DTCEs
Origin Interrupt Source Software Vector Number DTVECR Vector Address H'0400 (DTVECR [6:0]<<1) H'0420 H'0422 H'0424 H'0426 H'0428 H'042A H'042C H'042E H'0438 H'0440 H'0442 H'0444 H'0446 H'0450 H'0452 H'0458 H'045A
Interrupt Source Write DTVECR
DTCE*
Priority High
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 (A/D conversion end) TGI0A (GR0A compare match/input capture) TGI0B (GR0B compare match/input capture) TGI0C (GR0C compare match/input capture) TGI0D (GR0D compare match/input capture) TGI1A (GR1A compare match/input capture) TGI1B (GR1B compare match/input capture) TGI2A (GR2A compare match/input capture) TGI2B (GR2B compare match/input capture)
External
DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC7 DTCEC6
channel
channel
channel
Interrupt Source TGI3A (GR3A compare match/input capture) TGI3B (GR3B compare match/input capture) TGI3C (GR3C compare match/input capture) TGI3D (GR3D compare match/input capture) TGI4A (GR4A compare match/input capture) TGI4B (GR4B compare match/input capture) TGI5A (GR5A compare match/input capture) TGI5B (GR5B compare match/input capture) CMIA0 CMIB0 CMIA1 CMIB1 RXI0 (receive-data-full TXI0 (transmit-data-empty RXI1 (receive-data-full TXI1 (transmit-data-empty
Origin Interrupt Source channel
Vector Number
Vector Address H'0460 H'0462 H'0464 H'0466 H'0470 H'0472 H'0478 H'047A H'0480 H'0482 H'0488 H'048A H'04A2 H'04A4 H'04AA H'04AC
DTCE* DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0 DTCEE3 DTCEE2 DTCEE1 DTCEE0
Priority High
channel
channel
8-bit timer channel 8-bit timer channel channel channel
Note: DTCE bits with corresponding interrupt reserved, should written with
Operation Order: same interrupt selected activation source interrupt source, data transfer performed first, followed interrupt exception handling. Table 3.11 summarizes interrupt source selection interrupt source clearance control according setting DTCE registers DTCERA DTCERE DISEL DTC's register.
Table 3.11 Interrupt Source Selection Clearing Control
Settings DTCE DISEL Legend relevant interrupt used. Interrupt source clearing performed. (The should clear source flag interrupt handling routine.) relevant interrupt used. interrupt source cleared. relevant cannot used. Don't care Interrupt Source Selection/Clearing Control
Usage Note: converter interrupt sources cleared when reads writes prescribed register, dependent DISEL bit.
Section Controller
Overview
H8S/2319 H8S/2318 Series have on-chip controller (BSC) that manages external address space divided into eight areas. specifications, such width number access states, independently each area, enabling multiple memories connected easily. controller also arbitration function, controls operation internal masters-the data transfer controller (DTC). 4.1.1 Features
features controller listed below. Manages external address space area units advanced mode, manages external space areas Mbytes specifications independently each area Burst interfaces Basic interface Chip select signals (CS0 CS7) output areas 8-bit access 16-bit access selected each area 2-state access 3-state access selected each area Program wait states inserted each area Burst interface Burst interface area Selection 2-state burst access Idle cycle insertion idle cycle inserted case external read cycles different areas idle cycle inserted case external write cycle immediately after external read cycle arbitration function Includes arbiter that arbitrates mastership between Other features External release function
4.1.2
Block Diagram
Area decoder
Internal address
ABWCR External control signals ASTCR BCRH BCRL BREQ BACK BREQO Internal data controller Internal control signals
mode signal
WAIT
Wait controller
WCRH WCRL
request signal request signal arbiter acknowledge signal acknowledge signal
Figure Block Diagram Controller
4.1.3
Configuration
Table summarizes pins controller. Table
Name Address strobe Read High write
Controller Pins
Symbol Output Output Output Function Strobe signal indicating that address output address enabled. Strobe signal indicating that external space being read. Strobe signal indicating that external space written, upper half (D15 data enabled. Strobe signal indicating that external space written, lower half data enabled. Strobe signal indicating that area selected. Strobe signal indicating that area selected. Strobe signal indicating that area selected. Strobe signal indicating that area selected. Strobe signal indicating that area selected. Strobe signal indicating that area selected. Strobe signal indicating that area selected. Strobe signal indicating that area selected. Wait request signal when accessing external 3state access space. Request signal release external device. Acknowledge signal indicating that been released. External request signal used when internal master accesses external space when external released.
write
Output
Chip select Chip select Chip select Chip select Chip select Chip select Chip select Chip select Wait request request acknowledge request output
WAIT BREQ BACK BREQO
Output Output Output Output Output Output Output Output Input Input Output Output
4.1.4
Register Configuration
Table summarizes registers controller. Table Controller Registers
Initial Value Name width control register Access state control register Wait control register Wait control register control register control register Abbreviation ABWCR ASTCR WCRH WCRL BCRH BCRL Reset H'FF/H'00* H'FF H'FF H'FF H'D0 H'3C Address* H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5
Notes: Lower bits address. Determined operating mode.
4.2.1
Register Descriptions
Width Control Register (ABWCR)
ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0
Modes Initial value Mode Initial value
ABWCR 8-bit readable/writable register that designates each area either 8-bit access space 16-bit access space. ABWCR sets data width external memory space. width on-chip memory internal registers fixed regardless settings ABWCR. After reset hardware standby mode, ABWCR initialized H'FF modes H'00 mode initialized software standby mode. Note: Modes cannot used ROMless version. Bits 0-Area Width Control (ABW7 ABW0): These bits select whether corresponding area designated 8-bit access space 16-bit access space.
ABWn Description Area designated 16-bit access Area designated 8-bit access
4.2.2
Access State Control Register (ASTCR)
AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0
Initial value
ASTCR 8-bit readable/writable register that designates each area either 2-state access space 3-state access space. ASTCR sets number access states external memory space. number access states on-chip memory internal registers fixed regardless settings ASTCR. ASTCR initialized H'FF reset, hardware standby mode. initialized software standby mode. Bits 0-Area Access State Control (AST7 AST0): These bits select whether corresponding area designated 2-state access space 3-state access space. Wait state insertion enabled disabled same time.
ASTn Description Area designated 2-state access Wait state insertion area external space access disabled Area designated 3-state access Wait state insertion area external space access enabled (Initial value)
4.2.3
Wait Control Registers (WCRH, WCRL)
WCRH WCRL 8-bit readable/writable registers that select number program wait states each area. Program waits inserted on-chip memory internal register access. WCRH WCRL initialized H'FF reset, hardware standby mode. They initialized software standby mode.
WCRH
Initial value
Bits 6-Area Wait Control (W71, W70): These bits select number program wait states when area external space accessed while AST7 ASTCR
Description Program wait inserted when external space area accessed program wait state inserted when external space area accessed program wait states inserted when external space area accessed program wait states inserted when external space area accessed (Initial value)
Bits 4-Area Wait Control (W61, W60): These bits select number program wait states when area external space accessed while AST6 ASTCR
Description Program wait inserted when external space area accessed program wait state inserted when external space area accessed program wait states inserted when external space area accessed program wait states inserted when external space area accessed (Initial value)
Bits 2-Area Wait Control (W51, W50): These bits select number program wait states when area external space accessed while AST5 ASTCR
Description Program wait inserted when external space area accessed program wait state inserted when external space area accessed program wait states inserted when external space area accessed program wait states inserted when external space area accessed (Initial value)
Bits 0-Area Wait Control (W41, W40): These bits select number program wait states when area external space accessed while AST4 ASTCR
Description Program wait inserted when external space area accessed program wait state inserted when external space area accessed program wait states inserted when external space area accessed program wait states inserted when external space area accessed (Initial value)
WCRL
Initial value
Bits 6-Area Wait Control (W31, W30): These bits select number program wait states when area external space accessed while AST3 ASTCR
Description Program wait inserted when external space area accessed program wait state inserted when external space area accessed program wait states inserted when external space area accessed program wait states inserted when external space area accessed (Initial value)
Bits 4-Area Wait Control (W21, W20): These bits select number program wait states when area external space accessed while AST2 ASTCR
Description Program wait inserted when external space area accessed program wait state inserted when external space area accessed program wait states inserted when external space area accessed program wait states inserted when external space area accessed (Initial value)
Bits 2-Area Wait Control (W11, W10): These bits select number program wait states when area external space accessed while AST1 ASTCR
Description Program wait inserted when external space area accessed program wait state inserted when external space area accessed program wait states inserted when external space area accessed program wait states inserted when external space area accessed (Initial value)
Bits 0-Area Wait Control (W01, W00): These bits select number program wait states when area external space accessed while AST0 ASTCR
Description Program wait inserted when external space area accessed program wait state inserted when external space area accessed program wait states inserted when external space area accessed program wait states inserted when external space area accessed (Initial value)
4.2.4
Control Register (BCRH)
ICIS1 ICIS0
BRSTRM BRSTS1 BRSTS0
Initial value
BCRH 8-bit readable/writable register that selects enabling disabling idle cycle insertion, memory interface area BCRH initialized H'D0 reset, hardware standby mode. initialized software standby mode. 7-Idle Cycle Insert (ICIS1): Selects whether idle cycle state inserted between cycles when successive external read cycles performed different areas.
ICIS1 Description Idle cycle inserted case successive external read cycles different areas. Idle cycle inserted case successive external read cycles different areas. (Initial value)
6-Idle Cycle Insert (ICIS0): Selects whether idle cycle state inserted between cycles when successive external read external write cycles performed
ICIS0 Description Idle cycle inserted case successive external read external write cycles. Idle cycle inserted case successive external read external write cycles. (Initial value)
5-Burst Enable (BRSTRM): Selects whether area used burst interface area.
BRSTRM Description Area basic interface area Area burst interface area (Initial value)
4-Burst Cycle Select (BRSTS1): Selects number burst cycles burst interface.
BRSTS1 Description Burst cycle comprises state Burst cycle comprises states (Initial value)
3-Burst Cycle Select (BRSTS0): Selects number words that accessed burst access burst interface.
BRSTS0 Description Max. words burst access Max. words burst access (Initial value)
Bits 0-Reserved: Only should written these bits. 4.2.5
Control Register (BCRL)
BRLE BREQOE WAITE
Initial value
BCRL 8-bit readable/writable register that performs selection external bus-released state protocol, selection area partition unit, enabling disabling WAIT input. BCRL initialized H'3C reset, hardware standby mode. initialized software standby mode. 7-Bus Release Enable (BRLE): Enables disables external release.
BRLE Description External release disabled. BREQ, BACK, BREQO pins used ports (Initial value) External release enabled
6-BREQO Enable (BREQOE): Outputs signal that requests external master drop request signal (BREQ) external bus-released state when internal master performs external space access.
BREQOE Description BREQO output disabled. BREQO used port BREQO output enabled (Initial value)
5-External Address Enable (EAE): Designates addresses H'010000 H'03FFFF* either internal external addresses. Note: H'010000 H'05FFFF H8S/2315. H'010000 H'07FFFF H8S/2319.
Description H8S/2319, H8S/2318, H8S/2315 H8S/2317 On-chip Addresses H'010000 H'01FFFF on-chip addresses H'020000 H'03FFFF reserved area* H8S/2316, H8S/2313, H8S/2311 Reserved area*
Addresses H'010000 H'03FFFF* external addresses external expanded mode reserved area* single-chip mode
Notes: access reserved area. H'010000 H'05FFFF H8S/2315. H'010000 H'07FFFF H8S/2319.
Bits 2-Reserved: Only should written these bits. 1-Reserved: Only should written this bit. 0-WAIT Enable (WAITE): Selects enabling disabling wait input WAIT pin.
WAITE Description Wait input WAIT disabled. WAIT used port Wait input WAIT enabled (Initial value)
4.3.1
Overview Control
Area Partitioning
advanced mode, controller partitions 16-Mbyte address space into eight areas, 2-Mbyte units, performs control external space area units. Figure shows outline memory map. Chip select signals (CS0 CS7) output each area.
H'000000 Area Mbytes) H'1FFFFF H'200000 Area Mbytes) H'3FFFFF H'400000 Area Mbytes) H'5FFFFF H'600000 Area Mbytes) H'7FFFFF H'800000 Area Mbytes) H'9FFFFF H'A00000 Area Mbytes) H'BFFFFF H'C00000 Area Mbytes) H'DFFFFF H'E00000 Area Mbytes) H'FFFFFF Advanced mode
Figure Area Partitioning
4.3.2
Specifications
external space specifications consist three elements: width, number access states, number program wait states. width number access states on-chip memory internal registers fixed, affected controller. Width: width bits selected with ABWCR. area which 8-bit selected functions 8-bit access space, area which 16-bit selected functions a16-bit access space. areas designated 8-bit access, 8-bit mode set; area designated 16-bit access, 16-bit mode always set. When burst interface selected, 16-bit mode always set. Number Access States: three access states selected with ASTCR. area which 2-state access selected functions 2-state access space, area which 3-state access selected functions 3-state access space. With burst interface, number access states determined without regard ASTCR. When 2-state access space designated, wait insertion disabled. Number Program Wait States: When 3-state access space designated ASTCR, number program wait states inserted automatically selected with WCRH WCRL. From program wait states selected. Table shows specifications each basic interface area.
Table
ABWCR ABWn
Specifications Each Area (Basic Interface)
ASTCR ASTn WCRH, WCRL Specifications (Basic Interface) Width Access States Program Wait States
4.3.3
Memory Interfaces
memory interfaces H8S/2319 H8S/2318 Series comprise basic interface that allows direct connection ROM, SRAM, burst interface that allows direct connection burst ROM(only area area which basic interface designated functions normal space, area which burst interface designated functions burst space. 4.3.4 Advanced Mode
initial state each area basic interface, 3-state access space. initial width selected according operating mode. specifications described here cover basic items only, sections each memory interface (4.4 4.5) should referred further details. Area Area includes on-chip ROM, expanded mode with on-chip disabled, area external space. expanded mode with on-chip enabled, space excluding onchip external space. When area external space accessed, signal output. Either basic interface burst interface selected area Areas external expanded mode, area area external space.
When area external space accessed, signals output, respectively. Only basic interface used areas Area Area includes on-chip internal/O registers. external expanded mode, space excluding on-chip internal/O registers external space. on-chip enabled when RAME system control register (SYSCR) when RAME cleared on-chip disabled corresponding space becomes external space When area external space accessed, signal output. Only basic interface used area memory interface. 4.3.5 Chip Select Signals
chip output chip select signals (CS0 CS7) areas signal being driven when corresponding external space area accessed. Figure shows example output timing. Enabling disabling signal output performed setting data direction register (DDR) port corresponding particular pin. expanded mode with on-chip disabled, placed output state after reset. Pins placed input state after reset, corresponding bits should when outputting signals CS7. expanded mode with on-chip enabled, pins placed input state after reset, corresponding bits should when outputting signals CS7. details, section Ports.
cycle Address
Area external address
Figure Signal Output Timing
4.4.1
Basic Interface
Overview
basic interface enables direct connection ROM, SRAM, specifications selected with ABWCR, ASTCR, WCRH, WCRL. details, section 4.4, Basic Interface, Hardware Manual. 4.4.2 Wait Control
When accessing external space chip extend cycle inserting more wait states (Tw). There ways inserting wait states: program wait insertion wait insertion using WAIT pin. Program Wait Insertion: From wait states inserted automatically between state state individual area basis 3-state access space, according settings WCRH WCRL. Wait Insertion: Setting WAITE BCRL enables wait input means WAIT pin. When external space accessed this state, program wait first inserted accordance with settings WCRH WCRL. WAIT falling edge last state, another state inserted. WAIT held low, states inserted goes high. This useful when inserting four more states, when changing number states different external devices. WAITE setting applies areas. Figure shows example wait state insertion timing.
program wait
WAIT
WAIT Address
Read Data Read data
HWR, Write Data Write data
Note: Downward arrows indicates timing WAIT sampling.
Figure Example Wait State Insertion Timing settings after reset are: 3-state access, program wait state insertion, WAIT input disabled.
4.5.1
Burst Interface
Overview
With H8S/2319 H8S/2318 Series, external space area designated burst space, burst interfacing performed. burst space interface enables 16-bit with burst access capability accessed high speed. Area designated burst space means BRSTRM BCRH. Consecutive burst accesses maximum words words performed instruction fetches only. states selected burst access. 4.5.2 Basic Timing
number states initial cycle (full access) burst interface determined setting AST0 ASTCR. When AST0 wait state insertion also possible. states selected burst cycle, according setting BRSTS1 BCRH. Wait states cannot inserted. When area designated burst space, functions 16-bit access space regardless setting ABW0 ABWCR. When BRSTS0 BCRH cleared burst access words performed; when BRSTS0 burst access words performed. basic access timing burst space shown figures (b). timing shown figure case where AST0 BRSTS1 bits both that figure case where both these bits cleared
Full access
Burst access
Address
Only lower address changed
Data
Read data
Read data
Read data
Figure Example Burst Access Timing (When AST0 BRSTS1=
Full access
Burst access
Address
Only lower address changed
Data
Read data
Read data Read data
Figure Example Burst Access Timing (When AST0 BRSTS1 4.5.3 Wait Control
with basic interface, either program wait insertion wait insertion using WAIT used initial cycle (full access) burst interface. section 4.4.2, Wait Control. Wait states cannot inserted burst cycle.
4.6.1
Idle Cycle
Operation
When H8S/2319 H8S/2318 Series chip accesses external space, insert 1-state idle cycle (TI) between cycles following cases: when read accesses different areas occur consecutively, when write cycle occurs immediately after read cycle. inserting idle cycle possible, example, avoid data collisions between ROM, etc., with long output floating time, high-speed memory, interfaces, Consecutive Reads Different Areas: consecutive reads different areas occur while ICIS1 BCRH idle cycle inserted start second read cycle. This enabled advanced mode. Figure shows example operation this case. this example, cycle read cycle with long output floating time, cycle read cycle SRAM, each being located different area. (a), idle cycle inserted, collision occurs cycle between read data from that from SRAM. (b), idle cycle inserted, data collision prevented.
cycle Address (area (area Data
cycle
cycle Address
(area
cycle
Idle cycle inserted (ICIS1
(area Data Data collision Idle cycle inserted (ICIS1 (initial value))
Long output floating time
Figure Example Idle Cycle Operation
Write after Read: external write occurs after external read while ICIS0 BCRH idle cycle inserted start write cycle. Figure shows example operation this case. this example, cycle read cycle with long output floating time, cycle write cycle. (a), idle cycle inserted, collision occurs cycle between read data from write data. (b), idle cycle inserted, data collision prevented.
cycle
Address (area (area Data
cycle
Address (area (area
cycle
cycle
Long output floating time Idle cycle inserted (ICIS0
Data Data collision Idle cycle inserted (ICIS0 (initial value))
Figure Example Idle Cycle Operation
Relationship between Chip Select (CS) Signal Read (RD) Signal: Depending system's load conditions, signal behind signal. example shown figure 4.8. this case, with setting idle cycle insertion (a), there period overlap between cycle signal cycle signal. Setting idle cycle insertion, (b), however, will prevent overlap between signals. initial state after reset release, idle cycle insertion set.
cycle
Address (area (area
cycle
Address (area (area
cycle
cycle
Possibility overlap between (area Idle cycle inserted (ICIS1 Idle cycle inserted (ICIS1 (initial value))
Figure Relationship between Chip Select (CS) Read (RD)
4.6.2
States Idle Cycle
Table shows states idle cycle. Table
Pins
States Idle Cycle
State Contents following cycle High impedance High High High High High
4.7.1
Release
Overview
H8S/2319 H8S/2318 Series release external response request from external device. external bus-released state, internal master continues operate long there external access. internal master wants make external access external bus-released state, issue request off-chip request dropped. 4.7.2 Operation
external expanded mode, released external device setting BRLE BCRL Driving BREQ issues external request H8S/2319 H8S/2318 Series chip. When BREQ sampled, prescribed timing BACK driven low, address bus, data bus, control signals placed highimpedance state, establishing external bus-released state. external bus-released state, internal master perform accesses using internal bus. When internal master wants make external access, temporarily defers activation cycle, waits request from external master dropped.
BREQOE BCRL when internal master wants make external access external bus-released state, BREQO driven request made off-chip drop request. When BREQ goes high, BACK driven high prescribed timing external bus-released state terminated. external release request external access occur simultaneously, order priority follows: (High) External release Internal master external access (Low) 4.7.3 States External-Bus-Released State
Table shows states external-bus-released state. Table
Pins
States Bus-Released State
State High impedance High impedance High impedance High impedance High impedance High impedance High impedance
4.7.4
Transition Timing
Figure shows timing transition bus-released state.
cycle High impedance External-bus-released state cycle
Address Data
Address
High impedance
High impedance
HWR, BREQ
High impedance
High impedance
BACK
BREQO*
Minimum state
level BREQ sampled fall state. BACK driven read cycle, releasing external master. BREQ state still sampled external-bus-released state. High level BREQ sampled. BACK driven high, ending release cycle. BREQO signal goes high clocks after rise BACK signal.
Note: Output only when BREQOE
Figure Bus-Released State Transition Timing
4.7.5
Usage Note
MSTPCR H'FFFF H'EFFF transition made sleep mode, external release function will halt. Therefore, these settings should used.
4.8.1
Arbitration
Overview
H8S/2319 H8S/2318 Series have arbiter that arbitrates master operations. There masters, which perform read/write operations when they have possession bus. Each master requests means request signal. arbiter determines priorities prescribed timing, permits means request acknowledge signal. selected master then takes possession begins operation. 4.8.2 Operation
arbiter monitors masters' request signals, requested, sends request acknowledge signal master making request. there requests from more than master, request acknowledge signal sent with highest priority. When master receives request acknowledge signal, takes possession until that signal canceled. order priority masters follows: (High) (Low) external access internal master external release executed parallel. external release request external access internal master occur simultaneously, order priority follows: (High) External release Internal master external access (Low) 4.8.3 Transfer Timing
Even request received from master with higher priority than that master that acquired currently operating, necessarily transferred immediately. There specific times which each master relinquish bus.
CPU: lowest-priority master, request received from DTC, arbiter transfers master that issued request. timing transfer follows: transferred break between cycles. However, cycle executed discrete operations, case longword-size access, transferred between component operations. details times when transferred, appendix A.5, States During Instruction Execution, Hardware Manual. sleep mode, transfers immediately. DTC: sends arbiter request when activation request generated. release after vector read, register information read states), single data transfer, register information write states). does release during register information read states), single data transfer, register information write states). 4.8.4 Note External Release
External release performed completion external cycle. signal remain until external cycle. Therefore, when external release performed, signals change from level high-impedance state.
Controller Operation Reset
reset, chip, including controller, enters reset state immediately, executing cycle aborted.
Section Ports
Overview
H8S/2319 H8S/2318 Series have ports (ports inputonly port (port Table summarizes port functions. pins each port also have other functions. Each port includes data direction register (DDR) that controls input/output (not provided input-only ports), data register (DR) that stores output data, port register (PORT) used read states. Ports have built-in pull-up function, addition DDR, have input pull-up control register (PCR) control on/off state input pull-up. Port port include open drain control register (ODR) that controls on/off state output buffer PMOS. Ports drive single load capacitive load, ports drive single load capacitive load. Ports ports (only when used inputs), ports (only when used inputs), ports (only when used inputs) schmitt-triggered inputs.
Table
Port
Port Functions
Pins P17/TIOCB2/TCLKD P16/TIOCA2 P15/TIOCB1/TCLKC P14/TIOCA1 Mode Mode Mode Mode
Description
Port 8-bit port Schmitttriggered input
8-bit port also functioning pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, TIOCB2)
P13/TIOCD0/TCLKB/A23 When input port also functioning P12/TIOCC0/TCLKA/A22 pins (TCLKA, TCLKB, P11/TIOCB0/A21 TIOCA0, TIOCB0, TIOCC0, TIOCD0) P10/TIOCA0/A20 When A23E A20E Address output When A23E A20E value output Port 8-bit port Schmitttriggered input P27/TIOCB5/TMO1 P26/TIOCA5/TMO0 P25/TIOCB4/TMCI1 P24/TIOCA4/TMRI1 P23/TIOCD3/TMCI0 P22/TIOCC3/TMRI0 P21/TIOCB3 P20/TIOCA3 P35/SCK1/IRQ5 P34/SCK0/IRQ4 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0 8-bit port also functioning pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, TIOCB5), 8-bit timer (channels pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, TMO1)
Port 6-bit port Open-drain output capability Schmitttriggered input (IRQ5, IRQ4)
6-bit port also functioning (channels pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1) interrupt input pins (IRQ5, IRQ4)
Port
Description
Pins P47/AN7/DA1 P46/AN6/DA0 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0
Mode
Mode
Mode
Mode
Port 8-bit input port
8-bit input port also functioning converter analog inputs (AN7 AN0) converter analog outputs (DA1 DA0)
Port 4-bit port PA3/A19 PA0/A16 Built-in input pull-up Open-drain output capability
Address output
When ports (after reset): input ports When address output
Port 8-bit port Built-in input pull-up
PB7/A15 PB0/A8
Address output
When port (after reset): input port When address output
Port 8-bit port Built-in input pull-up
PC7/A7 PC0/A0
Address output
When port (after reset): input port When address output
Port 8-bit port Built-in input pull-up
PD7/D15 PD0/D8
Data input/output
port
Port
Description
Pins PE7/D7 PE0/D0
Mode
Mode
Mode
Mode port
Port 8-bit port Built-in input pull-up
8-bit mode: port 16-bit mode: data input/output
Port 8-bit port Schmitttriggered input (IRQ3 IRQ0)
When input port When (after reset): output
When (after reset): input port When output
PF6/AS
When ASOD port When ASOD output
port
PF5/RD PF4/HWR PF3/LWR/IRQ3
output 8-bit mode: When LWROD port also port functioning interrupt 16-bit mode: output also input pins functioning interrupt input (IRQ3) (IRQ3 IRQ0)
PF2/WAIT /IRQ2/BREQO When WAITE BRLE BREQOE (after reset): port also functioning interrupt input (IRQ2) When WAITE WAIT input also functioning interrupt input (IRQ2) When WAITE BRLE BREQOE BREQO output also functioning interrupt input (IRQ2) PF1/BACK /IRQ1/CS5 PF0/BREQ/IRQ0/CS4 When BRLE (after reset): port also functioning interrupt input pins (IRQ1, IRQ0) When CS25E PF1CS5S Also functions output When CS25E PF0CS4S Also functions output When BRLE BREQ input, BACK output also functioning interrupt input pins (IRQ1, IRQ0)
Port
Description PG4/CS0
Pins
Mode
Mode
Mode
Mode port also functions interrupt input pins (IRQ7, IRQ6) converter input (ADTRG)
Port 5-bit port Schmitttriggered input (IRQ7, IRQ6)
When 0*2: input port When 1*3: output
PG3/CS1/CS7
port When CS167E CSS17 Also functions output When CS167E CSS17 Also functions output
PG2/CS2
port When CS25E Also functions output
PG1/CS3/ IRQ7/CS6
port When CS25E CSS36 Also functions output When CSS36 CS167E Also functions output interrupt input (IRQ7)
PG0/IRQ6/ ADTRG
port also functioning interrupt input (IRQ6) converter input (ADTRG)
Notes: Modes available ROMless version. After reset mode After reset mode
5.2.1
Port
Overview
Port 8-bit port. Port pins also function pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, TIOCB2) address output function. Port functions change according operating mode. address output port output function selected according settings bits A23E A20E PFCR1. Port pins have Schmitt-trigger inputs. Figure shows port configuration.
Port pins (I/O)/TIOCB2 (I/O)/TCLKD (input) (I/O)/TIOCA2 (I/O) (I/O)/TIOCB1 (I/O)/TCLKC (input) Port (I/O)/TIOCA1 (I/O) (I/O)/TIOCD0 (I/O)/TCLKB (input)/A23 (output) (I/O)/TIOCC0 (I/O)/TCLKA (input)/A22 (output) (I/O)/TIOCB0 (I/O)/A21 (output) (I/O)/TIOCA0 (I/O)/A20 (output) functions modes (I/O)/TIOCB2 (I/O)/TCLKD (input) (I/O)/TIOCA2 (I/O) (I/O)/TIOCB1 (I/O)/TCLKC (input) (I/O)/TIOCA1 (I/O) (I/O)/TIOCD0 (I/O)/TCLKB (input)/A23 (output) (I/O)/TIOCC0 (I/O)/TCLKA (input)/A22 (output) (I/O)/TIOCB0 (I/O)/A21 (output) (I/O)/TIOCA0 (I/O)/A20 (output) functions mode (I/O)/TIOCB2 (I/O)/TCLKD (input) (I/O)/TIOCA2 (I/O) (I/O)/TIOCB1 (I/O)/TCLKC (input) (I/O)/TIOCA1 (I/O) (I/O)/TIOCD0 (I/O)/TCLKB (input) (I/O)/TIOCC0 (I/O)/TCLKA (input) (I/O)/TIOCB0 (I/O) (I/O)/TIOCA0 (I/O)
Note: Modes available ROMless version.
Figure Port Functions
5.2.2
Register Configuration
Table shows port register configuration. Table
Name Port data direction register Port data register Port register Port function control register
Port Registers
Abbreviation P1DDR P1DR PORT1 PFCR1 Initial Value H'00 H'00 Undefined H'0F Address* H'FEB0 H'FF60 H'FF50 H'FF45
Note: Lower bits address.
Port Data Direction Register (P1DDR)
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value
P1DDR 8-bit write-only register, individual bits which specify input output pins port P1DDR cannot read; undefined value will read. Setting P1DDR makes corresponding port output pin, while clearing makes input pin. P1DDR initialized H'00 reset, hardware standby mode. retains prior state after software standby mode. Whether address output pins maintain their output state high-impedance state transition software standby mode selected SBYCR. Port Data Register (P1DR)
P17DR Initial value P16DR P15DR P14DR P13DR P12DR P11DR P10DR
P1DR 8-bit readable/writable register that stores output data port pins (P17 P10).
P1DR initialized H'00 reset, hardware standby mode. retains prior state after software standby mode. Port Register (PORT1)
Initial value
Note: Determined state pins P10.
PORT1 8-bit read-only register that shows states. cannot written Writing output data port pins (P17 P10) must always performed P1DR. port read performed while P1DDR bits P1DR values read. port read performed while P1DDR bits cleared states read. After reset hardware standby mode, PORT1 contents determined states, P1DDR P1DR initialized. PORT1 retains prior state after software standby mode. Port Function Control Register (PFCR1)
CSS17 Initial value A23E A22E A21E A20E
CSS36 PF1CS5S PF0CS4S
PFCR1 8-bit readable/writable register that performs port control. PFCR1 initialized H'0F reset, hardware standby mode. 7-CS17 Select (CSS17): Selects whether output from pin. details section 5.12 port 6-CS36 Select (CSS36): Selects whether output from pin. details, section 5.12 port 5-Port Chip Select Select (PF1CS5S): Selects enabling disabling output. details, section 5.11 port 4-Port Chip Select Select (PF0CS4S): Selects enabling disabling output. details, section 5.11 port
3-Address Enable (A23E): Enables disables address output (A23). This valid modes
A23E Description P13DR output when P13DDR output when P13DDR (Initial value)
2-Address Enable (A22E): Enables disables address output (A22). This valid modes
A22E Description P12DR output when P12DDR output when P12DDR (Initial value)
1-Address Enable (A21E): Enables disables address output (A21). This valid modes
A21E Description P11DR output when P11DDR output when P11DDR (Initial value)
0-Address Enable (A20E): Enables disables address output (A20). This valid modes
A20E Description P10DR output when P10DDR output when P10DDR (Initial value)
5.2.3
Functions
Port pins also function pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, TIOCB2) address output pins (A23 A20). Port functions shown table 5.3.
Table
P17/TIOCB2/ TCLKD
Port Functions
Selection Method Functions function switched shown below according combination channel setting bits TMDR2, bits IOB3 IOB0 TIOR2, bits CCLR1 CCLR0 TCR2, bits TPSC2 TPSC0 TCR0 TCR5, P17DDR. Channel Setting P17DDR function Table Below TIOCB2 output Table Below input TCLKD input Channel Setting IOB3 IOB0
output
TIOCB2 input
B'0000 B'0100 B'1xxx
B'0001 B'0011 B'0101 B'0111 Output compare output
B'0010
B'xx00
B'0011
B'0000, B'01xx
Other than B'xx00
CCLR1, CCLR0 Output function
Other than B'10 mode output
B'10
Don't care Notes: TIOCB2 input when B'0000 B'01xx IOB3 TCLKD input when setting either TCR0 TCR5 TPSC2 TPSC0 B'111. TCLKD input when channels phase counting mode (MD3 B'01xx).
P16/TIOCA2
Selection Method Functions function switched shown below according combination channel setting bits TMDR2, bits IOA3 IOA0 TIOR2, bits CCLR1 CCLR0 TCR2, P16DDR. Channel Setting P16DDR function Table Below TIOCA2 output Table Below input output
TIOCA2 input
Channel Setting IOA3 IOA0
B'0000 B'0100 B'1xxx
B'001x
B'0011
B'0011
B'0000, B'01xx
B'0001 B'xx00 B'0011 B'0101 B'0111 Output compare output
Other than B'xx00
CCLR1, CCLR0 Output function
Other than B'01 mode output
B'01
mode output
Don't care Notes: TIOCA2 input when B'0000 B'01xx IOA3 TIOCB2 output disabled.
P15/TIOCB1/ TCLKC
Selection Method Functions function switched shown below according combination channel setting bits TMDR1, bits IOB3 IOB0 TIOR1, bits CCLR1 CCLR0 TCR1, bits TPSC2 TPSC0 TCR0, TCR2, TCR4, TCR5, P15DDR. Channel Setting P15DDR function Table Below TIOCB1 output Table Below input output
TIOCB1 input TCLKC input
Channel Setting IOB3 IOB0
B'0000 B'0100 B'1xxx
B'0001 B'0011 B'0101 B'0111
B'0010
B'xx00
B'0011
B'0000, B'01xx<
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