This reference programmers includes table showing addresses memory-map

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This reference programmers includes table showing addresses memory-map

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Appendix Programming Reference
This reference programmers includes table showing addresses memory-mapped peripherals, exception priority table, programming sheets major programmable registers. programming sheets grouped following order: central processor, Phase Lock Loop, (PLL), Host Interface (HI08), Enhanced Synchronous Serial Interface (ESSI), Serial Communication Interface (SCI), Timer, GPIO, EFCOP. Each sheet provides room write value each hexadecimal value each register. photocopy these sheets reuse them each application development project. details instruction DSP56300 family DSPs, DSP56300 Family Manual.
Table B-2, "Internal Memory Map," page Table B-3, "Internal Memory Map," page list memory addresses on-chip peripherals. Table B-4, "Interrupt Sources," page lists interrupt starting addresses sources. Table B-5, "Interrupt Source Priorities Within IPL," page B-10 lists priorities specific interrupts within interrupt priority levels. programming sheets appear this manual figures (listed Table B-1); they show major programmable registers DSP56311.
Table B-1. Guide Programming Sheet
Module Central Processor
Programming Sheet Figure B-1, "Status Register (SR)" Figure B-2, "Operating Mode Register" Figure B-3, "Address Attribute Registers (AAR3 AAR0)" Figure B-4, "Bus Control Register (BCR)" Figure B-5, "DMA Control Register (DCR)" Figure B-6, "Interrupt Priority Register-Core (IPR-C)" Figure B-7, "Interrupt Priority Register Peripherals (IPR-P)"
Page page B-12 page B-13 page B-14 page B-15 page B-16 page B-17 page B-18 page B-19
Figure B-8, "Phase Lock Loop Control Register (PCTL)"
Motorola
Programming Reference
Internal Memory
Table B-1. Guide Programming SheetHI08 Figure B-9, "Host Receive Host Transmit Data Registers" Figure B-10, "Host Control Host Status Registers" Figure B-11, "Host Base Address Host Port Control Registers" Figure B-12, "Interrupt Control Interrupt Status Registers" Figure B-13, "Interrupt Vector Command Vector Registers" Figure B-14, "Host Receive Host Transmit Data Registers" ESSI Figure B-15, "ESSI Control Register (CRA)" Figure B-16, "ESSI Control Register (CRB)" Figure B-17, "ESSI Status Register (SSISR)" Figure B-18, "ESSR Transmit Receive Slot Mask Registers (TSM, RSM)" Figure B-19, "SCI Control Register (SCR)" Figure B-20, "SCI Status Clock Control Registers (SSR, SCCR)" Figure B-21, "SCI Receive Transmit Data Registers (SRX, TRX)" Timers Figure B-22, "Timer Prescaler Load/Count Register (TPLR, TPCR)" Figure B-23, "Timer Control/Status Register (TCSR)" Figure B-24, "Timer Load, Compare, Count Registers (TLR, TCPR, TCR)" GPIO Figure B-25, "Host Data Direction Host Data Registers (HDDR, HDR)" Figure B-26, "Port Registers (PCRC, PRRC, PDRC)" Figure B-27, "Port Registers (PCRD, PRRD, PDRD)" Figure B-28, "Port Registers (PCRE, PRRE, PDRE)" EFCOP Figure B-29, "EFCOP Counter Control Status Registers (FCNT FCSR)" Figure B-30, "EFCOP FACR, FDBA, FCBA, FDCH Registers" page B-20 page B-21 page B-22 page B-23 page B-24 page B-25 page B-26 page B-27 page B-28 page B-29 page B-30 page B-31 page B-32 page B-33 page B-34 page B-35 page B-36 page B-37 page B-38 page B-39 page B-40 page B-41
Internal Memory
Table B-2. Internal Memory
Peripheral 16-Bit Address $FFFF $FFFE OnCE $FFFD $FFFC 24-Bit Address $FFFFFF $FFFFFE $FFFFFD $FFFFFC Register Name Interrupt Priority Register Core (IPR-C) Interrupt Priority Register Peripheral (IPR-P) Control Register (PCTL) OnCE Register (OGDB)
DSP56311 User's Manual
Motorola
Internal Memory
Table B-2. Internal Memory (Continued)
Peripheral 16-Bit Address $FFFB $FFFA $FFF9 $FFF8 $FFF7 $FFF6 $FFF5 $FFF4 $FFF3 $FFF2 $FFF1 $FFF0 DMA0 $FFEF $FFEE $FFED $FFEC DMA1 $FFEB $FFEA $FFE9 $FFE8 DMA2 $FFE7 $FFE6 $FFE5 $FFE4 DMA3 $FFE3 $FFE2 $FFE1 $FFE0 24-Bit Address $FFFFFB $FFFFFA $FFFFF9 $FFFFF8 $FFFFF7 $FFFFF6 $FFFFF5 $FFFFF4 $FFFFF3 $FFFFF2 $FFFFF1 $FFFFF0 $FFFFEF $FFFFEE $FFFFED $FFFFEC $FFFFEB $FFFFEA $FFFFE9 $FFFFE8 $FFFFE7 $FFFFE6 $FFFFE5 $FFFFE4 $FFFFE3 $FFFFE2 $FFFFE1 $FFFFE0 Register Name Control Register (BCR) DRAM Control Register (DCR) Address Attribute Register (AAR0) Address Attribute Register (AAR1) Address Attribute Register (AAR2) Address Attribute Register (AAR3) Register (IDR) Status Register (DSTR) Offset Register (DOR0) Offset Register (DOR1) Offset Register (DOR2) Offset Register (DOR3) Source Address Register (DSR0) Destination Address Register (DDR0) Counter (DCO0) Control Register (DCR0) Source Address Register (DSR1) Destination Address Register (DDR1) Counter (DCO1) Control Register (DCR1) Source Address Register (DSR2) Destination Address Register (DDR2) Counter (DCO2) Control Register (DCR2) Source Address Register (DSR3) Destination Address Register (DDR3) Counter (DCO3) Control Register (DCR3)
Motorola
Programming Reference
Internal Memory
Table B-2. Internal Memory (Continued)
Peripheral DMA4 16-Bit Address $FFDF $FFDE $FFDD $FFDC DMA5 $FFDB $FFDA $FFD9 $FFD8 $FFD7 $FFD6 $FFD5 $FFD4 $FFD3 $FFD2 $FFD1 $FFD0 $FFCF $FFCE $FFCD $FFCC $FFCB $FFCA Port $FFC9 $FFC8 HI08 $FFC7 $FFC6 $FFC5 $FFC4 $FFC3 $FFC2 24-Bit Address $FFFFDF $FFFFDE $FFFFDD $FFFFDC $FFFFDB $FFFFDA $FFFFD9 $FFFFD8 $FFFFD7 $FFFFD6 $FFFFD5 $FFFFD4 $FFFFD3 $FFFFD2 $FFFFD1 $FFFFD0 $FFFFCF $FFFFCE $FFFFCD $FFFFCC $FFFFCB $FFFFCA $FFFFC9 $FFFFC8 $FFFFC7 $FFFFC6 $FFFFC5 $FFFFC4 $FFFFC3 $FFFFC2 Register Name Source Address Register (DSR4) Destination Address Register (DDR4) Counter (DCO4) Control Register (DCR4) Source Address Register (DSR5) Destination Address Register (DDR5) Counter (DCO5) Control Register (DCR5) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Host Port GPIO Data Register (HDR) Host Port GPIO Direction Register (HDDR) Host Transmit Register (HTX) Host Receive Register (HRX) Host Base Address Register (HBAR) Host Port Control Register (HPCR) Host Status Register (HSR) Host Control Register (HCR)
DSP56311 User's Manual
Motorola
Internal Memory
Table B-2. Internal Memory (Continued)
Peripheral 16-Bit Address $FFC1 $FFC0 Port $FFBF $FFBE $FFBD ESSI $FFBC $FFBB $FFBA $FFB9 $FFB8 $FFB7 $FFB6 $FFB5 $FFB4 $FFB3 $FFB2 $FFB1 $FFB0 Port $FFAF $FFAE $FFAD 24-Bit Address $FFFFC1 $FFFFC0 $FFFFBF $FFFFBE $FFFFBD $FFFFBC $FFFFBB $FFFFBA $FFFFB9 $FFFFB8 $FFFFB7 $FFFFB6 $FFFFB5 $FFFFB4 $FFFFB3 $FFFFB2 $FFFFB1 $FFFFB0 $FFFFAF $FFFFAE $FFFFAD Reserved Reserved Port Control Register (PCRC) Port Direction Register (PRRC) Port GPIO Data Register (PDRC) ESSI Transmit Data Register (TX00) ESSI Transmit Data Register (TX01) ESSI Transmit Data Register (TX02) ESSI Time Slot Register (TSR0) ESSI Receive Data Register (RX0) ESSI Status Register (SSISR0) ESSI Control Register (CRB0) ESSI Control Register (CRA0) ESSI Transmit Slot Mask Register (TSMA0) ESSI Transmit Slot Mask Register (TSMB0) ESSI Receive Slot Mask Register (RSMA0) ESSI Receive Slot Mask Register (RSMB0) Reserved Port Control Register (PCRD) Port Direction Register (PRRD) Port GPIO Data Register (PDRD) Register Name
Motorola
Programming Reference
Internal Memory
Table B-2. Internal Memory (Continued)
Peripheral ESSI 16-Bit Address $FFAC $FFAB $FFAA $FFA9 $FFA8 $FFA7 $FFA6 $FFA5 $FFA4 $FFA3 $FFA2 $FFA1 $FFA0 Port $FF9F $FF9E $FF9D $FF9C $FF9B $FF9A $FF99 $FF98 $FF97 $FF96 $FF95 $FF94 $FF93 $FF92 $FF91 $FF90 24-Bit Address $FFFFAC $FFFFAB $FFFFAA $FFFFA9 $FFFFA8 $FFFFA7 $FFFFA6 $FFFFA5 $FFFFA4 $FFFFA3 $FFFFA2 $FFFFA1 $FFFFA0 $FFFF9F $FFFF9E $FFFF9D $FFFF9C $FFFF9B $FFFF9A $FFFF99 $FFFF98 $FFFF97 $FFFF96 $FFFF95 $FFFF94 $FFFF93 $FFFF92 $FFFF91 $FFFF90 Register Name ESSI Transmit Data Register (TX10) ESSI Transmit Data Register (TX11) ESSI Transmit Data Register (TX12) ESSI Time Slot Register (TSR1) ESSI Receive Data Register (RX1) ESSI Status Register (SSISR1) ESSI Control Register (CRB1) ESSI Control Register (CRA1) ESSI Transmit Slot Mask Register (TSMA1) ESSI Transmit Slot Mask Register (TSMB1) ESSI Receive Slot Mask Register (RSMA1) ESSI Receive Slot Mask Register (RSMB1) Reserved Port Control Register (PCRE) Port Direction Register (PRRE) Port GPIO Data Register (PDRE) Control Register (SCR) Clock Control Register (SCCR) Receive Data Register High (SRXH) Receive Data Register Middle (SRXM) Recieve Data Register (SRXL) Transmit Data Register High (STXH) Transmit Data Register Middle (STXM) Transmit Data Register (STXL) Transmit Address Register (STXA) Status Register (SSR) Reserved Reserved Reserved
DSP56311 User's Manual
Motorola
Internal Memory
Table B-2. Internal Memory (Continued)
Peripheral Triple Timer 16-Bit Address $FF8F $FF8E $FF8D $FF8C $FF8B $FF8A $FF89 $FF88 $FF87 $FF86 $FF85 $FF84 $FF83 $FF82 $FF81 $FF80 24-Bit Address $FFFF8F $FFFF8E $FFFF8D $FFFF8C $FFFF8B $FFFF8A $FFFF89 $FFFF88 $FFFF87 $FFFF86 $FFFF85 $FFFF84 $FFFF83 $FFFF82 $FFFF81 $FFFF80 Register Name Timer Control/Status Register (TCSR0) Timer Load Register (TLR0) Timer Compare Register (TCPR0) Timer Count Register (TCR0) Timer Control/Status Register (TCSR1) Timer Load Register (TLR1) Timer Compare Register (TCPR1) Timer Count Register (TCR1) Timer Control/Status Register (TCSR2) Timer Load Register (TLR2) Timer Compare Register (TCPR2) Timer Count Register (TCR2) Timer Prescaler Load Register (TPLR) Timer Prescaler Count Register (TPCR) Reserved Reserved
Table B-3. Internal Memory
Peripheral 16-Bit Address $FFBF $FFBE $FFBD $FFBC $FFBB $FFBA $FFB9 24-Bit Address $FFFFBF $FFFFBE $FFFFBD $FFFFBC $FFFFBB $FFFFBA $FFFFB9 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Name
Motorola
Programming Reference
Interrupt Sources Prioritie
Table B-3. Internal Memory
Peripheral Enhanced Filter Coprocessor (EFCOP) 16-Bit Address $FFB8 $FFB7 $FFB6 $FFB5 $FFB4 $FFB3 $FFB2 $FFB1 $FFB0 $FFAF- $FF80 24-Bit Address $FFFFB8 $FFFFB7 $FFFFB6 $FFFFB5 $FFFFB4 $FFFFB3 $FFFFB2 $FFFFB1 $FFFFB0 $FFFFAF- $FFFF80 Register Name EFCOP Decimation/Channel (FDCH) Register EFCOP Coefficient Base Address (FCBA) EFCOP Data Base Address (FDBA) EFCOP Control Register (FACR) EFCOP Control Status Register (FCSR) EFCOP Filter Count (FCNT) Register EFCOP K-Constant Register (FKIR) EFCOP Data Output Register (FDOR) EFCOP Data Input Register (FDIR) Reserved
Interrupt Sources PrioritieTable B-4. Interrupt SourceInterrupt Starting Address VBA:$00 VBA:$02 VBA:$04 VBA:$06 VBA:$08 VBA:$0A VBA:$0C VBA:$0E VBA:$10 VBA:$12 VBA:$14 VBA:$16 VBA:$18 VBA:$1A VBA:$1C Interrupt Priority Level Range Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Non-Maskable Interrupt (NMI) Reserved Reserved IRQA IRQB IRQC IRQD Channel Channel Channel Interrupt Source
DSP56311 User's Manual
Motorola
Interrupt Sources Prioritie
Table B-4. Interrupt Sources (Continued)
Interrupt Starting Address VBA:$1E VBA:$20 VBA:$22 VBA:$24 VBA:$26 VBA:$28 VBA:$2A VBA:$2C VBA:$2E VBA:$30 VBA:$32 VBA:$34 VBA:$36 VBA:$38 VBA:$3A VBA:$3C VBA:$3E VBA:$40 VBA:$42 VBA:$44 VBA:$46 VBA:$48 VBA:$4A VBA:$4C VBA:$4E VBA:$50 VBA:$52 VBA:$54 VBA:$56 VBA:$58 VBA:$5A VBA:$5C VBA:$5E Interrupt Priority Level Range Channel Channel Channel Timer Compare Timer Overflow Timer Compare Timer Overflow Timer Compare Timer Overflow ESSI0 Receive Data ESSI0 Receive Data With Exception Status ESSI0 Receive Last Slot ESSI0 Transmit Data ESSI0 Transmit Data With Exception Status ESSI0 Transmit Last Slot Reserved Reserved ESSI1 Receive Data ESSI1 Receive Data With Exception Status ESSI1 Receive Last Slot ESSI1 Transmit Data ESSI1 Transmit Data With Exception Status ESSI1 Transmit Last Slot Reserved Reserved Receive Data Receive Data With Exception Status Transmit Data Idle Line Timer Reserved Reserved Reserved Interrupt Source
Motorola
Programming Reference
Interrupt Sources Prioritie
Table B-4. Interrupt Sources (Continued)
Interrupt Starting Address VBA:$60 VBA:$62 VBA:$64 VBA:$66 VBA:$68 VBA:$6A VBA:$6C VBA:$6E VBA:$FE Interrupt Priority Level Range Host Receive Data Full Host Transmit Data Empty Host Command (Default) Reserved EFCOP Data Input Buffer Empty EFCOP Data Output Buffer Full Reserved Reserved Reserved Interrupt Source
Table B-5. Interrupt Source Priorities Within
Priority Interrupt Source Level (Nonmaskable) Highest Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Lowest Non-Maskable Interrupt Levels (Maskable) Highest IRQA (External Interrupt) IRQB (External Interrupt) IRQC (External Interrupt) IRQD (External Interrupt) Channel Interrupt Channel Interrupt Channel Interrupt Channel Interrupt Channel Interrupt
B-10
DSP56311 User's Manual
Motorola
Interrupt Sources Prioritie
Table B-5. Interrupt Source Priorities Within (Continued)
Priority Channel Interrupt Host Command Interrupt Host Transmit Data Empty Host Receive Data Full ESSI0 Data with Exception Interrupt ESSI0 Data Interrupt ESSI0 Receive Last Slot Interrupt ESSI0 Data With Exception Interrupt ESSI0 Transmit Last Slot Interrupt ESSI0 Data Interrupt ESSI1 Data With Exception Interrupt ESSI1 Data Interrupt ESSI1 Receive Last Slot Interrupt ESSI1 Data With Exception Interrupt ESSI1 Transmit Last Slot Interrupt ESSI1 Data Interrupt Receive Data With Exception Interrupt Lowest Highest Receive Data Transmit Data Idle Line Timer Timer0 Overflow Interrupt Timer0 Compare Interrupt Timer1 Overflow Interrupt Timer1 Compare Interrupt Timer2 Overflow Interrupt Timer2 Compare Interrupt EFCOP Data Input Buffer Empty Lowest EFCOP Data Output Buffer Full Interrupt Source
Motorola
Programming Reference
B-11
Programming Sheet
Programming Sheet
Central Processor
Unnormalized Acc(47) xnor Acc(46) Extension Limit Scaling Acc(46) Acc(45)
Scaling Mode S(1:0) Scaling Mode scaling Scale down Scale Reserved I(1:0) Interrupt Mask Exceptions Masked None
Carry Overflow Zero Negative
Reserved Sixteen-Bit Compatibilitity Double Precision Multiply Mode Loop Flag DO-Forever Flag Sixteenth-Bit Arithmetic Reserved Instruction Cache Enable Arithmetic Saturation Rounding Mode
Core Priority CP(1:0) Core Priority (lowest) (highest)
Extended Mode Register (MR)
Mode Register (MR)
Condition Code Register (CCR)
Status Register (SR) Read/Write Reset $C00300
Reserved, Program
Figure B-1. Status Register (SR)
B-12
DSP56311 User's Manual
Motorola
Programming Sheet
Central Processor
Asynchronous Arbitration Enable, Synchronization disabled Synchronization enabled
Chip Operating Mode, Bits Refer operating modes table Chapter External Disable, Enables external Disables external
Address Attribute Priority Disable, Priority mechanism enabled Priority mechanism disabled Stack Extension Select, Mapped memory Mapped memory Stack Extension Underflow Flag, stack underflow Stack underflow Stack Extension Overflow Flag, stack overflow Stack overflow Stack Extension Wrap Flag, stack extension wrap Stack extension wrap (sticky bit) Stack Extension Enable, Stack extension disabled Stack extension enabled Memory Switch Configuration, Bits MSW[1 Program Memory Memory: $4000 $BFFF Memory: $4000 $BFFF Memory: $6000 $BFFF Memory: $6000 $BFFF Memory: $8000 $BFFF Memory: $8000 $BFFF Memory: $A000 $BFFF Memory: $A000 $BFFF
Stop Delay Mode, Delay 128K clock cycles Delay clock cycless Memory Switch Mode, Memory switching disabled Memory switching enabled Core-DMA Priority, Bits CPD[1:0] Description Compare SR[CP] active channel priority higher priority than core same priority core lower priority than core Cache Burst Mode Enable, Burst Mode disabled Burst Mode enabled Synchronize Select, synchronized Synchronized Release Timing, Fast Release mode Slow Release mode
MSW1 MSW0
CPD1 CPD0
Operating Mode Register Reset $000300
Reserved, Program
Figure B-2. Operating Mode Register
Motorola
Programming Reference
B-13
Programming Sheet
Central Processor
Packing Enable, Disable internal packing/unpacking logic Enable internal packing/unpacking logic Data Memory Enable, Disable logic during external data space accesses Enable logic during external data space accesses Data Memory Enable, Disable logic during external data space accesses Enable logic during external data space accesses Program Memory Enable, Disable logic during external program space accesses Enable logic during external program space accesses Address Attribute Polarity, AA/RAS signal active AA/RAS signal active high Access Type, Bits (Combinations BNC[3 1111, 1110, 1101 reserved.) BAT[1 Encoding Reserved SRAM access DRAM access Reserved
Number Address Bits Compare, Bits BNC[3 number bits (from bits) that compared external addres
Address Compare, Bits BAC[11 address compare external address order decide whether assert
BPAC
BYEN BXENBPEN BAAP
Address Attribute Registers (AAR3 AAR0) Reset $000000
Reserved, Program
Figure B-3. Address Attribute Registers (AAR3 AAR0)
B-14
DSP56311 User's Manual
Motorola
Programming Sheet
Central Processor
NOTE: bits read/write control bits. State, master master Default Area Wait Control, Bits Area Wait Control, Bits Area Wait Control, Bits Area Wait Control, Bits Area Wait Control, Bits These read/write control bits define number wait states inserted into each external SRAM access designated area. value these bits should programmed zero. Number wait states: BDFW[20 BA3W[15 Lock Hold, asserted only attempted readwrite modify external access always asserted BA2W[12 BA1W[9 BA0W[4 Request Hold, asserted only attempted pending access always asserted
BDFWBDFW BDFWBDFWBDFWBA3W BA3W BA3WBA2W BA2W BA2W BA1WBA2WBA1W BA1WBA1W BA0W BA0W BA0WBA0W BA0W
Control Register (BCR) Reset $1FFFFF
Figure B-4. Control Register (BCR)
Motorola
Programming Reference
B-15
Programming Sheet
Central Processor
Request Source, Bits DRS[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 10111 11111 Requesting Device External( IRQA Pin) External (IRQB pin) External (IRQC pin) External (IRQD pin) Transfer done from channel Transfer done from channel Transfer done from channel Transfer done from channel Transfer done from channel Transfer done from channel ESSI Receive Data Reserved
Three-Dimensional Mode, Three-Dimensional mode disabled Three-Dimensional mode enabled Address Mode, Bits Non-Three-Dimensional Addressing Modes (D3D=0) DAM[2 source DAM[5 Destination Offset Register Selection DOR0 DOR1 DOR2 DOR3 None None
Continuous Mode Enable, Disables continuous mode Enables continuous mode Channel Priority, Bits DPR[1:0] Channel Priority Priority level (lowest) Priority level Priority level Priority level (highest)
DAM[5:3] Addressing Counter DAM[2:0] Mode Mode update PostincrementA by-1 reserved reserved
Three-Dimensional Addressing Modes (D3D= DAM[5:3] Addressing Mode update Postincrement-by1 Offset Selection DOR0 DOR1 DOR2 DOR3 None None DOR0: DOR1 DOR2: DOR3
Transfer Mode, Bits DTM[2:0] Triggered request request request request request reserved reserved Cleared Transfer Mode block transfer word transfer line transfer block transfer block transfer word transfer
Destination Space, Bits DSS[1:0] Destination Memory Memory Space Memory Space Memory Space Reserved
Interrupt Enable, Disables Interrupt Enables interrupt Channel Enable, Disables channel operation Enables channel operation
Source Space, Bits DSS[1:0] Source Memory Memory Space Memory Space Memory Space Reserved
DDDDPR DCON
Control Registers (DCR5 DCR0) Reset $000000
Figure B-5. Control Register (DCR)
B-16 DSP56311 User's Manual Motorola
Motorola
Central Processor
IRQA Mode
IAL2 XXL1 XXL0 Enabled IBL2 Trigger Level Neg. Edge IAL1 IAL0 Enabled ICL1 ICL0
Figure B-6. Interrupt Priority Register-Core (IPR-C)
IRQC Mode
ICL2 Trigger Level Neg. Edge
Programming Reference B-17
IRQB Mode
Trigger Level Neg. Edge
IRQD Mode
IDL2 Trigger Level Neg. Edge
IBL1 IDL1
IBL0 IDL0
Enabled
Interrupt Priority Register (IPR-C) X:$FFFFFF Read/Write Reset $000000
D5L1 D5L0 D4L1 D4L0 D3L1 D3L0 D2L1 D2L0 D1L1 D1L0 D0L1 D0L0 IDL2 IDL1
Programming Sheet
IDL0 ICL2 ICL1 ICL0 IBL2 IBL1 IBL0 IAL2 IAL1 IAL0
B-18
Programming Sheet
Central Processor
Figure B-7. Interrupt Priority Register Peripherals (IPR-P)
ESSI1
S1L1 S1L0 Enabled
Host
HPL1 HPL0 Enabled
SCL1 SCL0 Enabled
ESSI0
S0L1 S0L0 Enabled
DSP56311 User's Manual Motorola
Interrupt Priority Register (IPR-P) X:$FFFF Read/Write Reset $000000
**************
T0L1 T0L0 SCL1 SCL0 S1L1 S1L0 SOL1 S0L0 HPL1 HPL0
Reserved, Program
Motorola
PSTP Relationship Operation During STOP PSTP Oscillator Disabled Disabled Disabled Enabled Enabled Enabled
XTAL Disable (XTLD) Enable XTALOscillator EXTAL Driven From External Source
Figure B-8. Phase Lock Loop Control Register (PCTL)
Crystal Range (XTLR) External Xtal Freq> 200KHz External Xtal Freq 200KHz
Clock Output Disable (COD) Duty Cycle Clock Held High State
Predivision Factor Bits (PD0 PD3) Predivision Factor
Multiplication Factor Bits MF11 MF11 Multiplication Factor $000 $001 $002 $FFF 4095 $FFF 4096 Division Factor Bits (DF0 DF2) Division Factor
Programming Reference B-19
Programming Sheet
Control Register (PCTL) X:$FFFFFD Read/Write Reset $000000
PSTP XTLD XTLR
MF11 MF10
Programming Sheet
HOST
Host Receive Data (usually Read program)
Receive High Byte Receive Middle Byte
Receive Byte
Host Receive Data Register (HRX) X:$FFEC6 Read Only Reset empty Host Transmit Data (usually Loaded program)
Transmit High Byte Transmit Middle Byte
Transmit Byte
Host Transmit Data Register (HTX) X:$FFEC7 Write Only Reset empty
Figure B-9. Host Receive Host Transmit Data Register
B-20
DSP56311 User's Manual
Motorola
Programming Sheet
HOST
Host Receive Interrupt Enable Disable Enable HRDF Host Transmit Interrupt Enable Disable Enable HTDE Host Command Interrupt Enable Disable Enable Host Flag
Host Flag
Host Control Register (HCR) X:$FFFFC2 Read /Write Reset
HCIE HTIE HRIE
Side
Host Receive Data Full Wait Read Host Transmit Data Empty Wait Write Host Command Pending Wait Ready Host Flags Read Only
Host Staus Register (HSR) X:$FFFFC3 Read Only Reset
HTDE HRDF
Reserved, Program
Figure B-10. Host Control Host Status Register
Motorola
Programming Reference
B-21
Programming Sheet
HOST
Host Base Address Register (HBAR) X:$FFFFC5 Reset
BA10
Host Request Open Drain HDRQ HROD HREN/HEW Host Data Strobe Polarity Strobe Active Low, Strobe Active High Host Address Strobe Polarity Strobe Active Low, Strobe Active High Host Multiplexed Nonmultiplexed, Multiplexed Host Dual Data Strobe Single Strobe, Dual Strobe Host Chip Select Polarity Active HTRQ HRRQ Enable Active High HDRQ Host Request Polarity HREQ Active HREQ Active High HTRQ,HRRQ Active HTRQ,HRRQ Active High
Host GPIO Port Enable GPIO Pins Disable, GPIO Enable Host Address Line Enable GPIO, Host Address Line Enable GPIO, Host Chip Select Enable HCS/HAI0 GPIO, HCS/HA10 HC8, HMUX HCS/HA10 HC10, HMUX Host Request Enable HREQ/HACK GPIO, HREQ HREQ, HDRQ Host Acknowledge Enable HACK GPIO HDRQ HREN HACK HACK Host Enable HI08 Disable Pins GPIO HI08 Enable
Host Acknowledge Polarity HACK Active Low, HACK Active High
Host Port Control Register (HPCR) X:$FFFFC4 Read/Write Reset
HCSP
HASP
HDSP
HROD
HAEN
HDDS HMUX
HREN HCSEN HA9EN HA8EN HGEN
Reserved, Program
Figure B-11. Host Base Address Host Port Control Register
B-22
DSP56311 User's Manual
Motorola
Programming Sheet
HOST
Processor Side
Receive Request Enable Interrupts Disabled Host Transmit Request Enable Interrupts Disabled Host HDRQ HREQ/HTRQ HACK/HRRQ HREQ HACK HTRQ HRRQ Host Flags Write Only Host Little Endian Initialize (Write Only) Action Initialize
Interrupts Enabled Host Interrupts Enabled Host
INIT
Interrupt Control Register (ICR) Read/Write Reset
HLEND
HDRQ TREQ RREQ
Receive Data Register Full Wait Read Transmit Data Register Empty Wait Write Transmitter Ready Data Data Host Flags Read Only Status Disabled Host Request HREQ Deasserted Enabled HREQ Asserted
Interrupt Status Register (ISR) Read/Write Reset
HREQ
TRDY TXDE RXDF
Figure B-12.
Reserved, Program Interrupt Control Interrupt Status Register
Motorola
Programming Reference
B-23
Programming Sheet
HOST
Interrupt Vector Register (IVR) Reset
Contains interruptvectoror number
Host Vector Contains Host Command Interrupt Address Host Command Handshakes Executing Host Command Interrupt
Command Vector Register (CVR) Reset
Contains host command interrupt addressr
Figure B-13. Interrupt Vector Command Vector Register
B-24
DSP56311 User's Manual
Motorola
Programming Sheet
HOST
Processor Side
Host Receive Data (usually Read program)
Receive Byte
Receive Middle Byte
Receive High Byte
Used
Receive Byte Registers Read Only Reset
Receive Byte Register
Host Transmit Data (usually loaded program)
Transmit Byte
Transmit Middle Byte
Transmit High Byte
Used
Transmit Byte Registers Write Only Reset
Figure B-14. Host Receive Host Transmit Data Register
Motorola
Programming Reference
B-25
B-26
Programming Sheet
ESSI
Word Length Control Number bits/word (data first bits) (data last bits) Reserved Reserved ESSI Control Register (CRAx) ESSI0 :$FFFFB5 Read/Write ESSI1 :$FFFFA5 Read/Write Reset $000000
Figure B-15. ESSI Control Register (CRA)
DSP56311 User's Manual Motorola
Select Tx#0 drive enable functions serial flag functions driver enable Tx#0 external buffer
Alignment Control 16-bit data left aligned 16-bit data left aligned Frame Rate Divider Control DC4:0 $00-$1F Divide ratio Normal mode time slots Network
PM[7:0] forbidden Prescaler Range Prescale Modulus Select PM7:0 $00-$FF ÷256)
SSC1
Reserved, Program
Motorola
ESSI
Frame Sync Relative Timing Frame Sync only) with data clock cycle earlier than data level (negative)
FSL1 FSL0
Frame Sync Polarity high level (positive)
Clock Polarity (clk edge data Frame Sync clocked out/in) rising falling rising falling Sync/Async Control transfer together not) Asynchronous Synchronous Mode Select Normal Network
Frame Sync Length Word Word Word Word Output Flag SCD1
Figure B-16. ESSI Control Register (CRB)
Transmit Enable (SYN=1 only) Disable Enable Transmit Enable (SYN=1 only) Disable Enable Transmit Enable Disable Enable Receiver Enable Disable Enable Transmit Interrupt Enable Disable Enable Receive Interrupt Enable Disable Enable Transmit Last Slot Interrupt Enable Disable Enable Receive Last Slot Interrupt Enable Disable Enable Transmit Exception Interrupt Enable Disable Enable Receive Exception Interrupt Enable Disable Enable
Serial Control Direction Bits Input Shift Direction First Output
Programming Reference B-27
First
Clock Source Direction External Clock Internal Clock
Programming Sheet
ESSI Control Register (CRBx) ESSI0 :$FFFFB6 Read/Write ESSI1 :$FFFFA6 Read/Write Reset $000000
REIE TEIE RLIE TLIE
FSL1 FSL0 SHFD SCKD SCD2 SCD1 SCD0
Programming Sheet
ESSI
Serial Input Flag SCD0 latch Serial Input Flag SCD1 latch Transmit Frame Sync Sync Inactive Sync Active Receive Frame Sync Wait Frame Sync Occurred Transmitter Underrun Error Flag Error Receiver Overrun Error Flag Error Transmit Data Register Empty Wait Write Receive Data Register Full Wait Read
ESSI Status Register (SSISRx) ESSI0: $FFFFB7 (Read) ESSI1: $FFFFA7 (Read)
Status
Reserved, program
Figure B-17. ESSI Status Register (SSISR)
B-28
DSP56311 User's Manual
Motorola
Programming Sheet
ESSI
ESSI Transmit Slot Mask TSMAx ESSI0: $FFFFB4 Read/Write ESSI1: $FFFFA4 Read/Write Reset $FFFF
ESSI Transmit Slot Mask Ignore Time Slot Active Time Slot
TS15 TS14 TS13 TS12 TS11 TS10
ESSI Transmit Slot Mask
ESSI Transmit Slot Mask Ignore Time Slot Activ Time Slot
Reserved, Program
ESSI Transmit Slot Mask TSMBx ESSI0: $FFFFB3 Read/Write ESSI1: $FFFFA3 Read/Write Reset $FFFF
TS31 TS30 TS29 TS28 TS27 TS26 TS25 TS24 TS23 TS22 TS21 TS20 TS19 TS18 TS17 TS16
ESSI Transmit Slot Mask
ESSI Receive Slot Mask Ignore Time Slot Active Time Slot
Reserved, Program
ESSI Receive Slot Mask RSMAx ESSI0: $FFFFB2 Read/Write ESSI1: $FFFFA2 Read/Write Reset $FFFF
RS15 RS14 RS13 RS12 RS11 RS10
ESSI Receive Slot Mask
ESSI Receive Slot Mask Ignore Time Slot Active Time Slot
Reserved, Program
ESSI Receive Slot Mask RSMBx ESSI0: $FFFFB1 Read/Write ESSI1: $FFFFA1 Read/Write Reset $FFFF
RS31 RS30 RS29 RS28 RS27 RS26 RS25 RS24 RS23 RS22 RS21 RS20 RS19 RS18 RS17 RS16
Figure B-18.
Reserved, Program *Registers (TSM, RSM)0 ESSR Transmit Receive Slot Mask
ESSI Receive Slot Mask
Motorola
Programming Reference
B-29
Programming Sheet
Port Control Register (PCRE) X:$FFFF9F Read/Write Reset $000000
Port Control General-Purpose
*************
Port Control Register (PCRE)
Reserved, Program
Transmitter Enable Transmitter Disable Transmitter Enable Idle Line Interrupt Enable Idle Line Interrupt Disabled Idle Line Interrupt Enabled Receive Interrupt Enable Receive Interrupt Disabled Idle Line Interrupt Enabled Transmit Interrupt Enable Transmit Interrupts Disabled Transmit Interrupts Enabled Timer Interrupt Enable Timer Interrupts Disabled Timer Interrupts Enabled Timer Interrupt Rate Clock Polarity Clock Polarity Positive Clock Polarity Negative Receive Exception Inerrupt Receive Interrupt Disable Receive Interrupt Enable
Word Select Bits 8-bit Synchronous Data (Shift Register Mode) Reserved 10-bit Asynchronous Start, Data, Stop) Reserved 11-bit Asynchronous Start, Data, Even Parity, Stop) 11-bit Asynchronous Start, Data, Parity, Stop) 11-bit Multidrop Start, Data, Data Type, Stop) Reserved Receiver Wakeup Enable receiver awakened Wakeup function enabled Wired-Or Mode Select Multidrop Point Point Receiver Enable Receiver Disabled Receiver Enabled Shift Direction First First
Send Break Send break, then revert Continually send breaks Wakeup Mode Select Idle Line Wakeup Address Wakeup
Control Register (SCR) Address X:$FFFF9C Read/Write
REIE SCKP STIR TMIE ILIE
WOMS WAKE SSFTD WDS2 WDS1 WDS0
Control Register (SCR)
Reserved, Program
Figure B-19. Control Register (SCR)
B-30
DSP56311 User's Manual
Motorola
Programming Sheet
Overrun Error Flag error Overrun detected
Idle Line Flag Idle detected Idle State Receive Data Register Full Receive Data Register Full Receive Data Register Empty Transmitter Data Register Empty Transmitter Data Register full Transmitter Data Register empty Transmitter Empty Transmitter full Transmitter empty
Parity Error Flag error Incorrect Parity detected Framing Error Flag error Stop detected Received Data Addres
Status Register (SSR) Address X:$FFFF93 Read Only Reset $000003
IDLE RDRFTDRETRNE
Reserved, Program *Status Register (SSR)
Clock Divider Bits CD11 CD0) Clock Clock SCLK Mode Internal Internal Output Synchronous/Asynchronous Internal External Input Asynchronous only External Internal Input Asynchronous only External External Input Synchronous/Asynchronous Transmitter Clock Mode/Source Internal clock Transmitter External clock from SCLK Receiver Clock Mode/Source Internal clock Receiver External clock from SCLK Clock Divider Bits CD11 CD0) CD11 Icyc Rate $000 Icyc/1 $001 Icyc/2 $002 Icyc/3 $FFE Icyc/4095 $FFF Icyc/4096
Clock Divider Divide clock before feed SCLK Feed clock directly SCLK Clock Prescaler
CD11 CD10
Clock Control Register (SCCR)
Reserved, Program
Figure B-20. Status Clock Control Registers (SSR, SCCR)
Motorola
Programming Reference
B-31
Programming Sheet
Transmit Data Registers Address X:$FFFF95 X:$FFFF97 Write Reset xxxxxx X:$FFFF97 X:$FFFF96 X:$FFFF95 Unpacking
NOTE: same register decoded four different addresse
Transmit Transmit Data Register
X:$FFFF94
STXA
Receive
Receive Data Registers Address X:$FFFF98 X:$FFFF9A Read Reset xxxxxx X:$FFFF9A X:$FFFF99 X:$FFFF98
Packing
NOTE: same register decoded three different addresse
Receive Data Register
Figure B-21. Receive Transmit Data Registers (SRX, TRX)
B-32
DSP56311 User's Manual
Motorola
Programming Sheet
TimerPS (1:0) Prescaler Clock Source Internal CLK/2 TIO0 TIO1 TIO2
Prescaler Preload Value [0:20])
Timer Prescaler Load Register TPLR:$FFFF83 Read/Write Reset $000000
Reserved, Program
Timer Prescaler Count Register TPCR:$FFFF82 Read Only Reset $000000
Current Value Prescaler Counter [0:20])
Reserved, Program
Figure B-22. Timer Prescaler Load/Count Register (TPLR, TPCR)
Motorola
Programming Reference
B-33
Programming Sheet
Timer
Inverter to-1 transitions input increment counter, high pulse width measured, high pulse output 1-to-0 transitions input increment counter, pulse width measured, pulse output
Timer Reload Mode Timer operates free running counter Timer reloaded when selected condition occurs Direction input output Data Input Zero read read Data Output Zero written written Prescaled Clock Enable Clock source CLK/2 Clock source prescaler output Timer Compare Flag been written TCSR(TCF), timer compare interrupt serviced Timer Compare occurred Timer Overflow Flag been written TCSR(TOF), timer Overflow interrupt serviced Counter wraparound occurred
(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Timer Control Bits (TC0 TC3) Clock Mode GPIO Internal Timer Output Internal Timer Pulse Output Internal Timer Toggle Input External Event Counter Input Internal Input Width Input Internal Input Period Input Internal Capture Output Internal Pulse Width Modulation Reserved Output Internal Watchdog Pulse Output Internal Watchdog Toggle Reserved Reserved Reserved Reserved Reserved Timer Enable Timer Disabled Timer Enabled Timer Overflow Interrupt Enable Overflow Interrupts Disabled Overflow Interrupts Enabled
Timer Compare Interrupt Enable Compare Interrupts Disabled Compare Interrupts Enabled
TCIE TQIE
Timer Control/Status Register TCSR0:$FFFF8F Read/Write TCSR1:$FFFF8B Read/Write TCSR2:$FFFF87 Read/Write Reset $000000
Reserved, Program
Figure B-23. Timer Control/Status Register (TCSR)
B-34
DSP56311 User's Manual
Motorola
Programming Sheet
Timer23 Timer Reload Value
Timer Load Register TLR0:$FFFF8E Write Only TLR1:$FFFF8A Write Only TLR2:$FFFF86 Write Only Reset $000000
Value Compared Counter Value
Timer Compare Register TCPR0:$FFFF8D Read/Write TCPR1:$FFFF89 Read/Write TCPR2:$FFFF85 Read/Write Reset $000000
Timer Count Value
Timer Count Register TCR0:$FFFF8C Read Only TCR1:$FFFF88 Read Only TCR2:$FFFF84 Read Only Reset $000000
Figure B-24. Timer Load, Compare, Count Registers (TLR, TCPR, TCR)
Motorola
Programming Reference
B-35
Programming Sheet
GPIO
Host Data Direction Register
Port (HI08)
X:$FFFFC8 Write Reset
DR15 DR14 DR13 DR12 DR11 DR10
Output
Input
Host Data Register
X:$FFFFC9 Write Reset Undefined holds value corresponding HI08 GPIO pin. Function depends HDDR.
Figure B-25. Host Data Direction Host Data Registers (HDDR, HDR)
B-36
DSP56311 User's Manual
Motorola
Programming Sheet
GPIO
Port Control Register (PCRC) X:$FFFFBF ReadWrite Reset
Port (ESSI0)
STD0 SRD0 SCK0 SC02 SC01 SC00
Port configured ESSI Port configured GPIO
Port Direction Register (PRRC) X:$FFFFBE ReadWrite Reset
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
PDCn Port Output PDCn Port Input
Port GPIO Data Register (PDRC) X:$FFFFBD ReadWrite Reset
port GPIO input, then reflects value port port GPIO output, then value written reflected port
Reserved, Program
Figure B-26. Port Registers (PCRC, PRRC, PDRC)
Motorola
Programming Reference
B-37
Programming Sheet
GPIO
Port Control Register (PCRD) X:$FFFFAF ReadWrite Reset
Port (ESSI1)
STD1 SRD1 SCK1 SC12 SC11 SC10
Port configured ESSI Port configured GPIO
Port Direction Register (PRRD) X:$FFFFAE ReadWrite Reset
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
PDCn Port Output PDCn Port Input
Port GPIO Data Register (PDRD) X:$FFFFAD ReadWrite Reset
port GPIO input, then reflects value port port GPIO output, then value written reflected port
Reserved, Program
Figure B-27. Port Registers (PCRD, PRRD, PDRD)
B-38
DSP56311 User's Manual
Motorola
Programming Sheet
GPIO
Port Control Register (PCRE) X:$FFFF9F ReadWrite Reset
Port (SCI)
SCLK
Port configured Port configured GPIO
Port Direction Register (PRRE) X:$FFFF9E ReadWrite Reset
PDC2
PDC1
PDC0
PDCn Port Output PDCn Port Input
Port GPIO Data Register (PDRE) X:$FFFF9D ReadWrite Reset
port GPIO input, then reflects value port port GPIO output, then value written reflected port
Reserved, Program
Figure B-28. Port Registers (PCRE, PRRE, PDRE)
Motorola
Programming Reference
B-39
Programming Sheet
EFCOP
*********
Filter Count Register (FCNT) Y:$FFFFB3 Read/Write Reset $000000
FilterData Input Interrupt Enable (Read/write control bit) Interrupt disabled Interrupt enabled FilterData Output Interrupt Enable (Read/write control bit) Interrupt disabled Interrupt enabled FilterSaturation (Read only status bit) FMAC underflow/overflow FMAC underflow/overflow occurred FilterContention (Read only status bit) dual access occurred Core EFCOP tried access same bank Filter Data Input Buffer Empty (Read only status bit) FDIR empty FDIR empty Filter Data Output Buffer Full (Read only status bit) FDOR full FDOR full
Filter Count Value
Reserved, Program
Filter Enable EFCOP Disabled EFCOP Enabled Filter Type Adaptive Mode Enable Adaptive Mode Disabled Adaptive Mode Enabled Update Mode Enable Update Mode Disabled Update Mode Enabled Filter Operating ModeBits Real Alt. Complex Complex Magnitude Channels Single channel Multichannel Initialization Preprocess initialization initialization Coefficients shared Shared
FSAT FDOE FDIE CONT
FSCO FPCR FMLC FOM1FOM0 FUPD FADP
EFCOP Control Status Register (FCSR) Y:$FFFFB4 Read/Write Reset $000000
Reserved, Program
Figure B-29. EFCOP Counter Control Status Registers (FCNT FCSR)
B-40
DSP56311 User's Manual
Motorola
Programming Sheet
EFCOP
Saturation Mode Disabled Enabled Sixteen-bit Arithmetic Mode Disabled Enabled Filter Input Scaling used Used Filter Rounding Mode Bits Convergent Two's complement Truncation Reserved Filter Scaling Bits Reserved
******** ******
EFCOP Control Register (FACR) Y:$FFFFB5 Read/Write Reset $000000
FISL
Rounding Mode
Filter Scaling
Reserved,3Program as00
Data Base Address (FDM Pointer)
EFCOP Data Base Address (FDBA) Y:$FFFFB6 Read/Write Reset $000000
Coefficient Base Address (FDM Pointer)
EFCOP Coefficient Base Address (FCBA) Y:$FFFFB7 Read/Write Reset $000000 Filter Deci0 mation Value
************
Filter Channels Value
EFCOP Decimation/Channel Count Register (FDCH) Y:$FFFFB8 Read/Write Reset $000000
Reserved, Program
Figure B-30. EFCOP FACR, FDBA, FCBA, FDCH Register
Motorola
Programming Reference
B-41
Programming Sheet
B-42
DSP56311 User's Manual
Motorola

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