DSP56302UM/AD PROGRAMMING REFERENCE INTRODUCTION INTERNAL ME

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DSP56302UM/AD PROGRAMMING REFERENCE INTRODUCTION INTERNAL ME

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APPENDIX PROGRAMMING REFERENCE
DSP56302UM/AD
PROGRAMMING REFERENCE
INTRODUCTION INTERNAL MEMORY INTERRUPT ADDRESSES SOURCES D-11 INTERRUPT PRIORITIES. D-13 PROGRAMMING REFERENCE: CENTRAL PROCESSOR D-15 D-19 HOST INTERFACE (HI08) D-20 ENHANCED SYNCHRONOUS SERIAL INTERFACE (ESSI) D-26 SERIAL COMMUNICATIONS INTERFACE D-30 TIMERS D-33 GENERAL PURPOSE (GPIO). D-36
DSP56302UM/AD
PERIPHERAL ADDRESSES
PROGRAMMING REFERENCE
INTRODUCTION
This section been compiled reference programmers. contains table showing addresses DSP's memory-mapped peripherals, exception priority table, programming sheets major programmable registers DSP. programming sheets grouped following order: central processor, Phase Lock Loop, (PLL), Host Interface (HI08), Enhanced Synchronous Serial Interface (ESSI), Serial Communication Interface (SCI), Timer, GPIO. Each sheet provides room write value each hexadecimal value each register. programmer photocopy these sheets reuse them each application development project. details instruction DSP56300 family chips, DSP56300 Family Manual.
D.1.1
Peripheral Addresses
Table lists memory addresses on-chip peripherals.
D.1.2
Interrupt Addresses
Table lists interrupt starting addresses sources.
D.1.3
Interrupt Priorities
Table lists priorities specific interrupts within interrupt priority levels.
D.1.4
Programming Sheets
remaining figures describe major programmable registers DSP56302.
DSP56302UM/AD
PROGRAMMING REFERENCE
INTERNAL MEMORY
Table Internal Memory
Peripheral
16-Bit Address $FFFF $FFFE
24-Bit Address $FFFFFF $FFFFFE $FFFFFD $FFFFFC $FFFFFB $FFFFFA $FFFFF9 $FFFFF8 $FFFFF7 $FFFFF6 $FFFFF5 $FFFFF4 $FFFFF3 $FFFFF2 $FFFFF1 $FFFFF0 $FFFFEF $FFFFEE $FFFFED $FFFFEC
Register Name Interrupt Priority Register Core (IPR-C) Interrupt Priority Register Peripheral (IPR-P) Control Register (PCTL) OnCE Register (OGDB) Control Register (BCR) DRAM Control Register (DCR) Address Attribute Register (AAR0) Address Attribute Register (AAR1) Address Attribute Register (AAR2) Address Attribute Register (AAR3) Register (IDR) Status Register (DSTR) Offset Register (DOR0) Offset Register (DOR1) Offset Register (DOR2) Offset Register (DOR3) Source Address Register (DSR0) Destination Address Register (DDR0) Counter (DCO0) Control Register (DCR0)
OnCE
$FFFD $FFFC $FFFB $FFFA $FFF9 $FFF8 $FFF7 $FFF6 $FFF5
$FFF4 $FFF3 $FFF2 $FFF1 $FFF0
DMA0
$FFEF $FFEE $FFED $FFEC
DSP56302UM/AD
PROGRAMMING REFERENCE
Table Internal Memory (Continued)
Peripheral DMA1 16-Bit Address $FFEB $FFEA $FFE9 $FFE8 DMA2 $FFE7 $FFE6 $FFE5 $FFE4 DMA3 $FFE3 $FFE2 $FFE1 $FFE0 DMA4 $FFDF $FFDE $FFDD $FFDC DMA5 $FFDB $FFDA $FFD9 $FFD8 24-Bit Address $FFFFEB $FFFFEA $FFFFE9 $FFFFE8 $FFFFE7 $FFFFE6 $FFFFE5 $FFFFE4 $FFFFE3 $FFFFE2 $FFFFE1 $FFFFE0 $FFFFDF $FFFFDE $FFFFDD $FFFFDC $FFFFDB $FFFFDA $FFFFD9 $FFFFD8 Register Name Source Address Register (DSR1) Destination Address Register (DDR1) Counter (DCO1) Control Register (DCR1) Source Address Register (DSR2) Destination Address Register (DDR2) Counter (DCO2) Control Register (DCR2) Source Address Register (DSR3) Destination Address Register (DDR3) Counter (DCO3) Control Register (DCR3) Source Address Register (DSR4) Destination Address Register (DDR4) Counter (DCO4) Control Register (DCR4) Source Address Register (DSR5) Destination Address Register (DDR5) Counter (DCO5) Control Register (DCR5)
DSP56302UM/AD
PROGRAMMING REFERENCE
Table Internal Memory (Continued)
Peripheral 16-Bit Address $FFD7 $FFD6 $FFD5 $FFD4 $FFD3 $FFD2 $FFD1 $FFD0 $FFCF $FFCE $FFCD $FFCC $FFCB $FFCA PORT $FFC9 $FFC8 HI08 $FFC7 $FFC6 $FFC5 $FFC4 $FFC3 $FFC2 $FFC1 $FFC0 24-Bit Address $FFFFD7 $FFFFD6 $FFFFD5 $FFFFD4 $FFFFD3 $FFFFD2 $FFFFD1 $FFFFD0 $FFFFCF $FFFFCE $FFFFCD $FFFFCC $FFFFCB $FFFFCA $FFFFC9 $FFFFC8 $FFFFC7 $FFFFC6 $FFFFC5 $FFFFC4 $FFFFC3 $FFFFC2 $FFFFC1 $FFFFC0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Host Port GPIO Data Register (HDR) Host Port GPIO Direction Register (HDDR) Host Transmit Register (HTX) Host Receive Register (HRX) Host Base Address Register (HBAR) Host Polarity Control Register (HPCR) Host Status Register (HSR) Host Control Register (HCR) Reserved Reserved Register Name
DSP56302UM/AD
PROGRAMMING REFERENCE
Table Internal Memory (Continued)
Peripheral PORT 16-Bit Address $FFBF $FFBE $FFBD ESSI $FFBC $FFBB $FFBA $FFB9 $FFB8 $FFB7 $FFB6 $FFB5 $FFB4 $FFB3 $FFB2 $FFB1 $FFB0 PORT $FFAF $FFAE $FFAD 24-Bit Address $FFFFBF $FFFFBE $FFFFBD $FFFFBC $FFFFBB $FFFFBA $FFFFB9 $FFFFB8 $FFFFB7 $FFFFB6 $FFFFB5 $FFFFB4 $FFFFB3 $FFFFB2 $FFFFB1 $FFFFB0 $FFFFAF $FFFFAE $FFFFAD Register Name Port Control Register (PCRC) Port Direction Register (PRRC) Port GPIO Data Register (PDRC) ESSI Transmit Data Register (TX00) ESSI Transmit Data Register (TX01) ESSI Transmit Data Register (TX02) ESSI Time Slot Register (TSR0) ESSI Receive Data Register (RX0) ESSI Status Register (SSISR0) ESSI Control Register (CRB0) ESSI Control Register (CRA0) ESSI Transmit Slot Mask Register (TSMA0) ESSI Transmit Slot Mask Register (TSMB0) ESSI Receive Slot Mask Register (RSMA0) ESSI Receive Slot Mask Register (RSMB0) Reserved Port Control Register (PCRD) Port Direction Register (PRRD) Port GPIO Data Register (PDRD)
DSP56302UM/AD
PROGRAMMING REFERENCE
Table Internal Memory (Continued)
Peripheral ESSI 16-Bit Address $FFAC $FFAB $FFAA $FFA9 $FFA8 $FFA7 $FFA6 $FFA5 $FFA4 $FFA3 $FFA2 $FFA1 $FFA0 PORT $FF9F $FF9E $FF9D 24-Bit Address $FFFFAC $FFFFAB $FFFFAA $FFFFA9 $FFFFA8 $FFFFA7 $FFFFA6 $FFFFA5 $FFFFA4 $FFFFA3 $FFFFA2 $FFFFA1 $FFFFA0 $FFFF9F $FFFF9E $FFFF9D Register Name ESSI Transmit Data Register (TX10) ESSI Transmit Data Register (TX11) ESSI Transmit Data Register (TX12) ESSI Time Slot Register (TSR1) ESSI Receive Data Register (RX1) ESSI Status Register (SSISR1) ESSI Control Register (CRB1) ESSI Control Register (CRA1) ESSI Transmit Slot Mask Register (TSMA1) ESSI Transmit Slot Mask Register (TSMB1) ESSI Receive Slot Mask Register (RSMA1) ESSI Receive Slot Mask Register (RSMB1) Reserved Port Control Register (PCRE) Port Direction Register (PRRE) Port GPIO Data Register (PDRE)
DSP56302UM/AD
PROGRAMMING REFERENCE
Table Internal Memory (Continued)
Peripheral 16-Bit Address $FF9C $FF9B $FF9A $FF99 $FF98 $FF97 $FF96 $FF95 $FF94 $FF93 $FF92 $FF91 $FF90 24-Bit Address $FFFF9C $FFFF9B $FFFF9A $FFFF99 $FFFF98 $FFFF97 $FFFF96 $FFFF95 $FFFF94 $FFFF93 $FFFF92 $FFFF91 $FFFF90 Register Name Control Register (SCR) Clock Control Register (SCCR) Receive Data Register High (SRXH) Receive Data Register Middle (SRXM) Recieve Data Register (SRXL) Transmit Data Register High (STXH) Transmit Data Register Middle (STXM) Transmit Data Register (STXL) Transmit Address Register (STXA) Status Register (SSR) Reserved Reserved Reserved
DSP56302UM/AD
PROGRAMMING REFERENCE
Table Internal Memory (Continued)
Peripheral TRIPLE TIMER 16-Bit Address $FF8F $FF8E $FF8D $FF8C $FF8B $FF8A $FF89 $FF88 $FF87 $FF86 $FF85 $FF84 $FF83 $FF82 $FF81 $FF80 24-Bit Address $FFFF8F $FFFF8E $FFFF8D $FFFF8C $FFFF8B $FFFF8A $FFFF89 $FFFF88 $FFFF87 $FFFF86 $FFFF85 $FFFF84 $FFFF83 $FFFF82 $FFFF81 $FFFF80 Register Name Timer Control/Status Register (TCSR0) Timer Load Register (TLR0) Timer Compare Register (TCPR0) Timer Count Register (TCR0) Timer Control/Status Register (TCSR1) Timer Load Register (TLR1) Timer Compare Register (TCPR1) Timer Count Register (TCR1) Timer Control/Status Register (TCSR2) Timer Load Register (TLR2) Timer Compare Register (TCPR2) Timer Count Register (TCR2) Timer Prescaler Load Register (TPLR) Timer Prescaler Count Register (TPCR) Reserved Reserved
D-10
DSP56302UM/AD
PROGRAMMING REFERENCE
INTERRUPT ADDRESSES SOURCES
Table Interrupt Sources
Interrupt Starting Address VBA:$00 VBA:$02 VBA:$04 VBA:$06 VBA:$08 VBA:$0A VBA:$0C VBA:$0E VBA:$10 VBA:$12 VBA:$14 VBA:$16 VBA:$18 VBA:$1A VBA:$1C VBA:$1E VBA:$20 VBA:$22 VBA:$24 VBA:$26 VBA:$28 VBA:$2A VBA:$2C VBA:$2E VBA:$30 VBA:$32 VBA:$34 VBA:$36 Interrupt Priority Level Range Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Non-Maskable Interrupt (NMI) Reserved Reserved IRQA IRQB IRQC IRQD Channel Channel Channel Channel Channel Channel TIMER Compare TIMER Overflow TIMER Compare TIMER Overflow TIMER Compare TIMER Overflow ESSI0 Receive Data ESSI0 Receive Data With Exception Status ESSI0 Receive Last Slot ESSI0 Transmit Data
Interrupt Source
DSP56302UM/AD
D-11
PROGRAMMING REFERENCE
Table Interrupt Sources (Continued)
Interrupt Starting Address VBA:$38 VBA:$3A VBA:$3C VBA:$3E VBA:$40 VBA:$42 VBA:$44 VBA:$46 VBA:$48 VBA:$4A VBA:$4C VBA:$4E VBA:$50 VBA:$52 VBA:$54 VBA:$56 VBA:$58 VBA:$5A VBA:$5C VBA:$5E VBA:$60 VBA:$62 VBA:$64 VBA:$66 VBA:$FE Interrupt Priority Level Range
Interrupt Source
ESSI0 Transmit Data With Exception Status ESSI0 Transmit Last Slot Reserved Reserved ESSI1 Receive Data ESSI1 Receive Data With Exception Status ESSI1 Receive Last Slot ESSI1 Transmit Data ESSI1 Transmit Data With Exception Status ESSI1 Transmit Last Slot Reserved Reserved Receive Data Receive Data With Exception Status Transmit Data Idle Line Timer Reserved Reserved Reserved Host Receive Data Full Host Transmit Data Empty Host Command (Default) Reserved Reserved
D-12
DSP56302UM/AD
PROGRAMMING REFERENCE
INTERRUPT PRIORITIES
Table Interrupt Source Priorities within
Priority Interrupt Source Level (Nonmaskable) Highest Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Lowest Non-Maskable Interrupt Levels (Maskable) Highest IRQA (External Interrupt) IRQB (External Interrupt) IRQC (External Interrupt) IRQD (External Interrupt) Channel Interrupt Channel Interrupt Channel Interrupt Channel Interrupt Channel Interrupt Channel Interrupt Host Command Interrupt Host Transmit Data Empty Host Receive Data Full ESSI0 Data with Exception Interrupt
DSP56302UM/AD
D-13
PROGRAMMING REFERENCE
Table Interrupt Source Priorities within (Continued)
Priority Interrupt Source ESSI0 Data Interrupt ESSI0 Receive Last Slot Interrupt ESSI0 Data With Exception Interrupt ESSI0 Transmit Last Slot Interrupt ESSI0 Data Interrupt ESSI1 Data With Exception Interrupt ESSI1 Data Interrupt ESSI1 Receive Last Slot Interrupt ESSI1 Data With Exception Interrupt ESSI1 Transmit Last Slot Interrupt ESSI1 Data Interrupt Receive Data With Exception Interrupt Receive Data Transmit Data Idle Line Timer TIMER0 Overflow Interrupt TIMER0 Compare Interrupt TIMER1 Overflow Interrupt TIMER1 Compare Interrupt TIMER2 Overflow Interrupt Lowest TIMER2 Compare Interrupt
D-14
DSP56302UM/AD
PROGRAMMING REFERENCE
Application:
Date: Programmer:
Sheet
Central Processor
Unnormalized Acc(47) xnor Acc(46) Extension Limit Scaling Acc(46) Acc(45)
Scaling Mode S(1:0) Scaling Mode scaling Scale down Scale Reserved I(1:0) Interrupt Mask Exceptions Masked None
Carry Overflow Zero Negative
Reserved Sixteen-Bit Compatibilitity Double Precision Multiply Mode Loop Flag DO-Forever Flag Sixteenth-Bit Arithmetic Reserved Instruction Cache Enable Arithmetic Saturation Rounding Mode
Core Priority CP(1:0) Core Priority (lowest) (highest)
Extended Mode Register (MR)
Mode Register (MR)
Condition Code Register (CCR)
Status Register (SR) Read/Write Reset $C00300
Reserved, Program
Figure Status Register (SR)
DSP56302UM/AD
D-15
PROGRAMMING REFERENCE
Application:
Date: Programmer:
Sheet
Central Processor
Chip Operating Modes MOD(D:A) Reset Vector Description 0000 $C00000 Expanded mode X001 $FF0000 Bootstrap from byte wide memory X010 $FF0000 Bootstrap through X011 Reserved X100 $FF0000 Host Bootstrap mode (32-bit wide) X101 $FF0000 Host Bootstrap 16-bit wide mode (ISA) X110 $FF0000 Host Bootstrap 8-bit wide mode (dbl strb) X111 $FF0000 Host Bootstrap 8-bit wide mode (sgl strb) 1000 $008000 Expanded mode
External Disable Stop Delay Memory Switch Mode
CDP(1:0) Core-DMA Priority Core-DMA Priority Core Priority accesses Core accesses Core accesses Core
Burst Mode Enable Synchronize Select Release Timing Stack Extension Space Select Extended Stack Underflow Flag Extended Stack Overflow Flag Extended Stack Wrap Flag Stack Extension Enable
CDP1 CDP0
System Stack Control Status Register (SCS)
Extended Chip Operating Mode Register (COM)
Chip Operating Mode Register (COM)
Operating Mode Register (OMR) Read/Write Reset $00030X
Reserved, Program *==Latched from levels Mode pins
Figure Operating Mode Register (OMR)
D-16
DSP56302UM/AD
Application:
IRQC Mode
Trigger Level Neg. Edge ICL1 ICL0 Enabled IAL1 IAL0 IAL2 Trigger Level Neg. Edge Enabled
CENTRAL PROCESSOR
IRQA Mode
ICL2
IRQD Mode
Trigger Level Neg. Edge IDL1 IDL0 Enabled IBL2 Trigger Level Neg. Edge IBL1
IRQB Mode
IBL0 Enabled
Figure Interrupt Priority Register-Core (IPR-C)
DSP56302UM/AD
D5L1 D5L0 D4L1 D4L0 D3L1 D3L0 D2L1 D2L0 D1L1 D1L0 D0L1 D0L0 IDL2 IDL1
IDL2
Date:
IDL0 ICL2 ICL1 ICL0 IBL2
IBL1
IBL0
IAL2
IAL1
IAL0
Programmer:
Interrupt Priority Register (IPR-C) X:$FFFF Read/Write Reset $000000
Sheet
PROGRAMMING REFERENCE
D-17
D-18
Application: ESSI1
S1L1 S1L0 Enabled HPL1 HPL0 Enabled
CENTRAL PROCESSOR
Host
PROGRAMMING REFERENCE
SCL1 SCL0 Enabled
ESSI0
S0L1 S0L0 Enabled
Figure Interrupt Priority Register Peripherals (IPR-P)
DSP56302UM/AD
Date:
T0L1 T0L0 SCL1 SCL0 S1L1 S1L0 SOL1 S0L0 HPL1 HPL0
Programmer:
Interrupt Priority Register (IPR-P) X:$FFFF Read/Write Reset $000000
**************
Sheet
Reserved, Program
Application:
XTAL Disable (XTLD) Enable Xtal Oscillator EXTAL Driven From External Source Crystal Range (XTLR) External Xtal Freq 200KHz External Xtal Freq 200KHz Multiplication Factor Bits MF11 MF11 Multiplication Factor $000 $001 $002 $FFF 4095 $FFF 4096
PSTP Relationship Operation During STOP PSTP Oscillator Disabled Disabled Disabled Enabled Enabled Enabled
Clock Output Disable (COD) Duty Cycle Clock Held High State
Figure Phase Lock Loop Control Register (PCTL)
DSP56302UM/AD
Division Factor Bits (DF0 DF2) Division Factor
Predivision Factor Bits (PD0 PD3) Predivision Factor
Date:
Programmer:
PSTP XTLD XTLR
MF11 MF10
Sheet
PROGRAMMING REFERENCE
Control Register (PCTL) X:$FFFFFD Read/Write Reset $000000
D-19
PROGRAMMING REFERENCE
Application:
Date: Programmer:
Sheet
HOST
Host Receive Data (usually Read program)
Receive High Byte Receive Middle Byte
Receive Byte
Host Receive Data Register (HRX) X:$FFEC6 Read Only Reset empty Host Transmit Data (usually Loaded program)
Transmit High Byte Transmit Middle Byte
Transmit Byte
Host Transmit Data Register (HTX) X:$FFEC7 Write Only Reset empty
Figure Host Receive Host Transmit Data Registers
D-20
DSP56302UM/AD
PROGRAMMING REFERENCE
Application:
Date: Programmer:
Sheet
HOST
Host Receive Interrupt Enable Disable Enable HRDF Host Transmit Interrupt Enable Disable Enable HTDE Host Command Interrupt Enable Disable Enable Host Flag
Host Flag
Host Control Register (HCR) X:$FFFFC2 Read /Write Reset
HRIE
HCIE HTIE
Side
Host Receive Data Full Wait Read Host Transmit Data Empty Wait Write Host Command Pending Wait Ready Host Flags Read Only
Host Staus Register (HSR) X:$FFFFC3 Read Only Reset
HTDE HRDF
Reserved, Program
Figure Host Control Host Status Registers
DSP56302UM/AD
D-21
PROGRAMMING REFERENCE
Application:
Date: Programmer:
Sheet
HOST
Host Base Address Register (HBAR) X:$FFFFC5 Reset
BA10
Host Request Open Drain HDRQ HROD HREN/HEW Host Data Strobe Polarity Strobe Active Low, Strobe Active High Host Address Strobe Polarity Strobe Active Low, Strobe Active High Host Multiplexed Nonmultiplexed, Multiplexed Host Dual Data Strobe Singles Stroke, Dual Stoke Host Chip Select Polarity Active HTRQ HRRQ Enable Active High HDRQ Host Request Priority HREQ Active HREQ Active High HTRQ,HRRQ Active HTRQ,HRRQ Active High
Host GPIO Port Enable GPIO Pins Disable, GPIO Enable Host Address Line Enable GPIO, Host Address Line Enable GPIO, Host Chip Select Enable HCS/HAI0 GPIO, HCS/HA10 HC8, HMUX HCS/HA10 HC10, HMUX Host Request Enable HREQ/HACK GPIO, HREQ HREQ, HDRQ Host Acknowledge Enable HACK GPIO HDRQ HREN HACK HACK Host Enable HI08 Disable Pins GPIO HI08 Enable
Host Acknowledge Priority HACK Active Low, HACK Active High
Host Port Control Register (HPCR) X:$FFFFC4 Read/Write Reset
HCSP
HASP
HDSP
HROD
HAEN
HDDS HMUX
HREN HCSEN HA9EN HA8EN HGEN
Reserved, Program
Figure Host Base Address Host Port Control Registers
D-22
DSP56302UM/AD
PROGRAMMING REFERENCE
Application:
Date: Programmer:
Sheet
HOST
Processor Side
Receive Request Enable Interrupts Disabled Host Transmit Request Enable Interrupts Disabled Host HDRQ HREQ/HTRQ HACK/HRRQ HREQ HACK HTRQ HRRQ Host Flags Write Only Host Little Endian Initialize (Write Only) Action Initialize
Interrupts Enabled Host Interrupts Enabled Host
INIT
HLEND
Interrupt Control Register (ICR) Read/Write Reset
HDRQ TREQ RREQ
Receive Data Register Full Wait Read Transmit Data Register Empty Wait Write Transmitter Ready Data Data Host Flags Read Only Status Disabled Enabled
Host Request HREQ Deasserted HREQ Asserted
HREQ
RXDF
Interrupt Status Register (ISR) Read/Write Reset
TRDY TXDE
Reserved, Program Figure Interrupt Control Interrupt Status Registers
MOTOROLA DSP56302UM/AD D-23
PROGRAMMING REFERENCE
Application:
Date: Programmer:
Sheet
HOST
Interrupt Vector Register (IVR) Reset
Contains interruptvectoror number
Host Vector Contains Host Command Interrupt Address Host Command Handshakes Executing Host Command Interrupts
Command Vector Register (CVR) Reset
Contains host command interrupt addressr
Figure D-10 Interrupt Vector Command Vector Registers
D-24
DSP56302UM/AD
PROGRAMMING REFERENCE
Application:
Date: Programmer:
Sheet
HOST
Processor Side
Host Receive Data (usually Read program)
Receive Byte
Receive Middle Byte
Receive High Byte
Used
Receive Byte Registers Read Only Reset
Receive Byte Registers
Host Transmit Data (usually loaded program)
Transmit Byte
Transmit Middle Byte
Transmit High Byte
Used
Transmit Byte Registers Write Only Reset
Figure D-11 Host Receive Host Transmit Data Registers
DSP56302UM/AD
D-25
D-26
Application:
ESSI Control Register (CRAx) ESSI0 :$FFFFB5 Read/Write ESSI1 :$FFFFA5 Read/Write Reset $000000 Alignment Control 16-bit data left aligned 16-bit data left aligned Frame Rate Divider Control DC4:0 $00-$1F Divide ratio Normal mode time slots Network Prescaler Range PM[7:0] Prescale Modulus Select PM7:0 $00-$FF ÷256)
PROGRAMMING REFERENCE
ESSI
Word Length Control Number bits/word (data first bits) (data last bits) Reserved Reserved
Figure D-12 ESSI Control Register (CRA)
DSP56302UM/AD
Select Tx#0 drive enable functions serial flag functions driver enable Tx#0 external buffer
Date:
Programmer:
SSC1
Reserved, Program
Sheet
Application:
ESSI
Frame Sync Relative Timing Frame Sync only) with data clock cycle earlier than data level (negative) Output Flag SCD1 FSL1 FSL0
Frame Sync Length Word Word Word Word Serial Control Direction Bits SCDx (Output) SCDx 1(Output) Flag Frame Sync Flag Frame Sync Frame Sync Shift Direction First First Clock Source Direction External Clock Internal Clock
Frame Sync Polarity high level (positive)
Clock Polarity (clk edge data Frame Sync clocked out/in) rising falling rising falling
Sync/Async Control transfer together not) Asynchronous Synchronous
Mode Select Normal
Network
Transmit Enable (SYN=1 only) Disable Enable
Transmit Enable (SYN=1 only) Disable Enable
Transmit Enable Disable Enable
Receiver Enable Disable Enable
Transmit Interrupt Enable Disable Enable
Figure D-13 ESSI Control Register (CRB)
DSP56302UM/AD
REIE TEIE RLIE TLIE
Receive Interrupt Enable Disable Enable
Transmit Last Slot Interrupt Enable Disable Enable
Receive Last Slot Interrupt Enable Disable Enable
Date:
Transmit Exception Interrupt Enable Disable Enable
Programmer:
Receive Exception Interrupt Enable Disable Enable
FSL1 FSL0 SHFD SCKD SCD2 SCD1 SCD0
Sheet
PROGRAMMING REFERENCE
ESSI Control Register (CRBx) ESSI0 :$FFFFB6 Read/Write ESSI1 :$FFFFA6 Read/Write Reset $000000
D-27
PROGRAMMING REFERENCE
Application:
Date: Programmer:
Sheet
ESSI
Serial Input Flag SCD0 latch Serial Input Flag SCD1 latch Transmit Frame Sync Sync Inactive Sync Active Receive Frame Sync Wait Frame Sync Occurred Transmitter Underrun Error Flag Error Receiver Overrun Error Flag Error Transmit Data Register Empty Wait Write Receive Data Register Full Wait Read
Status Register (SSISRx) ESSI0: $FFFFB7 (Read) ESSI1: $FFFFA7 (Read)
Status Bits
Reserved, program
Figure D-14 ESSI Status Register (SSISR)
D-28
DSP56302UM/AD
PROGRAMMING REFERENCE
Application:
Date: Programmer:
Sheet
ESSI
ESSI Transmit Slot Mask TSMAx ESSI0: $FFFFB4 Read/Write ESSI1: $FFFFA4 Read/Write Reset $FFFF
Transmit Slot Mask IgnoreTime Slot Activ Time Slot
TS15 TS14 TS13 TS12 TS11 TS10
ESSI Transmit Slot Mask
Transmit Slot Mask IgnoreTime Slot Active Time Slot
Reserved, Program
ESSI Transmit Slot Mask TSMBx ESSI0: $FFFFB3 Read/Write ESSI1: $FFFFA3 Read/Write Reset $FFFF
TS31 TS30 TS29 TS28 TS27 TS26 TS25 TS24 TS23 TS22 TS21 TS20 TS19 TS18 TS17 TS16
ESSI Transmit Slot Mask
Receive Slot Mask IgnoreTime Slot Active Time Slot
Reserved, Program
Receive Slot Mask RSMAx ESSI0: $FFFFB2 Read/Write ESSI1: $FFFFA2 Read/Write Reset $FFFF
RS15 RS14 RS13 RS12 RS11 RS10
ESSI Receive Slot Mask
Receive Slot Mask Ignore Time Slot Active Time Slot
Reserved, Program
Receive Slot Mask RSMBx ESSI0: $FFFFB1 Read/Write ESSI1: $FFFFA1 Read/Write Reset $FFFF
RS31 RS30 RS29 RS28 RS27 RS26 RS25 RS24 RS23 RS22 RS21 RS20 RS19 RS18 RS17 RS16
Reserved, Program Figure D-15 ESSR Transmit Receive Slot Mask Registers (TSM, RSM)
MOTOROLA DSP56302UM/AD D-29
ESSI Receive Slot Mask
PROGRAMMING REFERENCE
Application:
Date: Programmer:
Sheet Port Control General Purpose
Port Control Register (PCRE) X:$FFFF9F Read/Write Reset $000000
*************
Port Control Register (PCRE)
Reserved, Program
Transmitter Enable Transmitter Disable Transmitter Enable Idle Line Interrupt Enable Idle Line Interrupt Disabled Idle Line Interrupt Enabled Receive Interrupt Enable Receive Interrupt Disabled Idle Line Interrupt Enabled Transmit Interrupt Enable Transmit Interrupts Disabled Transmit Interrupts Enabled Timer Interrupt Enable Timer Interrupts Disabled Timer Interrupts Enabled Timer Interrupt Rate Clock Polarity Clock Polarity Positive Clock Polarity Negative Receive Exception Inerrupt Receive Interrupt Disable Receive Interrupt Enable
Word Select Bits 8-bit Synchronous Data (Shift Register Mode) Reserved 10-bit Asynchronous Start, Data, Stop) Reserved 11-bit Asynchronous Start, Data, Even Parity, Stop) 11-bit Asynchronous Start, Data, Parity, Stop) 11-bit Multidrop Start, Data, Data Type, Stop) Reserved Receiver Wakeup Enable receiver awakened Wakeup function enabled Wired-Or Mode Select Multidrop Point Point Receiver Enable Receiver Disabled Receiver Enabled Shift Direction First First
Send Break Send break, then revert Continually send breaks Wakeup Mode Select Idle Line Wakeup Address Wakeup
Control Register (SCR) Address X:$FFFF9C Read/Write
REIE SCKP STIR TMIE ILIE
WOMS WAKE SSFTD WDS2 WDS1 WDS0
Control Register (SCR)
Reserved, Program
Figure D-16 Control Register (SCR)
D-30
DSP56302UM/AD
PROGRAMMING REFERENCE
Application:
Date: Programmer:
Sheet
Overrun Error Flag error Overrun detected
Idle Line Flag Idle detected Idle State Receive Data Register Full Receive Data Register Full Receive Data Register Empty Transmitter Data Register Empty Transmitter Data Register full Transmitter Data Register empty Transmitter Empty Transmitter full Transmitter empty
Parity Error Flag error Incorrect Parity detected Framing Error Flag error Stop detected Received Data Address
Status Register (SSR) Address X:$FFFF93 Read Only Reset $000003
IDLE RDRF TDRE TRNE
Reserved, Program *Status Register (SSR)as
Clock Divider Bits CD11 CD0) Clock Clock SCLK Mode Internal Internal Output Synchronous/Asynchronous Internal External Input Asynchronous only External Internal Input Asynchronous only External External Input Synchronous/Asynchronous Transmitter Clock Mode/Source Internal clock Transmitter External clock from SCLK Receiver Clock Mode/Source Internal clock Receiver External clock from SCLK Clock Divider Bits CD11 CD0) CD11 Icyc Rate $000 Icyc/1 $001 Icyc/2 $002 Icyc/3 $FFE Icyc/4095 $FFF Icyc/4096
Clock Divider Divide clock before feed SCLK Feed clock directly SCLK Clock Prescaler
CD11 CD10
Clock Control Register (SCCR)
Reserved, Program
Figure D-17 Status Clock Control Registers (SSR, SCCR)
DSP56302UM/AD
D-31
PROGRAMMING REFERENCE
Application:
Date: Programmer:
Sheet
Transmit Data Registers Address X:$FFFF95 X:$FFFF97 Write Reset xxxxxx Note: X:$FFFF97 X:$FFFF96 X:$FFFF95 Unpacking
same register decoded four different addresses Transmit Transmit Data Registers
X:$FFFF94
STXA
Receive
Receive Data Registers Address X:$FFFF98 X:$FFFF9A Read Reset xxxxxx X:$FFFF9A X:$FFFF99 X:$FFFF98
Packing Note: same register decoded three different addresses Receive Data Registers
Figure D-18 Receive Transmit Data Registers (SRX, TRX)
D-32
DSP56302UM/AD
PROGRAMMING REFERENCE
Application:
Date: Programmer:
Sheet
Timers
(1:0) Prescaler Clock Source Internal CLK/2 TIO0 TIO1 TIO2
Prescaler Preload Value [0:20])
Timer Prescaler Load Register TPLR:$FFFF83 Read/Write Reset $000000
Reserved, Program
Timer Prescaler Count Register TPCR:$FFFF82 Read Only Reset $000000
Current Value Prescaler Counter [0:20])
Reserved, Program
Figure D-19 Timer Prescaler Load/Count Register (TPLR, TPCR)
DSP56302UM/AD
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Timers
Inverter to-1 transitions input increment counter, high pulse width measured, high pulse output 1-to-0 transitions input increment counter, pulse width measured, pulse output
Timer Reload Mode Timer operates free running counter Timer reloaded when selected condition occurs Direction input output Data Input Zero read read Data Output Zero written written Prescaled Clock Enable Clock source CLK/2 Clock source prescaler output Timer Compare Flag been written TCSR(TCF), timer compare interrupt serviced Timer Compare occurred Timer Overflow Flag been written TCSR(TOF), timer Overflow interrupt serviced Counter wraparound occurred
(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Timer Control Bits (TC0 TC3) Clock Mode GPIO Internal Timer Output Internal Timer Pulse Output Internal Timer Toggle Input External Event Counter Input Internal Input Width Input Internal Input Period Input Internal Capture Output Internal Pulse Width Modulation Reserved Output Internal Watchdog Pulse Output Internal Watchdog Toggle Reserved Reserved Reserved Reserved Reserved Timer Enable Timer Disabled Timer Enabled Timer Overflow Interrupt Enable Overflow Interrupts Disabled Overflow Interrupts Enabled
Timer Compare Interrupt Enable Compare Interrupts Disabled Compare Interrupts Enabled
TCIE TQIE
Timer Control/Status Register TCSR0:$FFFF8F Read/Write TCSR1:$FFFF8B Read/Write TCSR2:$FFFF87 Read/Write Reset $000000
Reserved, Program
Figure D-20 Timer Control/Status Register (TCSR)
D-34
DSP56302UM/AD
PROGRAMMING REFERENCE
Application:
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Timers
Timer Reload Value
Timer Load Register TLR0:$FFFF8E Write Only TLR1:$FFFF8A Write Only TLR2:$FFFF86 Write Only Reset $000000
Value Compared Counter Value
Timer Compare Register TCPR0:$FFFF8D Read/Write TCPR1:$FFFF89 Read/Write TCPR2:$FFFF85 Read/Write Reset $000000
Timer Count Value
Timer Count Register TCR0:$FFFF8C Read Only TCR1:$FFFF88 Read Only TCR2:$FFFF84 Read Only Reset $000000
Figure D-21 Timer Load, Compare, Count Registers (TLR, TCPR, TCR)
DSP56302UM/AD
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GPIO
Port (HI08)
Host Data Direction Register (HDDR) X:$FFFFC8 Write Reset
DR15
DR12
DR11
DR10
DR14 DR13
Output
Input
Host Data Register (HDR) X:$FFFFC9 Write Reset Undefined
holds value corresponding HI08 GPIO pin. Function depends HDDR.
Figure D-22 Host Data Direction Host Data Registers (HDDR, HDR)
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PROGRAMMING REFERENCE
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GPIO
Port Control Register (PCRC) X:$FFFFBF ReadWrite Reset
Port (ESSI0)
Port configured ESSI Port configured GPIO
Port Direction Register (PRRC) X:$FFFFBE ReadWrite Reset
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
PDCn Port Output PDCn Port Input
Port GPIO Data Register (PDRC) X:$FFFFBD ReadWrite Reset
port GPIO input, then reflects value port port GPIO output, then value written reflected port
Reserved, Program
Figure D-23 Port Registers (PCRC, PRRC, PDRC)
DSP56302UM/AD
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GPIO
Port Control Register (PCRD) X:$FFFFAF ReadWrite Reset
Port (ESSI1)
Port configured ESSI Port configured GPIO
Port Direction Register (PRRD) X:$FFFFAE ReadWrite Reset
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
PDCn Port Output PDCn Port Input
Port GPIO Data Register (PDRD) X:$FFFFAD ReadWrite Reset
port GPIO input, then reflects value port port GPIO output, then value written reflected port
Reserved, Program
Figure D-24 Port Registers (PCRD, PRRD, PDRD)
D-38
DSP56302UM/AD
PROGRAMMING REFERENCE
Application:
Date: Programmer:
Sheet
GPIO
Port Control Register (PCRE) X:$FFFF9F ReadWrite Reset
Port (SCI)
Port configured Port configured GPIO
Port Direction Register (PRRE) X:$FFFF9E ReadWrite Reset
PDC2
PDC1
PDC0
PDCn Port Output PDCn Port Input
Port GPIO Data Register (PDRE) X:$FFFF9D ReadWrite Reset
port GPIO input, then reflects value port port GPIO output, then value written reflected port
Reserved, Program
Figure D-25 Port Registers (PCRE, PRRE, PDRE)
DSP56302UM/AD
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PROGRAMMING REFERENCE
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DSP56302UM/AD

DSP56302UM/AD PROGRAMMING REFERENCE INTRODUCTION INTERNAL ME

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