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Appendix Programming Reference
This reference programmers includes table showing addresses memory-mapped peripherals, exception priority table, programming sheets major programmable registers. programming sheets grouped following order: central processor, Phase Lock Loop, (PLL), Enhanced Synchronous Serial Interface (ESSI), Serial Communication Interface (SCI), Timer, GPIO. Each sheet provides room write value each hexadecimal value each register. photocopy these sheets reuse them each application development project. details instruction DSP56300 family DSPs, DSP56300 Family Manual. Note that there programmer's reference HI32 HI32 chapter.
Table B-2, "Internal Memory Map," page lists memory addresses on-chip peripherals. Table B-3, "Interrupt Sources," page lists interrupt starting addresses sources. Table B-4, "Interrupt Source Priorities Within IPL," page lists priorities specific interrupts within interrupt priority levels. programming sheets appear this manual figures (listed Table B-1); they show major programmable registers DSP56301.
Table B-1. Guide Programming Sheet
Module
Programming Sheet Figure B-1, "Status Register (SR)" Figure B-2, "Operating Mode Register" Figure B-3, "Address Attribute Registers (AAR3 AAR0)"
Page page B-11 page B-12 page B-13 page B-14 page B-15 page B-16 page B-17 page B-18
Central Processor
Figure B-4, "Bus Control Register (BCR)" Figure B-5, "DRAM Control Register (DCR)" Figure B-6, "DMA Control Register (DCR)" Figure B-7, "Interrupt Priority Register-Core (IPR-C)" Figure B-8, "Interrupt Priority Register Peripherals (IPR-P)"
Motorola
Programming Reference
Internal Memory
Table B-1. Guide Programming SheetPLL Figure B-9, "Phase Lock Loop Control Register (PCTL)" Figure B-10, "ESSI Control Register (CRAx)" Figure B-11, "ESSI Control Register (CRBx)" ESSI Figure B-12, "ESSI Status Register (SSISR)" Figure B-13, "ESSI Transmit Receive Slot Mask Registers (TSM, RSM)" Figure B-14, "SCI Control Register (SCR)" Figure B-15, "SCI Status Clock Control Registers (SSR, SCCR)" Figure B-16, "SCI Receive Transmit Data Registers (SRX, TRX)" Figure B-17, "Timer Prescaler Load/Count Register (TPLR, TPCR)" Timers Figure B-18, "Timer Control/Status Register (TCSR)" Figure B-19, "Timer Load, Compare, Count Registers (TLR, TCPR, TCR)" Figure B-21, "DSP Control Register (DPCR)" HI32 Host Interface Figure B-20, "DSP Control Register (DCTR)" Figure B-22, "Host Interface Status Register (HSTR)" Figure B-23, "Host Interface Control Register (HCTR)" Figure B-24, "DSP Host Port GPIO Direction Data Registers, DIRH DATH" GPIO Figure B-25, "Port Registers (PCRC, PRRC, PDRC)" Figure B-26, "Port Registers (PCRD, PRRD, PDRD)" Figure B-27, "Port Registers (PCRE, PRRE, PDRE)" page B-22 page B-23 page B-24 page B-25 page B-26 page B-27 page B-28 page B-29 page B-31 page B-30 page B-32 page B-33 page B-34 page B-35 page B-36 page B-37 page B-19 page B-20 page B-21
Internal Memory
Table B-2. Internal Memory
Peripheral 16-Bit Address $FFFF $FFFE OnCE $FFFD $FFFC $FFFB $FFFA $FFF9 $FFF8 $FFF7 $FFF6 $FFF5 24-Bit Address $FFFFFF $FFFFFE $FFFFFD $FFFFFC $FFFFFB $FFFFFA $FFFFF9 $FFFFF8 $FFFFF7 $FFFFF6 $FFFFF5 Register Name Interrupt Priority Register Core (IPR-C) Interrupt Priority Register Peripheral (IPR-P) Control Register (PCTL) OnCE Register (OGDB) Control Register (BCR) DRAM Control Register (DCR) Address Attribute Register (AAR0) Address Attribute Register (AAR1) Address Attribute Register (AAR2) Address Attribute Register (AAR3) Register (IDR)
DSP56301 User's Manual
Motorola
Internal Memory
Table B-2. Internal Memory (Continued)
Peripheral 16-Bit Address $FFF4 $FFF3 $FFF2 $FFF1 $FFF0 DMA0 $FFEF $FFEE $FFED $FFEC DMA1 $FFEB $FFEA $FFE9 $FFE8 DMA2 $FFE7 $FFE6 $FFE5 $FFE4 DMA3 $FFE3 $FFE2 $FFE1 $FFE0 DMA4 $FFDF $FFDE $FFDD $FFDC DMA5 $FFDB $FFDA $FFD9 $FFD8 24-Bit Address $FFFFF4 $FFFFF3 $FFFFF2 $FFFFF1 $FFFFF0 $FFFFEF $FFFFEE $FFFFED $FFFFEC $FFFFEB $FFFFEA $FFFFE9 $FFFFE8 $FFFFE7 $FFFFE6 $FFFFE5 $FFFFE4 $FFFFE3 $FFFFE2 $FFFFE1 $FFFFE0 $FFFFDF $FFFFDE $FFFFDD $FFFFDC $FFFFDB $FFFFDA $FFFFD9 $FFFFD8 Register Name Status Register (DSTR) Offset Register (DOR0) Offset Register (DOR1) Offset Register (DOR2) Offset Register (DOR3) Source Address Register (DSR0) Destination Address Register (DDR0) Counter (DCO0) Control Register (DCR0) Source Address Register (DSR1) Destination Address Register (DDR1) Counter (DCO1) Control Register (DCR1) Source Address Register (DSR2) Destination Address Register (DDR2) Counter (DCO2) Control Register (DCR2) Source Address Register (DSR3) Destination Address Register (DDR3) Counter (DCO3) Control Register (DCR3) Source Address Register (DSR4) Destination Address Register (DDR4) Counter (DCO4) Control Register (DCR4) Source Address Register (DSR5) Destination Address Register (DDR5) Counter (DCO5) Control Register (DCR5)
Motorola
Programming Reference
Internal Memory
Table B-2. Internal Memory (Continued)
Peripheral 16-Bit Address $FFD7 $FFD6 $FFD5 $FFD4 $FFD3 $FFD2 $FFD1 $FFD0 PORT $FFCF $FFCE HI32 $FFCD $FFCC $FFCB $FFCA $FFC9 $FFC8 $FFC7 $FFC6 $FFC6 $FFC4 $FFC3 $FFC2 $FFC1 $FFC0 PORT $FFBF $FFBE $FFBD 24-Bit Address $FFFFD7 $FFFFD6 $FFFFD5 $FFFFD4 $FFFFD3 $FFFFD2 $FFFFD1 $FFFFD0 $FFFFCF $FFFFCE $FFFFCD $FFFFCC $FFFFCB $FFFFCA $FFFFC9 $FFFFC8 $FFFFC7 $FFFFC6 $FFFFC5 $FFFFC4 $FFFFC3 $FFFFC2 $FFFFC1 $FFFFC0 $FFFFBF $FFFFBE $FFFFBD Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Host Port GPIO Data Register (DATH) Host Port GPIO Direction Register (DIRH) Slave Transmit Data FIFO (DTXS) Master Transmit DATA FIFO (DTXM) Receive Data FIFO (DRXR) Status Register (DPSR) Status Register (DSR) Address Register (DPAR) Master Control Register (DPMC) Control Register (DPCR) Control Register (DCTR) Reserved Reserved Reserved Reserved Reserved Port Control Register (PCRC) Port Direction Register (PRRC) Port GPIO Data Register (PDRC) Register Name
DSP56301 User's Manual
Motorola
Internal Memory
Table B-2. Internal Memory (Continued)
Peripheral ESSI 16-Bit Address $FFBC $FFBB $FFBA $FFB9 $FFB8 $FFB7 $FFB6 $FFB5 $FFB4 $FFB3 $FFB2 $FFB1 $FFB0 PORT $FFAF $FFAE $FFAD 24-Bit Address $FFFFBC $FFFFBB $FFFFBA $FFFFB9 $FFFFB8 $FFFFB7 $FFFFB6 $FFFFB5 $FFFFB4 $FFFFB3 $FFFFB2 $FFFFB1 $FFFFB0 $FFFFAF $FFFFAE $FFFFAD Register Name ESSI Transmit Data Register (TX00) ESSI Transmit Data Register (TX01) ESSI Transmit Data Register (TX02) ESSI Time Slot Register (TSR0) ESSI Receive Data Register (RX0) ESSI Status Register (SSISR0) ESSI Control Register (CRB0) ESSI Control Register (CRA0) ESSI Transmit Slot Mask Register (TSMA0) ESSI Transmit Slot Mask Register (TSMB0) ESSI Receive Slot Mask Register (RSMA0) ESSI Receive Slot Mask Register (RSMB0) Reserved Port Control Register (PCRD) Port Direction Register (PRRD) Port GPIO Data Register (PDRD)
Motorola
Programming Reference
Internal Memory
Table B-2. Internal Memory (Continued)
Peripheral ESSI 16-Bit Address $FFAC $FFAB $FFAA $FFA9 $FFA8 $FFA7 $FFA6 $FFA5 $FFA4 $FFA3 $FFA2 $FFA1 $FFA0 PORT $FF9F $FF9E $FF9D $FF9C $FF9B $FF9A $FF99 $FF98 $FF97 $FF96 $FF95 $FF94 $FF93 $FF92 $FF91 $FF90 24-Bit Address $FFFFAC $FFFFAB $FFFFAA $FFFFA9 $FFFFA8 $FFFFA7 $FFFFA6 $FFFFA5 $FFFFA4 $FFFFA3 $FFFFA2 $FFFFA1 $FFFFA0 $FFFF9F $FFFF9E $FFFF9D $FFFF9C $FFFF9B $FFFF9A $FFFF99 $FFFF98 $FFFF97 $FFFF96 $FFFF95 $FFFF94 $FFFF93 $FFFF92 $FFFF91 $FFFF90 Register Name ESSI Transmit Data Register (TX10) ESSI Transmit Data Register (TX11) ESSI Transmit Data Register (TX12) ESSI Time Slot Register (TSR1) ESSI Receive Data Register (RX1) ESSI Status Register (SSISR1) ESSI Control Register (CRB1) ESSI Control Register (CRA1) ESSI Transmit Slot Mask Register (TSMA1) ESSI Transmit Slot Mask Register (TSMB1) ESSI Receive Slot Mask Register (RSMA1) ESSI Receive Slot Mask Register (RSMB1) Reserved Port Control Register (PCRE) Port Direction Register (PRRE) Port GPIO Data Register (PDRE) Control Register (SCR) Clock Control Register (SCCR) Receive Data Register High (SRXH) Receive Data Register Middle (SRXM) Recieve Data Register (SRXL) Transmit Data Register High (STXH) Transmit Data Register Middle (STXM) Transmit Data Register (STXL) Transmit Address Register (STXA) Status Register (SSR) Reserved Reserved Reserved
DSP56301 User's Manual
Motorola
Interrupt Sources Prioritie
Table B-2. Internal Memory (Continued)
Peripheral Triple Timer 16-Bit Address $FF8F $FF8E $FF8D $FF8C $FF8B $FF8A $FF89 $FF88 $FF87 $FF86 $FF85 $FF84 $FF83 $FF82 $FF81 $FF80 24-Bit Address $FFFF8F $FFFF8E $FFFF8D $FFFF8C $FFFF8B $FFFF8A $FFFF89 $FFFF88 $FFFF87 $FFFF86 $FFFF85 $FFFF84 $FFFF83 $FFFF82 $FFFF81 $FFFF80 Register Name Timer Control/Status Register (TCSR0) Timer Load Register (TLR0) Timer Compare Register (TCPR0) Timer Count Register (TCR0) Timer Control/Status Register (TCSR1) Timer Load Register (TLR1) Timer Compare Register (TCPR1) Timer Count Register (TCR1) Timer Control/Status Register (TCSR2) Timer Load Register (TLR2) Timer Compare Register (TCPR2) Timer Count Register (TCR2) Timer Prescaler Load Register (TPLR) Timer Prescaler Count Register (TPCR) Reserved Reserved
Interrupt Sources PrioritieTable B-3. Interrupt SourceInterrupt Starting Address VBA:$00 VBA:$02 VBA:$04 VBA:$06 VBA:$08 VBA:$0A VBA:$0C VBA:$0E VBA:$10 VBA:$12 Interrupt Priority Level Range Hardware RESET Stack error Illegal instruction Debug request interrupt Trap Nonmaskable interrupt (NMI) Reserved Reserved
Interrupt Source
IRQA IRQB
Motorola
Programming Reference
Interrupt Sources Prioritie
Table B-3. Interrupt Sources (Continued)
Interrupt Starting Address VBA:$14 VBA:$16 VBA:$18 VBA:$1A VBA:$1C VBA:$1E VBA:$20 VBA:$22 VBA:$24 VBA:$26 VBA:$28 VBA:$2A VBA:$2C VBA:$2E VBA:$30 VBA:$32 VBA:$34 VBA:$36 VBA:$38 VBA:$3A VBA:$3C VBA:$3E VBA:$40 VBA:$42 VBA:$44 VBA:$46 VBA:$48 VBA:$4A VBA:$4C VBA:$4E VBA:$50 VBA:$52 VBA:$54 Interrupt Priority Level Range
Interrupt Source
IRQC IRQD
channel channel channel channel channel channel TIMER compare TIMER overflow TIMER compare TIMER overflow TIMER compare TIMER overflow ESSI0 receive data ESSI0 receive data with exception status ESSI0 receive last slot ESSI0 transmit data ESSI0 transmit data with exception status ESSI0 transmit last slot Reserved Reserved ESSI1 receive data ESSI1 receive data with exception status ESSI1 receive last slot ESSI1 transmit data ESSI1 transmit data with exception status ESSI1 transmit last slot Reserved Reserved receive data receive data with exception status transmit data
DSP56301 User's Manual
Motorola
Interrupt Sources Prioritie
Table B-3. Interrupt Sources (Continued)
Interrupt Starting Address VBA:$56 VBA:$58 VBA:$5A VBA:$5C VBA:$5E VBA:$60 VBA:$62 VBA:$64 VBA:$66 VBA:$68 VBA:$6A VBA:$6C VBA:$6E VBA:$70 VBA:$72 VBA:$74 VBA:$FE Interrupt Priority Level Range idle line timer assigned assigned assigned Host transaction termination Host transaction abort Host parity error Host transfer complete Host master receive request Host slave receive request Host master transmit request Host slave transmit request Host master address request Host command Host (default) assigned assigned
Interrupt Source
Table B-4. Interrupt Source Priorities Within
Priority Interrupt Source Level (nonmaskable) Highest Hardware RESET Stack error Illegal instruction Debug request interrupt Trap Nonmaskable interrupt Lowest Nonmaskable Host Command Interrupt Levels (maskable) IRQA (external interrupt) IRQB (external interrupt) IRQC (external interrupt) IRQD (external interrupt)
Motorola
Programming Reference
Interrupt Sources Prioritie
Table B-4. Interrupt Source Priorities Within (Continued)
Priority Highest channel interrupt channel interrupt channel interrupt channel interrupt channel interrupt channel interrupt Host command interrupt Host Transaction Termination Host Transaction Abort Host Parity Error Host Transfer Complete Host Master Receive Request Host Slave Receive Request Host Master Transmit Request Host Slave Transmit Request Host Master Address Request ESSI0 data with exception interrupt ESSI0 data interrupt ESSI0 receive last slot interrupt ESSI0 data with exception interrupt ESSI0 transmit last slot interrupt ESSI0 data interrupt ESSI1 data with exception interrupt ESSI1 data interrupt ESSI1 receive last slot interrupt ESSI1 data with exception interrupt ESSI1 transmit last slot interrupt ESSI1 data interrupt receive data with exception interrupt receive data transmit data idle line timer TIMER0 overflow interrupt TIMER0 compare interrupt TIMER1 overflow interrupt TIMER1 compare interrupt TIMER2 overflow interrupt Lowest TIMER2 compare interrupt Interrupt Source
B-10
DSP56301 User's Manual
Motorola
Programming Sheet
Programming Sheet
Central Processor
Unnormalized Extension Limit Scaling
Scaling Mode Scaling Mode scaling Scale down Scale Reserved Interrupt Mask Exceptions Masked None
Carry Over?ow Zero Negative
Sixteen-Bit Compatibility Double-Precision Multiply Mode Loop Flag Forever Flag Sixteenth-Bit Arithmetic Instruction Cache Enable Arithmetic Saturation Rounding Mode
Core Priority CP[1 Core Priority (lowest) (highest)
Extended Mode Register (MR)
Mode Register (MR)
Condition Code Register (CCR)
Status Register (SR) Read/Write Reset $C00300
Reserved, Program
Figure B-1. Status Register (SR)
Motorola
Programming Reference
B-11
Programming Sheet
Central Processor
Asynchronous Arbitration Enable, Synchronization disabled Synchronization enabled Address Attribute Priority Disable, Priority mechanism enabled Priority mechanism disabled Address Trace Enable, Address Trace mode disabled Address Trace mode enabled Stack Extension Select, Mapped memory Mapped memory Stack Extension Underflow Flag, stack underflow Stack underflow Stack Extension Overflow Flag, stack overflow Stack overflow Stack Extension Wrap Flag, stack extension wrap Stack extension wrap (sticky bit) Stack Extension Enable, Stack extension disabled Stack extension enabled
Chip Operating Mode, Bits Refer operating modes table Chapter External Disable, Enables external Disables external
Stop Delay Mode, Delay 128K clock cycles Delay clock cycless Memory Switch Mode, Memory switching disabled Memory switching enabled Core-DMA Priority, Bits CPD[1:0] Description Compare SR[CP] active channel priority higher priority than core same priority core lower priority than core Cache Burst Mode Enable, Burst Mode disabled Burst Mode enabled Synchronize Select, synchronized Synchronized Release Timing, Fast Release mode Slow Release mode
CPD1 CPD0
System Stack Control Status (SCS)
Extended Chip Operating Mode (EOM)
Chip Operating Mode (COM)
Operating Mode Register Reset $000300
Reserved, Program
DSP56301 User's Manual Motorola
Figure B-2. Operating Mode Register
B-12
Programming Sheet
Central Processor
Data Memory Enable, Disable logic during external data space accesses Enable logic during external data space accesses Data Memory Enable, Disable logic during external data space accesses Enable logic during external data space accesses Program Memory Enable, Disable logic during external program space accesses Enable logic during external program space accesses Address Attribute Polarity, AA/RAS signal active AA/RAS signal active high Access Type, Bits (Combinations BNC[3 1111, 1110, 1101 reserved.) BAT[1 Encoding Reserved SRAM access DRAM access Reserved
Address Multiplexing, Eight LSBs address appear Eight LSBs address appear A[23
Packing Enable, Disable internal packing/unpacking logic Enable internal packing/unpacking logic
Number Address Bits Compare, Bits Number bits (from bits) that compared external addres
Address Compare, Bits Address compare external address order decide whether assert
BPAC BYEN BXENBPEN BAAP
Address Attribute Registers (AAR3 AAR0) Reset $000000
Figure B-3. Address Attribute Registers (AAR3 AAR0)
Motorola
Programming Reference
B-13
Programming Sheet
Central Processor
NOTE: bits read/write control bits, except BBS, which read-only.
State,
master master Default Area Wait Control, Bits Area Wait Control, Bits Area Wait Control, Bits Area Wait Control, Bits Area Wait Control, Bits These read/write control bits define number wait states inserted into each external SRAM access designated area. value these bits should programmed zero. Number wait states: BDFW[20 BA3W[15
Lock Hold,
asserted only attempted readwrite modify external access always asserted
BA2W[12 BA1W[9 BA0W[4
Request Hold,
asserted only attempted pending access always asserted
BDFWBDFW BDFWBDFWBDFWBA3W BA3W BA3W BA2W BA2W BA2W BA1W BA2WBA1W BA1WBA1W BA0W BA0W BA0WBA0W BA0W
Control Register (BCR) Reset $1FFFFF
Figure B-4. Control Register (BCR)
B-14
DSP56301 User's Manual
Motorola
Programming Sheet
Central Processor
Software-Triggered Refresh, Disables software-triggered refresh Enables software-triggered refresh
Refresh Enable, Refresh disable Refresh enable Mastership Enable, DRAM refresh requires mastership DRAM refresh does require mastership Page Logic Enable, Disable in-page identifying logic Enable in-page identifying logic DRAM Page Size, Bits BPS[1:0] Column Address Width bits bits bits bits DRAM Page Size 512K
Out-Of-Page Wait States, Bits BRW[1:0] DRAM External Access w.s. each out-of-page access w.s. each out-of-page access w.s. each out-of-page access w.s. each out-of-page acces
Refresh Rate, Bits Specify divide rate (BRF[7:0] $00) (BRF[7:0] $FF). Refresh Prescaler, Bypass prescaler Connect prescaler
In-Page Wait States, Bits BCW[1:0] DRAM External Access w.s. each in-page access w.s. each in-page access w.s. each in-page access w.s. each in-page acces
BSTR BREN BPLE
BCWBCW
DRAM Control Registers (DCR) Reset $000000
Reserved, Program
Figure B-5. DRAM Control Register (DCR)
Motorola
Programming Reference
B-15
Programming Sheet
Central Processor
Request Source, Bits Chapter Section 4.3, Table 4-6.
Three-Dimensional Mode, Three-Dimensional mode disabled Three-Dimensional mode enabled Address Mode, Bits Non-Three-Dimensional Addressing Modes (D3D=0) DAM[2 source DAM[5 Destination Offset Register Selection DOR0 DOR1 DOR2 DOR3 None None
Continuous Mode Enable, Disables continuous mode Enables continuous mode Channel Priority, Bits DPR[1:0] Channel Priority Priority level (lowest) Priority level Priority level Priority level (highest)
DAM[5:3] Addressing Counter DAM[2:0] Mode Mode update PostincrementA by-1 reserved reserved
Three-Dimensional Addressing Modes (D3D= DAM[5:3] Addressing Mode update Postincrement-by1 Offset Selection DOR0 DOR1 DOR2 DOR3 None None DOR0: DOR1 DOR2: DOR3
Transfer Mode, Bits DTM[2:0] Triggered request request request request request reserved reserved Cleared Transfer Mode block transfer word transfer line transfer block transfer block transfer word transfer
Destination Space, Bits DSS[1:0] Destination Memory Memory Space Memory Space Memory Space Reserved
Interrupt Enable, Disables Interrupt Enables interrupt Channel Enable, Disables channel operation Enables channel operation
Source Space, Bits DSS[1:0] Source Memory Memory Space Memory Space Memory Space Reserved
DDDDPR DCON
Control Registers (DCR5 DCR0) Reset $000000
Figure B-6. Control Register (DCR)
B-16 DSP56301 User's Manual Motorola
Motorola
Central Processor
IRQA Mode
IAL2 XXL1 XXL0 Enabled IBL2 Trigger Level Neg. Edge IAL1 IAL0 Enabled ICL1 ICL0
Figure B-7. Interrupt Priority Register-Core (IPR-C)
IRQC Mode
ICL2 Trigger Level Neg. Edge
Programming Reference B-17
IRQB Mode
Trigger Level Neg. Edge
IRQD Mode
IDL2 Trigger Level Neg. Edge
IBL1 IDL1
IBL0 IDL0
Enabled
Interrupt Priority Register (IPR-C)
X:$FFFFFF Read/Write Reset $000000
D5L1 D5L0 D4L1 D4L0 D3L1 D3L0 D2L1 D2L0 D1L1 D1L0 D0L1 D0L0 IDL2 IDL1
Programming Sheet
IDL0 ICL2 ICL1 ICL0 IBL2 IBL1 IBL0 IAL2 IAL1 IAL0
B-18
Programming Sheet
Central Processor
Figure B-8. Interrupt Priority Register Peripherals (IPR-P)
Timer
T0L1 T0L0 Enabled S1L1
ESSI1
S1L0 Enabled
Host
HPL1 HPL0 Enabled
SCL1 SCL0 Enabled S0L1
ESSI0
S0L0 Enabled
DSP56301 User's Manual Motorola
Interrupt Priority Register (IPR-P)
X:$FFFFFE Read/Write Reset $000000
**************
T0L1 T0L0 SCL1 SCL0 S1L1 S1L0 SOL1 S0L0 HPL1 HPL0
Reserved, Program
Motorola
XTAL Disable (XTLD) Enable XTALOscillator EXTAL Driven From External Source Crystal Range (XTLR) External Xtal Freq> 200KHz External Xtal Freq 200KHz Multiplication Factor Bits MF11 MF11 Multiplication Factor $000 $001 $002 $FFF 4095 $FFF 4096 Division Factor Bits (DF0 DF2) Division Factor
PSTP Relationship Operation During STOP PSTP Oscillator Disabled Disabled Disabled Enabled Enabled Enabled
Clock Output Disable (COD)
Duty Cycle Clock
Figure B-9. Phase Lock Loop Control Register (PCTL)
Programming Reference
PSTP XTLD XTLR
Held High State
Predivision Factor Bits (PD0 PD3) Predivision Factor
MF11 MF10
Control Register (PCTL)
Programming Sheet
X:$FFFFFD Read/Write Reset $000000
B-19
B-20
Word Length Control Number bits/word (data first bits) (data last bits) Reserved Reserved ESSI Control Register (CRAx) ESSI0 X:$FFFFB5 Read/Write ESSI1 X:$FFFFA5 Read/Write Reset $000000 Alignment Control 16-bit data left aligned 16-bit data left aligned Frame Rate Divider Control DC4:0 $00-$1F Divide ratio Normal mode time slots Network PM[7:0] forbidden Prescaler Range Prescale Modulus Select PM7:0 $00-$FF 256)
Programming Sheet
ESSI
Figure B-10. ESSI Control Register (CRAx)
DSP56301 User's Manual
Select Tx#0 drive enable functions serial flag functions driver enable Tx#0 external buffer
SSC1
Reserved, Program
Motorola
Motorola
Frame Sync Relative Timing Frame Sync only) with data clock cycle earlier than data FSL1 FSL0 Frame Sync Length Word Word Word Word Output Flag Bits SCD1
ESSI
Frame Sync Polarity, high level (positive) level (negative)
Clock Polarity (clk edge data Frame Sync clocked out/in) rising falling rising falling
Sync/Async Control transfer together not) Asynchronous Synchronou
Mode Select, Normal Network
Transmit Enable (SYN=1 only) Disable Enable Input
Serial Control Direction, Bits Output
Transmit Enable (SYN=1 only) Disable Enable
Transmit Enable, Disable Enable
Shift Direction, First First Clock Source Direction, External Clock Internal Clock
ipper2
Receiver Enable, Disable Enable
Transmit Interrupt Enable, Disable Enable
Figure B-11. ESSI Control Register (CRBx)
Programming Reference
REIE TEIE RLIE TLIE
Receive Interrupt Enable, Disable Enable
Transmit Last Slot Interrupt Enable Disable Enable
Receive Last Slot Interrupt Enable Disable Enable
Transmit Exception Interrupt Enable Disable Enable
Receive Exception Interrupt Enable Disable Enable
FSL1 FSL0 SHFD SCKD SCD2 SCD1 SCD0
Programming Sheet
ESSI Control Register (CRBx) ESSI0 X:$FFFFB6 Read/Write ESSI1 X:$FFFFA6 Read/Write Reset $000000
B-21
Programming Sheet
ESSI
Serial Input Flag SCD0 latch Serial Input Flag SCD1 latch Transmit Frame Sync, Sync Inactive Sync Active Receive Frame Sync, Wait Frame Sync Occurred Transmitter Underrun Error Flag, Error Receiver Overrun Error Flag, Error Transmit Data Register Empty, Wait Write Receive Data Register Full, Wait Read
ESSI Status Register (SSISRx) ESSI0 $FFFFB7 (Read) ESSI1 $FFFFA7 (Read)
Status
Reserved, program
Figure B-12. ESSI Status Register (SSISR)
B-22
DSP56301 User's Manual
Motorola
Programming Sheet
ESSI
ESSI Transmit Slot Mask TSMAx ESSI0 $FFFFB4 Read/Write ESSI1 $FFFFA4 Read/Write Reset $FFFF
ESSI Transmit Slot Mask Ignore Time Slot Active Time Slot
TS15 TS14 TS13 TS12 TS11 TS10
ESSI Transmit Slot Mask
ESSI Transmit Slot Mask Ignore Time Slot Activ Time Slot
Reserved, Program
ESSI Transmit Slot Mask TSMBx ESSI0 $FFFFB3 Read/Write ESSI1 $FFFFA3 Read/Write Reset $FFFF
TS31 TS30 TS29 TS28 TS27 TS26 TS25 TS24 TS23 TS22 TS21 TS20 TS19 TS18 TS17 TS16
ESSI Transmit Slot Mask
ESSI Receive Slot Mask Ignore Time Slot Active Time Slot
Reserved, Program
ESSI Receive Slot Mask RSMAx ESSI0 $FFFFB2 Read/Write ESSI1 $FFFFA2 Read/Write Reset $FFFF
RS15 RS14 RS13 RS12 RS11 RS10
ESSI Receive Slot Mask
ESSI Receive Slot Mask Ignore Time Slot Active Time Slot
Reserved, Program
ESSI Receive Slot Mask RSMBx ESSI0 $FFFFB1 Read/Write ESSI1 $FFFFA1 Read/Write Reset $FFFF
RS31 RS30 RS29 RS28 RS27 RS26 RS25 RS24 RS23 RS22 RS21 RS20 RS19 RS18 RS17 RS16
Figure B-13.
Reserved, Program ESSI Transmit Receive Slot Mask Registers (TSM, RSM)
ESSI Receive Slot Mask
Motorola
Programming Reference
B-23
Programming Sheet
Port Control Register (PCRE) X:$FFFF9F Read/Write Reset $000000
Port Control General-Purpose
*************
Port Control Register (PCRE)
Reserved, Program
Transmitter Enable, Transmitter Disable Transmitter Enable Idle Line Interrupt Enable, Idle Line Interrupt Disabled Idle Line Interrupt Enabled Receive Interrupt Enable, Receive Interrupt Disabled Idle Line Interrupt Enabled Transmit Interrupt Enable, Transmit Interrupts Disabled Transmit Interrupts Enabled Timer Interrupt Enable, Timer Interrupts Disabled Timer Interrupts Enabled Timer Interrupt Rate, Clock Polarity, Clock Polarity Positive Clock Polarity Negative Receive Exception Inerrupt Receive Interrupt Disable Receive Interrupt Enable
Word Select, Bits 8-bit Synchronous Data (Shift Register Mode) Reserved 10-bit Asynchronous Start, Data, Stop) Reserved 11-bit Asynchronous Start, Data, Even Parity, Stop) 11-bit Asynchronous Start, Data, Parity, Stop) 11-bit Multidrop Start, Data, Data Type, Stop) Reserved Receiver Wakeup Enable receiver awakened Wakeup function enabled Wired-Or Mode Select Multidrop Point Point Receiver Enable Receiver Disabled Receiver Enabled Shift Direction First First
Send Break Send break, then revert Continually send breaks Wakeup Mode Select Idle Line Wakeup Address Wakeup
Control Register (SCR) Address X:$FFFF9C Read/Write Reset $000000
REIE SCKP STIR TMIE ILIE
WOMS WAKE SSFTD WDS2 WDS1 WDS0
Reserved, Program
Figure B-14. Control Register (SCR)
B-24
DSP56301 User's Manual
Motorola
Programming Sheet
Overrun Error Flag, error Overrun detected Parity Error Flag, error Incorrect Parity detected Framing Error Flag, error Stop detected Received Data Address Idle Line Flag, Idle detected Idle State Receive Data Register Full, Receive Data Register Empty Receive Data Register Full Transmitter Data Register Empty, Transmitter Data Register full Transmitter Data Register empty Transmitter Empty, Transmitter full Transmitter empty
Status Register (SSR) Address X:$FFFF93 Read Only Reset $000003
IDLE RDRF TDRE TRNE
Status Register (SSR)
Reserved, Program
Clock Divider, Bits CD11 Icyc Rate $000 Icyc/1 $001 Icyc/2 $002 Icyc/3 $FFE Icyc/4095 $FFF Icyc/4096
Clock Divider Bits Clock Clock SCLK Mode Internal Internal Output Synchronous/Asynchronous Internal External Input Asynchronous only External Internal Input Asynchronous only External External Input Synchronous/Asynchronous Transmit Clock Mode Source Internal clock Transmitter External clock from SCLK Receive Clock Mode/Source Internal clock Receiver External clock from SCLK
Clock Divider, Divide clock before feed SCLK Feed clock directly SCLK Clock Prescaler
Clock Control Register (SCCR) Address X:$FFFF9B Read/Write Reset $000003
CD11 CD10
Clock Control Register (SCCR)
Reserved, Program
Figure B-15. Status Clock Control Registers (SSR, SCCR)
Motorola
Programming Reference
B-25
Programming Sheet
Transmit Data Registers Address X:$FFFF95 X:$FFFF97 Write-only Reset xxxxxx X:$FFFF97 X:$FFFF96 X:$FFFF95 Unpacking
NOTE: same register decoded four different addresse
Transmit Transmit Data Register
X:$FFFF94
STXA
Receive
Receive Data Registers Address X:$FFFF98 X:$FFFF9A Read-only Reset xxxxxx X:$FFFF9A X:$FFFF99 X:$FFFF98
Packing
NOTE: same register decoded three different addresse
Receive Data Register
Figure B-16. Receive Transmit Data Registers (SRX, TRX)
B-26
DSP56301 User's Manual
Motorola
Programming Sheet
TimerPS (1:0) Prescaler Clock Source Internal CLK/2 TIO0 TIO1 TIO2
Prescaler Preload Value [0:20])
Timer Prescaler Load Register TPLR X:$FFFF83 Read/Write Reset $000000
Reserved, Program
Timer Prescaler Count Register TPCR X:$FFFF82 Read Only Reset $000000
Current Value Prescaler Counter [0:20])
Reserved, Program
Figure B-17. Timer Prescaler Load/Count Register (TPLR, TPCR)
Motorola
Programming Reference
B-27
Programming Sheet
Timer
Inverter, to-1 transitions input increment counter, high pulse width measured, high pulse output 1-to-0 transitions input increment counter, pulse width measured, pulse output
Timer Reload Mode, Timer operates free running counter Timer reloaded when selected condition occurs Direction, input output Data Input, Zero read read Data Output, Zero written written Prescaled Clock Enable, Clock source CLK/2 Clock source prescaler output Timer Compare Flag, been written TCSR(TCF), timer compare interrupt serviced Timer Compare occurred Timer Overflow Flag, been written TCSR(TOF), timer Overflow interrupt serviced Counter wraparound occurred
Timer Control Bits (TC0 TC3) (3:0) Clock Mode 0000 GPIO Internal Timer 0001 Output Internal Timer Pulse 0010 Output Internal Timer Toggle 0011 Input External Event Counter 0100 Input Internal Input Width 0101 Input Internal Input Period 0110 Input Internal Capture 0111 Output Internal Pulse Width Modulation 1000 Reserved 1001 Output Internal Watchdog Pulse 1010 Output Internal Watchdog Toggle 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved Timer Enable, Timer Disabled Timer Enabled Timer Overflow Interrupt Enable, Overflow Interrupts Disabled Overflow Interrupts Enabled Timer Compare Interrupt Enable, Compare Interrupts Disabled Compare Interrupts Enabled
****
TCIE TQIE
Timer Control/Status Register
TCSR0 X:$FFFF8F Read/Write TCSR1 X:$FFFF8B Read/Write TCSR2 X:$FFFF87 Read/Write Reset $000000
Reserved, Program
Figure B-18. Timer Control/Status Register (TCSR)
B-28
DSP56301 User's Manual
Motorola
Programming Sheet
Timer23 Timer Reload Value
Timer Load Register TLR0 X:$FFFF8E Write Only TLR1 X:$FFFF8A Write Only TLR2 X:$FFFF86 Write Only Reset $000000
Value Compared Counter Value
Timer Compare Register TCPR0 X:$FFFF8D Read/Write TCPR1 X:$FFFF89 Read/Write TCPR2 X:$FFFF85 Read/Write Reset $000000
Timer Count Value
Timer Count Register TCR0 X:$FFFF8C Read Only TCR1 X:$FFFF88 Read Only TCR2 X:$FFFF84 Read Only Reset $000000
Figure B-19. Timer Load, Compare, Count Registers (TLR, TCPR, TCR)
Motorola
Programming Reference
B-29
Programming Sheet
Host Processor (HI32)
Host Reset Polarity, HRST active high HI32 reset HRST high. HRST active HI32 reset HRST low.
Host Request Polarity, HDRQ active high. HDRQ active low. Host Transfer Acknowledge Polarity, active high. active low. Host Read/Write Polarity, Host-to-DSP direction HRW. Host-to-DSP direction high HRW.
Host Interrupt Request Handshake Mode, HIRQ asserted specified number core clock cycles, which CLAT[LT]. HIRQ negated when interrupt request source cleared.
Host Data Strobe Mode, Double-Strobe mode selected. Single-strobe mode selected.
Host Interrupt Request Drive Control, HIRQ open-drain output. HIRQ always driven.
Host Interrupt HINTA released. HINTA driven low. Host Flags, Bits Used DSP-to-host communication. cleared DSP, visible host
HI32 Mode, Bits Control HI32 operating modes, follows:
Slave Receive Interrupt Enable, SRRQ interrupt requests disabled. Core interrupt when DSR[SRRQ] set. Slave Transmit Interrupt Enable, STRQ interrupt requests disabled. Core interrupt when DSR[STRQ] set. Host Command Interrupt Enable, interrupt requests disabled. Core interrupt when DSR[HCP] set.
Terminate Reset Universal Enhanced Universal GPIO Self-Configuration Reserved Reserved
HIRD HIRH HRSP HDRPHRWP HRWP HDSM
****
HINT
SRIE STIE HCIE
Control Register (DCTR) Read/Write Address: FFFFC5 Reset $000000
bits mode setting bits (Bits work only Universal Mode (DCTR[HM]
Reserved, Program
Figure B-20. Control Register (DCTR)
B-30 DSP56301 User's Manual Motorola
Programming Sheet
Host Processor (HI32)
Master Transfer Terminate, idle state. Generates master-initiated transaction termination
Clear Transmitter, data transaction pending. Clears HI32 master-tohost data path.
Sytem Error Force, HI32 hardware controls HSERR pin. Pulse HSERR clock cycle.
Transfer Complete Interrupt Enable, Disables transfer complete interrupt requests. Enables transfer complete interrupt requests.
Master Access Counter Enable, Disables master access counter. Enables master access counter.
Transaction Termination Interrupt Enable, Disables transaction interrupt requests. Enables transaction interrupt requests.
Transaction Abort Interrupt Enable,
Master Wait State Disable, Enables insertion wait states. Disables insertion wait states.
Disables transaction abort interrupts. Enables transaction abort interrupts.
Parity Error Interrupt Enable,
Disables parity error interrupts. Enables parity error interrupts.
Receive Buffer Lock Enable, HDTC set. write access HTXR occur. HDTC set. write access HTXR cannot occur. Master Address Interrupt Enable,
Disables master address interrupts. Enables master address interrupts.
Master Receive Interrupt Enable, Disables master receive interrupts. Enables master receive interrupts. Master Transmit Interrupt Enable,
Insert Address Enable, Does write transaction address. Writes transaction address HTXR. (Ignored when HI32 mode. only when DPCR[RBLE]]
Disables master transmit interrupts. Enables master transmit interrupts.
TAIE
RBLE MWSD MACE
SERF CLRT
TCIE
TTIE
PEIE MAIE
MRIE MTIE
Control Register (DPCR) Address: X:FFFFC6 Read/Write Reset $000000
bits work only mode (DCTR[HM] $1).
Reserved, Program
Figure B-21. Control Register (DPCR)
Motorola Programming Reference B-31
Programming Sheet
Host Processor (HI32)
Host Processor Side
Host Request, TREQ RREQ HREQ cleared HRRQ=1 otherwise cleared HTRQ=1 otherwise cleared HTRQ=1 HRRQ=1 otherwise cleared
HREQ HINT
HRRQ HTRQ TRDY
Transmitter Ready, Host processor writes HTXR. HTXR DRXR empty.
Host Transmit Data Request,
Host Interrupt DCTR[HINT] cleared HINTA driven DCTR[HINT] HINTA driven DRXR filled host processor writes. Data transferred from HTXR DRXR.
Host Flags, Bits Indicates state DCTR[HF5 bits.
Host Receive Data Request, HRXS empty. Data transferred from DTXS HRXS read host.
Host Interface Status Register (HSTR) Read-only Reset $00000000
Reserved, Program
Figure B-22. Host Interface Status Register (HSTR)
B-32
DSP56301 User's Manual
Motorola
Programming Sheet
Host Processor (HI32)
Host Processor Side
Reserved, Program
TWSD
Target Wait State Disable, Disables wait states. Modes: only.
Host Semaphores, Bits Serve only read/write respository semaphors when multiple master hosts used. (UBM, PCI)
HTF1
HTF0
HRF1 HRF0
DMAE
RREQ TREQ
Host Receive Data Transfer Format, Bits Define data transfer formats DSP-to-host communication. (See table "Receive Transfer Data Rormats". Modes: UBM, Host Transmit Data Transfer Format, Bits Define data transfer formats host-to-DSP. Table Modes: UMB,
Transmit Request Enable, Host processor writes HTXR. HTXR DRXR empty. Modes: only (DCTR[HM] Receive Request Enable, Controls HIRQ HDRQ pins DSP-to-host data transfers. DMAE TREQ RREQ HIRQ HDRQ
negated (HRRQ, HTRQ polling) HTRQ host interrupt request enabled HRRQ, HTRQ interrupt requests enabled negated negated negated negated high impedance high impedance
Slave Fetch Type, Pre-fetch Fetch Modes: Enable, Used host enable ISA/EISA DMA-type accesses. text. Mode:
high impedance
Host Flags, Bits Used host-to-DSP communication. cleared host. Visible DSP.
Modes: UBM,
Host Interface Control Register (HCTR) Reset $00000000
NOTE: DCTR[HM]
high impedance HRRQ request enabled HTRQ request enabled HRRQ, HTRQ host requests enabled
Modes: only (DCTR[HM]
Figure B-23. Host Interface Control Register (HCTR)
Motorola Programming Reference B-33
Programming Sheet
GPIO
DIR23 DIR15 DIR7 DIR22 DIR14 DIR6 DIR21 DIR13 DIR5
Port (HI32)
DIR19 DIR11 DIR3
DIR18 DIR10 DIR2
DIR17 DIR9 DIR1
DIR16 DIR8 DIR0
DIR20 DIR12 DIR4
Host Port GPIO Direction Register (DIRH) Controls direction host port pins GPIO mode. Address: X:$FFFFCE Read/Write Reset: $000000
DAT23 DAT15 DAT7
DAT22 DAT14 DAT6
DAT21 DAT13 DAT5
DAT20 DAT12 DAT4
DAT19 DAT11 DAT3
DAT18 DAT10 DAT2
DAT17 DAT9 DAT1
DAT16 DAT8 DAT0
Host Port GPIO Data Register (DATH) Register which DSP56300 core reads data from writes data host port pins configured GPIO. Address:X:FFFFCF Read/Write Reset: $000000 DATH DIRH Functionality DATx DIRx GPIO Pin1 Read-only bit. value read binary value pin. corresponding configured input. Read/write bit. value written same value read. corresponding configured output, driven with data written DATx. Non-GPIO Pin1 Read-only bit. Does contain significant data. Read/write bit. value written same value read.
NOTE Defined selected mode
Figure B-24. Host Port GPIO Direction Data Registers, DIRH DATH
B-34 DSP56301 User's Manual Motorola
Programming Sheet
GPIO
Port Control Register (PCRC) X:$FFFFBF ReadWrite Reset
Port (ESSI0)
STD0 SRD0 SCK0 SC02 SC01 SC00
Port configured ESSI Port configured GPIO
Port Direction Register (PRRC) X:$FFFFBE ReadWrite Reset
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
PDCn Port Output PDCn Port Input
Port GPIO Data Register (PDRC) X:$FFFFBD ReadWrite Reset
port GPIO input, then reflects value port port GPIO output, then value written reflected port
Reserved, Program
Figure B-25. Port Registers (PCRC, PRRC, PDRC)
Motorola
Programming Reference
B-35
Programming Sheet
GPIO
Port Control Register (PCRD) X:$FFFFAF ReadWrite Reset
Port (ESSI1)
STD1 SRD1 SCK1 SC12 SC11 SC10
Port configured ESSI Port configured GPIO
Port Direction Register (PRRD) X:$FFFFAE ReadWrite Reset
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
PDCn Port Output PDCn Port Input
Port GPIO Data Register (PDRD) X:$FFFFAD ReadWrite Reset
port GPIO input, then reflects value port port GPIO output, then value written reflected port
Reserved, Program
Figure B-26. Port Registers (PCRD, PRRD, PDRD)
B-36
DSP56301 User's Manual
Motorola
Programming Sheet
GPIO
Port Control Register (PCRE) X:$FFFF9F ReadWrite Reset
Port (SCI)
SCLK
Port configured Port configured GPIO
Port Direction Register (PRRE) X:$FFFF9E ReadWrite Reset
PDC2
PDC1
PDC0
PDCn Port Output PDCn Port Input
Port GPIO Data Register (PDRE) X:$FFFF9D ReadWrite Reset
port GPIO input, then reflects value port port GPIO output, then value written reflected port
Reserved, Program
Figure B-27. Port Registers (PCRE, PRRE, PDRE)
Motorola
Programming Reference
B-37
Programming Sheet
B-38
DSP56301 User's Manual
Motorola
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