0.35µ CMOS Standard Cell ASICs Advance Information DS4830 Novembe
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GSC200 Series
0.35µ CMOS Standard Cell ASICs Advance Information
DS4830 November 1998
GSC200 standard cell ASIC family from Mitel Semiconductor standard cell product combining power, mixed voltage capability with very high density architecture 0.35µm process. broad cell library includes range complex embedded functions highdensity ROMs RAMs, well oscillators. These cells optimised easy synthesis, supported high quality design kits range industry standard tools providing risk solution faster time-to-market.
FEATURES
Three four layer metal 0.35µm (drawn) process Operation from 1.8V 3.6V High density 18,900 gates/mm2 gates 97ps gate delay 2-input NAND with loads (3.3V) power, 0.06µW/MHz/gate supply (NAND driving inputs) 3.3V capability same device tolerant inputs outputs Full cells direct synthesis Accurate delay modelling gates tracks with sign quality design libraries QuickSim Verilog VITAL libraries optimized synthesis Methodologies ensuring clock skew High density memories including single dual port Expanding range Mitel Semiconductor SystemBuilder soft hard cells complex functions including 85C30, 8051, 8251 devices OakDSPCore ARM7TDMIprogrammable cores Wide range packaging options including ball grid arrays Variable output speeds noise Supports IDDQ testing high reliability Operating range -55°C +125°C
BENEFITS
Fast customer time market Direct sign-off industry standard tools Comprehensive industry standard tools SystemBuildermegacell libraries World-wide design centre support Reliable prototype production delivery Dual silicon sources Cost -effective Solutions Optimised architecture high density silicon utilisation ISO9001 Factory with Statistical process control optimum yield
GSC200 SERIES
ADVANTAGES STANDARD CELL ARCHITECTURE
Using GSC200 represent significant saving chip area many designs, with D-types smaller than their gate array counterparts. GSC200 also offers wide range speed power options three different sizes 2-input NAND gate, example making synthesis retargetting existing technology easier quicker. Linear staggered pads available giving high density option suited application. building design from these cells, standard cell technology allows designer achieve similar chip size fully-handcrafted custom fraction time. small chip size means that GSC200 chips cost manufacture, while ability GSC200 designs include areas gate array logic allows designer retain flexibility last-minute design changes, rapid introduction derivative products.
CELL LIBRARIES
cell library optimized synthesis includes expanding range soft hard macros. Cells include basic logic, such inverters, NAND gates, adders, multiplexers, latches flip flops, choice drive strengths, allowing designers make trade-offs between speed, power silicon area. Memories macros also available from extensive SystemBuilder library including microprocessors, UARTs, core. wide range cells leads shorter design cycle times.
CLA200 Family Gate Arrays
High density array Metal-only customisation
ARM7
MVA200 Family Embedded Arrays
CLA200 base with embedded function blocks: Memory (ROM, SPRAM, DPRAM) Analog Functions Hard macros (e.g. RISC Core) Initial base all-layer: variants metal-only
ARM7
Logic
GSC200 Family Standard Cell
Optimised Low-level Standard Cell Library Embedded Blocks above Gives optimum size/power/performance All-layer customisation
Cell Cell Logic
Fig.1 Mitel Semiconductor 0.35µm ASIC Families
GSC200 SERIES
Cells GSC200 standard cell series libraries contain wide choice input, output bi-directional cells. GSC200 series I/Os have following features: Cell library contains distinct complete inputs, outputs bidirectionals allow direct synthesis Selectable output speeds allow designer maintain noise reduce number power supply pins output speed critical inputs have optional pullup, pulldown resistors have hold option hold input tristate applications Device interface logic with static power consumption while still benefiting from voltage, power core input output cells noninverting cells optimized 3.3V fully functional down 1.8V with derated current speed Device operate different voltage from device core Output currents 12mA supported from single cell 24mA current drive available Floppy disc/tape functions including controllers data separators Standard Serial Communications controllers including 85C30, 16C450, 16C550, 8251 8250 interface cores including PCMCIA, Ethernet, IEEE1284,
addition SystemBuilder library also contains range clearly defined functions that frequently required Systems Level Integration (SLI) ASICs. Please page Further functions continually being added. date list obtained from Mitel Semiconductor Sales Design Centre. Core ARM7 core offers following features: RISC core Operation 40MHz with 3.3V supply Hardware debug capabilities TDMI version Support `Thumb' instruction improvement code density over native code Efficient operation Software Development Toolkit with compiler, board development products available Notes `Thumb' operating mode uses subset standard instruction that been re-coded into wide op-codes. small amount additional logic decompresses these instructions back their 32bit equivalent real time execution. Mitel Semiconductor will supply datasheets behavioural VHDL models ARM7TDMI core SystemBuilder customers, will incorporate core itself hard macro layout stage embedded array cell-based device. OakDSPCoreOakDSPCore offers following features: 16-bit fixed point core, with modified Harvard architecture Power-saving modes portable applications Single cycle 36-bit Multiply-accumulate instruction User-configurable on-chip registers program/data memory Special support Operation 60MHz with 3.3V supply Expandable data Expandable program Please contact your Mitel Semiconductor Customer Service Centre more details programmable cores.
GSC200 four separate supply rails three rails, rail core, input buffers, output areas chip. intermediate buffer supply rail completely isolated very noise. This offers benefit good noise immunity with multiple supply voltage capability suit application. mixed 3.3V capability used power saving interfacing with 3.3V systems. tolerant input output cells also available offer advantages very power core whilst interfacing systems. Electrostatic discharge (ESD) protection built into input output cells, specified withstand least (human body model). structure process also highly resistant latch-up able withstand forward bias currents excess 200mA. SYSTEMBUILDER SystemBuilder library contains broad range macrofunctions designed improve designers efficiency. Most SystemBuilder macrofunctions supplied synthesizable models both VHDL Verilog. addition these macrofunctions fully supported with synthesis scripts, test-benches full documentation. More information provided SystemBuilder page SystemBuilder library includes following functions: ARM7TDMI RISC microprocessor core OakDSPCore- Core processor Standard Microprocessor Cores including 8048, 8051 8086 Standard Microprocessor peripherals including controllers, programmable interval timers, real time clock programmable interrupt controllers.
GSC200 SERIES
MEMORY BLOCKS
memory compiler (PMG) available which allows designers specify number bits words required. automatically create design views supported tools. Available memories, RAMs ROMs include Single port true dual port RAMs Single Port Flexible RAMs 128Kbits Word size from bits steps Address words Range options Wide operating range 3.6V 150°C Interface Simple clocked interface Input output buses Zero power (intrinsic leakage) Size Cycle time Access time Read power Write power Area 0.08 0.26 128K Bits mW/MHz mW/MHz Flexible ROMs 256kbits Word 64bits Address words Range options (16, Contact mask programming Interface Simple clocked interface Zero power Zero static power consumption (Intrinsic leakage) 150,000 Bits/mm2 Wide operating range 3.6V 150°C
ANALOG BLOCKS
Phase Locked Loop increasingly high clock rates used smaller technology devices give rise increased problems with clock delay clock skew. phase-locked loop (PLL) provides means synchronize internal clock edges. connection high speed clocks from external sources becoming significant problem high frequencies. solve this problem multiplying (relatively) speed off-chip clock provide high speed on-chip clock. GSC200 been designed internal loop stabilization filter. configured used either clock multiplication clock synchronization modes, following main features: Clock multiplication clock synchronization either external internal clocks Output clock frequencies from 10MHz 250MHz Phase alignment offset: ±0.3ns Phase alignment jitter: ±0.5ns power consumption: 20MHz input, 80MHz output frequency Cell area 0.2mm2 package count requirement Internal programmable divider clock multiplication between Integrated loop filter Operation from 3.6V supplies
Table.
Dual Port Same generator options operating range single port Full read write access from both ports Separate input output data buses Wide range instance sizes RAMs from 128KBits Word size from bits steps Address words Zero static power consumption (Intrinsic leakage) Wide operating range 3.6V 150°C
GSC200 SERIES
Oscillator Cells following crystal oscillators supported: 32kHz oscillator 10MHz oscillator 16MHz oscillator 25MHZ oscillator 30MHz overtone oscillator
Stage output grid
Features IDDQ test compatible Dual enable pins supports power down Iddq testing ENBO power down input clamp Operating range Supply voltage: 3.6V Overtone operation 60MHz supported
Stage output grid
CLOCK POWER DISTRIBUTION
known that large, complex designs working high speed vulnerable problems associated with poor clock power distribution. Mitel Semiconductor published design notes that describe approaches clock power distribution. Clock Distribution GSC200 series supports number clock distribution methodologies which implemented depending particular design tools being used designer. small designs with light clock load, single large buffer sufficient. large designs, with large clock loads, clock grid clock tree recommended avoid clock skew metal electromigration clock network. Clock trees either synthesized manually specified clock hierarchy designer. GSC200 Series clock grid methodology uses three stages buffers, where each stage drives grid which feeds next stage cells (Fig.
Stage output grid
Fig.
GSC200 series utilises grid methodology power distribution. This grid, which automatically constructed during layout, uses metal layers three horizontal power rails metal layer vertical connections. Metal layer four also available vertical connections, which useful some larger devices. Methods implementation available with flat layout, manual methods, hierarchical layout. Advanced Delay Modelling Delay calculation includes following features: Edge speed modelling timings Non-linear delay modelling Accurate delay derating Conditional delay modelling
Stage Stage Stage
Fig.
final stage grid starting point routing actual clocked inputs. Fig. illustrates each buffer stage, which generated layout. Power Distribution GSC200 used from 3.3V, giving great flexibility supply voltage. Core supply chosen from nominal 3.3V, with mixed voltage available core supply cells available either CMOS compatible supply configurations.
Delays Delay models times between individual input output pins both rising falling delays, illustrated Fig. below.
Fig.
GSC200 SERIES
Calculation uses individual delays, e.g. which improves simulation accuracy modelling considerable variation delay between different input pins. complex gates (e.g. AND-NOR gates adders) variation 40%. simple NAND logic gates typical variation 20%. Non-linear delay modelling fast input edges (0.5ns) delay time increases linearly with output load, whereas high output loads delay increases linearly with edge speed. Delays slow input edges light input loads follow linear model, simple linear model cannot represent delays accurately. more complex equation, which includes interaction between edge load factors, used model delays. Thermal Management increase speed density available through advanced CMOS processes results corresponding increase power dissipation. Designs have more than half million used gates chip power consumption important issue. GSC200 series offers following: Lower power CMOS improved thermal management Software constructed power grids efficient power distribution Copper lead frame QFPs lower thermal resistance High pinout power packages Design Review Held beginning design cycle check agree performance, packaging, specification design time scales Design Review Held after logic simulation prior layout ensure satisfactory functionality, timing performance adequate fault coverage Design Review Held after layout post layout simulation verification. This checks correct performance with actual track loads. This final check device specifications prior prototype manufacture
SUPPORT
GSC200 series supported comprehensive design kits industry standard design tools, including Mentor Graphics, Cadence Design Systems, Synopsys. VITAL-compliant library also available. Features design kits include: Sign-off simulation with Mentor Cadence VITAL sign-off with Synopsys Full top-down design flow support Synthesis with Synopsys, Mentor Cadence Electrical Rule Checks (ERC) Paracell Model Generator (PMG) VIEWLOGIC simulator supported Sunrise ATPG supported Advanced Pin-to-Pin Delay modelling Direct routes layout test
DESIGN SUPPORT
Mitel Semiconductor offers flexible design support allowing customers wide choice design interfaces. Whichever design interface chosen each customer design supported fully applications engineer with software support from Mitel Semiconductor group that produces design kits. Four main design interfaces supported. These described Table below. design process incorporates audit procedure verify compliance ensure manufacturability. procedure includes three design reviews held stages design process ensure device performance timescales.
Mitel Semiconductor design kits sign-off enables customers sign-off their design without need resimulate golden simulator. This benefit customers having learn tools. There also overhead engineering effort time taken rechecking simulation results.
Interface
Description Netlist interface. Customer completes logical design simulation using Mitel Semiconductor design kit. Mitel Semiconductor performs layout only. Technology mapping. Mitel Semiconductor converts customer-supplied netlist created using non-Mitel Semiconductor library (e.g., FPGA other vendor's library) simulates using customer-supplied test patterns. production test program based these test patterns. Mitel Semiconductor performs layout. Layout interface. Customer completes logical design simulation. Customer performs layout. Turnkey. Mitel Semiconductor completes schematic capture logic synthesis both based paper schematic specification VHDL Verilog description. Mitel Semiconductor performs layout.
Table. Design interfaces
GSC200 SERIES
CORE CELL LIBRARY
Most core cells have number drive variants. large number functions variety drive strengths each logic function helps synthesis produce optimum gate-level implementation design. following table list basic functions:
Inverter Noninverting buffer Tristate inverting buffer Tristate noninverting buffer 2-input NAND 2-input NAND with inverting input 3-input NAND 3-input NAND with inverting input 4-input NAND 4-input NAND with inverting input 4-input NAND with inverting inputs 2-input 2-input with inverting input 3-input 3-input with inverting input 4-input 4-input with inverting input 4-input with inverting inputs 2-input 3-input 4-input 2-input 3-input 4-input 2-input into 2-input 2-input with inverting inputs into 2-input 2-input ANDs into 2-input 2-input ANDs (one with inverting inputs) into 2-input 3-input into 2-input 3-input 2-input into 2-input 3-input ANDs into 2-input 2-input into 3-input 2-input ANDs into 3-input Three 2-input ANDs into 3-input 2-input into 2-input NAND 2-input with inverting inputs into 2-input NAND 2-input into 2-input NAND 2-input (one with inverting inputs) into 2-input NAND 3-input into 2-input NAND 3-input 2-input into 2-input NAND 3-input into 2-input NAND 2-input into 3-input NAND 2-input into 3-input NAND Three 2-input into 3-input NAND 2-input exclusive 2-input exclusive 2-bit half adder 2-bit full adder 2-input multiplexer with inverting output 2-input multiplexer 4-input multiplexer with inverting output 4-input multiplexer Active high D-type transparent latch Active high D-type transparent latch with active asynchronous reset Active high D-type transparent latch with active asynchronous Active high D-type transparent latch with active asynchronous reset Active D-type transparent latch Active D-type transparent latch with active asynchronous reset Active D-type transparent latch with active asynchronous Active D-type transparent latch with active asynchronous reset High-speed, positive-edge triggered, static D-type flip-flop High-speed, positive-edge triggered, static D-type flip-flop with asynchronous active-low reset High-speed, positive-edge triggered, static D-type flip-flop with asynchronous active-low High-speed, positive-edge triggered, static D-type flip-flop with asynchronous active-low reset Positive-edge triggered, static D-type flip-flop Positive-edge triggered, static D-type flip-flop with asynchronous active-low reset Positive-edge triggered, static D-type flip-flop with asynchronous active-low Positive-edge triggered, static D-type flip-flop with asynchronous active-low reset Negative-edge triggered static D-type flip-flop Negative-edge triggered static D-type flip-flop with asynchronous active-low reset Negative-edge triggered static D-type flip-flop with asynchronous active-low Negative-edge triggered static D-type flip-flop with asynchronous active-low reset High-speed positive-edge gritted static D-type flip-flop with scan input active-high scan enable High-speed positive-edge triggered static D-type flip-flop with scan input (SI) active-high scan enable with asynchronous active-low reset High-speed positive-edge triggered static D-type flip-flop with scan input active-high scan enable with asynchronous active-low High-speed positive-edge triggered static D-type flip-flop with scan input active-high scan enable Positive-edge triggered static D-type flip-flop with scan input activehigh scan enable Positive-edge triggered static D-type flip-flop with scan input activehigh scan enable with asynchronous active-low reset Positive-edge triggered static D-type flip-flop with scan input activehigh scan enable with asynchronous active-low Positive-edge triggered static D-type flip-flop with scan input activehigh scan enable with asynchronous active-low reset Negative-edge triggered static D-type flip-flop with scan input active-high scan enable Negative-edge triggered static D-type flip-flop with scan input active-high scan enable with asynchronous active-low reset Negative-edge triggered static D-type flip-flop with scan input active-high scan enable with asynchronous active-low Negative-edge triggered static D-type flip-flop with scan input active-high scan enable with asynchronous active-low reset Positive-edge triggered flip-flop Positive-edge triggered flip-flop with asynchronous active-low reset Positive-edge triggered flip-flop with asynchronous active-low Positive-edge triggered flip-flop with asynchronous active-low reset latch with active-high reset latch with active-low reset Delay Long delay Cell hold data tristate Fast rise noninverting buffer Fast rise 2-input gate
GSC200 SERIES
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage (VDD) Bias tolerant cells (VBIAS) Input Voltage Output Voltage Static Discharge (HBM) Storage Temperature Plastic -0.5 -0.5 -0.5 -0.5 Units NORMAL OPERATING CONDITIONS Parameter Supply Voltage (VDD) Bias tolerant cells (VBIAS) Input Voltage Input Voltage Tolerant inputs with >2.7V Output Voltage Input Voltage tristated tolerant cells with >2.7V Current Bond Ambient TemperatureCommercial Industrial Military VBIAS VBIAS Units
Table.
Exceeding absolute maximum ratings cause permanent damage device. Extended exposure maximum ratings will affect device reliability. stands Human Body Model.
Table.
ELECTRICAL SPECIFICATION
Typical characteristics 3.3V, 25°C typical processing. values defined over process conditions, from +85°C between 3.6V unless otherwise stated. Parameter Min. Input Loads Input Leakage Output (Tristate) Leakage Input Capacitance Output Capacitance Output Capacitance Weak Pull-Up Current Weak Pull-Down Current Input Hold Cell Hold-Up Current Hold Threshold Hold-Down Current CMOS Input Levels Cells Types CMOS CMOS negative Schmitt threshold positive Schmitt threshold Value Typ. Max. Pull Up/Down, 3.6V Pull Up/Down, 3.6V including package including package including package Input Input Units
1.48
3.3V
1.8V 3.6V 1.8V 3.6V 3.0V 3.6V 3.0V 3.6V 3.3V 3.3V
Table.
GSC200 SERIES
CMOS Output Levels Parameter 2.4V 3.0V 3.6V Units Conditions 1.8V 3.6V
CMOS
Table.
Note: These figures apply speeds output current conditions given Table. below.
Output Currents Drive Strength Device Voltage 1.8V 2.2V 2.2V 2.7V 2.7V 3.3V 3.0V 3.6V *2mA 1.5mA 10mA 12mA 10mA 12mA 12mA 16mA 20mA 24mA 12mA 20mA 24mA
Table.
*1.5mA tolerant push-pull cells. Note: These figures apply available speeds.
MANUFACTURING
GSC200 Series product manufactured Mitel Semiconductor advanced wafer fabrication facility near Plymouth, England. This facility purpose-built, vibrationfree facility equipped with latest automated technology inch wafer processing. This equipment utilises minienvironments together with SMIF boxes achieve ultra clean processing conditions. Computer aided manufacture ensures production efficiency. addition world class wafer fabrication facility, probe final test areas equipped with latest analog digital testers. Mitel Semiconductor committed continuous investment provide state-of-the-art CMOS ASICs. qualified second source this silicon process also available.
QUALITY RELIABILITY
Mitel Semiconductor, quality reliability built into product statistical control processing operations minimising random uncontrolled effects manufacturing operations. Process management involves full documentation procedures with recording batch batch data using computerised tracking systems. common information management system used monitor manufacturing Mitel Semiconductor CMOS processes operations. products benefit from this integrated monitoring system resulting highest quality standards technologies. Further information reliability results contained Quality brochure, available from Mitel Semiconductor Customer Service Centres.
GSC200 SERIES
PACKAGING
GSC200 Series available wide range metric quad flat packages (MQFP) plastic ball grid array packages (BGA) tables below show preferred packaging range time preparing this datasheet. Detailed package specifications available from Mitel Semiconductor Design Centres request. Additional packages being regularly added this list, particular package listed, please enquire through your Mitel Semiconductor sales representative. Stock held preferred packages ensure fast prototype assembly turn around.
PLASTIC QUAD FLAT PACKS SURFACE MOUNT
Code Lead Count Body Size* Lead Pitch 0.80 0.50 0.80 0.65 0.80 0.50 0.65 0.80 0.80 0.50 0.65 0.50 0.65 0.50 0.50 Description
gull wing metric quad flat pack
Table.
PLASTIC BALL GRID ARRAYS (OMPAC STYLE) SURFACE MOUNT
Code Lead Count Body Size* Lead Pitch 1.50 1.50 1.27 1.27S 1.27 Description
1.73 1.73 1.73 1.73 1.73
Table.
dimensions millimetres
GSC200 SERIES
SYSTEMBUILDER HARD MACROFUNCTIONS
Complex Programmable Cores ARM7TDMI (Thumb) 16/32 RISC Core OakDSPCore (16-bit) (Release SystemBuilder: 1998) Power Control Module Versatile Programmable Peripheral (parallel port) System Address Decoder Dual Timer Counter Watchdog Timer
Memory ROMs (size specified software) SPRAMs (size specified software) DPRAMs (size specified software)
Floppy Disk/Tape Functions 765A 91C36 91C360 DDS24 Floppy Disk Controller (82077SL) Floppy Disk Controller Floppy Disk Data Separator (1.25Mbit/s) High Margin Floppy Disk /Tape DataSeparator (1.25Mbit/s) Enhanced Floppy Disk/ Tape Data Separator (2Mbit/s)
Analog Functions Current Reference Bandgap References Voltage Multiplier Power-on-Reset 9-bit Video Control 8-bit 10MS/s 8-bit Control
Standard Serial Communications Cores 85C30 82530 16C450 16C550A 8251A 8250B 8868A 6402 Channel Channel UART UART with FIFOs USART UART UART UART
LICENCES HARD MACROFUNCTIONS
SystemBuilder hard macrofunction blocks supplied customers only behavioural models. actual Intellectual Property (IP) encapsulated mask data, which Mitel Semiconductor adds layout stage. Mitel Semiconductor necessary licences able offer hard macrofunction blocks customers without signing additional agreements.
Interface Cores PCMCIA Ethernet IEEE1284 Both Master (82365SL) Slave interfaces (79C90) Host Parallel Port Host, peripherals cores Both 64-bit
SYSTEMBUILDER SYNTHESISABLE MACROFUNCTIONS
Standard Microprocessor Cores 8042 8048 8051 8052 8086
Standard Microprocessor Peripheral Cores 82C206 8237A 8253 8254 6845 146818 8259A 8255 Integrated Peripherals Controller Channel Controller Channel Prog. Interval Timer Channel Prog. Interval Timer Controller Real Time Clock Prog. Interrupt Controller Prog. Peripheral Interface
Because range functions available SystemBuilder customers subject regular additions, lists this brochure complete. up-to-date list, consult your Mitel Semiconductor representative, visit Website: http://www.gpsemi.com
SystemBuilder Licences Each SystemBuilder soft macrofunction represents significant amount design effort, resulting must protected. Mitel Semiconductor brief straightforward agreement customers sign which protects
Bus-based Microcontroller Macrofunctions Test/Diagnostic Module arbiter cell ARM7TDMI Core-to-bus interface channel multi-mode Controller Interrupt Controller Memory/Peripheral Controller (for 16-, external buses) UART
http://www.mitelsemi.com
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