HDMP-1012 Transmitter HDMP-1014 Receiver Features Transparent, Ex

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HDMP-1012 Transmitter HDMP-1014 Receiver Features Transparent, Ex

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Cost Gigabit Rate Transmit/Receive Chip Technical Data
HDMP-1012 Transmitter HDMP-1014 Receiver
Features Transparent, Extended
Ribbon Cable Replacement Implemented Cost Aluminum M-Quad Package High-Speed Serial Rate 1501500 MBaud Standard 100K Interface Bits Wide Reliable Monolithic Silicon Bipolar Implementation On-chip Phase-Locked Loops Transmit Clock Generation Receive Clock Extraction
Description
HDMP-1012 transmitter HDMP-1014 receiver used build high speed data link point point communication. monolithic silicon bipolar transmitter chip receiver chip each provided standard aluminum M-Quad package. From user's viewpoint, these products thought providing "virtual ribbon cable" interface transmission data. Parallel data loaded into (transmitter) chip delivered (receiver) chip over serial channel, which either coaxial copper cable optical link. chip hides from user complexity encoding, multiplexing, clock extraction, demultiplexing decoding. Unlike other links, phaselocked-loop clock extraction circuit also transparently provides frame synchronization user troubled with periodic insertion frame synchronization words. addition, balance line code automatically maintained chip set. Thus, user transmit arbitrary data without restriction. chip also includes state-machine
controller (SMC) that provides startup handshake protocol duplex link configuration. serial data rate link selectable four ranges (see tables page extends from Mbits/s 1.25 Gbits/s. parallel data interface single-ended ECL, selectable. flag available used extra 17th 21st under user's control. flag also used even frame indicator dual-frame transmission. used, link performs expanded error detection. serial link synchronous, both frame synchronization
Applications Backplane/Bus Extender Video, Image Acquisition Point Point Data Links Implement SCI-FI Standard Implement Serial HIPPI
Specification
5962-0049E (6/94)
synchronization maintained. When data available send, link maintains synchronization transmitting fill frames. (training) fill frames reserved handshaking during link startup. User control space also supported. Control Available asserted chip, least significant bits data sent Control Available line will indicate data Control Word. intention this data sheet provide design engineer information regarding HDMP-1012/1014 chipset necessary design this product into their application. assist using this data sheet, following Table Contents provided.
Table Contents
Topic Page Typical Applications Setting Operating Rate .576 Transmitter Block Diagram .578 Receiver Block Diagram Transmitter Timing Characteristics Receiver Timing Characteristics Electrical Specifications Electrical Specifications Typical Lock-Up Times Absolute Maximum Ratings Thermal Characteristics Type Definitions Pin-Out Diagrams Transmitter Definitions Receiver Definitions Mechanical Dimensions Surface Mount Assembly Instructions Appendix Additional Internal Architecture Information .596 Line Code Description Data Frame Codes Control Frame Codes Fill Frame Codes Operation Principles Encoding Phase Locked Loop .600 Operation Principles Encoding HDMP-1014 (Rx) Phase Locked Loop HDMP-1014 (Rx) Decoding .602 HDMP-1014 (Rx) Link Control State Machine Operation Principle State Machine Handshake Protocol .603 Appendix Link Configuration Examples Duplex/Simplex Configurations Full Duplex .605 Simplex Method Simplex with Speed Return Path Simplex Method Simplex with Periodic Sync Pulse .607 Simplex Method III: Simplex with External Reference Oscillator .607 Data Interface Single/Double Frame Mode Single Frame Mode (MDFSEL=0) Double Frame Mode (MDFSEL=1) Supply Bypassing Integrator Capacitor Integrating Capacitor .610 Power Supply Bypassing Grounding Electrical Connections I-ECL O-ECL High Speed Interface: I-H50 O-BLL .612 Positive Operation Mode Options
Typical Applications
HDMP-1012/1014 chipset designed ease flexibility. This allows customer tailor this product, through configuration link, based their specific system requirements application needs. Typical applications range from backplane extension digital video transmission. latency extension wide data achieved using standard duplex configuration (see Figure 1d). full duplex, HDMP1012/1014 chipset handles issues link startup, maintenance, simple error detection. width bits wide, HDMP-1012/1014 chipset capable sending large data frame separate frame segments, shown Figure this mode, called Double Frame Mode, FLAG used transmitter receiver indicate first second frame segment. HDMP-1012/1014 chipset Double Frame Mode also configured full duplex achieve 32/40 wide extension. digital video transmission, simplex links more common. HDMP-1012/1014 chipset transmit bits parallel data standard broadcast simplex mode. Additionally, wide data transmitted over single line Double Frame Mode) parallel lines, Figure
16/20 SIMPLEX TRANSMISSION
DEMUX
32/40 SIMPLEX TRANSMISSION
32/40 SIMPLEX TRANSMISSION WITH HIGH CLOCK RATES
16/20 DUPLEX TRANSMISSION
SIMPLEX BROADCAST TRANSMISSION
Figure Various Configurations Using HDMP-1012/1014.
timing diagrams standard configurations, Appendix section entitled Link Configuration Examples. HDMP-1012/1014 chipset support serial transmission rates from each these configurations. chipset requires user input link data rate asserting DIV1 DIV0 accordingly. determine DIV1/DIV0 setting necessary each application, refer section: Setting Operating Data Rate Range next page.
desired transmit parallel word operating MWord/sec). Both must range that this word rate falls in-between. According table entitled "Typical Operating Rates Mode" next page, setting DIV1/DIV0 logic `0/0' allows parallel input word rate 32.9 62.5 This setting easily accommodates required word rate. user serial data rate calculated Serial Data Rate (------) (------) word 1100 MBits/sec
Setting Operating Data Rate Range
HDMP-1012/1014 chipset operate from MBaud 1500 MBaud. divided into four operating data ranges with each range selected setting DIV1 DIV0 shown tables below. purpose following example help understanding using these tables. This specific example uses table figure entitled "Typical 20-bit Mode Data Rates".
baud rate includes additional bits that G-LINK transmits link control error detection. serial baud rate calculated Serial bits Baud Rate (------) (------) word 1320 MBaud example which parallel word rate provides only possible DIV1/ DIV0 setting.
Some applications have parallel word rate that seems ranges. example, MWord/s) parallel data rate fall within ranges (DIV0/ DIV1 DIV0/DIV1 Mode. table, setting DIV1/DIV0 gives upper rate 53.3 while setting DIV1/DIV0 gives lower rate 32.9 MHz. These transition data rates stated tables typical values vary between individual parts. Each transmitter/ receiver continuous band cover across entire 1500 MBaud range overlap between ranges. Each transmitter/receiver will permit parallel data rate, suggested that DIV0 jumper that either logic (ground) logic (open). This allows design accommodate both ranges maximum flexibility. This technique recommended whenever operating near maximum minimum word rate ranges. above information also applies HDMP-1012/ 1014 chipset when operating mode.
HDMP-1012 (Tx), HDMP-1014 (Rx)
Typical Operating Rates Mode[1] +85°C, -4.5 -5.5 Parallel Word Rate (Mword/sec) Range 75.0 (max) (min) Serial Data Rate (Mbit/sec) Range 1200.0 (max) 120.0 (min) Serial Baud Rate (MBaud) Range 1500.0 (max) 1010 150.0 (min)
DIV1
DIV0
Notes: Extended operating rates 1800 MBaud/sec (typ) possible +60°C. values typical over temperature process, unless otherwise noted (min) (max). Typical Serial Baud Rates DIV1/DIV0 1800 MBd. values this table expected less than 10-14. This estimation based maximum data rate characterization, which performed serial data rate 2000 Mbits/s less than 10-11. Production units 100% screened less than 10-7.
Figure Typical 16-bit Mode Data Rates.
HDMP-1012 (Tx), HDMP-1014 (Rx)
Typical Operating Rates Mode[1] +85°C, -4.5 -5.5 Parallel Word Rate (Mword/sec) Range 62.5 (max) (min) 10.5
,,,, ,,,,
FRAME RATE (Mwords/sec) 1010 1000 1500 SERIAL DATA RATE (Mbaud)
1800
BAUD RATE FRAME RATE
2000
2500
DIV1
DIV0
Serial Data Rate (Mbit/sec) Range 1250.0 (max) 125.0 (min)
Serial Baud Rate (MBaud/Sec) Range 1500 (max) 1010 (min)
Notes: Extended operating rates 1800 MBaud/sec possible +60°C. values typical over temperature process, unless otherwise noted (min) (max). Typical Serial Baud Rates DIV1/DIV0 1800 MBd. values this table expected less than 10-14. This estimation based maximum data rate characterization, which performed serial data rate 2000 Mbits/s less than 10-11. Production units 100% screened less than 10-7.
Figure Typical 20-Bit Mode Data Rates.
,,,,, ,,,,
FRAME RATE (Mwords/sec)
1800
1010
BAUD RATE FRAME RATE
1000
1500
2000
2500
SERIAL DATA RATE (Mbaud)
EHCLKSEL
FLAGSEL
INPUT LATCH INTERNAL CLOCKS CLOCK GENERATOR
MDFSEL
M20SEL
STRBIN
DIV0
DIV1
CAP0 CAP1
CAV* DAV* FLAG CONTROL LOGIC C-FIELD ENCODER
LATCH
STRBOUT SIGN HCLK
ACCUMULATE INVERT
LOCKED
D0-D19 RST*
LATCH
DOUT OUTPUT SELECT LOUT
D-FIELD ENCODER
FRAME
LOOPEN
Figure HDMP-1012 Transmitter Block Diagram.
HDMP-1012 Block Diagram
HDMP-1012 designed accept wide parallel data transmit over high speed serial line, while minimizing user's necessary interface high speed circuitry. order accomplish this task, HDMP-1012 performs following functions: Parallel Word Input High Speed Clock Multiplication Frame Encoding Parallel Serial Multiplexing PLL/Clock Generator Phase Lock-loop Clock Generator responsible generating internal clocks needed transmitter perform functions. These clocks based supplied frame clock (STRBIN) control signals (M20SEL, MDFSEL, EHCLKSEL, DIV1, DIV0). normal operation (MDFSEL=0), STRBIN expected
incoming frame clock. PLL/ Clock Generator locks this incoming rate multiplies clock needed high speed serial clock. Based M20SEL, which determines whether incoming data frame bits wide, PLL/Clock Generator multiplies frame rate clock respectively (data bits control bits). DIV1/DIV0 inform transmitter frequency range incoming data frames. internal frame rate clock accessible through STRBOUT high speed serial clock accessible through HCLK. When MDFSEL high, transmitter Double Frame Mode. Using this option, user send wide data frame segments while supplying original frame clock STRBIN. Doubling frame rate performed
transmitter. clock generator section performs clock multiplication necessary serial clock rate. setting EHCLKSEL high, user provide external high speed serial clock STRBIN. This clock used directly high speed serial circuitry output serial data. Control Logic C-Field Encoder Control Logic responsible determining what information serially sent output. CAV* low, sends data D0.D8 D9.D17 control word information. CAV* high DAV* low, sends parallel word data data inputs. neither CAV* DAV* low, then transmitter assumes link being used. this state, control logic triggers Data Encoder send Fill Frames maintain link balance allow receiver
maintain frequency phase lock. type fill frames sent (FF0 FF1) determined input. duplex system, normally connected Rx's STAT1 pin. C-Field Encoder, based inputs DAV*, CAV*, FLAGSEL, FLAG, supplies four encoded bits frame mux. This encoded data contains master transition (which receiver uses frequency locking), well information regarding data type: control, data, fill frame. order FLAG used additional data bit, FLAGSEL must high both D-Field Encoder D-Field Encoder provides remaining parallel word data frame mux. Based control signals from Control Logic, D-Field Encoder either outputs parallel information
data inputs (D0.D19) designated Fill Frame. RST*, when low, resets internal chip registers. Frame Frame accepts output from C-Field DField Encoders. four control bits attached data bits, either data bits based M20SEL input. This parallel information, either bits wide, multiplexed serial line based internal high speed serial clock. SIGN sign circuitry determines cumulative sign outgoing data frame, containing data control bits. This used accumulator/inverter maintain balance transmission line. Accumulator/Invert Accumulator/Invert block responsible maintaining
balance serial line. determines, based history sign current data frame, whether current frame should inverted bring line closer desired duty cycle. high when data frame inverted. Output Select normal operation, serial data stream placed DOUT. asserting LOOPEN, user also direct serial data stream LOUT, which used loopback testing. When LOOPEN asserted, LOUT disabled reduce power consumption.
INPUT SELECT
LOOPEN
EQEN
INPUT SAMPLER
FRAME DEMUX
D-FIELD DECODER
D0.D19
FLAG PHASE FREQ DETECT INTERNAL CLOCKS DAV* C-FIELD DECODER CAV* ERROR CAP0 CAP1 STATE MACHINE FILTER LINKRDY* STAT1 STAT0 CLOCK SELECT CLOCK GENERATOR FLAGSEL
FDIS
SMRTST1*
SMRTST0*
TCLKSEL
Figure HDMP-1014 Receiver Block Diagram.
HDMP-1014 Block Diagram
HDMP-1014 receiver designed convert serial data signal sent from HDMP-1012 into either 16,17, wide parallel data. doing this, performs functions Clock Recovery Data Recovery Demultiplexing Frame Decoding Frame Synchronization Frame Error Detection Link State Control Input Select input select block determines which input line used. normal operation (LOOPEN=0), accepted input signal. improved distance using coax cable, input equalizer used asserting EQEN. setting
STRBOUT
M20SEL
LOOPEN high, receiver accepts input signal. This feature allows loop back testing exclusive transmission medium. Phase/Freq Detect This block compares either phase frequency incoming signal internal serial clock, generated from Clock Select block. frequency detect disable (FDIS) high disable frequency detector enable phase detector. HDMP-1014 (Rx) Phase Locked Loop more details. output this block, PH1, used filter determine control signal VCO. Filter This loop filter that accepts output from Phase/ Freq Detector converts into
control signal VCO. This control signal tells whether increase decrease frequency. Filter uses input determine proportional signal integral signal. proportional signal determines whether should increase decrease frequency. integral signal filters high frequency signal stores historical output level. signals combined determine magnitude frequency change VCO. This Voltage Controlled Oscillator that controlled output Filter. outputs high speed digital signal Clock Select.
ACTIVE
BCLK
FCLK
NCLK
DIV1
TCLK
DIV0
Clock Select Clock Select accepts high speed digital signal from outputs internal high speed serial clock. frequency divided, based DIV1/DIV0 inputs, input signal's frequency range. Clock Select output, accessible through BCLK, internal serial clock. phase frequency locked incoming signal. This internal serial clock used Input Sampler sample data. also used Clock Generator generate recovered frame rate clock. setting TCLKSEL high, user input external high speed serial clock TCLK. Clock Select accepts this signal directly outputs internal serial clock. Clock Generator Clock Generator accepts serial clock generated from Clock Select generates frame rate clock, based setting M20SEL. M20SEL asserted, incoming encoded data frame expected bits wide data bits control bits). master transition control section encoded data stream expected every bits, used ensure proper frame synchronization output frame clock, STRBOUT.
Input Sampler serial input signal converted into serial stream, using extracted internal serial clock from Clock Select. This output sent frame demux. Frame Demux Frame Demux demultiplexes serial stream from Input Sampler into wide parallel data word, based setting M20SEL. most significant bits sent C-Field Decoder, while remaining bits sent D-Field Decoder. C-Field Decoder C-Field Decoder accepts control information from Frame Demux determines what kind frame being received whether inverted. control bits sent State Machine error checking. decoded information sent D-Field Decoder. CAV* incoming frame control data. DAV* information data. neither DAV* CAV* low, then incoming frame expected fill frame. FLAGSEL asserted, FLAG restored original form. Otherwise, FLAG used differentiate between
even frames Double Frame Mode. more information about this, refer Double Frame Mode. D-Field Decoder D-Field Decoder accepts data field incoming data frame from Frame Demux. Based information from C-Field Decoder, which determines what type data being received, D-Field Decoder restores parallel data back original form. State Machine State Machine used full duplex mode perform functions link startup, link maintenance, error checking. setting SMRST0* SMRST1* low, user, too, reset state machine initiate link startup. SMRST1* usually connected transmitters LOCKED output. STAT1 STAT0 denote current state link during startup. ACTIVE input normally driven STAT1 STAT0 outputs. This ACTIVE input retimed STRBOUT presented user LINKRDY*. LINKRDY* active output that indicates when link ready transmit data. Refer State Machine Handshake Protocol section page more details.
HDMP-1012 (Tx) Timing
Figure shows timing diagram. Under normal operations, locks internally generated clock incoming STRBIN. incoming data, D0-D19, DAV*, CAV*, FLAG, latched this internal clock. MDFSEL=0, input rate STRBIN expected same parallel data rate. MDFSEL=1, STRBIN should incoming parallel data
rate. data must valid before it's sampled set-up time (ts), remain valid after it's sampled hold time (th). set-up hold times referenced STRBIN. This reference positive edge STRBIN MDFSEL=0, frame period from positive negative edge STRBIN MDFSEL=1. STRBOUT appears after this reference with delay Tstrb. rate STRBOUT always
same word rate incoming data, independent MDFSEL. start frame, high speed serial output occurs after delay after rising edge STRBIN. typical value calculated using following formula: serial duration
HDMP-1012 (Tx) Timing Characteristics
+85°C, -4.5 -5.5 Symbol Tstrb Parameter Setup Time, Rising Edge STRBIN Relative D0-D19, DAV*, CAV* FLAG Hold Time, Rising Edge STRBIN Relative D0-D19, DAV*, CAV* FLAG STRBOUT STRBIN Delay Units nsec nsec nsec Min. Typ. Max.
STRBIN MDFSEL FRAME PERIOD STRBIN MDFSEL
DAV*, CAV* FLAG
STRBOUT tstrb
DOUT D-FIELD HCLK C-FIELD
Figure HDMP-1012 (Tx) Timing Diagram.
HDMP-1014 (Rx) Timing
Figure timing diagram when internal locked incoming serial data. BCLK's frequency same input data rate. size input data frame either bits bits, depending setting M20SEL. Independent frame size, STBROUT's falling edge aligned
data frame's boundary, while rising edge center data frame. synchronous outputs, D00D19, LINKRDY*, DAV*, CAV*, ERROR, FLAG, updated every data frame, with delay after falling edge STRBOUT. There latency delay frames from
input serial data frame update synchronous outputs. state machine outputs, STAT0, STAT1, appear with falling edge STRBOUT after delay td2. These outputs updated once every frames.
HDMP-1014 (Rx) Timing Characteristics
+85°C Symbol Parameter Synchronous Output Delay State Machine Output Delay Units nsec nsec Min. Typ. Max.
D-FIELD C-FIELD
BCLK
STRBOUT
LINKRDY* DAV*, CAV* ERROR FLAG
STAT1 STAT0
Figure HDMP-1014 (Rx) Timing Diagram.
HDMP-1012 (Tx), HDMP-1014 (Rx)
Electrical Specifications +85°C, Ground, -4.5 -5.5 Symbol VIH,ECL VIL,ECL VOH,ECL VOL,ECL VIP,H50 VDC,BLL VOP,BLL IEE,Tx IEE,Rx Parameter Input High Voltage Level, Guaranteed high signal inputs Input Voltage Level, Guaranteed signal inputs Output High Voltage Level, Terminated with -2.0 Output Voltage Level, Terminated with -2.0 Input Peak-To-Peak Voltage Output Bias Voltage Level Output Peak-To-Peak Voltage, Terminated with coupled Transmitter Supply Current, with HCLKSEL 50°C Receiver Supply Current, 50°C Units -900 +600 +403 +512 -1050 -1600 Min. -1150 Typ. Max.
-1500
Note: outputs measured with external pull-up resistors ground. Refer Figure additional information.
HDMP-1012 (Tx), HDMP-1014 (Rx)
Electrical Specifications 25°C Symbol tr,ECL tf,ECL tf,BLL VSWRi,H50 VSWRo,BLL Parameter Rise Time, Terminated with -2.0 Fall Time, Terminated with -2.0 Rise Time, Terminated with coupled Fall Time, Terminated with coupled Input VSWR Output VSWR Units nsec nsec psec psec Min. Typ. Max.
Note: outputs measured with external pull-up resistors ground. Refer Figure additional information.
HDMP-1012 (Tx), HDMP-1014 (Rx)
Typical Lock-Up Time 25°C DIV1 DIV0 HDMP-1012, msec HDMP-1014, msec 11.0 LINK[1], msec 12.0
Note: Measured Local Loop-Back mode with state machine engaged cable length.
HDMP-1012 (Tx), HDMP-1014 (Rx)
Absolute Maximum Ratings 25°C, except specified. Operation excess these conditions result permanent damage this device. Symbol VIN,ECL VIN,BLL IO,ECL Tstg Tmax Parameter Supply Voltage Input Voltage Input Voltage Output Source Current Storage Temperature Junction Temperature Maximum Assembly Temperature (for seconds maximum) Units Min. Max. +0.5 +0.5 +130 +130 +260
HDMP-1012 (Tx)
Thermal Characteristics, 25°C Symbol Parameter Thermal Resistance Case Power Dissipation, volts Units °C/Watt Watt Typ.
HDMP-1014 (Rx)
Thermal Characteristics, 25°C Symbol Parameter Thermal Resistance Case Power Dissipation, volts Units °C/Watt Watt Typ.
Type Definitions
Type I-ECL Definition Input ECL. Similar ECL, with pull-down. Thus input left unconnected, buffer generates default value "0". input also directly connected ground generate "1". Output ECL. Similar should terminated with exceed 10cm connection distance. matched output driver. Will drive coupled loads, with pull-up resistors broad band matching. unused outputs should have pull-up resistors, coupled resistor ground. Input with internal terminations. Input diode level shifted that swing around ground. driven with single-end configuration. Commonly used with input single-end coupling from O-BLL driver another source, differential direct coupling from O-BLL driver. Filter capacitor node. Power supply ground.
O-ECL O-BLL
I-H50
STRBOUT
EHCLKSE
FLAGSEL
ECLGND
LOCKED
ECLGND
MDFSEL
M20SEL
DAV*
CAV*
CAP0B CAP0A CAP1A CAP1B HGND STRBIN STRBIN* HCLKON HCLK HCLK* HGND LOUT LOUT* LOOPEN DOUT DOUT* DIV0 DIV1
FLAG
DATECODE
HDMP-1012
LOT#
ECLGND
RST*
Figure HDMP-1012 (Tx) Package Layout, View.
ECLGND
TEMP
NCLK
FCLK
CAP0B CAP0A CAP1A CAP1B DIV0 DIV1 BCLK* BCLK TCLKSEL TCLK* TCLK HGND DIN* LOOPEN LIN* EQEN FDIS
ECLGND ECLGND FLAG
DATECODE
HDMP-1014
LOT#
ACTIVE
STAT1
STAT0
SMRST1
SMRST2
M20SEL
ECLGND
FLAGSEL
STRBOUT
LINKRDY*
DAV*
CAV*
Figure HDMP-1014 (Rx) Package Layout, View.
ERROR
Definition
Name CAP0A CAP0B CAP1A CAP1B CAV* Type Signal Loop Filter Capacitor: CAP0A should shorted CAP0B. CAP1A should shorted CAP1B. loop filter capacitor must connected across CAP0 CAP1 inputs increase loop time constant. Control Word Available Input: This active-low input tells chip that user requesting control word transmitted. This should only asserted after user determined line active given frame cycle. When this asserted, information Data inputs sent control frame. asserted simultaneously, takes precedence. Data Inputs: data encoded transmitted when M20SEL active; otherwise least significant bits encoded transmitted. encoded bits transmitted first. (e.g.: sent first, through either D19, followed coding bits C0-C3.)
I-ECL
DAV*
I-ECL
I-ECL
DIV0 DIV1 DOUT DOUT* ECLGND
I-ECL O-BLL
I-ECL
Data Available Input: This active-low input tells chip that user valid data transmitted. This should asserted only after user determined that line active given frame cycle. When this asserted, information Data Flag inputs encoded sent Data frame. Divider Select: These pins program divider chain operate full speed, half speed, quarter speed one-eighth speed. Normal Serial Data Output: Output used when LOOPEN active. This output special buffer line logic driver, which back-terminated compatible output. Ground: Normally volts. This ground used drivers. best performance, coupling noisy ECLGND clean HGND grounds minimized. Enable Data: This signal comes from chip state machine used control output chip. state machine only allows data enabled when both sides link have established stable lock.
Definition (cont'd.)
Name EHCLKSEL Type I-ECL Signal EHCLK Enable: When active, this input causes STRBIN inputs used transmit serial clock, rather than internal clock. This useful generating extremely jitter test signals, operating link speeds that within range. When STRBIN active, necessary data source take clock from link rather than usual operation where Link phase-locks onto data source clock. Fill Frame Select: When neither asserted, when false, fill frames automatically transmitted allow chip maintain lock. type fill frame sent determined state this pin. FF0s sent low, either FF1a FF1b sent high. choice FF1a FF1b determined state cumulative line balance. Extra Flag Bit: When FLAGSEL active, this input sent extra data addition normal Data inputs. When FLAGSEL asserted, this input ignored transmitted Flag internally alternated allow chip perform enhanced frame error detection. Flag Mode Select: When this input high, extra FLAG input sent extra transparent data bit. Otherwise, FLAG input ignored transmitted flag internally alternated transmitter. chip provide enhanced frame error detection checking strict alternation flag during data frames. FLAGSEL input chip should same value FLAGSEL input. Ground: Normally volts. This ground used everything other than noisy outputs.
I-ECL
FLAG
I-ECL
FLAGSEL
I-ECL
HCLK HCLK*
O-BLL
HCLKON
I-ECL
HGND
High Speed Clock Monitor: Used monitor actual clock signal used transmit serial data. This signal will either divided output, divided EHCLK external clock input, depending value EHCLKSEL input. HCLK Power-down Control: When this de-asserted, HCLK, HCLK* outputs powered down reduce power dissipation. High Speed Ground: Normally volts. This ground used provide clean reference STRBIN STRBIN* inputs. optimum impedance matching, suggested that physical distance between this ground plane minimized.
Definition (cont'd.)
Name Type O-ECL Signal Invert Signal: high value implies that current frame being sent inverted maintain long-term balance. With buffer, pulled down with resistor coupled, this signal useful analyzing serial output stream with oscilloscope. Loop In-lock Indication: This signal indicates lock status PLL. high value indicates lock. This signal normally connected SMTRST1 reset input state machine force link into start-up state until locked. This signal give multiple false-lock indications during acquisition process, should debounced used other purpose than drive chip. Loop Back Control: Input which controls whether DOUT, DOUT*, LOUT, LOUT* outputs currently enabled. active, LOUT, LOUT* enabled. unused output powered down reduce dissipation. Loop Back Serial Data Output: Output used when LOOPEN active. Typically this output will used drive LIN, LIN* inputs chip. Word Select: When this signal high, link operates data transmission mode. Otherwise, link operates mode. Select Double Frame Mode: When this signal high, expects speed parallel clock STRBIN. chip then internally multiplies this clock produces full-rate parallel clock STRBOUT. Note that phase relationship STRBIN STRBOUT sampling point change with asserting MDFSEL, shown timing diagram. This feature provided that either word easily transmitted words. When MDFSEL low, expects full-rate parallel clock STRBIN. Ready Data: Output tell user Link ready transmit data. This retimed version input, which driven chip state machine controller. Chip Reset: This active-low initializes internal chip registers. should asserted during power minimum parallelrate clock cycles ensure complete reset. Data Clock Input: When EHCLKSEL low, this input phase locked multiplied generate high speed serial clock. chip expects clock frequency which equal input frame rate MDFSEL (double frame mode) low, frame rate MDFSEL high. When EHCLKSEL high, bypassed, STRBIN directly becomes high speed serial clock. Refer Timing diagram phase relationship between STRBIN, data STRBOUT.
LOCKED
O-ECL
LOOPEN
I-ECL
LOUT LOUT* M20SEL
O-BLL
I-ECL
MDFSEL
I-ECL
O-ECL
RST*
I-ECL
STRBIN STRBIN*
I-H50
Definition (cont'd.)
Name STRBOUT Type O-ECL Signal Frame-rate Data Clock Output: This output always frame rate clock derived from STRBIN. With buffer pulled down with resistor coupled, this output ideal triggering oscilloscope examining serial output pattern DOUT LOUT. Power: Normally 10%.
Definition
Name ACTIVE Type I-ECL Signal Chip Enable: This input normally driven state machine output. ACTIVE signal internally retimed STRBOUT presented user LINKRDY signal. This state machine signals user that start-up sequence complete. Monitor Output: These pins provide access internal clock. Loop Filter Capacitor: CAP0A should shorted CAP0B. CAP1A should shorted CAP1B. loop filter capacitor must connected across CAP0 CAP1 inputs increase loop time constant. Control Frame Available Output: This active-low output indicates that chip data outputs receiving Control Frames. False indications generated during link startup. Data Outputs: data received decoded when M20SEL active; otherwise data decoded D16-D19 bits undefined.
BCLK BCLK* CAP0A CAP0B CAP1A CAP1B CAV*
O-BLL
O-ECL
DAV*
O-ECL
O-ECL
DIN*
I-H50
DIV0 DIV1
I-ECL
Data Available Output: This active-low output indicates that chip data outputs, D0.D19, have received data frames. Data should latched rising edge STRBOUT. Note that during link startup, false data indications given. DAV* LINKRDY outputs used together avoid confusion during link startup. Normal Serial Data Input: This input used when LOOPEN active. When LOOPEN high, loop back data inputs LIN, LIN* used instead. optional cable equalizer enabled DIN, DIN* inputs asserting EQEN. Divider Select: These pins program divider chain operate full speed, half speed, quarter speed one-eighth speed.
Definition (cont'd.)
Name ECLGND Type Signal Ground: Normally volts. This ground used drivers. best performance suggested that coupling noisy ECLGND clean HGND grounds minimized. Enable Input Cable Equalization: When asserted, this signal activates cable equalization amplifier DIN, DIN* serial data inputs. Received Data Error: Asserted when frame received that does correspond either valid Data, Control, Fill frame encoding. When FLAGSEL active, chip also tests strict alternation flag bits during data frames. flag alternation error will also cause ERROR indication. Frame Clock Monitor: Leave unterminated normal use. Frequency Detector Disable Input: When active, this input disables Frequency detector enables phase detector. Frequency detector used during start-up sequence acquire wide-band lock Fill Frames, must disabled prior sending data patterns. This input normally controlled state machine. Fill Frame Status: During given STRBOUT clock cycle, neither DAV, CAV, ERROR active, then currently received frame Fill frame. type fill frame received indicated pin. low, then been received. high, then either FF1a FF1b been received. Flag Bit: both have FLAGSEL asserted, this output indicates value transmitted flag bit, then this received treated just like extra data bit. both have FLAGSEL low, FLAG used differentiate even frame from frame line code. Flag Mode Select: When this input high, extra FLAG output effectively extra transparent data bit. Otherwise, FLAG checked alternation during data frames. break strict alternation results ERROR indication user. Ground: Normally volts. This ground used core logic other than output drivers.
EQEN
I-ECL
ERROR
O-ECL
FCLK FDIS
O-ECL I-ECL
O-ECL
FLAG
O-ECL
FLAGSEL
I-ECL
HGND
High Speed Ground: Normally volts. This ground used provide clean references high speed DIN, DIN*, LIN, LIN*, TCLK, TCLK* inputs.
Definition (cont'd.)
Name LIN* Type I-H50 Signal Loop Back Serial Data Input: this input when LOOPEN active. Unlike DIN, DIN* inputs, this input does have cable equalizer. normal usage, this input will connected chip LOUT, LOUT* outputs. This allows user check near-end functionality pair independent transmission medium Loop Back Control: When asserted, this signal causes loop back data inputs LIN, LIN* used instead normal data inputs DIN, DIN*. Link Ready Indicator: This active-low output retimed version ACTIVE input. ACTIVE normally driven state machine output. LINKRDY* then indicates that startup sequence complete that data control indications valid. Word Select: When this signal high, link operates data reception mode. Otherwise, link operates mode data outputs D16-D19 undefined. Nibble Clock Monitor: Leave unterminated normal use. Temperature Sense Diode: Used during wafer package test only. should left open. Phase Detector Test Output: output from phase/frequency detector PLL. When high, should increase frequency. When low, should decrease frequency. State Machine Reset Inputs: Each these active-low input pins reset state machine initial start-up state. This initiates complete restart handshake both ends duplex link. Normally, SMCRST0* connected power-up reset circuit host system reset signal. SMCRST1* input normally connected LOCKED output. LOCKED signal holds state-machine start-up state until locked. State Machine Status Outputs: These outputs indicate current state-machine state. They used directly control FDIS, ACTIVE lines. Recovered Frame-rate Data Clock Output: This output recovered frame rate clock. D0-D19, FLAG, DAV, CAV, LINKRDY, ERROR should latched rising edge STRBOUT. External Replacement Test Clock: When TCLKSEL enabled, this input used place normal signal, effectively disabling allowing user provide external retiming clock testing. Enable Test Clock Input: When this input active, TCLK, TCLK* inputs used place normal signal. This feature useful both synchronous systems chip testing.
LOOPEN
I-ECL
LINKRDY*
O-ECL
M20SEL
I-ECL
NCLK TEMP
O-ECL O-ECL
SMRST0* SMRST1*
I-ECL
STAT0 STAT1 STRBOUT
O-ECL
O-ECL
TCLK TCLK*
I-H50
TCLKSEL
I-ECL
Definition (cont'd.)
Name Type Signal Power: Normally +10%
Mechanical Dimensions Surface Mount Assembly Recommendations
Both HDMP-1012 HDMP1014 implemented industry standard M-Quad package. package outline
dimensions conform JEDEC plastic specifications shown below Figure MQuad package material aluminum leads have been formed into "Gull-Wing" configuration surface mounting.
recommend keeping package temperature, below 75°C. Forced cooling required.
M-Quad Package Information
Item Package Material Lead Finish Material Lead Finish Thickness Lead Coplanarity Details Aluminum 85/15 Sn/Pb inches 0.004 inches maximum
19.786 (0.779
+0.18 -0.08 +0.008 -0.002 23.20 0.10 (0.913 0.004)
VIEW
0.15 (0.006)
+0.16 13.792 -0.04 +0.008 (0.543 -0.002 17.20 0.10 (0.677 0.004) 2.64 0.13 (0.104 0.005)
0.35 TYP. (0.014 TYP.) 0.80 TYP. (0.0315 TYP.)
0.80 0.13 (0.031 0.005) 0.38 0.05 (0.015 0.002)
DIMENSIONS MILLIMETERS (INCHES).
Figure Mechanical Dimensions HDMP-1012 HDMP-1014.
Appendix Additional Internal Architecture Information
Line Code Description HDMP-1012/1014 line code Conditional Invert Master Transition (CIMT), illustrated Figure CIMT line uses three types frames: data frames, control frames, fill frames. Fill frames internally generated chip during link start when there input from user.
Each frame consists Data Field (D-Field) followed Coding Field (C-Field). DField either 16-bits 20bits wide, depending link configuration. C-Field master transition which serves fixed timing reference receivers clock recovery circuit. Users send arbitrary data carried Data Control Frames. balance line code automatically enforced Fill frames have single rising edge
master transition which used clock recovery frame synchronization receiver. Detailed coding schemes described following subsections. tables given this section show data bits same configuration scope display. other words, leftmost each table first transmitted time, while rightmost last transmitted.
CODING FIELD BITS DATA FIELD 16/20 BITS SERIAL DATA
MASTER TRANSITION
FILL FRAME FRAME FRAME
Figure HDMP-1012/1014 (Tx/Rx Pair) Line Code.
Data Frame Codes When FLAGSEL mode, FLAG user controllable alternately sent chip during data frames provide enhanced error detection. Control Fill frames cause toggling between even frames occur (The FLAG available during control frames). receiver performs differential detection make sure that every data frame received opposite pattern from previous frame. break strict alternation observed,
frame error flagged asserting ERROR output. This pattern detection makes impossible static input data pattern generate undetectable false lock point transmitted data stream. detection also reduces probability that loop could lock onto random data point away from true master transition significant time before would detected false lock. This mode detect single-bit errors C-field (non-data fields) frame.
When chip FLAGSEL mode, extra FLAG freely user definable extra data bit. This provides 17th mode, 21st mode. probability undetected false lock higher, users (e.g., SCI-FI) that need extra detect false lock higher level network protocol with clock recovery circuits, etc. higher level protocols consistently receive wrong data, they initiate link restart resetting state machine.
HDMP-1012 (Tx), HDMP-1014 (Rx)
Operating Modes M20SEL FLAGSEL Description data plus error checking data plus FLAG data plus error checking data plus FLAG
HDMP-1012 (Tx), HDMP-1014 (Rx)
Data Frame Structure M20SEL Asserted data mode) Data Status True Inverted True Inverted Flag D-Field C-Field 1101 0010 1011 0100
HDMP-1012 (Tx), HDMP-1014 (Rx)
Data Frame Structure M20SEL Asserted data mode) Data Status True Inverted True Inverted Flag D-Field C-Field 1101 0010 1011 0100
Control Frame Codes There control words provided mode. user desires send control word, lower bits (D0-D8) sent bits D0-D8 DField. user's next bits (D9D17) sent bits D11-D19
D-Field. control frame either inverted inverted needed maintain balance, with coding bits 0011 used indicate true control, bits 1100 used indicate complement control. bits always forced true control frames
complement control frames. These middle bits used distinguish control frames from fill frames, which always have middle bits either Similarly, there control words provided mode.
HDMP-1012 (Tx), HDMP-1014 (Rx)
Control Frame Structure M20SEL Asserted mode) D-Field C-Field
HDMP-1012 (Tx), HDMP-1014 (Rx)
Control Frame Structure M20SEL Asserted mode) D-Field D11-D19 D9-D17 D9-D17 C-Field
Fill Frame Codes
logical fill frames provided: FF1. physically duty cycle wave form with sole rising edge
occurring between Logical toggles between different physical codes, first which advances falling edge bit, second
which retards falling edge bit. logical fill frame types required link start duplex mode.
HDMP-1012 (Tx), HDMP-1014 (Rx)
Fill Frame Structure M20SEL Asserted mode) Fill Frame 1111111 1111111 1111111 D-Field 0000000 0000000 0000000 C-Field 0011 0011 0011
HDMP-1012 (Tx), HDMP-1014 (Rx)
Fill Frame Structure M20SEL Asserted mode) Fill Frame 111111111 111111111 111111111 D-Field 000000000 000000000 000000000 C-Field 0011 0011 0011
HDMP-1014 (Rx)
Detectable Error States M20SEL Asserted mode) xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx D-Field xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx C-Field x00x x11x 1100 1100 1010 0101
HDMP-1014 (Rx)
Detectable Error States M20SEL Asserted mode) xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx D-Field xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx C-Field x00x x11x 1100 1100 1010 0101
Operation Principles
HDMP-1012 (Tx) implemented high performance silicon bipolar process. performs following functions link operation: Phase lock frame rate clock Clock multiplication Frame encoding Multiplexing normal operation, phase locks user supplied frame rate clock multiplies frequency produce high speed serial clock. When locked, indicates that locked asserting LOCKED output. When input asserted, asserts signal
indicating that ready transmit data control frames. accept either wide parallel data produce frame. also accept data produce frame. Similarly, either control words transmitted frame respectively.
Encoding
simplified block diagram transmitter shown Figure PLL/Clock Generator locks onto incoming frame rate one-half frame rate) clock multiplies serial clock rate. also generates internal clock signals required chip.
data inputs, D0-D19, well control signals; DAV*, CAV*, FLAG latched rising edge internally generated frame rate clock. data field then encoded depending state control signals. same time, coding field generated. this point, entire frame been constructed parallel form sign determined. This frame sign compared with accumulated sign previously transmitted bits decide whether invert frame. sign current frame same sign previously transmitted bits, then frame inverted. signs opposite, frame inverted. inversion
performed frame fill frame. Output Select block allows user select between sets differential high speed serial outputs. This feature useful loop back testing. LOOPEN high, LOUT enabled DOUT disabled. LOOPEN low, DOUT enabled LOUT disabled. active-low RST* input resets internal registers balanced state. This should held least five frame rate clock cycles ensure complete reset. Data Field Control Field encoded depending DAV*, CAV*, FLAG, FLAGSEL, M20SEL well internally generated signals, ACCMSB. When FLAGSEL high, equivalent FLAG. This equivalent adding additional data field. When FLAGSEL low, alternates
between high data frames. This allows link perform more extensive error detection when extra unused. ACCMSB sign previously transmitted data. This used determine which type should sent. When ACCMSB low, FF1a sent when ACCMSB high, FF1b sent. This effectively drives accumulated offset transmitted bits back toward balanced state.
loop response. external high-speed clock used instead clock. This accomplished applying high signal EHCLKSEL differential clock STRBIN. four frequency bands selected applying appropriate inputs DIV0 DIV1. STRBIN frequency divided where corresponding binary number represented DIV1, DIV0. This divided version clock STRBIN used serial rate clock available differential signal HCLK output. clock generator block creates clock signals required chip. Depending M20SEL, STRBOUT either HCLK/20 HCLK/24. MDFSEL low, then STRBOUT phase-locked version STRBIN. MDFSEL high, STRBOUT twice frequency STRBIN.
Phase-Locked Loop
block diagram transmitter phase-locked loop shown Figure consists sequential frequency detector, loop filter, VCO, clock generation circuitry, lock indicator. outputs frequency detector pass through charge pump filter that controls center frequency VCO. These outputs also directly effectively zero
STRBIN
FREQ DETECT
FILTER
INTERNAL CLOCKS
M20SEL MDFSEL
CLOCK GENERATOR
STRBIN
EHCLKSEL LOCK DETECT STRBOUT HCLK DIV0 DIV1
LOCKED
Figure HDMP-1012 (Tx) Phase-Locked Loop.
lock detect circuit samples STRBIN with phase shifted versions STRBOUT. samples proper values, LOCKED signal goes stays least frames.
Operation Principles
HDMP-1014 (Rx) monolithically implemented high performance bipolar process. When properly configured, accept 20B/24B CIMT line code frames, then output parallel 16B/17B/ 20B/21B Data Word 14B/18B Control Word. provides following functions link operation: Clock recovery Frame synchronization Data recovery Demultiplexing Frame decoding Frame error detection Link state control
Integrated chip LinkControl State Machine link status monitoring link startup. Figure shows details Input Select. Input Select chooses either nominal serial data (DIN) loopback (LIN) signal Input Sampler's input. loopback enable (LOOPEN) asserted, input selected. Also included Input Selector cable equalization circuitry. When coaxial cable used transmission media, setting EQEN=1 (enable equalization), equalization circuitry signal path compensate high-frequency cable loss. Because Data Field CIMT line code either 16bit 20-bit wide, width selection made setting input M20SEL (Figure M20SEL=1, then configured accept serial input with 20-bit data field, i.e., bits frame. M20SEL 16-bit data field selected.
HDMP-1014 (Rx) PhaseLocked Loop
more detailed block diagram phase-locked loop (PLL) shown Figure PLL, phase serial input, SIN, compared with synchronizing signals from internal clock generator, using either phase detector frequency detector. frequency detector disable signal, FDIS, selects which detector use. synchronization link established, HDMP-1012 (Tx) should send Fill Frame (FF0) Fill Frame (FF1) remote setting FDIS=0, uses
Encoding
Figure shows simplified block diagram receiver. data path consists Input Select, Input Sampler, Frame Demultiplexer, Control Field (CField) Decoder, Data Field (D-Field) Decoder. on-chip phase-locked loop (PLL) used extract timing reference from serial input (DIN LIN). includes Phase-Frequency Detector, Loop Filter, variable-frequency oscillator (VCO). internal clock signals generated from Clock Generator. Clock Generator driven either internal external signal, TCLK, depending Clock Select configuration.
LOOPEN
EQEN
CABLE
Figure HDMP-1014 (Rx) Input Selector.
FDIS
FREQ PHASE
STRBOUT CLOCK FILTER DIV0 BCLK DIV1 TCLKSEL TCLK
Figure HDMP-1014 (Rx) Phase-Locked Loop.
frequency detector align internal clock with rising edge FF0/FF1. Once frequency lock accomplished, FDIS then uses only phase detector synchronization adjustment ready receive data. narrow frequency acquisition range phase detector, frequency detector used internal frequency acquisition. frequency detector, however, only work with necessary selecting phase detector setting FDIS=1) before receiving random data. output phasefrequency detector externally available through PHI. external clock source also used (through TCLK) setting TCLKSEL=1. broaden usable frequency range chip, there programmable divider before clock generator. TCLK frequency divided
setting DIV1, DIV0 (see Operating Rate Tables).
HDMP-1014 (Rx) Decoding
Figure frame demultiplexer de-serializes recovered serial data from Input Sampler, outputs resulting parallel data frame time. Every frame composed 16-bit 20-bit Data Field (D-Field) 4-bit Control Field (C-Field). CField, C0-C3, together with center bits D-Field mode, mode) then decoded C-Field decoder determine content frame. D-Field decoder controlled outputs CField decoder. inverted Data Word Control Word detected, D-Field decoder will automatically invert D-Field data. Control Frame detected, D-Field decoder will shift bottom half DField that outputs
M20SEL M20SEL =0). data Frame detected receiver when control Frame detected receiver Fill Frame detected receiver C-Field decoder will iERR when detects error. internal error (iERR) combined with internal flag (iFLAG) flag-bit modeselect signal (FLAGSEL) produce externally available error (ERROR) flag (FLAG) bits. FLAGSEL=1, FLAG used extra data ERROR=iERR. FLAG=iFLAG. Fill Frame detected, then FLAG=0. Control Frame detected, FLAG should ignored. FLAGSEL=0, serial input assumed consist alternating
even frames (iFLAG=0) frames (iFLAG=1). iERR=1, then ERROR=1. Fill Frame detected, then FLAG=0. Data Frame detected, then FLAG=iFLAG, iFLAG should alternate between starting with ending with otherwise, ERROR=1. Control Frame detected, then FLAG automatically alternates between starting with even feature allows 32/40-bit wide data word transmitted through link. multiplexer demultiplexer required. FLAG used synchronize even frames. Note, both Data Control Frames transmitted even/odd pairs, only Data Frames detected order errors.
without additional controller hardware.
State Machine Handshake Protocol
Figure shows simplified block diagram HDMP1012/1014 data channel configured full duplex operation. HDMP-1012/1014 chipsets required perform handshake parallel. There three states that link must through complete link startup process: State Frequency Acquisition State Waiting Peer State Sending Data Each side link decides which three states that should decision based past memory type frame that currently receiving from other side link. Considering only local port link, there transmitter (Tx), receiver (Rx) state machine controller (SMC). entity, although logically distinct, implemented same chip. monitors data frame status indicators (ERROR, DAV, CAV, from able force control) various characteristics chips. chip following controllable features: forced send Fill Frame using input. type Fill Frame sent controlled using input. Chip following controllable features:
Frequency acquisition Phase-lock/Data reception mode depending state FDIS input. enabled data reception mode which data frames ignored depending ACTIVE input. chip also distinguish between various types frames. also communicate frame type SMC. various frame types are: Fill Frame (FF0) Fill Frame (FF1) Data/Control frames (Data) Error frames (ERROR) also reset either SMCRST0* SMCRST1* inputs. Usually these inputs used power-on reset, other connected LOCKED output. This holds state until transmitter locked. Figure shows state diagram SMC. debounced allowing state transitions made only after least consecutive frames give same indication. This prevents single errors from causing false state transitions. addition this debouncing mechanism, when consecutive ERROR Resets occur, timer enabled forcing into state zero frame times. transition this initial state only occur after link been error-free frames. This prevents false transitions from being made during bitslipping that occurs initial frequency acquisition both PLLs.
HDMP-1014 (Rx) LinkControl State Machine Operation Principle
link-control state machine (SMC) chip provides link handshake protocol enabling duplex link transition from frequency acquisition training mode into data mode. HDMP-1012/1014 Tx/Rx link uses explicit frequency acquisition mode startup that operates square-wave training sequence. This makes possible with very wide tuning range avoid harmonic false lock problems associated with other circuits this type. Using SMC, full duplex data channel implemented
SEND DATA
DISABLE DATA TRANSMISSION ERROR DISABLE DATA RECEPTION RESET FREQUENCY DETECTOR
ERROR RESET
SEND ERROR RESET
DISABLE DATA TRANSMISSION ENABLE DATA RECEPTION FREQUENCY DETECTOR
DATA
SEND
ENABLE DATA TRANSMISSION ENABLE DATA RECEPTION FREQUENCY DETECTOR
DATA
Figure HDMP-1014 (Rx) State Machine State Diagram.
When local port State reset state, where both local parallel interfaces disabled. local transmits continuously, local frequency detection mode. When local phase-locked remote transitions State local transmits acknowledge phase-locked condition (its parallel input still disabled). local phase detection mode parallel output enabled. When State two-way synchronization between local port remote port established. Both local parallel interfaces enabled, local
phase detection mode. Parallel data sent local same time, received local chip state machine logic built status outputs, STAT0 STAT1, that control various features chips depending current state. inputs that need controlled inputs that need controlled FDIS ACTIVE. control chips shown state diagram Figure following interchip connections must made (Figure 16):
driven STAT1 driven STAT0 FDIS driven STAT1 ACTIVE driven STAT1 SMCRST0 driven power-on, user, reset circuit.
LOCKED
DATA INTERFACE
DOUT
SMCRST1* SMCRST0*
DATA INTERFACE
STAT1
POWER-ON RESET
OPTIONS
OPTIONS
STAT0
RST*
LOUT
ACTIVE
FDIS
POWER-ON RESET
STAT0
STAT1
SMCRST0*
SMCRST1*
FDIS
ACTIVE
LOUT DOUT
LOCKED
RST*
DATA INTERFACE
DATA INTERFACE
Figure Full Duplex Configuration.
Appendix Link Configuration Examples
This section shows some application examples using HDMP-1012/1014 chipset. Refer Definition detailed circuit-level interconnection. This guide intended user designing G-LINK into system. provides necessary details getting system without detailed description inner circuitry chip set. first section description various configurations duplex simplex operation. second section describes interface both single frame double frame mode. Following that section integrating capacitor power supply bypassing recommendations. Next guide various types electrical connections. final section discussion translations
single positive supply. Also included list various options their definitions.
Duplex/Simplex Configurations
following describes common setups link. cases, differential high speed lines, unused leads should terminated with coupled ground. Since data stream component, coupling recommended inputs. Full Duplex Figure shows HDMP-1012/ 1014 full duplex configuration connecting bidirectional (parallel) buses. Each link pair. receiver's state machine outputs (STAT0 STAT1) used control status link. Various options such 16/20
mode (M20SEL) speed selections (DIV0,DIV1) grouped together under label `options'. power-on reset available user reset link during startup Since outputs STAT0 STAT1 levels, they tied directly pins shown. When acquired lock incoming STRBIN frame rate, LOCKED activated, which enables this state, both STAT0 STAT1 low, forcing send FF0, which square wave pattern used remote acquire frame lock. When local acquire frame lock, STAT1 high first turn frequency detector (FDIS), then sets itself active mode (ACTIVE), tells local send signal remote that local pair ready. Likewise, when remote pair ready, local will
receive FF1, causing STAT0 high, which asserts enable data (ED) signal retimed signify host that ready send data (RFD). Other configurations duplex mode also possible with external user-defined state machines. Simplex operation using G-LINK also possible. following sections discuss three different types simplex configurations.
Simplex Method Simplex with Low-Speed Return Path Low-speed lines used simplex method Figure 17a. remote controls states both local using these speed lines. This ideal cases where these noncritical lines available. Again, power reset available user. This connection between identical side duplex configuration.
When locked, enabled LOCKED line. Rx's STAT0 STAT1 outputs low, causing local send FF0. When frame locked, STAT1 raised, which disables frequency detector, sets itself active mode, tells send FF1. Upon receiving from Rx's STAT0 line raised, which enables (ED) data transmission. desired, reset (SMCRST1) tied high,
LOCKED
DATA INTERFACE
DOUT
SMCRST1* SMCRST0*
DATA INTERFACE
STAT1
OPTIONS POWER-ON RESET
OPTIONS POWER-ON RESET
SPEED LINES
SIMPLEX METHOD WITH LOW-SPEED RETURN PATH
LOCKED
DATA INTERFACE
DOUT
SMCRST1* SMCRST0*
DATA INTERFACE
STAT1
POWER-ON RESET PERIODIC SYNC PULSES
OPTIONS
OPTIONS POWER-ON RESET
SIMPLEX METHOD WITH PERIODIC SYNC PULSE
LOCKED
DATA INTERFACE
DOUT
SMCRST1* SMCRST0* LOOPEN ACTIVE
DATA INTERFACE
STAT1
OPTIONS POWER-ON RESET
OPTIONS FREQ FRAME RATE
STAT0
RST*
LOUT
FDIS
STAT0
RST*
LOUT
ACTIVE
FDIS
STAT0
RST*
LOUT
ACTIVE
FDIS
POWER-ON RESET
SIMPLEX METHOD WITH EXTERNAL REFERENCE OSCILLATOR
Figure Simplex Configurations.
LOCKED line eliminated. Simplex Method Simplex with Periodic Sync Pulse. Another configuration simplex operation shown Figure 17b. frame lock, normally relies either FF1. this example, fill frame forced high with connection ground, enable data pulsed periodically force send FF1. During this pulse, however, link available data transmission. pulse width applied should long enough acquire lock. typical lock-up time around high frequency band, thus pulse adequate this case. other bands, longer pulses required. Typical lock-up times four data rate ranges found table Typical Lock-Up Time front data sheet. Note that these lockup times assume integrating capacitor being used PLL. Refer section Supply Bypassing Integrator Capacitor more details. After G-LINK locked, needs only often needed ensure that link locked. Lock lost serial line broken, consecutive frame errors detected receiver's state machine. length time between pulses will determine long user needs wait before lock re-established.
Simplex Method III: Simplex with Reference Oscillator third configuration simplex operation shown Figure 17c. high-speed serial line brought into receiver through input, reference clock frame rate connected input. uses reference clock frequency acquisition. Upon frequency lock, STAT1 goes high, sets detector from frequency phase detection mode through FDIS. same time, switches input from reference clock data stream. Since relative phase reference clock that data stream random, phase detector will lock onto random transition data stream. Errors detected phase lock locked master transition. consecutive errors occur, STAT1 line forced low, state machine switches receiver back reference oscillator. This process repeated until master transition found, errorfree condition exists. Because nature this hunting process, possible static code emulate master transition. Therefore, recommended that flag reserved error detection. With FLAGSEL disabled, flag toggled internally uses this strict alternation detect errors, thus making link much more reliable. lock time this simplex configuration dependent frequency match between local oscillators. This method
relies slight difference between frequencies order guarantee lock within reasonable time. theory, perfect match could result lock causing receiver consistantly lock same non-master transition point incoming frames. Fortunately there such thing perfect match real world. recommended select crystal oscillators between 0.1% 0.001% matching. above method uses line high-speed serial data line. This works well simple implement, doesn't take advantage coaxial equalizer line. Adding external inverter Loop Back Control (LOOPEN) allows reference oscillator injected into serial data line (DIN) used high-speed data line. coaxial equalizer needed path, inputs interchanged with external inverter before LOOPEN.
Data Interface Single/ Double Frame Mode.
G-LINK designed work with single frame double frame modes, either bits wide frame. extra flag available with FLAGSEL used signify first second frames double- frame mode. 16/20 frame width option selected with M20SEL pin. this discussion, width assumed. both single double frame modes, data frame (D0-D19), flag (FLAG), data/control word available pins (DAV*, CAV*), must appear before setup time remain valid hold time Refer HDMP-1012
Timing. Since designed with very high-gain frequency/phase detector, relative alignment internal clock STRBIN very tight, insensitive temperature other variations. observed external changes mainly variations buffers, which relatively small. convenience, setup hold times referenced back user-supplied clock, STRBIN. actual sampling clock slightly advanced relative STRBIN internal delays, hold time typically negative. user make sure that M20SEL, FLAGSEL, DIV0, DIV1 have same setting both word width parallel data from host either bits M20SEL bits M20SEL Also, FLAG used additional setting
FLAGSEL=1. last case, parallel data word width either bits bits. local loopback test enabled setting LOOPEN high. Single Frame Mode (MDFSEL=0) block diagram showing single-frame mode data interface both their associated timing diagrams shown Figure xxx. side, expected frequency input clock STRBIN rate data frame. this case, setup hold times referenced rising edge STRBIN. internal clock buffered form STRBOUT which appears with delay Tstrb after STRBIN. side, data frame, flag bit, CAV*, DAV*, LINKRDY, ERROR appear with delay after falling edge STRBOUT. state machine
outputs STAT0 STAT1 appear with delay td2. Double Frame Mode (MDFSEL=1) block diagram showing double-frame mode data interface both their associated timing diagrams shown Figure This configuration works best duty cycle STRBIN 50%. side, expected frequency combined frame period. This combined frame, D0-D19, formed interlacing frames C0C19 C20-C39 with external multiplexer. locks onto STRBIN, which same frequency rate C0-C39, with internal frequency doubler, generates sampling clock latch D0D19, DAV*, CAV*, FLAG. STRBIN also used toggle multiplexer, into
CAV*, DAV* FLAG STRBOUT STRBIN CONFIGURATIONS CONFIGURATIONS
CAV*, DAV*, LINKRDY, ERROR FLAG STRBOUT STAT0, STAT1
STRBIN tstrb CAV*, DAV* FLAG
STRBOUT FLAG CAV*, DAV*, LINKRDY, ERROR
STRBOUT SETUP TIME HOLD TIME tstrb STRBIN STRBOUT DELAY
STAT0, STAT1 STRBOUT SYNCHRONOUS OUTPUTS DELAY STRBOUT STATE MACHINE OUTPUTS DELAY
Figure Data Interface Single Frame Mode (MDFSEL=0).
flag input signify frames. setup hold times referenced frame period D0-D19, deg, from edges STRBIN. multiplexer delay, tmux, should considered timing margins. STRBOUT derived from internal sampling clock, thus frequency double that STRBIN. falling edge STRBOUT appears after rising falling edges STRBIN after delay Tstrb. Other interlacing techniques also achieved with edge-triggered latches improved timing margins. side, frame D0-D19 demultiplexed back original C0-C19, C20-C39 frames with external edge-triggered flip-flops.
toggle clock flip-flops, RCLK, derived state FLAG bit. RCLK toggle with rising edge STRBOUT with delay tda. frames appear with rising falling edges RCLK with delay tdb. synchronous outputs state machine outputs appear after falling edge STRBOUT with delays respectively. lower frame C0-C19 delayed further with additional latches that both C0-C19 C20-C39 frames synchronous.
required grounding chips. Integrating Capacitor integrating capacitors (C2) required both function properly. These caps used frequency phase lock directly stability lockup times. designed value with tolerance 10%. internal charging currents scaled with DIV0 DIV1 settings such that same capacitor value works with four frequency bands. Larger values improve jitter performance, extend lockup times. Power Supply Bypassing Grounding G-LINK chip been tested work well with single
CAV*, DAV*, LINKRDY, ERROR RCLK STRBOUT STAT0 STAT1
Supply Bypassing Integrator Capacitor
Figure shows location integrator capacitors, power supply capacitors
CAV*, DAV* STRBOUT STRBIN CONFIGURATIONS CONFIGURATIONS FLAG
FLAG
STRBOUT FRAME PERIOD STRBIN FLAG FRAME PERIOD CAV*, DAV* LINKRDY ERROR
CAV*, DAV* tstrb tmux STRBOUT STAT0 STAT1 RCLK FLAG
SETUP TIME HOLD TIME tstrb STRBIN STRBOUT DELAY tmux MULTIPLEXER DELAY
STRBOUT SYNCHRONOUS OUTPUTS DELAY STRBOUT STATE MACHINE OUTPUTS DELAY STRBOUT RCLK DELAY RCLK C00-C39 OUTPUT DELAY
Figure Transmitter Receiver Data Interface Timing Double Frame Mode (MDFSEL=0).
ECLGND
ECLGND
CAP0B CAP0A CAP1A CAP1B HGND
VIEW
HGND
ECLGND
ground plane, assuming that fairly clean ground plane. Thus, separate grounds (HGND, GND, ECLGND) connected onto this plane. bypassing ground should accomplished with capacitor (C1) series resistor (R1) This series network prevents possible oscillations caused package, capacitor, layout parasitics. ECLGND leads grounded using These resistors reduce excessive ringing caused current spikes generated parasitic inductance ECLGND leads. This effect more pronounced receiver because multiple outputs.The ECLGND pins simply grounded. some instances, either extreme high end, frequency STRBOUT exceeds maximum frequency allowed hosts. this case, recommended that diode clamp, used across integrating such that upper frequency limited. typical swing volts, thus, clamping diode should have turn-on voltage below such with germanium schottky diodes. This will vary with each application. This diode will also initial frequency lock-in process. Electrical Connections electrical I/Os both shown Figures 2123. data sheet uses prefix, logic type order identify input output lines respectively. Additional information names their functions
ECLGND
CAP0B CAP0A CAP1A CAP1B
VIEW
HGND
ECLGND ECLGND
ECLGND
BYPASS DAMPING RESISTOR ECLGND DAMPING RESISTOR BYPASS CAPACITOR INTEGRATOR CAPACITOR OPTIONAL CLAMPING DIODE OHMS OHMS
Figure Power Supply Bypass.
I-ECL
O-ECL ECLGND
-1.3 OUTPUT -1.9
INPUT
Figure I-ECL O-ECL Simplified Circuit Schematic.
found data sheet under Definitions. I-ECL O-ECL These designed interface directly ECL-100K family. simplified schematic diagram cell shown Figure Many interface theories techniques found commercial data books. I-ECL inputs have internal pull down resistors, such that left opened, logic level will float low. Also, inputs tied ground directly yield logic high. These inputs driven from standard buffers, using conventional termination techniques. Series terminations source also used. most cases, unconnected IECL input will suffice logic low. However, some I-ECL pins with adjacent high speed lines, such TCLKSEL affected crosstalk dependent trace separations board layout. this case, pins with logic lows
tied together bypassed ground with capacitor. O-ECL each drive line terminated with However, because multiple outputs, driving lines into loads will cause excessive power dissipation lead undesirable current spikes power ground planes. Therefore, recommended that termination resistor, which sets output bias current, limited minimize reflections, desirable match characteristic impedance line termination resistance. because board limitations, realistic values transmission lines more achievable. With lines, recommended that maximum distance transmission lines exceed preferred termination resistors individual surfacemount resistors, commonly connected which properly bypassed ground. Resistor packs such SIPs
acceptable, will reduce noise margins extra parasitics. Each O-ECL outputs small trickle current which turns output emitter follower such that logic levels would appear without external pull-down terminations. This feature useful testing system debugging. High Speed Interface: I-H50 O-BLL simplified schematic diagrams I-H50 O-BLL shown Figure I-H50 input cell internal resistors built into differential input lines. termination connected HGND which isolates high speed ground currents from internal grounds. level inputs Since high speed inputs into G-LINK have component, recommended that I-H50 inputs coupled with capacitor. also recommended that unused differential inputs terminated with OBLL output cell designed
deliver swings directly into output impedance matched with VSWR less than above GHz. This output ideal driving IH50 input through cable coupling capacitor. shunt resistor ground improves internal bias O-BLL differential output circuit. O-BLL driver also connected directly into high speed oscilloscope. optimum performance, both output should same impedance. necessary that used O-BLL outputs terminated into Figure shows various methods
interfacing O-BLL I-H50 standard logic.
Positive Operation
Many applications require interface standard logic family. Such TTL/ECL translators available industry from various semiconductor manufacturers. This works well, requires power supplies since system supporting different logic families. This technique preferred, since easier keep single clean ground plane.
Although G-LINK been designed work with conventional negative supply, single positive supply also used. This basically replaces traditional ground planes with ground planes. Also, termination plane shifted theory, since voltages relative, there should difference. practice, however, differences well plane bypassed ground, since I/Os referenced this plane. therefore necessary separate CMOS this chip set, that cleanest plane achieved.
O-BLL
I-H50
HGND
Figure I-H50 O-BLL Simplified Circuit Schematic.
Likewise, plane must also bypassed equally well. positive supply configuration, logic outputs PECL (positive ECL) states. Commercial translation chips available which will translate PECL between CMOS.
OBLL
IH50
SINGLE-ENDED DRIVE O-BLL I-H50 INTERFACE
Mode Options
GLlink several option pins which modes operation. Common both M20SEL, DIV0, DIV1, FLAGSEL, LOOPEN. Local MDFSEL, EHCLKSEL, HCLKON. While local EQEN TCLKSEL. These pins I-ECL, described below. M20SEL sets width frame 16/20 bits. DIV1 DIV0 frequency bands operation. Refer Setting Operating Data Rate Range section frequency band selection. recommended that applications near ends bands have jumpers DIV0 DIV1 inputs, that board accommodate possible lot-tolot band variations over life board design. FLAGSEL selects either flag reserved error detection link, extra available user.
OBLL IH50
DIFFERENTIAL DRIVE O-BLL I-H50
-1.3
OBLL
-1.3
DIFFERENTIAL DRIVE O-BLL
OBLL
SINGLE-ENDED DRIVE O-BLL
Figure Methods Interfacing O-BLL I-H50.
LOOPEN selects either normal data loop channels I/O. MDFSEL selects single double frame modes. ECHKSEL selects either lock onto frame-rate clock STRBIN this clock high speed clock bypass This input used mainly testing, should normally low. HCLKON turns high speed serial clock outputs This option added conserve power. EQEN disables enables data equalizer cable applications. TCLKSEL selects clock source from either derived from serial data stream from TCLK inputs This input testing only, should normally low.

HDMP-1012 Transmitter HDMP-1014 Receiver Features Transparent, Ex

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