Preparing Files Warp Enterprise/Professional When user receives c

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Preparing Files Warp Enterprise/Professional When user receives c

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Method Instantiate Core Warp Enterprise/ProfessionalThis application note intended assist people cores from party vendors Cypress CPLDs. These cores distributed using file format which generated WarpTM. This note contains detailed description steps required instantiate core contained file using Warp Enterprise/ProfessionalTool. Please refer application note "Method Instantiate Core Warp with Cypress CPLDs" additional information. Choose path library. Usually, should same path design mentioned Step
Preparing Files Warp Enterprise/Professional
When user receives core package from party Vendor, Cores form files. files used Warp describe functional blocks cores. core package consists core files VHDL Verilog wrappers. Start Warp Enterprise/Professional select "View Flow". Figure will appear user click different component design flow accomplish task described figure.
Creating Project Warp Enterprise/Professional
Upon entering Warp Enterprise/Professional, user required create design. "File Design." obtain Figure
Figure Creating Design Warp Enterprise/Professional. user choose existing resource files create empty design. user should choose existing resource files downloaded wrapper used. Follow instruction this wizard create design. Choose default device Delta39K. user choose directory where design stored. default, design will created directory "C:\Cypress\Designs\library name". Where "library name" library name created Step user choose create library within design. "Design Create Library.". Follow instructions create library wizard create library.
Figure Design Flow Diagram Warp Enterprise/Professional. Figure click `Tools' picture, then `Synthesis Library Manager' picture shown arrow Figure library window will automatically appear Warp Enterprise/Professional will automatically create Warp library. content Warp library stored synthesis folder under same directory design created section Creating project Warp Enterprise/Professional".
Cypress Semiconductor Corporation
3901 North First Street
Jose
95134
408-943-2600 August 2000
Method Instantiate Core Warp Enterprise/ProfessionalDesign Using Downloaded Wrapper files Warp Enterprise/Professional". directory .\synthesis\vhd obtain postfit netlist Step import into project. Instantiate this postfit netlist user's design. Make sure that component declaration postfit netlist matches instantiation user's design. original wrapper generics, postfit netlist will contain generics. user must compile wrapper with generic values wanted design. This involves changing default values generics original wrapper compiling wrapper with change. "Design Compile All" compile files project. Write appropriate testbench instantiate design containing core testbench. Figure Warp Synthesis Library Click cancel close library window. same synthesis folder created step copy downloaded files index file folder named "lc<devicename>" where "<devicename>" name device. example, files were c39k100 device, folder name would "lc39k100". index file automatically generated Warp upon Warp project compilation. "Simulation Initialize Simulation". This will allow user pick top-level file simulated. This top-level file testbench file. Note: Even though this prefit simulation, there time delays core post-fit netlist.
Creating Block Diagram Warp Enterprise/Professional
block diagram created VHDL component. This application note will VHDL wrapper source block diagram created. Create design follow instructions given section "How Core Prefit Simulation Warp Enterprise/Professional" prepare files this design. Import VHDL wrapper file this design. Highlight this file Design Browser "Design Compile" compile this file. When design successfully compiled, check mark should appear beside wrapper file design browser. Click drop-down arrow `New' button choose `Block Diagram' shown Figure arrow. This will create block diagram editor without going through wizard.
Compile Design Using Downloaded Wrapper Files Warp Enterprise/Professional
wrapper VHDL Verilog file Warp project. Instantiate wrapper user's design. user also compile wrapper Warp itself. process both same. After files present library, click `Synthesis Option' button Figure make sure that synthesis options correctly. suggested that user disables "logic memory mapping". Specify target device clicking 'Device' picture Figure select device. Click `Implementation' picture Figure another window will come displaying files library. Select files compiled synthesized Warp. `OK' this will link Warp synthesize design library using Warp. user `Report` button view report file.
Core Prefit Simulation Warp Enterprise/Professional.
user prefit simulation with real timing values cores Warp Enterprise/Professional. This means that user's design functionally simulated only post-fit model core contains propagation delays. user's design Cypress CPLD. Create project directed section "Creating Project Warp Enterprise/Professional". Compile wrapper core following entire procedure outlined section "How compile Figure Button Drop-down display
Method Instantiate Core Warp Enterprise/Professional
Once Block editor file comes click `Show Symbols Toolbox' button shown below. This will bring list symbols user import into block editor. This `Show Symbols Toolbox' button.
Attach appropriate input output terminals block diagram. user should input output terminals std_logic_vector. example final block diagram shown Figure
Figure pick entity Wrapper file. Click yellow rectangular component pointed arrow drag Block Editor file. generic rectangular block instantly generated with correct port names.
Figure Block Diagram Wrapper mi2c. After user done with their design wishes create file either VHDL, Verilog EDIF based this block design, "Diagram Target HDL." click appropriate language generate. Save block design "Diagram Generate Code" generate VHDL code.
Conclusion
Figure Symbols Toolbox Block Editor. user then `Block Editor' feature Warp Enterprise/Professional shown Figure his/her design with core wrappers. This document illustrates steps required Warp Enterprise/Professional with cores. Having pre-verified optimized solutions functional blocks enables designers concentrate developing custom logic, resulting significant reduction design cycle time.
Testing Block Diagram
After creating block diagram based VHDL file described previous section, user wish compile block diagram Warp obtain timing values test functionality design. example given this application note, block diagram core. Create Block Editor File following Step section "Creating Block Diagram Warp Enterprise/Professional" instantiate block following Steps same section. `terminal' button shown below. Click drop-down arrow obtain different input output terminals. This button varies according last terminal selected.
Cypress Semiconductor Corporation, 2000. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

Preparing Files Warp Enterprise/Professional When user receives c

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