order meet demand increasingly complex designs, Cypress formed Oasis p

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order meet demand increasingly complex designs, Cypress formed Oasis p

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Method Instantiate Core Warpwith Cypress CPLDs
order meet demand increasingly complex designs, Cypress formed Oasis partnership program with leading vendors provide cores Cypress CPLDs. Cores blocks that have been tested optimized specifically Cypress CPLDs. These cores represent multitude functions like PCI, SDRAM, UTOPIA, HDLC more. Having pre-verified optimized solutions functional blocks enables designers concentrate developing custom logic, resulting significant reduction design cycle time. This application note describes detail customers incorporate cores their system level designs. cores available file format, generated Warp- Cypress's CPLD development system. This note contains detailed description steps required instantiate files both VHDL Verilog designs.
Preparing files Warp
When user receives core package from party Vendor, cores form files. files used Warp describe functional blocks such cores. files design, following: same directory newly created Warp project, create folder. name this folder should same device design with `lc' prefix attached example, target device c39k100, then folder name `lc39k100'. Copy entire folder containing files index file into this newly created folder.
Create Wrapper files VHDL
Though Cypress cores supplied with wrappers, this section included illustrate wrapper constructed. Find entity declaration original source file. example, VHDL code below contains original Entity declaration source file from which created. library ieee; ieee.std_logic_1164.all; entity VIFexample port( rxclav_int: std_logic; rx_tristate_clav: std_logic; rxaddr: std_logic; rxenb: std_logic; tristate_all_outputs: std_logic; rxsoc_int: std_logic; rxdata_int: std_logic;
Create files Warp
most cases, user will need perform steps mentioned this section files wrappers downloaded from vendor's page. Create project Warp import correct Verilog files into this project. Disable `Set Top' icon shows file clicking button shown below. This will cause Warp compile file format, there only file project, "Compile Selected File(s)" create file this file. compile using "Compile Project" option `Set Top' icon automatically placed file. This `Set Top' button
Choose device going "Project Select Device.". data sheet cores will state device downloaded core targeted example, suppose device selected c39k100. Compile entire project. This will create files each files compiled this project. `Set Top' feature step turned off, file created file with `Set Top' feature. files placed directory that same name device selected with `lc' prefix. this example, directory name `lc39k100'. path this directory same path project created step generate files different device, repeat step
rxprty_int: std_logic; underrun: std_logic VIFexample;
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Method Instantiate Core Warpwith Cypress CPLDs
Create entity wrapper with same ports entity declaration original file. user choose different name same name entity file, keep mode type same. VHDL code below, prefix `top' added port names. entity VIFVHDLWrapper port( toprxclav_int: std_logic; toprx_tristate_clav: std_logic; toprxaddr: std_logic_vector(4 downto toprxenb: std_logic; toptristate_all_outputs: toprxsoc_int: std_logic; toprxdata_int: std_logic_vector(15 downto toprxprty_int: std_logic; topunderrun: std_logic VIFVHDLWrapper; After architecture section this wrapper before `begin' reserved word, create component with same name entity file. code below, component name VIFExample, which same entity name declared step architecture arch_VHDLWrapper VIFVHDLWrapper component VIFExample port rxclav_int: std_logic; rx_tristate_clav: std_logic; rxaddr: std_logic_vector(4 downto rxenb: std_logic; tristate_all_outputs: std_logic; rxsoc_int: std_logic; rxdata_int: std_logic_vector(15 downto rxprty_int: std_logic; underrun: std_logic component; begin architecture body after `begin' section, instantiate component component's ports top-level signals. example below, signals right side `=>' sign signals declared entity section this wrapper step VIFExample port rxclav_int toprxclav_int, rx_tristate_clav toprx_tristate_clav, std_logic;
rxaddr toprxaddr, rxenb toprxenb, tristate_all_outputs toptristate_all_outputs, rxsoc_int toprxsoc_int, rxdata_int toprxdata_int, rxprty_int toprxprty_int, underrun topunderrun compile, design create simulation model, please section "Compiling, Fitting, Creating Simulation Model".
Create Wrapper files Verilog
Though Cypress cores supplied with wrappers, this section included illustrate wrapper constructed. this section, assume that entity declaration file same code displayed step section "How Create Wrapper files VHDL". Create project file. This will wrapper file file. Create module with appropriate parameters. Usually, they same signal declaration your module shown below. -This beginning Verilog wrapper module toprx_tristate_clav, [4:0]toprxaddr, toprxenb, toptristate_all_outputs, toprxsoc_int, underrun) below signal declaration entity output toprxclav_int; output toprx_tristate_clav; input [4:0]toprxaddr; input toprxenb; output toptristate_all_outputs; output toprxsoc_int; output [15:0]toprxdata_int; output toprxprty_int; output underrun; above declarations instantiating entity file.
Method Instantiate Core Warpwith Cypress CPLDs
Instantiate entity files verilog file created step Note: Verilog case sensitive, make sure that component ports same entity declaration file. this code continues from Verilog code above instantiates entity file. VIFExample myVIF (.rxclav_int (toprxclav_int), .rx_tristate_clav (toprx_tristate_clav), .rxaddr (toprxaddr), .rxenb (toprxenb), .tristate_all_outputs (toptristate_all_outputs), .rxsoc_int (toprxsoc_int), .rxdata_int (toprxdata_int), .rxprty_int (toprxprty_int), .underrun (topunderrun) compile, design create simulation model, please section "Compiling, Fitting Creating Simulation Model".
architecture body after `begin' section, instantiate component signals wrapper. example below, signals right side "=>" sign signals user plans design with this wrapper component. begin following code continuation above code consisting component declaration. VIFVHDLWrapper toprxclav_int "fill this section with proper signals" toprx_tristate_clav insert proper signals here. toprxaddr insert proper signals here toprxenb toptristate_all_outputs toprxsoc_int toprxdata_int toprxprty_int topunderrun After instantiating this wrapper, user link signals his/her design.
Downloaded Wrapper Files VHDL
steps described this section intended help users have received core files wrappers want them VHDL design. Instantiating core with wrappers same instantiating other component VHDL. user's design, create component with same name entity wrapper file. This component should declared after architecture section before `begin' reserved word. example component declaration VHDL wrapper described section "How Create Wrapper files VHDL" shown below. architecture arch_userdesign userdesign below component declaration placed between architecture begin reserved words. component VIFVHDLWrapper port( toprxclav_int: std_logic; toprx_tristate_clav: std_logic; toprxaddr: std_logic_vector(4 downto0); toprxenb: std_logic; toptristate_all_outputs: std_logic; toprxsoc_int: std_logic; toprxdata_int: std_logic_vector(15 downto toprxprty_int: std_logic; topunderrun: std_logic begin
Downloaded Wrapper Files Verilog
steps described this section intended help users have received core files wrappers want them Verilog design. Instantiating core with wrappers same instantiating other module Verilog. Verilog example Verilog wrapper created section "How Create Wrapper Files Verilog" shown below. This instantiated body Verilog code. module userdesign output signal1 signal declaration this placed after signal declaration Verilog code VerilogVIFWrapper myVerilogwrapper (.toprxclav_int(signal1), .toprx_tristate_clav(signal2), .toprxaddr(signal3), .toprxenb(signal4), .toprxsoc_int(signal6), .toprxdata_int(signal7), .toprxprty_int(signal8), .topunderrun(signal9) Signal1, Signal2, etc. signals defined user's design linked wrapper's signals.
Method Instantiate Core Warpwith Cypress CPLDs
Verilog compilation, make sure wrapper compiled before user's design that Warp properly link wrapper appropriate file that instantiate
Compiling, Fitting, Creating Simulation Model
Make sure that "Enable Testbench Output" Warp file fitted. This accomplished going "Project Compiler Options." click `Synthesis' Folder. example this shown Figure user compiling post-fit netlist simulated Mentor Graphic's ModelSim, user should choose Timing Model "ModelT" shown Figure user compiling post-fit netlist simulated AldecTM, user should choose Timing Model "Active HDLSim Active VHDL"
"Compile Project" generate post-fit netlists ModelSim. default output netlist VHDL file, other output options chosen. default setting, netlists located folder having same path Warp project. more information importing simulating post-fit model ModelSim, please refer application note "Importing Warp post-fit netlists into Mentor Graphics' ModelSim". more information simulating post-fit model Aldec, please refer application note Introduction Active-HDLSim".
Making Core Input/Output Signal Visible User's Design
When core instantiated design, Warp will optimize Input/Output logic Core. This result some input output signals being visible simulation model. make these signals visible, "Synthesis_off" attribute should only signals that non-visible. This however, result slower performance complete design. This only recommended understanding behavior core final implementation.
Conclusion
Through applying procedure described this application note, user synthesize Cypress CPLDs Cypress software, increasing speed reducing design cycle time.
Figure Setting Testbench Output Simulation ModelSim.
Figure Setting Timing Model Compatible with Aldec Simulation Tool
Cypress Semiconductor Corporation, 2000. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

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