FLASH MEMORY 8/1M FEATURES Single read, program, erase

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FLASH MEMORY 8/1M FEATURES Single read, program, erase

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DS05-20877-1E
FLASH MEMORY
8/1M
FEATURES
Single read, program, erase Minimizes system level power requirements Compatible with JEDEC-standard commands Uses same software commands E2PROMs Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(I) (Package suffix: PFTN Normal Bend Type, PFTR Reversed Bend Type) 48-ball FBGA (Package suffix: PBT) Minimum 100,000 program/erase cycles High performance maximum access time Sector erase architecture Eight word thirty word sectors word mode Eight byte thirty byte sectors byte mode combination sectors concurrently erased. Also supports full chip erase. Boot Code Sector Architecture sector Bottom sector Time Protect (OTP) region Byte accessible through "OTP Enable" command sequence Factory serialized protected provide secure electronic serial number (ESN) WP/ACC input VIL, allows protection boot sectors, regardless sector protection/unprotection status VIH, allows removal boot sector protection VHH, increases program performance Embedded EraseAlgorithms Automatically pre-programs erases chip sector Embedded ProgramAlgorithms Automatically writes verifies data specified address Data Polling Toggle feature detection program erase cycle completion Ready/Busy output (RY/BY) Hardware method detection program erase cycle completion
(Continued)
Embedded Eraseand Embedded Programare trademarks Advanced Micro Devices, Inc.
(Continued) Automatic sleep mode When addresses remain stable, automatically switch themselves power mode. Erase Suspend/Resume Suspends erase operation allow read another sector within same device Sector group protection Hardware method disables combination sector groups from program erase operations Sector Group Protection function Extended sector group protection command Fast Programming Function Extended Command Temporary sector group unprotection Temporary sector group unprotection RESET pin. accordance with (Common Flash Memory Interface)
PACKAGE
48-pin plastic TSOP
Marking Side
48-pin plastic TSOP
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
48-ball FBGA
(BGA-48P-M13)
GENERAL DESCRIPTION
MBM29SL160TD/BD 16M-bit, V-only Flash memory organized bytes bits each words bits each. MBM29SL160TD/BD offered 48-pin TSOP(I) 48-ball FBGA Package. These devices designed programmed in-system with standard system supply. 12.0 required write erase operations. devices also reprogrammed standard EPROM programmers. standard MBM29SL160TD/BD offer access times allowing operation high-speed microprocessors without wait states. eliminate contention devices have separate chip enable (CE), write enable (WE), output enable (OE) controls. MBM29SL160TD/BD command compatible with JEDEC standard E2PROMs. Commands written command register using standard microprocessor write timings. Register contents serve input internal state-machine which controls erase programming circuitry. Write cycles also internally latch addresses data needed programming erase operations. Reading data devices similar reading from 12.0 Flash EPROM devices. MBM29SL160TD/BD programmed executing program command sequence. This will invoke Embedded Program Algorithm which internal algorithm that automatically times program pulse widths verifies proper cell margin. Typically, each sector programmed verified about seconds. Erase accomplished executing erase command sequence. This will invoke Embedded Erase Algorithm which internal algorithm that automatically preprograms array already programmed before executing erase operation. During erase, devices automatically time erase pulse widths verify proper cell margin. sector typically erased verified second. already completely preprogrammed.) devices also feature sector erase architecture. sector mode allows each sector erased reprogrammed without affecting other sectors. MBM29SL160TD/BD erased when shipped from factory. devices feature single power supply operation both read write functions. Internally generated regulated voltages provided program erase operations. detector automatically inhibits write operations loss power. program erase detected Data Polling DQ7, Toggle feature DQ6, RY/BY output pin. Once program erase cycle been completed, devices internally reset read mode. Fujitsu's Flash technology combines years EPROM E2PROM experience produce highest levels quality, reliability, cost effectiveness. MBM29SL160TD/BD memories electrically erase entire chip bits within sector simultaneously Fowler-Nordhiem tunneling. bytes/words programmed byte/word time using EPROM programming mechanism electron injection.
Table Sector Address Sector SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
Sector Address Tables (MBM29SL160TD)
Sector Size (Kbytes/ Kwords)
Address Range 000000H 00FFFFH 010000H 01FFFFH 020000H 02FFFFH 030000H 03FFFFH 040000H 04FFFFH 050000H 05FFFFH 060000H 06FFFFH 070000H 07FFFFH 080000H 08FFFFH 090000H 09FFFFH 0A0000H 0AFFFFH 0B0000H 0BFFFFH 0C0000H 0CFFFFH 0D0000H 0DFFFFH 0E0000H 0EFFFFH 0F0000H 0FFFFFH 100000H 10FFFFH 110000H 11FFFFH 120000H 12FFFFH 130000H 13FFFFH 140000H 14FFFFH 150000H 15FFFFH 160000H 16FFFFH 170000H 17FFFFH 180000H 18FFFFH 190000H 19FFFFH 1A0000H 1AFFFFH 1B0000H 1BFFFFH 1C0000H 1CFFFFH 1D0000H 1DFFFFH 1E0000H 1EFFFFH 1F0000H 1F1FFFH 1F2000H 1F3FFFH 1F4000H 1F5FFFH 1F6000H 1F7FFFH 1F8000H 1F9FFFH 1FA000H 1FBFFFH 1FC000H 1FDFFFH 1FE000H 1FFFFFH
Address Range 000000H 007FFFH 008000H 00FFFFH 010000H 017FFFH 018000H 01FFFFH 020000H 027FFFH 028000H 02FFFFH 030000H 037FFFH 038000H 03FFFFH 040000H 048000H 048000H 04FFFFH 050000H 058000H 058000H 05FFFFH 060000H 068000H 068000H 06FFFFH 070000H 078FFFH 078000H 07FFFFH 080000H 088000H 088000H 08FFFFH 090000H 098000H 098000H 09FFFFH 0A0000H 0A7FFFH 0A8000H 00AFFFH 0B0000H 0B7000H 0B8000H 0BFFFFH 0C0000H 0C7FFFH 0C8000H 0CFFFFH 0D0000H 0D7FFFH 0D8000H 0DFFFFH 0E0000H 0E7FFFH 0E8000H 0EFFFFH 0F0000H 0F7000H 0F8000H 0F8FFFH 0F9000H 0F9FFFH 0FA000H 0FAFFFH 0FB000H 0FBFFFH 0FC000H 0FCFFFH 0FD000H 0FDFFFH 0FE000H 0FEFFFH 0FF000H 0FFFFFH
64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
Note: address range A19: byte mode (BYTE VIL). address range A19: word mode (BYTE VIH)
Table Sector Address Sector SA38 SA37 SA36 SA35 SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10
Sector Address Tables (MBM29SL160BD)
Sector Size (Kbytes/ Kwords)
Address Range 1F0000H 1FFFFFH 1E0000H 1EFFFFH 1D0000H 1DFFFFH 1C0000H 1CFFFFH 1B0000H 1BFFFFH 1A0000H 1AFFFFH 190000H 19FFFFH 180000H 18FFFFH 170000H 17FFFFH 160000H 16FFFFH 150000H 15FFFFH 140000H 14FFFFH 130000H 13FFFFH 120000H 12FFFFH 110000H 11FFFFH 100000H 10FFFFH 0F0000H 0FFFFFH 0E0000H 0EFFFFH 0D0000H 0DFFFFH 0C0000H 0CFFFFH 0B0000H 0BFFFFH 0A0000H 0AFFFFH 090000H 0FFFFFH 080000H 08FFFFH 070000H 07FFFFH 060000H 06FFFFH 050000H 05FFFFH 040000H 04FFFFH 030000H 03FFFFH 020000H 02FFFFH 010000H 01FFFFH 00E000H 00FFFFH 00C000H 00DFFFH 00A000H 00BFFFH 008000H 009FFFH 006000H 007FFFH 004000H 005FFFH 002000H 003FFFH 000000H 001FFFH
Address Range 0F8000H 0FFFFFH 0F0000H 0F7FFFH 0E8000H 0EFFFFH 0E0000H 0E7FFFH 0D8000H 0DFFFFH 0D0000H 0D7FFFH 0C8000H 0CFFFFH 0C0000H 0C7FFFH 0B8000H 0BFFFFH 0B0000H 0B7FFFH 0A8000H 0AFFFFH 0A0000H 0A7FFFH 098000H 09FFFFH 090000H 097FFFH 088000H 08FFFFH 080000H 087FFFH 078000H 07FFFFH 070000H 077FFFH 068000H 06FFFFH 060000H 067FFFH 058000H 05FFFFH 050000H 057FFFH 048000H 04FFFFH 040000H 047FFFH 038000H 03FFFFH 030000H 037FFFH 028000H 02FFFFH 020000H 027FFFH 018000H 01FFFFH 010000H 017FFFH 008000H 008FFFH 007000H 007FFFH 006000H 006FFFH 005000H 005FFFH 004000H 004FFFH 003000H 003FFFH 002000H 002FFFH 001000H 001FFFH 000000H 000FFFH
64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
Note: address range A19: byte mode (BYTE VIL). address range A19: word mode (BYTE VIH).
Table Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16
Sector Group Addresses (MBM29SL160TD) (Top Boot Block) SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA28 SA30 SA11 SA12 SA15 SA16 SA19 SA20 SA23 SA24 SA27 Sectors
Table Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16
Sector Group Addresses (MBM29SL160BD) (Bottom Boot Block) SA38 SA35 SA37 SA11 SA14 SA15 SA18 SA19 SA22 SA23 SA26 SA27 SA30 SA31 SA34 SA10 Sectors
PRODUCT LINE
Part Ordering Part Max. Address Access Time (ns) Max. Access Time (ns) Max. Access Time (ns) V±0.2V MBM29SL160TD/MBM29SL160BD
BLOCK DIAGRAM
RY/BY Buffer RY/BY
Erase Voltage Generator
Input/Output Buffers
BYTE RESET WP/ACC Command Register Program Voltage Generator Chip Enable Output Enable Logic Data Latch State Control
Y-Decoder
Y-Gating
Detector
Timer Program/Erase
Address Latch
X-Decoder
Cell Matrix
CONNECTION DIAGRAMS
TSOP(I) N.C. RESET WP/ACC RY/BY (Marking Side) BYTE 15/A-1 DQ14 DQ13 DQ12 DQ11 DQ10
MBM29SL160TD/MBM29SL160BD Standard Pinout
FPT-48P-M19 RY/BY WP/ACC N.C. RESET N.C. (Marking Side) DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 BYTE
MBM29SL160TD/MBM29SL160BD Reverse Pinout
FPT-48P-M20
(Continued)
FBGA (TOP VIEW) Marking side
(BGA-48P-M03)
RY/BY N.C. DQ10 DQ11
RESET N.C. DQ12
DQ14 DQ13
BYTE DQ15/A-1
WP/ACC
LOGIC SYMBOL
Table MBM29SL160TD/BD Configuration
DQ15 RESET BYTE WP/ACC RY/BY
Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Ready/Busy Output Hardware Reset Pin/Temporary Sector Group Unprotection Selects 8-bit 16-bit mode Hardware Write Protection/Program Acceleration Internal Connection Device Ground Device Power Supply
A-1, DQ15 RY/BY RESET BYTE WP/ACC N.C.
Table MBM29SL160TD/BD User Operations (BYTE VIH) Operation Auto-Select Manufacturer Code Auto-Select Device Code Read Standby Output Disable Write (Program/Erase) Enable Sector Group Protection (2), Verify Sector Group Protection (2), Temporary Sector Group Unprotection Reset (Hardware)/Standby Boot Block Sector Write Protection DQ15 RESET WP/ACC Code Code DOUT HIGH-Z HIGH-Z Code HIGH-Z
Table MBM29SL160TD/BD User Operations (BYTE VIL) Operation Auto-Select Manufacturer Code Auto-Select Device Code Read Standby Output Disable Write (Program/Erase) Enable Sector Group Protection (2), Verify Sector Group Protection (2), Temporary Sector Group Unprotection Reset (Hardware)/Standby Boot Block Sector Write Protection DQ15/ RESET WP/ACC Code Code DOUT HIGH-Z HIGH-Z Code HIGH-Z
Legend: VIL, VIH, VIH,
Pulse input. Characteristics voltage levels.
Notes: Manufacturer device codes also accessed command register write sequence. Table Refer section Sector Group Protection. VIL, initiates write operations. also used extended sector group protection.
FUNCTIONAL DESCRIPTION
Read Mode
MBM29SL160TD/BD have control functions which must satisfied order obtain data outputs. power control should used device selection. output control should used gate data output pins device selected. Address access time (tACC) equal delay from stable addresses valid output data. chip enable access time (tCE) delay from stable addresses stable valid data output pins. output enable access time delay from falling edge valid data output pins. (Assuming addresses have been stable least tACC-tOE time.) When reading data without changing addresses after power-up, necessary input hardware reset change from
Standby Mode
There ways implement standby mode MBM29SL160TD/BD devices, using both RESET pins; other RESET only. When using both pins, CMOS standby mode achieved with RESET inputs both held Under this condition current consumed less than max. During Embedded Algorithm operation, active current (ICC2) required even "H". device read with standard access time (tCE) from either these standby modes. When using RESET only, CMOS standby mode achieved with RESET input held "L"). Under this condition current consumed less than max. Once RESET taken high, device requires wake time before outputs valid read access. standby mode outputs high impedance state, independent input.
Automatic Sleep Mode
There function called automatic sleep mode restrain power consumption during read-out MBM29SL160TD/BD data. This mode used effectively with application requested power consumption such handy terminals. activate this mode, MBM29SL160TD/BD automatically switch themselves power mode when MBM29SL160TD/BD addresses remain stably during access fine necessary control mode. Under mode, current consumed typically (CMOS Level). During simultaneous operation, active current (ICC2) required. Since data latched during this mode, data read-out continuously. addresses changed, mode canceled automatically MBM29SL160TD/BD read-out data changed addresses.
Output Disable
With input logic high level (VIH), output from devices disabled. This will cause output pins high impedance state.
Autoselect
autoselect mode allows reading binary code from devices will identify manufacturer type. This mode intended programming equipment purpose automatically matching devices programmed with corresponding programming algorithm. This mode functional over entire temperature range devices. activate this mode, programming equipment must force address identifier bytes then sequenced from devices outputs toggling address from VIH. addresses DON'T CARES except (A-1). (See Tables
manufacturer device codes also read command register, instances when MBM29SL160TD/BD erased programmed system without access high voltage pin. command sequence illustrated Table (Refer Autoselect Command section.) Word VIL) represents manufacturer's code (Fujitsu 04H) word VIH) represents device identifier code (MBM29SL160TD MBM29SL160BD mode; MBM29SL160TD 22E4H MBM29SL160BD 22E7H mode). These bytes/words given tables 6.2. identifiers manufactures device will exhibit parity with defined parity bit. order read proper device codes when executing autoselect, must VIL. (See Tables 6.2.) Table Type Manufacture's Code Byte MBM29SL160TD Device Code MBM29SL160BD Word Sector Group Protection Byte mode. Outputs protected sector group addresses outputs unprotected sector group addresses. Table Type Manufacturer's Code MBM29SL160TD Device Code MBM29SL160BD 22E7H Sector Group Protection (B): Byte mode (W): Word mode
A-1/0
MBM29SL160TD/BD Sector Group Protection Verify Autoselect Codes Word Byte Sector Group Addresses 22E7H 01H*2 22E4H A-1*1 Code (HEX)
Expanded Autoselect Code Table
Code
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 A-1/0
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
22E4H
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
Write
Device erasure programming accomplished command register. contents register serve inputs internal state machine. state machine outputs dictate function device. command register itself does occupy addressable memory location. register latch used store commands, along with address data information needed execute command. command register written bringing VIL, while VIH. Addresses latched falling edge whichever happens later; while data latched rising edge whichever happens first. Standard microprocessor write timings used. Refer Write Characteristics Erase/Programming Waveforms specific timing parameters.
Sector Group Protection
MBM29SL160TD/BD feature hardware sector group protection. This feature will disable both program erase operations combination seventeen sector groups memory. (See Tables 2.2). sector group protection feature enabled using programming equipment user's site. device shipped with sector groups unprotected. activate this mode, programming equipment must force address control (suggest 11V), VIL, VIH. sector group addresses (A19, A18, A17, A16, A15, A14, A13, A12) should sector protected. Tables define sector address each thirty nine (39) individual sectors, tables define sector group address each seventeen (17) individual group sectors. Programming protection circuitry begins falling edge pulse terminated with rising edge same. Sector group addresses must held constant during pulse. figures sector group protection waveforms algorithm. verify programming protection circuitry, programming equipment must force address with VIH. Scanning sector group addresses (A19, A18, A17, A16, A15, A14, A13, A12) while (A6, will produce logical code device output protected sector. Otherwise device will produce unprotected sector. this mode, lower order addresses, except DON'T CARES. Address locations with reserved Autoselect manufacturer device codes. requires apply byte mode. also possible determine sector group protected system writing Autoselect command. Performing read operation address location XX02H, where higher order addresses (A19, A18, A17, A16, A15, A14, A13, A12) desired sector group address will produce logical protected sector group. Tables Autoselect codes.
Temporary Sector Group Unprotection
This feature allows temporary unprotection previously protected sector groups MBM29SL160TD/BD devices order change data. Sector Group Unprotection mode activated setting RESET high voltage (VID). During this mode, formerly protected sector groups programmed erased selecting sector group addresses. Once taken away from RESET pin, previously protected sector groups will protected again. Refer Figures
RESET Hardware Reset
MBM29SL160TD/BD devices reset driving RESET VIL. RESET pulse requirement kept (VIL) least "tRP" order properly reset internal state machine. operation process being executed will terminated internal state machine will reset read mode "tREADY" after RESET driven low. Furthermore, once RESET goes high, devices require additional "tRH" before will allow read access. When RESET low, devices will standby mode duration pulse data output pins will tri-stated. hardware reset occurs during program erase operation, data that particular location will corrupted. Please note that RY/BY output signal should ignored during RESET pulse. Figure timing diagram. Refer Temporary Sector Group Unprotection additional functionality.
Boot Block Sector Protection
Write Protection function provides hardware method protecting certain boot sectors without using VID. This function provided WP/ACC pin. system asserts WP/ACC pin, device disables program erase functions "outermost" byte boot sectors independently whether those sectors were protected unprotected using method described "Sector Protection/Unprotection". outermost byte boot sectors sectors containing lowest addresses bottom-boot-configured device, sectors containing highest addresses top-boot-congfigured device. (MBM29SL160TD: SA37 SA38, MBM29SL160BD: SA1) system asserts WP/ACC pin, device reverts whether outermost byte boot sectors were last protected unprotected. That sector protection unprotection these sectors depends whether they were last protected unprotected using method described "Sector protection/unprotection".
Accelerated Program Operation
device offers accelerated program operations through function. This functions provided WP/ACC pin. This function primarily intended allow faster factory throughput percent. system asserts this pin, device automatically enters after mentioned Fast mode, temporarily unprotects protected sectors, uses higher voltage reduce time required program operations. system would two-cycle program command sequence required Fast mode. Removing from WP/ACC returns device normal operation. this function, please contact Fujitsu representative more information.
Table MBM29SL160TD/BD Command Definitions Command Sequence
Read/Reset Read/Reset Write Cycles Req'd
First Second Third Fourth Fifth Sixth Write Cycle Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data XXXH 555H AAAH 555H AAAH 555H AAAH 555H AAAH 555H AAAH XXXH XXXH 555H AAAH XXXH XXXH XXXH XXXH 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H 555H AAAH 555H AAAH 555H AAAH 555H AAAH 555H AAAH 555H AAAH
Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte
Autoselect
Program
Chip Erase
Sector Erase
Erase Suspend Erase Resume
Fast Mode Fast Program Reset from Fast Mode Extended Sector Group Protection Query Entry Program Exit
555H 2AAH 555H AAAH 555H AAAH 555H 2AAH AAAH 555H
Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte
XXXH XXXH
XXXH 555H AAAH 555H AAAH 555H AAAH
2AAH 555H 555H AAAH 2AAH 555H 555H AAAH 2AAH 555H XXXH 555H AAAH
Notes: Address bits address commands except Program Address (PA), Sector Address (SA). operations defined Tables Address memory location read Address memory location programmed Addresses latched falling edge write pulse. Address sector erased. combination A19, A18, A17, A16, A15, A14, A13, will uniquely select sector. Data read from location during read operation. Data programmed location Data latched falling edge write pulse. Sector group address protected. sector group address (SGA) (A6, Sector group protection verify data. Output protected sector group addresses output unprotected sector group addresses. OTPA Address area 29SL160TD (Top Boot Type) Word Mode: FFF7FH FFFFFH Byte Mode: 1FFEFFH 1FFFFFH 29SL160BD (Bottom Boot Type) Word Mode: 00000H 00080H Byte Mode: 00000H 00100H This command valid while Fast Mode. This command valid while RESET VID. valid addresses This command valid while mode. data "00H" also acceptable. system should generate following address patterns: Word Mode: 555H 2AAH addresses Byte Mode: AAAH 555H addresses Both Read/Reset commands functionally equivalent, resetting device read mode.
Command Definitions
Device operations selected writing specific address data sequences into command register. Writing incorrect address data values writing them improper sequence will reset devices read mode. Table defines valid register command sequences. Note that Erase Suspend (B0H) Erase Resume (30H) commands valid only while Sector Erase operation progress. Moreover both Read/Reset commands functionally equivalent, resetting device read mode. Please note that commands always written DQ15 bits ignored.
Read/Reset Command
order return from Autoselect mode Exceeded Timing Limits (DQ5 Read/Reset mode, Read/ Reset operation initiated writing Read/Reset command sequence into command register. Microprocessor read cycles retrieve array data from memory. devices remain enabled reads until command register contents altered. devices will automatically power-up Read/Reset state. this case, command sequence required read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that spurious alteration memory content occurs during power transition. Refer Read Characteristics Waveforms specific timing parameters.
Autoselect Command
Flash memories intended applications where local alters memory contents. such, manufacture device codes must accessible while devices reside target system. PROM programmers typically access signature codes raising high voltage. However, multiplexing high voltage onto address lines generally desired system design practice. device contains Autoselect command operation supplement traditional PROM programming methodology. operation initiated writing Autoselect command sequence into command register. Following command write, read cycle from address (XX)00H retrieves manufacture code 04H. read cycle from address (XX)01H returns device code (MBM29SL160TD MBM29SL160BD mode; MBM29SL160TD 22E4H MBM29SL160BD 22E7H mode), (See Tables 6.2.) manufacturer device codes will exhibit parity with defined parity bit. Sector state (protection unprotection) will informed address (XX)02H ((XX)04H Scanning sector group addresses (A19, A18, A17, A16, A15, A14, A13, A12) while (A6, will produce logical device output protected sector group. programming verification should performed verify sector group protection protected sector. (See Tables terminate operation, necessary write Read/Reset command sequence into register, also write Autoselect command during operation, execute after writing Read/Reset command sequence.
Byte/Word Programming
devices programmed byte-by-byte word-by-word) basis. Programming four cycle operation. There "unlock" write cycles. These followed program set-up command data write cycles. Addresses latched falling edge whichever happens later data latched rising edge whichever happens first. rising edge (whichever happens first) begins programming. Upon executing Embedded Program Algorithm command sequence, system required provide further controls timings. device will automatically provide adequate internally generated program pulses verify programmed cell margin.
system determine status program operation using (Data Polling), (Toggle Bit), RY/BY. Data Polling Toggle must performed memory location which being programmed. automatic programming operation completed when data equivalent data written this which time devices return read mode addresses longer latched. (See Table Hardware Sequence Flags.) Therefore, devices require that valid address devices supplied system this particular instance time. Hence, Data Polling must performed memory location which being programmed. commands written chip during this period will ignored. hardware reset occurs during programming operation, impossible guarantee data being written. Programming allowed sequence across sector boundaries. Beware that data cannot programmed back "1". Attempting either hang device result apparent success according data polling algorithm read from Read/Reset mode will show that data still "0". Only erase operations convert "0"s "1"s. Figure illustrates Embedded ProgramAlgorithm using typical command strings operations.
Chip Erase
Chip erase cycle operation. There "unlock" write cycles. These followed writing "set-up" command. more "unlock" write cycles then followed chip erase command. Chip erase does require user program device prior erase. Upon executing Embedded Erase Algorithm command sequence devices will automatically program verify entire memory zero data pattern prior electrical erase (Preprogram function). system required provide controls timings during these operations. system determine status erase operation using (Data Polling), (Toggle Bit), RY/BY. chip erase begins rising edge last whichever happens first command sequence terminates when data (See Write Operation Status section.) which time device returns read mode. Chip Erase Time; Sector Erase Time sectors Chip Program Time (Preprogramming) Figure illustrates Embedded EraseAlgorithm using typical command strings operations.
Sector Erase
Sector erase cycle operation. There "unlock" write cycles. These followed writing "set-up" command. more "unlock" write cycles then followed Sector Erase command. sector address (any address location within desired sector) latched falling edge whichever happens later, while command (Data 30H) latched rising edge which happens first. After time-out 50µs from rising edge last sector erase command, sector erase operation will begin. Multiple sectors erased concurrently writing cycle operations Table This sequence followed with writes Sector Erase command addresses other sectors desired concurrently erased. time between writes must less than 50µs otherwise that command will accepted erasure will start. recommended that processor interrupts disabled during this time guarantee this condition. interrupts re-enabled after last Sector Erase command written. time-out 50µs from rising edge last whichever happens first will initiate execution Sector Erase command(s). another falling edge whichever happens first occurs within 50µs time-out window timer reset. (Monitor determine sector erase timer window still open, section DQ3, Sector Erase Timer.) command other than Sector Erase Erase Suspend during this time-out period will reset devices read mode, ignoring previous command string. Resetting devices once execution begun will corrupt data sector. that case, restart erase those sectors allow them
complete. (Refer Write Operation Status section Sector Erase Timer operation.) Loading sector erase buffer done sequence with number sectors 38). Sector erase does require user program devices prior erase. devices automatically program memory locations sector(s) erased prior electrical erase (Preprogram function). When erasing sector sectors remaining unselected sectors affected. system required provide controls timings during these operations. system determine status erase operation using (Data Polling), (Toggle Bit), RY/BY. sector erase begins after 50µs time from rising edge whichever happens first last sector erase command pulse terminates when data (See Write Operation Status section.) which time devices return read mode. Data polling Toggle must performed address within sectors being erased. Multiple Sector Erase Time; [Sector Erase Time Sector Program Time (Preprogramming)] Number Sector Erase Figure illustrates Embedded EraseAlgorithm using typical command strings operations.
Erase Suspend/Resume
Erase Suspend command allows user interrupt Sector Erase operation then perform data reads from programs sector being erased. This command applicable ONLY during Sector Erase operation which includes time-out period sector erase. Erase Suspend command will ignored written during Chip Erase operation Embedded Program Algorithm. Writting Erase Suspend command (B0H) during Sector Erase time-out results immediate termination time-out period suspension erase operation. Writing Erase Resume command (30H) resumes erase operation. address DON'T CARES when writing Erase Suspend Erase Resume command (30H). When Erase Suspend command written during Sector Erase operation, device will take maximum 20µs suspend erase operation. When devices have entered erase-suspended mode, RY/BY output will Hi-Z will logic "1", will stop toggling. user must address erasing sector reading determine erase operation been suspended. Further writes Erase Suspend command ignored. When erase operation been suspended, devices default erase-suspend-read mode. Reading data this mode same reading from standard read mode except that data must read from sectors that have been erase-suspended. Successively reading from erase-suspended sector while device erase-suspend-read mode will cause toggle. (See section DQ2.) After entering erase-suspend-read mode, user program device writing appropriate command sequence Program. This program mode known erase-suspend-program mode. Again, programming this mode same programming regular Program mode except that data must programmed sectors that erase-suspended. Successively reading from erase-suspended sector while devices erase-suspend-program mode will cause toggle. erasesuspended Program operation detected RY/BY output pin, Data polling Toggle (DQ6) which same regular Program operation. Note that must read from Program address while read from address. resume operation Sector Erase, Resume command (30H) should written. further writes Resume command this point will ignored. Another Erase Suspend command written after chip resumed erasing.
Extended Command
Fast Mode MBM29SL160TD/BD Fast Mode function. This mode dispenses with initial unclock cycles required standard program command sequence writing Fast Mode command into command register. this mode, required cycle programming cycles instead four cycles standard program command. write erase command this mode.) read operation also executed after exiting this mode. exit this mode, necessary write Fast Mode Reset command into command register. (Refer Figure 27.) active current required even during Fast Mode. Fast Programming During Fast Mode, programming executed with cycles operation. Embedded Program Algorithm executed writing program set-up command (A0H) data write cycles (PA/PD). (Refer Figure 27.) Extended Sector Group Protection addition normal sector group protection, MBM29SL160TD/BD Extended Sector Group Protection extended function. This function enable protect sector group forcing RESET write command sequence. Unlike conventional procedure, necessary force control timing control pins. only RESET requires sector group protection this mode. extended sector group protection requires RESET pin. With this condition, operation initiated writing set-up command (60H) into command register. Then, sector group addresses pins (A19, A18, A17, A16, A15, A14, A12) (A6, should sector group protected (recommend other addresses pins), write extended sector group protection command (60H). sector group typically protected verify programming protection circuitry, sector group addresses pins (A19, A18, A17, A16, A15, A14, A12) (A6, should write command (40H). Following command write, logical device output will produce protected sector read operation. output data logical "0", please repeat write extended sector group protection command (60H) again. terminate operation, necessary RESET VIH. (Refer Figures 28.) (Common Flash Memory Interface) (Common Flash Memory Interface) specification outlines device host system software interrogation handshake which allows specific vendor-specified software algorithms used entire families devices. This allows device-independent, JEDEC ID-independent, forward-and backwardcompatible software support specified flash device families. Refer specification detail. operation initiated writing query command (98H) into command register. Following command write, read cycle from specific address retrives device information. Please note that output data upper byte (DQ8 DQ15) word mode bit) read. Refer code table. terminate operation, necessary write read/reset command sequence into register. (See Table 15.)
Time Protect (OTP) Region
feature provides Flash memory region that system access through command sequence. This primarily intended customers wish Electronic Serial Number (ESN) device with protected against modification. Once region protected, further modification that region impossible. This ensures security once product shipped field. region bytes length. MBM29SL160TD occupies address byte mode 1FFEFFH 1FFFFFH (word mode FFF7FH FFFFFH) MBM29SL160BD type occupies address byte mode 00000H 00100H (word mode 00000H 00080H). After system written Enter command sequence, system read region using addresses normally occupied boot sectors. That device sends commands that would normally sent boot sectors region. This mode operation continues until system issues Exit command sequence, until power removed from device. power-up, following hardware reset, device reverts sending commands boot sectors. request Fujitsu program device, please contact Fujitsu representative more information.
Write Operarion Status
Table Hardware Sequence Flags Status Embedded Program Algorithm Embedded Erase Algorithm Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) Mode Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Embedded Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspended (Non-Erase Suspended Sector) Mode Data Toggle Toggle Data Toggle (Note Toggle Toggle Toggle Toggle (Note Toggle Data (Note
Progress
Data Data
Notes: Performing successive read operetions from address will cause toggle. Reading byte address being programmed while erase-suspend program mode will indicate logic bit. However, successive reads from erase-suspend sector will cause toggle. reserve pins future use. Fujitsu internal only
Data Polling
MBM29SL160TD/BD devices feature Data Polling method indicate host that Embedded Algorithms progress completed. During Embedded Program Algorithm attempt read devices will produce complement data last written DQ7. Upon completion Embedded Program Algorithm, attempt read device will produce true data last written DQ7. During Embedded Erase Algorithm, attempt read device will produce output. Upon completion Embedded Erase Algorithm attempt read device will produce output. flowchart Data Polling (DQ7) shown Figure programming, Data Polling valid after rising edge fourth write pulse four write pulse sequence. chip erase sector erase, Data Polling valid after rising edge sixth write pulse write pulse sequence. Data Polling must performed sector address within sectors being erased protected sector. Otherwise, status valid. Once Embedded Algorithm operation close being completed, MBM29SL160TD/BD data pins (DQ7) change asynchronously while output enable (OE) asserted low. This means that devices driving status information instant time then that byte's valid data next instant time. Depending when system samples output, read status valid data. Even device completed Embedded Algorithm operation valid data, data outputs still invalid. valid data will read successive read attempts. Data Polling feature only active during Embedded Programming Algorithm, Embedded Erase Algorithm sector erase time-out. (See Table Figure Data Polling timing specifications diagrams.
Toggle
MBM29SL160TD/BD also feature "Toggle method indicate host system that Embedded Algorithms progress completed. During Embedded Program Erase Algorithm cycle, successive attempts read toggling) data from devices will result toggling between zero. Once Embedded Program Erase Algorithm cycle completed, will stop toggling valid data will read next successive attempts. During programming, Toggle valid after rising edge fourth write pulse four write pulse sequence. chip erase sector erase, Toggle valid after rising edge sixth write pulse write pulse sequence. Toggle active during sector time out. programming, sector being written protected, toggle will toggle about then stop toggling without data having changed. erase, devices will erase selected sectors except ones that protected. selected sectors protected, chip will toggle toggle about then drop back into read mode, having changed none data. Either toggling will cause toggle. addition, Erase Suspend/Resume command will cause toggle. Figure Toggle timing specifications diagrams.
Exceeded Timing Limits
will indicate program erase time exceeded specified limits (internal pulse count). Under these conditions will produce "1". This failure condition which indicates that program erase cycle successfully completed. Data Polling only operating function devices under this condition. circuit will partially power down device under these conditions approximately mA). pins will control output disable functions described Tables failure condition also appear user tries program blank location without erasing. this case devices lock never complete Embedded Algorithm operation. Hence, system never reads valid data never stops toggling. Once devices have exceeded timing limits, will indicate "1." Please note that this device failure condition since devices were incorrectly used. this occurs, reset device with command sequence.
Sector Erase Timer
After completion initial sector erase command sequence sector erase time-out will begin. will remain until time-out complete. Data Polling Toggle valid after initial sector erase command sequence. Data Polling Toggle indicates device been written with valid erase command, used determine sector erase timer window still open. high ("1") internally controlled erase cycle begun; attempts write subsequent commands device will ignored until erase operation completed indicated Data Polling Toggle ("0"), device will accept additional sector erase commands. insure command been accepted, system software should check status prior following each subsequent Sector Erase command. were high second status check, command have been accepted. Table Hardware Sequence Flags.
Toggle
This toggle along with DQ6, used determine whether devices Embedded Erase Algorithm Erase Suspend. Successive reads from erasing sector will cause toggle during Embedded Erase Algorithm. devices erase-suspended-read mode, successive reads from erase-suspended sector will cause toggle. When devices erase-suspended-program mode, successive reads from byte address non-erase suspended sector will indicate logic bit. different from that toggles only when standard program Erase, Erase Suspend Program operation progress. behavior these status bits, along with that DQ7, summarized follows: example, used together determine erase-suspend-read mode progress. (DQ2 toggles while does not.) also Table Figure Furthermore, also used determine which sector being erased. When device erase mode, toggles this read from erasing sector.
Table Toggle Status Mode Program Erase Erase-Suspend Read (Erase-Suspended Sector) Erase-Suspend Program Toggle Toggle Toggle (Note Toggle Toggle (Note
Note: 1.Performing successive read operetions from address will cause toggle. 2.Reading byte address being programmed while erase-suspend program mode will indicate logic bit. However, successive reads from erase-suspend sector will cause toggle.
RY/BY Ready/Busy
MBM29SL160TD/BD provide RY/BY open-drain output indicate host system that Embedded Algorithms either progress been completed. output low, devices busy with either program erase operation. output high, devices ready accept read/ write erase operation. When RY/BY low, devices will accept additional program erase commands. MBM29SL160TD/BD placed Erase Suspend mode, RY/BY output will high. During programming, RY/BY driven after rising edge fourth write pulse. During erase operation, RY/BY driven after rising edge sixth write pulse. RY/BY will indicate busy condition during RESET pulse. Refer Figures detailed timing diagram. RY/BY pulled high standby mode. Since this open-drain output, RY/BY pins tied together parallel with pull-up resistor VCC.
Byte/Word Configuration
BYTE selects byte (8-bit) mode word (16-bit) mode MBM29SL160TD/BD devices. When this driven high, devices operate word (16-bit) mode. data read programmed DQ15. When this driven low, devices operate byte (8-bit) mode. Under this mode, DQ15/A-1 becomes lowest address DQ14 bits tri-stated. However, command cycle always 8-bit operation hence commands written DQ15 bits ignored. Refer Figures timing diagram.
Data Protection
MBM29SL160TD/BD designed offer protection against accidental erasure programming caused spurious system level signals that exist during power transitions. During power devices automatically reset internal state machine Read mode. Also, with control register architecture, alteration memory contents only occurs after successful completion specific multi-bus cycle command sequences. devices also incorporate several features prevent inadvertent write cycles resulting form power-up power-down transitions system noise. Embedded Erase Algorithm interrupted, there possibility that erasing sector(s) cannot used.
Write Pulse "Glitch" Protection
Noise pulses less than (typical) will initiate write cycle.
Logical Inhibit
Writing inhibited holding VIL, VIH, VIH. initiate write cycle must logical zero while logical one.
Power-Up Write Inhibit
Power-up devices with will accept commands rising edge internal state machine automatically reset read mode power-up.
Table Common Flash Memory Interface Code Description Query-unique ASCII string "QRY" Primary Command AMD/FJ standard type Address Primary Extended Table Alternate Command (00h applicable) Address Alternate Extended Table Min. (write/erase) D7-4: volt, D3-0: mvolt Max. (write/erase) D7-4: volt, D3-0: mvolt Min. voltage Max. voltage Typical timeout single byte/word write Typical timeout Min. size buffer write Typical timeout individual block erase Typical timeout full chip erase Max. timeout byte/word write times typical Max. timeout buffer write times typical Max. timeout individual block erase times typical Max. timeout full chip erase times typical Device Size byte Flash Device Interface description Max. number byte multi-byte write Number Erase Block Regions within device Erase Block Region Information
DQ15
0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h 0018h 0027h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h 0015h 0002h 0000h 0000h 0000h 0002h 0007h 0000h 0020h 0000h
Description Erase Block Region Information29SL160
Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock Required Required Erase Suspend Supported Read Only Read Write Sector Protection Supported Number sectors group Sector Temporary Unprotection Supported Supported Sector Protection Algorithm Number Sector Bank Supported Burst Mode Type Supported Page Mode Type Supported (Acceleration) Supply Minimum Supported, D7-4: volt, D3-0: mvolt (Acceleration) Supply Maximum Supported, D7-4: volt, D3-0: mvolt Boot Type MBM29SL160BD MBM29SL160TD
DQ15
001Eh 0000h 0000h 0001h 0050h 0052h 0049h 0031h 0031h 0000h
0002h
0001h
0001h
0004h 0000h 0000h 0000h 0085h
0095h
00XXh
ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with respect Ground pins except RESET (Note Power Supply Voltage (Note RESET (Note WP/ACC Symbol Tstg VIN, VOUT Conditions Rating Min. -0.5 -0.5 -0.5 -0.5 Max. +125 +3.0 +11.0 +10.5 Unit
Notes: Minimum voltage input pins -0.5 During voltage transitions, inputs negative overshoot -2.0 periods Maximum voltage output pins +0.5 During voltage transitions, outputs positive overshoot +2.0 periods Minimum input voltage RESET pins -0.5 During voltage transitions, RESET pins negative overshoot -2.0 periods Maximum input voltage RESET pins +11.0 which positive overshoot 12.0 periods Voltage difference between input voltage supply voltage (VIN VCC) exceed WARNING: Semiconductor devices permanently damaged application stress (voltage, current, temperature, etc.) excess absolute maximum ratings. exceed these ratings.
RECOMMENDED OPERATING CONDITIONS
Parameter Ambient Temperature Power Supply Voltage Symbol Conditions Value Min. +1.8 Max. +2.2 Unit
Operating ranges define those limits between which functionality devices guaranteed. WARNING: recommended operating conditions required order ensure normal operation semiconductor device. device's electrical characteristics warranted when device operated within these ranges. Always semiconductor devices within their recommended operating condition ranges. Operation outside these ranges adversely affect reliability could result device failure. warranty made with respect uses, operating conditions, combinations represented data sheet. Users considering application outside listed conditions advised contact their FUJITSU representatives beforehand.
MAXIMUM OVERSHOOT
-0.5 -2.0
Figure
Maximum Negative Overshoot Waveform
+2.0 +0.5
Figure
Maximum Positive Overshoot Waveform
+12.0 +11.0 +0.5
This waveform applied RESET.
Figure
Maximum Positive Overshoot Waveform
CHARACTERISTICS
Parameter Symbol ILIT ILIA Parameter Description Input Leakage Current Output Leakage Current RESET Inputs Leakage Current WP/ACC Inputs Leakage Current Test Conditions VCC, Max. VOUT VCC, Max. Max. RESET Max. WP/ACC Max. VIL, VIH, f=10 ICC1 Active Current (Note VIL, VIH, ICC2 ICC3 ICC4 Active Current (Note Current (Standby) Current (Standby, Reset) VIL, Max., RESET Max., RESET Byte Word Byte Word Min. -1.0 -1.0 Max. +1.0 +1.0 Unit
ICC5 VACC
Max., Current RESET (Automatic Sleep Mode) (Note Input Level Input High Level Voltage WP/ACC Sector Protection/Unprotection Program Accelaration Voltage Autoselect Sector Protection (A9, RESET) (Note Output Voltage Level Output High Voltage Level
-0.5
VCC+0.3
Notes:
Min. -100
VCC-0.1
current listed includes both operating current frequency dependent component. active while Embedded Algorithm (program erase) progress. Automatic sleep mode enables power mode when address remain stable This timing Sector Protection operation. Applicable only applying.
CHARACTERISTICS
Read Only Operations Characteristics Parameter Symbols JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Standard tACC tREADY tELFL tELFH Read Cycle Time Address Output Delay Chip Enable Output Delay Output Enable Output Delay Chip Enable Output High-Z Output Enable Output High-Z Output Hold Time From Addresses, Whichever Occurs First RESET Read Mode BYTE Switching High Min. (Note) (Note)
Description
Test Setup
Unit
Max. Max. Max. Max. Max. Min. Max. Max.
Notes: Test Conditions: Output Load:1 gate (MBM29SL160TD/BD-10) gate (MBM29SL160TD/BD-12) Input rise fall times: Input pulse levels: Timing measurement reference level Input: Output:
IN3064 Equivalent Device Under Test Diodes IN3064 Equivalent
Notes: including capacitance (MBM29SL160TD/BD-10) including capacitance (MBM29SL160TD/BD-12)
Figure
Test Conditions
Write/Erase/Program Operations Parameter Symbols Description JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 Standard tOES tOEH tGHWL tGHEL tWPH tCPH tWHWH1 tWHWH2 tVCS tVIDR tVACCR tVLHT tWPP tOESP tCSP Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle Data Polling Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Typ. Typ. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. 10.6 10.6 Unit
Read Recover Time Before Write Read Recover Time Before Write Setup Time Setup Time Hold Time Hold Time Write Pulse Width Pulse Width Write Pulse Width High Pulse Width High Byte Programming Operation Sector Erase Operation (Note Setup Time Rise Time (Note Rise Time VACC Voltage Transition Time (Note Write Pulse Width (Note Setup Time Active (Note Setup Time Active (Note Recover Time From RY/BY RESET Pulse Width RESET Hold Time Before Read
(Continued)
(Continued)
Parameter Symbols Description JEDEC Standard tFLQZ tFHQV tBUSY tEOE BYTE Switching Output High-Z BYTE Switching High Output Active Program/Erase Valid RY/BY Delay
Delay Time from Embedded Output Enable Power On/Off Timing
Max. Min. Max. Max. Min.
Unit
Notes: This does include preprogramming time. This timing Sector Group Protection operation.
SWITCHING WAVEFORMS
Switching Waveforms
WAVEFORM
INPUTS Must Steady Change from Change from Change Permitted Does Apply
OUTPUTS Will Steady Will Changing from Will Changing from Changing State Unknown Center Line HighImpedance "Off" State
Addresses
Addresses Stable
Outputs
High-Z
Output Valid
High-Z
Figure
Waveforms Read Operations
Addresses
Addresses Stable
RESET
Outputs
High-Z
Output Valid
Figure
Waveforms Hardware Reset/Read Operations
Cycle Addresses
555H
Data Polling
GHWL WHWH1
Data
Notes:
address memory location programmed. data programmed byte address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence. These waveforms mode. (The addresses differ from mode.)
Figure
Waveforms Alternate Controlled Program Operations
Cycle
Data Polling
Addresses
555H
GHEL WHWH1
Data
Notes:
address memory location programmed. data programmed byte address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence. These waveforms mode. (The addresses differ from mode.)
Figure
Waveforms Alternate Controlled Program Operations
Addresses
555H
2AAH
555H
555H
2AAH
GHWL
10H/
Data
Notes: sector address Sector Erase. Addresses 555H (Word), AAAH (Byte) Chip Erase. These waveforms mode. (The addresses differ from mode.)
Figure
Waveforms Chip/Sector Erase Operations
Data Valid Data High-Z
WHWH1
Data
Output Flag
Valid Data
High-Z
Valid Data (The device completed Embedded operation). Figure Waveforms Data Polling during Embedded Algorithm Operations
tOEH
tOES
Data
Toggle
Toggle
Stop Toggling
Valid
stops toggling (The device completed Embedded operation). Figure Waveforms Toggle during Embedded Algorithm Operations
rising edge last signal
Entire programming erase operations
RY/BY
BUSY
Figure
RY/BY Timing Diagram during Program/Erase Operations
RESET
RY/BY
tREADY
Figure
RESET/RY/BY Timing Diagram
BYTE
Data Output (DQ0 DQ7) tELFH tFHQV DQ15 Data Output (DQ0 DQ14)
DQ14
DQ15/A-1
Figure
Timing Diagram Word Mode Configuration
BYTE
tELFL
DQ14
Data Output (DQ0 DQ14)
Data Output (DQ0 DQ7)
DQ15/A-1
DQ15 tFLQZ
Figure
Timing Diagram Byte Mode Configuration
falling edge last write signal
BYTE
tSET (tAS)
Input Valid
tHOLD (tAH)
Figure
BYTE Timing Diagram Write Operations
A18, A17, A15, A13,
VLHT
VLHT VLHT VLHT
OESP
Data
SGAX:Sector Group Address initial sector SGAY:Sector Group Address next sector Note: byte mode. Figure Waveforms Sector Group Protection Timing Diagram
tVCS
tVIDR
RESET
tVLHT RY/BY
Program Erase Command Sequence
tVLHT
Figure
Temporary Sector Group Unprotection Timing Diagram
Enter Embedded Erasing
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
Toggle with
Note: read from erase-suspended sector.
Figure
tVCS
RESET tVIDR
tVLHT
SGAX
SGAX
SGAY
TIME-OUT
Data
SGAX Sector Group Address protected SGAY Next Sector Group Address protected TIME-OUT Time-Out window (min) Figure Extended Sector Group Protection Timing Diagram
RESET
Addresses
Input Valid
Data
Output Valid
Figure
Power ON/OFF Timing Diagram
tVCS VACC WP/ACC
tVACCR tVLHT
tVLHT RY/BY Accelerated Program tVLHT Program Command Sequence
Figure
Accelerated Program Operation Timing Diagram
EMBEDDED ALGORITHMS
Start
Write Program Command Sequence (See below)
Data Polling Device
Increment Address
Last Address
Programming Completed
Program Command Sequence* (Address/Command):
555H/AAH
2AAH/55H
555H/A0H
Program Address/Program Data
sequence applied mode. addresses differ from mode.
Figure
Embedded ProgramAlgorithm
EMBEDDED ALGORITHMS
Start
Write Erase Command Sequence (See below) Data Polling Toggle Successfully Completed
Erasure Completed Individual Sector/Multiple Sector* Erase Command Sequence (Address/Command): 555H/AAH
Chip Erase Command Sequence* (Address/Command): 555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/80H
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/10H
Sector Address/30H
Sector Address/30H
Additional sector erase commands optional.
Sector Address/30H
sequence applied mode. addresses differ from mode.
Figure
Embedded EraseAlgorithm
Start
Read Addr.
Data? Read Addr.
Byte address programming sector addresses within sector being erased during sector erase multiple sector erases operation sector addresses within sector being protected during chip erase
Data? Fail
Pass
Note: rechecked even because change simultaneously with DQ5.
Figure
Data Polling Algorithm
Start
Read Addr.
Toggle Read Addr.
Toggle Fail
Pass
Note: rechecked even because stop toggling same time changing
Figure
Toggle Algorithm
Start
Setup Sector Addr. (A18, A17, A16, A15, A14, A13, A12)
PLSCNT
RESET Activate Pulse
Increment PLSCNT
Time
should remain
Read from Sector (Addr. IL)* PLSCNT Remove from Write Reset Command Data 01H? Protect Another Sector? Device Failed Remove from Write Reset Command
Sector Protection Completed
byte mode.
Figure
Sector Protection Algorithm
Start
RESET (Note
Perform Erase Program Operations
RESET
Temporary Sector Unprotection Completed (Note
Notes: protected sectors unprotected. previously protected sectors protected once again.
Figure
Temporary Sector Unprotection Algorithm
FAST MODE ALGORITHM
Start
555H/AAH
2AAH/55H
Fast Mode
555H/20H
XXXH/A0H
Program Address/Program Data
Data Polling Device
Verify Byte?
Fast Program
Increment Address
Last Address Programming Completed
XXXH/90H Reset Fast Mode XXXH/F0H
sequence applied mode. addresses differ from mode. Figure Embedded ProgramAlgorithm Fast Mode
FAST MODE ALGORITHM
Start
RESET
Wait
Device Operating Temporary Sector Unprotection Mode
Extended Sector Protection Entry? Setup Sector Protection Write XXXH/60H
PLSCNT
Sector Protection Write SPA/60H VIL, VIH, VIL)
Increment PLSCNT
Time
Verify Sector Protection Write SPA/40H VIL, VIH, VIL)
Setup Next Sector Address
Read from Sector Address VIL, VIH, VIL) PLSCNT Remove from RESET Write Reset Command Data 01H? Protection Other Sector Remove from RESET Write Reset Command
Device Failed
Sector Protection Completed
Figure
Extended Sector Protection Algorithm
ERASE PROGRAMMING PERFORMANCE
Limits Parameter Min. Sector Erase Time Word Programming Time Byte Programming Time Chip Programming Time Program/Erase Cycle Note: 100,000 Typ. 14.6 10.6 15.4 Max. cycles Excludes programming time prior erasure Excludes system-level overhead Excludes system-level overhead Unit Comments
TSOP(I) CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance Test Setup VOUT Typ. Max. Unit
Note: Test conditions 25°C,
FBGA CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance Test Setup VOUT Typ. Max. Unit
Note: Test conditions 25°C,
ORDERING INFORMATION
Standard Products
Fujitsu standard products available several packages. order number formed combination
MBM29SL160
PFTN
PACKAGE TYPE PFTN 48-Pin Thin Small Outline Package (TSOP) Standard Pinout PFTR 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout 48-Ball Fine pitch Ball Grid Array Package (FBGA) SPEED OPTION Product Selector Guide DEVICE REVISION
BOOT CODE SECTOR ARCHITECTURE sector Bottom sector
DEVICE NUMBER/DESCRIPTION MBM29SL160 16Mega-bit 8-Bit 16-Bit) CMOS Flash Memory V-only Read, Program, Erase
PACKAGE DIMENSIONS
48-pin plastic TSOP(I) (FPT-48P-M19)
LEAD
Resin Protrusin. (Each Side: 0.15 (.006)Max)
INDEX
Details part 0.15(.006)
0.15(.006)
0.35(.014) 0.25(.010)
20.00±0.20 (.787±.008) 18.40±0.20 (.724±.008)
12.00±0.20
(.472±.008) 11.50REF (.460) 1.10 -0.05
+0.10 +.004
.043 -.002 (Mounting height
0.10(.004)
0.50(.0197) 0.15±0.05 (.006±.002) 0.20±0.10 (.008±.004)
0.05(0.02)MIN (STAND OFF) 0.10(.004)
19.00±0.20 (.748±.008)
0.50±0.10 (.020±.004)
1996 FUJITSU LIMITED F48029S-2C-2
Dimensions (inches)
(Continued)
(Continued)
48-pin plastic TSOP(I) (FPT-48P-M20)
LEAD
Resin Protrusin. (Each Side: 0.15 (.006)Max)
INDEX
Details part 0.15(.006)
0.15(.006)
0.35(.014) 0.25(.010)
19.00±0.20 (.748±.008)
0.50±0.10 (.020±.004) 0.15±0.10 (.006±.002) 0.20±0.10 (.008±.004) 0.10(.004)
0.10(.004)
0.50(.0197)
0.05(0.02)MIN (STAND OFF)
1.10 -0.05
+0.10 +.004
18.40±0.20
(.724±.008) 20.00±0.20 (.787±.008)
11.50(.460)REF
.043 -.002 (Mounting height)
12.00±0.20(.472±.008)
1996 FUJITSU LIMITED F48030S-2C-2
Dimensions (inches)
(Continued)
(Continued)
48-pin plastic FBGA (BGA-48P-M13)
Note: actual shape corners differ from dimension.
9.00±0.20(.354±.008)
1.05 -0.10 .041 -.004 (Mounting height) 0.38±0.10(.015±.004) (Stand off)
+0.15
+.006
5.60(.221) 0.80(.031)TYP
8.00±0.20 (.315±.008) INDEX 4.00(.157)
C0.25(.010)
(48-.018±.004)
0.10(.004)
1998 FUJITSU LIMITED B480013S-1C-1
Dimensions (inches)
FUJITSU LIMITED
further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
Rights Reserved. contents this document subject change without notice. Customers advised consult with FUJITSU sales representatives before ordering. information circuit diagrams this document presented examples semiconductor device applications, intended incorporated devices actual use. Also, FUJITSU unable assume responsibility infringement patent rights other rights third parties arising from this information circuit diagrams. FUJITSU semiconductor devices intended standard applications (computers, office automation other office equipment, industrial, communications, measurement equipment, personal household devices, etc.). CAUTION: Customers considering products special applications where failure abnormal operation directly affect human lives cause physical injury property damage, where extremely high levels reliability demanded (such aerospace systems, atomic energy controls, floor repeaters, vehicle operating controls, medical devices life support, etc.) requested consult with FUJITSU sales representatives before such use. company will responsible damages arising from such without prior approval. semiconductor devices have inherent chance failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. products described this document represent goods technologies subject certain restrictions export under Foreign Exchange Foreign Trade Japan, prior authorization Japanese government will required export those products from Japan.
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North South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street Jose, 95134-1804, Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. Fri.: (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
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F9910 FUJITSU LIMITED Printed Japan

FLASH MEMORY 8/1M FEATURES Single read, program, erase

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