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ORCA® Series Microprocessor Interface
ORCA Series Microprocessor Interface
With increased demand larger faster FPGAs, goals FPGA designers utilize much programmable logic possible. reach this goal, system-level features have been added Series base architecture. These system-level features reduce glue-logic requirements and, hence, conserve programmable logic. many system-level features, multiuse microprocessor interface (MPI) used configuration, readback, general-purpose interface FPGA, well other basic device control status functions. synchronous, 8-bit interface, programmable operate with both PowerPC MPC800 series microprocessor Intel i960 core processors (see Figure will shown later, this interface also very powerful when used interface many other processors well, such device, with minimal amounts glue logic.
PowerPC registered trademark International Business Machines Corporation. Intel i960 registered trademarks Intel Corporation.
D[7:0]IN D[7:0]OUT FPGA ROUTING
ORCA SERIES
DONE RD_DATA INIT D7IN D7OUT D6IN D6OUT D5IN D5OUT D4IN D4OUT D3IN D3OUT D2IN D2OUT D1IN D1OUT D0IN D0OUT
STATUS REGISTER
SCRATCHPAD REGISTER READBACK DATA REGISTER
POWERPC ONLY
CCLK MPI_IRQ MPI_ACK MPI_CLK MPI_STRB MPI_ALE MPI_RW MPI_B1
READBACK ADDR REGISTER RESET CONTROL REGISTERS RD_CFG PRGM PART REGISTERS
BLOCK
DECODE/CONTROL
USER_START USER_END WR_CTRL A[3:0]
FPGA ROUTING
RDYRCV RD/WR CLKOUT
i960 LOGIC
POWERPC LOGIC
KEY: DEVICE BUFFER
5-8511(F)
Figure Block Diagram
ORCA Series Microprocessor Interface
PowerPC System
Figure ORCA FPGA memory-mapped peripheral PowerPC processor. address lines used decode memory map. Other forms selection possible using FPGA chip selects (CS0 CS1) different way. used configure FPGA, then decoding logic implemented internally FPGA. decode implemented FPGA, then decode logic routed output pins connected externally select lines. (Note this possible before configuration, this only available used configure FPGA.) Figure shows basic connection PowerPC FPGA. descriptions shown Table both read write transactions, address, chip select, read/write (read high, write low) signals driven FPGA pins PowerPC. PowerPC then asserts transfer start signal (TS) low. Data available during write rising clock edge after clock cycle during which low. transfer acknowledged PowerPC from assertion signal. PowerPC interface does support burst transfers, burst inhibit signal (BI) also asserted during transfer acknowledge. same process applies read from except that read data expected FPGA data pins PowerPC rising edge clock when low. only drives clock cycle. Table PowerPC Configuration
PowerPC Signal
D[0:7] A[27:31] CLKOUT RD/WR IRQ[7:0}
ORCA Name
D[7:0] A[4:0] RD/MPI_STRB A7/MPI_CLK A8/MPI_RW A9/MPI_ACK A10/MPI_BI A11/MPI_IRQ
8-bit data bus.
Function 5-bit address bus. Transfer start signal. Active-low select. Active-high select.
PowerPC interface clock. Read (high)/Write (low) signal. Active-low transfer acknowledge signal. Active-low burst transfer inhibit signal. Active-low interrupt request signal.
Interrupt requests sent PowerPC asynchronously read/write process. Interrupt requests generated FPGA user logic. When interrupt requested, will assert request PowerPC direct interrupt signal and/or status register. interrupt will continue asserted until user logic FPGA deasserts signal.
DAISYCHAINED DEVICES
DOUT CCLK D[7:0] A[27:31] CLKOUT RD/WR IRQx D[7:0] A[4:0] MPI_CLK MPI_RW MPI_ACK MPI_BI MPI_IRQ MPI_STRB
POWERPC
ORCA SERIES FPGA
DONE INIT
5-8507(F)
Figure PowerPC/MPI Configuration Schematic
Lucent Technologies Inc.
ORCA Series Microprocessor Interface
i960 System
Figure shows schematic connection Intel i960 processor. descriptions shown Table schematic shows FPGA only system peripheral with fixed-chip selects. mentioned PowerPC System section, i960 system also memory FPGA. basic flow transaction with i960 follows. both read write transactions, address latch enable (ALE) driven i960 FPGA falling edge clock. address, byte enables, chip selects, read/write (read low, write high) signals normally driven FPGA pins i960 next rising edge clock. this same rising clock edge, i960 asserts address/data strobe (ADS) low. Data available during write rising clock edge following clock cycle. transfer acknowledged i960 driving assertion ready/recover (RDYRCV) signal. same process applies read from except that read data expected FPGA data pins i960 rising edge clock when RDYRCV low. only drives RDYRCV clock cycle. Interrupt requests handled with i960 same described PowerPC System (see PowerPC System section). Table i960/MPI Configuration
i960 Signal
AD[7:0] System Clock RDYRCV XINT[7:0]
ORCA Name
D[7:0] RDY/RCLK/MPI_ALE RD/MPI_STRB A7/MPI_CLK A8/MPI_RW A9/MPI_ACK A11/MPI_IRQ A0/MPI_BE0 A1/MPI_BE1
Fuction Multiplexed 5-bit address/8-bit data bus. address appears D[4:0]. Address latch enable used capture address from AD[4:0] falling edge clock. Address/data strobe indicate start transaction. Active-low select. Active-high select.
i960 system clock. This clock sourced system i960. Write (high)/read (low) signal. Active-low ready/recover signal indicating acknowledgement transaction. Active-low interrupt request signal.
Byte-enable used address i960 8-bit mode. Byte-enable used address i960 8-bit mode.
i960 SYSTEM CLOCK
AD[7:0] CLKIN RDYRCV XINTx D[7:0] MPI_CLK MPI_RW MPI_ACK MPI_IRQ MPI_ALE MPI_STRB MPI_BE0 MPI_BE1 DAISYCHAINED DEVICES
DOUT CCLK
i960
ORCA SERIES FPGA
DONE INIT
5-8508(F)
Figure i960/MPI Configuration Schematic Lucent Technologies Inc.
ORCA Series Microprocessor Interface
Download
M[2:0] pins determine download method FPGA. order download through MPI, M[2:0] appropriate microprocessor. Table correct configuration mode. Table Configuration Modes CCLK Output Output Configuration Mode Data Parallel Parallel
DONE INIT POWER INITIALIZE WITH VALID M[3:0]
WRITE CONFIGURATION CONTROL REGISTER BITS
READ STATUS REGISTER
Motorola* PowerPC Intel i960
READ STATUS REGISTER
DONE
handles configuration control handshaking with host processor. single FPGA configuration, host processor sets configuration control register PRGM zero then back one. Then, after reading that INIT signal high status register, transfers data bits time FPGA's D[7:0] input pins. configuring multiple FPGAs through daisy-chain operation, MP_DAISY must configuration control register host processor. Because latency involved daisy-chain configuration, MP_HOLD_BUS zero rather than daisy-chain operation. This allows acknowledge data transfer before configuration information been serialized transferred FPGA daisy chain. early acknowledgment frees host processor perform other system tasks. Configuring with MP_HOLD_BUS zero requires that host microprocessor poll RDY/BUSY status register and/or interrupt capability confirm readiness more configuration data. There options using host interrupt request configuration mode. configuration control register offers control bits enable interrupt either stream error notify host processor when FPGA ready more configuration data. status register used conjunction with, place interrupt request options. status register contains 2-bit field indicate stream error status. flow chart configuration process shown Figure status configuration registers described more detail Control Status Registers section.
ERROR
STREAM ERROR
RDY_
WRITE DATA CONFIGURATION DATA
5-8510(F)
Figure Configuration Through Microprocessor Interface
Motorola registered trademark Motorola, Inc.
Lucent Technologies Inc.
ORCA Series Microprocessor Interface
Readback
Configuration readback performed when user mode. user mode, either instantiate library macro design code, schematic capture, have host processor MP_USER prior download process. MP_USER bit, host processor, ideally should while configuring control registers download. addition putting user mode, designer must instantiate readback controller (READBK library element) design code schematics capture. Lastly, designer must enable readback download stream through generation program ORCA Foundry control center. Under advanced options, designer should activate Allow Readback also type readback under Capture Readback. system ready perform readback. host processor writes 14-bit readback start address readback address registers sets RD_CFG control register. Readback data returned bits time readback data register valid when DATA_RDY status register flow chart readback operation shown Figure RD_DATA used dedicated FPGA readback invalid during readback.
ENABLE MICROPROCESSOR INTERFACE USER MODE
READBACK ADDRESS WRITE RD_CFG CONTROL REGISTER
READ STATUS REGISTER
DATA_RDY
READ DATA REGISTER
ERROR
DATA 0xFF
READ DATA REGISTER
ERROR
DATA 0xFF
READ DATA REGISTER
ERROR
START FRAME FOUND READ UNTIL FRAME INCREMENT ADDRESS COUNTER SOFTWARE
STOP
WRITE RD_CFG CONTROL REGISTER
FINISHED READBACK
5-8509(F)
Figure Readback Through Microprocessor Interface
Lucent Technologies Inc.
ORCA Series Microprocessor Interface
Finally, device registers four registers holding byte each. These registers provide device code. This same boundary-scan code. Please refer Setup Control subsection section FPGA data book more details registers. Table Setup Control Registers Address 0B-0F 10-1F Register Control register Control register Scratchpad register. Status register. Configuration/readback data register. Readback address register (bits [7:0]). Readback address register (bits [15:8]). Device register (bits [7:0]). Device register (bits [15:8]). Device register (bits [23:16]). Device register (bits [31:24]). Reserved. User-definable address space.
Control Status Registers
series addressable registers that provide control status, configuration readback data transfer, FPGA device identification, dedicated user scratchpad register. registers bits wide most significant bit, while least significant bit. Table illustrates address these registers functionality. control registers read/write registers. host processor writes control byte configure MPI. readable host processor verify status control bits previously written. scratchpad register read/write register with defined operation. used userdefined function. status register read-only register, providing various information host processor. Data ready, pending, error flags, INIT, DONE status information provided host processor. configuration data register writable register configuration mode readable readback mode. During configuration, data register where host processor writes configuration data bytes sequentially. Conversely, readback mode, provides readback data configuration data register. readback address registers writable registers used accept address bytes configuration data location read back. Readback address register accepts least significant address byte (bits [7:0]), while readback address register accepts most significant address byte (bits [15:8]).
Lucent Technologies Inc.
ORCA Series Microprocessor Interface
Interface
user-programmable FPGA logic interfaces 4-bit address, read/write control signal, interrupt request signal, user handshaking signals. Figure ORCA Foundry Library macro both PowerPC i960. These library macros represent hardware FPGA. order conventional situation, 3state bidirectional buffers needed included. ORCA Foundry SCUBA® macrocell generation tool automatically inserts 3-state bidirectional buffers along with macro. This recommend flow. shown Figures module created SCUBA attached host processor. signals left side module communicate with off-chip host processor (i960 PowerPC) shown Table while signals right side communicate with user-logic portion FPGA shown Table Table explains user-logic signals FPGA side. These signals common both PowerPC i960. Table PowerPC Signal Definition-External Side Signal CS0N RDWRN A[31:27] D[7:0] IRQN Direction into Input Input Input Input Input Input Input/Output Output Output Output Function Connected host processor synchronize communication. Active-low chip enable. Active-high chip enable. Read/Write signal specifies write, high specifies read. Active-low transfer start signal. 5-bit address bus. 8-bit bidirectional data coming from host processor generated open-drain, active-low transfer acknowledge. generated burst inhibits signal, which informs host that incapable sending more data. generated open-drain, active-low interrupt request.
Table i960 Signal Definition-External Side Signal CS0N WRRDN ADSn BE0n BE1n ACKn AD[7:0] IRQN Direction into Input Input Input Input Input Input Input Input Input/Output Input/Output Output Function Connected i960 system order synchronous communication between host processor. Active-low chip enable. Active-high chip enable. Read/Write signal. High specifies write, specifies read. Address latch enable used capture address from AD[4:0] falling edge clock. Address/data strobe used indicate start transaction. Byte-enable used address i960 8-bit mode. Byte-enable used address i960 8-bit mode. Active-low ready/recover signal indicating acknowledgment transaction. buf_rdrcvn. 8-bit bidirectional address data bus. generated open-drain, active-low interrupt request.
Lucent Technologies Inc.
ORCA Series Microprocessor Interface
Interface (continued)
Table User-logic Signal Definition-Internal FPGA Side Signal UA[3:0] URDWRN Direction Output Output Function User logic address. Addresses unique user registers control signals. User logic read/write control signal. High indicates read from user logic host processor, indicates write user-logic host processor. Active-high user start signal. Indicates start transaction between host processor user logic. Active-high user signal. Indicates that user-logic finished with current transaction. Active-low interrupt. Sends interrupt request from user-logic host processor. User data out. Eight data bits going user-logic*. User data Eight data bits from user-logic host processor*. Clock generated external FPGA used synchronize user-logic FPGA. signal produced set/reset user-logic registers.
USTART UEND UIRQn UDOUT[7:0] UDIN[7:0] MPI_CLK MPI_GSR
Output Input Input Output Input Input Input
figures SCUBA generated code indicate that user data sent through MPI. This modeling simulation purposes, true hardware. hardware, user data actually routed externally block. model emulates hardware functionality correctly.
INPUTS CS0N RDWRN A[27:31] DIN[7:0] UEND UIRQN UDOUT[7:0]
INPUTS ASDN CS0N WRRDN ADIN[7:0] BE1N BE0N RRCVNIN UEND UIRQN UDOUT[7:0]
OUTPUTS DOUT[7:0] MPGSR DDRVCTL IRQN TAN_TS SIDE URDWRN USTART UA[3:0] UDIN[7:0] FPGA SIDE
OUTPUTS DOUT[7:0] MPGSR DDRVCTL IRQN RDYRCVN RDRCV_TS SIDE URDWRN USTART UA[3:0] UDIN[7:0] FPGA SIDE
POWERPC INTERFACE
i960 INTERFACE
5-8518(F)
Figure Interface
Lucent Technologies Inc.
ORCA Series Microprocessor Interface
Interface (continued)
MODULE CREATED SCUBA D[7:0] DATA[7:0] DDRVCTL DOUT[7:0] DIN[7:0] DECODE (OPTIONAL) CS0N TAN_TS ACKN STRBN RDWR IRQN RDWRN IRQN UA[3:0] UDOUT[7:0] UDIN[7:0]
ADDR
POWERPC
MPIPPC URDWRN USTART UEND UIRQN MPIGSR
POWERPC SYSTEM CLOCK
FPGA
5-8512(F)
Figure PowerPC Interface
Lucent Technologies Inc.
USER LOGIC
ORCA Series Microprocessor Interface
Interface (continued)
MODULE CREATED SCUBA ADDR_ DATA[7:0] AD[7:0] DDRVCTL DOUT[7:0] AIN[7:0] UA[3:0] DECODE (OPTIONAL) BE0N BE1N CS0N BE0N BE1N ACKn RDYRCVN ADSN RDWR XINTx RDRCV_TS RDYRCVN RRCVNIN ADSN WRRDN IRQN MPI960 URDWRN USTART UEND UIRQN MPIGSR UDOUT[7:0] UDIN[7:0]
i960
i960 SYSTEM CLOCK
FPGA
5-8513(F)
Figure i960 Interface
Basic User-Logic Communication Transactions
After host processor initiates transaction discussed PowerPC System i960 System sections, outputs 4-bit user address (UA[3:0]) read/write control signal (URDWR, which read-high, writelow regardless host processor). then asserts user start signal, USTART. During write from host processor, user logic accept data written host processor from D[7:0] pins once USTART signal asserted. user logic ends transaction asserting active-high user (UEND) signal MPI. UEND signal never returned after USTART, microprocessor will typically hang. Thus guaranteed return UEND potential issue. avoid this issue, watchdog timer circuit have added FPGA logic will insert wait-states host processor cycles, holding host processor until user-logic completes task returns UEND signal, upon which generates acknowledge signal. host processor reading from FPGA, user logic must have read data available D[7:0] pins FPGA when UEND signal asserted. user logic fast user address being decoded control signal, transaction time minimized routing USTART signal directly UEND input MPI. user-logic also assert active-low interrupt request (UIRQ) MPI, which, turn, asserts interrupt host processor. Assertion interrupt request asynchronous host processor clock read write transaction occurring MPI. user-logic responsible providing required interrupt vectors host processor, user-logic must deassert interrupt request once serviced. interrupt request deasserted user logic, will continue asserted host processor. PowerPC System section this application note more information. Lucent Technologies Inc.
USER LOGIC
ORCA Series Microprocessor Interface
seen Figure host processor's sixth address (A5) used determine address internal external. This sixth should connected address bits. address host processor that should routed externally block created SCUBA. Setting address bits this fashion organizes location such that lower locations internal upper locations external. Figure shows logic mapping. When address located internally; likewise, when address located externally MPI. Furthermore, when bottom half locations, when half address locations. Notice that locations simply mapped same registers address This fact that address extension only external thus creates 16-word repeated internal address mapping. this address space needed, further decodes chip select pins required disable this device repeated address blocks. Extending number data bits fairly easy. Figure data bits D[15:8] from host processor brought into FPGA through bidirectional buffers exactly same other UDOUT UDIN buses. DDRVCTL signal used control bidirectional buffers. order this signal will need slightly modify SCUBA module adding DDRVCTL port list connecting DDRVCTL signal port port map.
Extending Address Data
Although includes internal address register locations programmable user-logic locations (external MPI, FPGA), design need more non-MPI specific locations. same time, host processor larger than data bits, therefore needing larger data bus. With modifications, designer will able create larger address data buses. default, uses address lines A[4:0] decode address locations. Signal A[4] determines which FPGA address locations will accessed, internal external block. A[4] internal registers used, A[4] external locations used. remaining address signals A[3:0], determine which locations used, internal external. passes A[3:0] through FPGA signals UA[3:0]. designer should then take UA[3:0] decode them resolve appropriate user location. USTART signal determines when data ready, described previously. order extend number external address locations, designer must additional address lines. Figure demonstrates this done. order increase number MPI-external address locations must take additional address from host processor bring into FPGA through normal buffer. additional address should then used decode address locations.
Lucent Technologies Inc.
ORCA Series Microprocessor Interface
Extending Address Data (continued)
WIDE MODULE CREATED SCUBA D[7:0] DDRVCTL DOUT[7:0] DIN[7:0] UA[3:0] DECODE DEEP UDOUT[7:0] UDIN[7:0] MPIPPC DDRVCTL
DATA[7:0]
POWERPC
FPGA
5-8514(F)
Figure Extending Number External Address Locations
HOST PROCESSOR ADDRESS BITS EXTERNAL EXTERNAL INTERNAL MAPPED ADDRESS 0-15 INTERNAL
5-8517(F)
ADDRESS LOCATION
Figure Address Location Mapping Lucent Technologies Inc.
ORCA Series Microprocessor Interface
Extending Address Data (continued)
Note that when increasing number data bits, internal data bits registers still remain bits, only external data width increased.
DDRVCTL UDIN[15:8] UDOUT[15:8] D[15:8] D[7:0] DATA[15:0] MODULE CREATED SCUBA DDRVCTL DOUT[7:0] DIN[7:0] UA[3:0] DECODE UDOUT[7:0] ADDR A[4:0] MPIPPC UDIN[7:0] DDRVCTL
POWERPC
FPGA
5-8515(F)
Figure Extending Number External Data Bits
Lucent Technologies Inc.
ORCA Series Microprocessor Interface
Other Microprocessors
PowerPC i960 only host processors that hooked MPI. example shown Figure shows FPGA hooked Lucent Technologies digital signal processor. Although this setup appears seamless, many design considerations need taken.
MODULE CREATED SCUBA DDRVCTL DOUT UA[3:0] ADDR UDOUT[7:0] UDIN[7:0]
READY
CSON TAN_TS RDWRN
MPIPPC URDWRN USTART UEND UIRQN MPIGSR
CLKO
FPGA
5-8516(F)
Figure Interface
Lucent Technologies Inc.
USER LOGIC
DECODE (OPTIONAL)
ORCA Series Microprocessor Interface
Conclusion
microprocessor Interface feature reduces glue-logic requirement conserves programmable logic. prevously discussed microprocessor interface (MPI) used configuration, readback, general-purpose interface FPGA, well other basic device control status functions. With small modifications, 8-bit, address locations (internal external), easily increased accommodate designer's needs. more detailed information, such timing information, FPGA data book Microprocessor Interface Design Notes website: http://www.lucent.com/orca
Lucent Technologies Inc.
additional information, contact your Microelectronics Group Account Manager following: http://www.lucent.com/micro, FPGA information, http://www.lucent.com/orca INTERNET: docmaster@micro.lucent.com E-MAIL: AMERICA: Microelectronics Group, Lucent Technologies Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18103 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 8833, (65) 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Fong Universe Building, 1800 Zhong Shan Road, Shanghai 200233 China Tel. (86) 6440 0468, ext. 316, (86) 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 5421 1600, (81) 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 368, (44) 1189 Technical Inquiries: GERMANY: (49) 95086 (Munich), UNITED KINGDOM: (44) 1344 (Ascot), FRANCE: (33) (Paris), SWEDEN: (46) (Stockholm), FINLAND: (358) 4354 2800 (Helsinki), ITALY: (39) 6608131 (Milan), SPAIN: (34) 1441 (Madrid)
Lucent Technologies Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. rights under patent accompany sale such product(s) information. ORCA SCUBA registered trademarks Lucent Technologies Inc. Foundry trademark Xilinx Inc.
Copyright 1999 Lucent Technologies Inc. Rights Reserved
November 1999 AP99-050FPGA

ORCA Series Microprocessor Interface With increased demand larger

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