This application note describes design PCIbased Fibre Channel Adapter

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

This application note describes design PCIbased Fibre Channel Adapter

Datasheet Thumbnail

Top Searches for this datasheet

PCI-Based Gbit/s Fibre Channel Adapter Using ORCA Series FPGAs
This application note describes design PCIbased Fibre Channel Adapter that includes ORCA field-programmable gate arrays. This adapter connects fibre-channel fabric operating rate 1.0625 Gbits/s bus. maximum sustained throughput Mbytes/s client/server adapters Mbytes/s communications adapters. adapter (Figure contains following elements:
This allows design networks whose bandwidth scales linearly with number attached nodes. example, simple 16-node fabric switch provides aggregate bandwidth approximately Gbits/s (i.e., 1.0625 Gbits/s). Fibre channel restricted 1.0625 Gbits/s. ANSI standard that allows wide range data transfer rates ranging from Mbits/s Gbits/s. Currently, shipping products clustered frequencies; Mbits/s (commonly called speed) 1.0625 Gbits/s. these frequencies, off-the-shelf fiber-optic transceivers currently available. spectrum, disk drive manufacturers providing fibre channel interfaced disk drives low-cost, higher speed replacements SCSI-2 SCSI-3. other spectrum, fibre channel provides switched networks over distances kilometers.
FIBER-OPTIC TRANSCEIVER
Finisar fiber-optic transceiver that translates between optic electrical worlds Lucent Technologies Microelectronics Group serializer/deserializer that translates 20-bit parallel code gigabit data stream ASIC that provides fibre channel functions data communications buffer that sits between fibre channel ASIC 32-bit RISC processor that handles transport higher level functions ORCA FPGA that provides control glue functions interconnect above elements well interface
SERIALIZER/DESERIALIZER
FIBER CHANNEL ASIC
EMBEDDED RISC PROCESSOR
VRAM
What Fibre Channel?
Fibre channel local area metropolitan area network that combines advantages highbandwidth channel with low-latency characteristics traditional network. fibre channel node (called N-port) interfaces fibre channel fabric, which routes data other nodes. Unlike traditional networks, fibre channel two-dimensional fabric, which both timedivision space-division switching component- connected parallel. addition, much like telephone system, each nodes simultaneously sending receiving traffic.
RECEIVE BUFFER
TRANSMIT BUFFER
FPGA
INTERNAL
FPGA
Figure PCI-Based Fibre Channel Adapter
PCI-Based Gbit/s Fibre Channel Adapter Using ORCA Series FPGAs
Type traffic best sent connectionless services because time required transmit short 128-byte packet 1.0625 Gbits/s only about 1.25 which doesn't warrant additional time required establish connection. important note that fibre channel provides intermix capability. This allows node support simultaneous Class connection while still allowing connectionless traffic share link. This guarantees that traffic that requires latency suspended while large data block being moved. embedded RISC processor manages flow data through fibre channel ASIC; handles initiation termination connections directly handle small volume connectionless traffic. cannot, however, cope with volume type traffic without external hardware assistance. This hardware assistance consists multithreaded controller that moves data between host fibre channel ASIC. Unfortunately, even with high-performance such PCI, cannot move data directly between fiber bus. fiber provides requires data continuously while latency associated with thus, data buffers required. determine size type data communications buffer examining constraints imposed traffic flow requirements. full-duplex design, adapter 1.0625 Gbits/s data links; receive transmit. Taking into account link packet coding overheads, this yields Mbytes/s payload bandwidth (100 Mbytes/s each direction). peak design bandwidth Mbytes/s (assuming clock 33.33 MHz). communicationsonly adapter (one which data consumed adapter) total peak bandwidth communications buffer Mbytes/s. multimedia adapters, where some data consumed adapter, total peak bandwidth Mbytes/s. latter case, communications buffer Mbytes/s data flowing between fabric buffer Mbytes/s data flowing between buffer outside world. minimum buffer size dictated maximum latency either on-board bus. specification suggests worst-case latency With data rates mentioned, require minimum buffer size approximately Kbytes. This minimum buffer size assumes zero latency within host software on-board embedded software.
What Bus?
peripheral component interface (PCI) high-performance used nearly 100% Pentium*based growing number RISC-based workstations. synchronous that supports clock rates MHz. This translates peak data transfer rate Mbytes/s 32-bit systems expandable bits. specification supports 256-byte configuration space that allows dynamic reconfiguration plug play environment. Since processor-independent nonterminated bus, used essentially system requiring cost high speed.
Data Stream
begin discussion examining flow data from fiber. actual fibre channel interface consists integrated fibre-optic transceiver, serializer/deserializer component, fibre channel ASIC. This devices takes 32-bit data stream handles physical- link-level formatting requirements fibre channel. design began studying statistics traffic flow existing large networks. found that traffic consisted types: Type first type traffic constituted only packets, large package size, required fiber bandwidth. Type second type traffic required latency constituted packets travelling over network, small packet size, required less than fiber bandwidth. There three classes service fibre channel:
Class connection-oriented Class connectionless acknowledged Class connectionless unacknowledged
decided that type traffic, because bandwidth requirements, would best sent Class service. This type service requires short initial period order microseconds) physical connection between originator destination then works like fire hose; providing continuous stream data maximum data rate fabric.
Pentium trademark Intel Corporation.
Lucent Technologies Inc.
PCI-Based Gbit/s Fibre Channel Adapter Using ORCA Series FPGAs
FPGA always least serial register ahead incoming data, delay start transfer after transfer required before overrun underrun condition occur. FPGA also controls interface Fibre Channel ASIC. Fibre Channel ASIC contains synchronous Kbyte FIFO. external interface this FIFO consists FIFO length counter, direction signal, transfer enable signal. Once transfer enabled, FPGA will continuously move data between Fibre Channel ASIC VRAM serial register port. transfers synchronized Fibre Channel ASIC supplied clock, which provides 36-bit word bits plus parity) 26.5625 rate (100 Mbytes/s). second function FPGA control transfer data VRAM parallel port. particular VRAM chosen supports maximum fast-page mode cycle time With 32-bit word, this results peak throughput only Mbytes/s. increasing word size bits, support Mbytes/s rate this internal also ease transition future 64-bit bus. control logic must arbitrate between following requestors VRAM parallel port interface:
Data Stream (continued)
other words, once data starts flow fiber, would need immediately begin transfer data between communications buffer bus. This unrealistic assumption minimum buffer size must increased. many systems, there more important application-imposed latency constraints. example, applications this adapter could handle real-time uncompressed video traffic. This application requires buffer size least uncompressed video frame. Assuming minimum video frame size Megapixels bits, arrive buffer size Mbytes Mbytes inbound Mbytes outbound). summarize, communications buffer must least Mbytes with bandwidth Mbytes/s this video application. first requirement eliminates some traditional buffer architectures (FIFOs, fast SRAM). second requirement eliminates standard DRAM architectures. only remaining choice, restrict ourselves off-the-shelf components, multiported DRAM (i.e., VRAM).
ORCA FPGA Functionality
first function FPGA control transfer data between Fibre Channel ASIC serial port VRAM. accomplish this, FPGA contains serial port controllers: receive transmit. Each these controllers consists address pointer location within VRAM), length counter associated control circuitry start stop data transfer, interrupt circuitry inform local processor when transfer completed. start transfer, circuitry arbitrates parallel VRAM port then performs full serial register transfer. This transfer establishes base address direction subsequent split serial register transfers. FPGA generates serial port clock maintains serial register position count. particular VRAM chosen given example serial register length bits each) words. After every words Kbytes), control circuitry within FPGA arbitrates parallel VRAM port performs split serial register transfer, which moves entire Kbyte chunk from DRAM. 1.0625 Gbits/s data rate, circuitry must perform split serial register transfer approximately every each direction). Since
Refresh Split serial register transfers Full serial register transfers mastering transfers to/from Slave access host Direct access local processor
Refresh easily handled using internal FPGA counter generate refresh requests appropriate intervals. Once refresh request gains control VRAM port, FPGA synthesizes standard before refresh cycle. mentioned previously, FPGA counts each word that transmitted recovered. each serial register boundary, split serial register transfer request generated during transfer cycle FPGA uses internal counters generate correct address split serial register transfer. FPGA also counts number split serial register transfers. When programmed number transfers have occurred, FPGA will inhibit further transfers will generate completion status local processor.
Lucent Technologies Inc.
PCI-Based Gbit/s Fibre Channel Adapter Using ORCA Series FPGAs
number 32-bit multiplexers. Although this feasible FPGA chosen, uses large amount internal routing resources. much simpler (and more flexible) approach implement register file using internal capabilities ORCA FPGAs single counters. When function becomes active (i.e., wins arbitration), appropriate counters fetched from register file written into corresponding counters. When function suspended because higher priority request preempted, current values counters written back into register file. This approach allows additional functions added with minor changes. minor functions FPGA function full DRAM controller slave accesses either host processor local processor. These requests have medium priority, below that refresh serial register transfers above transfers. This guarantees that these accesses starved during long transfer operations. FPGA provides full 32-bit interface between on-board embedded RISC processor internal well external bus. This allows local processor directly access internal FPGA control status registers access on-board VRAM directory. final function FPGA provide full master/target interface. Although this interface requires only small percentage total FPGA silicon available, imposes some most stringent timing drive requirements. Unlike many other technologies, uses reflective rather than incident-wave switching mechanism. This requirement means that selecting driver based current sink source specifications. Instead, complete specification provided. specification also stringent input capacitance signal trace length requirements. However, most difficult specifications (from FPGA viewpoint) input setup time clock output signal delay These specifications typically only latest generation FPGA technology, which specifically address requirements. Meeting timing requirements also requires careful FPGA assignment.
Data Stream (continued)
FPGA also provides multithreaded host controller, which controls bus-mastering transfer data between data communications buffer. FPGA maintains pointer control block within local processor's memory space. When current operation completed, retrieves next control words from memory then initiates transfer. control words specify VRAM base address, host memory base address, length transfer bytes). control blocks form circular queue task requests. interrogating FPGA, local processor easily determine which task currently progress which have already been completed. storing control blocks local processor memory, task overhead local processor minimized channel kept continuously active. back-end host controller decoupled from front-end mastering logic. This allows each section independently optimized. also allows each section reused future designs. most important advantage this decoupling that allows, necessary, each section have clock. front must, course, system clock. controller section, however, tightly coupled VRAM uses clock that optimized particular DRAM speed chosen. small internal FIFO sixteen 32-bit words provides necessary speed matching between front back end. important feature provided FPGA byte alignment big-endian, little-endian conversion logic. Even though 32-bit bus, host controller been designed allow starting ending transfer byte boundary, with transfer length which also specified bytes. This requires that data moving from host local communications realigned through 32-bit barrel shifter. also requires that local data communications buffer support byte writes, that starting ending transfers require read-modify-write cycles. There three simultaneously active functions: receiver DMA, transmitter DMA, host DMA. Each require three 32-bit registers (for source address, destination address, length). Separately implementing these three controllers would require seven 32-bit registers
Lucent Technologies Inc.
PCI-Based Gbit/s Fibre Channel Adapter Using ORCA Series FPGAs
ORCA series FPGAs meet these requirements were used implementation this design. They consist array cells (called PFUs), each which four 4-bit look-up tables 4-bit register. Alternatively, each cell used 4-bit cell. devices have very large amount routing resources provide multiple high-speed clock lines that meet clock-to-output timing requirement. Another important consideration selection FPGA availability third-party design tools, performance-driven placement routing tools, simulation tools that save many man-weeks effort during project. These available ORCA series FPGAs.
Data Stream (continued)
most useful features 256-byte configuration space. After powerup, adapter fully disabled must configured before being enabled. Configuration involves assigning adapter required resources (I/O ports, memory regions, interrupts, latency timers, etc.). This configuration space most easily implemented directly within FPGA. These registers readonly read-write cells that easily implemented SRAM-based ORCA FPGA architecture where individual functional units used either normal look-up tables registers cells. full 256-byte space would require sixty-four 32bit registers. PCI, however, specifies minimum universal configuration registers, which provided fewer than sixteen 32-bit registers. remaining optional locations must respond accesses implemented read-only registers that return data zeros. mapping addresses into this reduced space, using internal capabilities ORCA FPGAs, entire configuration space implemented with only eight cells FPGA. This represents total device utilization only 15,000 gate device full implementation with bytes would require 8%). final design resulted total requirement less than chosen device, including configuration space. more information implementing interface using ORCA FPGAs, ORCA Series FPGAs Applications application note (AP95-033FPGA).
Summary
design PCI-based Fibre Channel Adapter using ORCA series field-programmable gate arrays been described. This design provides lowlatency, high-bandwidth network solution, which capable peak transfer rates Mbytes/s capable sustained transfer rates Mbytes/s (for client server adapters) rates Mbytes/s (for communications adapters using 32-bit interface).
Credits
This application note written Frank Artner Ancor Communications Inc. Minneapolis,
Choosing FPGA
From preceding discussion, summarize requirements FPGA follows:
High pin-count support multiple 32-bit 64-bit buses)-approximate count High complexity-to support three separate interfaces, four controllers, VRAM control logic, etc. compatible buffers High speed-for guaranteed external clock output delays SRAM-based-for internal FIFO architectures
Lucent Technologies Inc.
PCI-Based Gbit/s Fibre Channel Adapter Using ORCA Series FPGAs
FPGA technical applications support, please call 1-800-327-9374. Outside U.S.A., please call 1-610-712-4331. additional information, contact your Microelectronics Group Account Manager following: INTERNET: U.S.A.: Microelectronics Group, Lucent Technologies Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18103 1-800-372-2447, 1-610-712-4106 CANADA: 1-800-553-2448, 1-610-712-4106), e-mail docmaster@micro.lucent.com ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 8833, (65) 7495 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 5421 1600, (81) 5421 1700 data requests Europe: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1734 299, (44) 1734 technical inquiries Europe: CENTRAL EUROPE: (49) 95086 (Munich), NORTHERN EUROPE: (44) 1344 (Bracknell UK), FRANCE: (33) (Paris), SOUTHERN EUROPE: (39) 6601 1800 (Milan) (34) 1700 (Madrid)
Lucent Technologies Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. rights under patent accompany sale such product(s) information. ORCA trademark Lucent Technologies Inc.
Copyright 1996 Lucent Technologies Inc. Rights Reserved Printed U.S.A.
October 1996 AP96-060FPGA (Replaces AP95-037FPGA)
Printed Recycled Paper

This application note describes design PCIbased Fibre Channel Adapter

Top Searches for this datasheet

Other recent searches