This application note designed serve supplement ATT3000 Series Data Sh

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This application note designed serve supplement ATT3000 Series Data Sh

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Additional ATT3000 Data
This application note designed serve supplement ATT3000 Series Data Sheet. covers wide range topics, including number electrical parameters specified data sheet. These additional parameters sufficiently accurate most design purposes. Unlike parameters specified data sheet, however, they worstcase values over temperature voltage, they not100% production tested. Therefore, they cannot guaranteed.
Configurable Logic Blocks
ATT3000 configurable logic block (CLB) shown Figure comprised combinatorial function generator D-type flip-flops. output pins driven either function generators flip-flops. flip-flop outputs routed directly back function generator inputs without going outside CLB.
DATA
COMBINATORIAL FUNCTION
OUTPUTS
LOGIC VARIABLES
ENABLE CLOCK
(ENABLE)
CLOCK
RESET
(INHIBIT) (GLOBAL RESET)
5-3103(F)
Figure Configurable Logic Block (CLB)
Additional ATT3000 Data
Configurable Logic Blocks (continued)
function generator consists four-input lookup tables that used separately combined into single function. Figure shows three available options. Since only five inputs function generator, inputs must shared between look-up tables. mode, function generator provides four-input functions plus choice between made separately each function. mode, five inputs combined into single five-input function five-input function emulated. mode superset mode, where four-input functions multiplexed together according fifth variable, modes, either inputs selectively replaced flip-flop outputs. mode, this selection made separately look-up tables, extending functionality functions four variables chosen from seven, provided variables stored flip-flops. This particularly useful state machine-like applications. mode, function generators implement single function five variables that chosen from seven, described above. selection constrained same both look-up tables. mode differs from mode that selected separately look-up tables, mode. This added flexibility permits emulation selected functions that include seven possible inputs.
FUNCTION VARIABLES
FUNCTION VARIABLES
FUNCTION VARIABLES
FUNCTION VARIABLES FUNCTION VARIABLES
5-3104(F)
Combinatorial Logic Option generates functions four variables each. variable, must common both functions. second third variables choice among fourth variable either Combinatorial Logic Option generates function five variables: choices among Combinatorial Logic Option allows variable select between functions four variables: both have common inputs, choice among remaining variables. Option then implement some functions seven variables.
Figure Logic Options
Lucent Technologies Inc.
Additional ATT3000 Data
Configurable Logic Blocks (continued)
D-type flip-flops share common clock, common clock enable, common asynchronous reset signal. asynchronous preset achieved using asynchronous reset data stored activelow form; created RESET corresponds being asserted. flip-flops cannot used latches. input data flip-flop derived directly from input pad, without intervening flip-flop, data clock hold time will typically nonzero. This hold time equal delay from clock reduced according rule, (described later Input section this application note). Under this rule, hold time reduced delay from data CLB, excluding setup time. minimum hold time zero, even when applying rule results negative number. pins which long lines have direct access shown Table Note that clock enable (CE) TBUF control both driven from/to same vertical long line. Consequently, cannot easily used enable register that must 3-stated onto bus. Similarly, cannot easily used register that uses reset direct (RD). Table Long Line Direct Access
Long Line
Input/Output Blocks
ATT3000 IOB, shown Figure includes 3-state output driver that driven directly registered. polarities both output data 3-state control determined configuration bits. Each output buffer configured have either fast slow slew rate. input also direct registered. Additionally, input flip-flop configured latch. When used exclusively input, optional pull-up resistor available, value which k-150 This resistor cannot used when configured output bidirectional pin. Unused lOBs should left unconfigured. They default inputs pulled high with internal resistor.
Inputs
inputs have limited hysteresis, typically excess input thresholds excess CMOS thresholds. Exceptions this PWRDWN XTL2 pin, when configured crystal oscillator input. Experiments show that input rise fall times should exceed This value established through worst-case test using internal ring oscillators drive pins except two, therefore generating maximum on-chip noise. remaining pins configured input tested singleedge response-the other used output monitor response. These test conditions possibly overly demanding, although assumed that board negligible ground noise good power supply decoupling. While conservative, resulting specification most instances, easily satisfied. input flip-flops guaranteed operate correctly without data hold times (with respect device clock-input pad), provided dedicated CMOS clockin GCLK buffer used. clock different clock will result data holdtime requirement. length this hold time equal delay from actual clock GCLK buffer minus delay from dedicated CMOS clock GCLK buffer.
TBUF
Left-most Vertical (GCLK) Left Middle Vertical Right Middle Vertical Right-most Vertical (ACLK) Upper Horizontal Lower Horizontal
Lucent Technologies Inc.
Additional ATT3000 Data
Input/Output Blocks (continued)
PROGRAM-CONTROLLED MEMORY CELLS PASSIVE PULL
INVERT
3-STATE INVERT
OUTPUT SELECT
SLEW RATE
3-STATE OUTPUT ENABLE
OUTPUT BUFFER
FLIPFLOP DIRECT REGISTERED FLIPFLOP LATCH (GLOBAL RESET)
CMOS INPUT THRESHOLD
PROGRAMCONTROLLED MULTIPLEXER PROGRAMMABLE INTERCONNECTION POINT
5-3102(F)
Figure Input/Output Block (IOB)
ensure that input flip-flop zero hold time, delay incorporated input flip-flop, causing have relatively long setup time. However, setup time specified data sheet with respect clock reaching IOB. Since there unavoidable delay between clock IOB, input clock setup time actually less than data sheet number. Part clock delay subtracted from internal setup time. Ideally, clock delay could subtracted, possible clock delay less than maximum while internal setup time maximum value. Consequently, recommended that, worst-case design, only clock delay subtracted.
clock delay only less than maximum internal setup time requirement also less than maximum. this case, data clock setup time actually required will less than that calculated. example, ATT3000-125, input setup time with respect clock reaching delay from clock then this delay, subtracted arrive maximum pad-to-pad setup time
Lucent Technologies Inc.
Additional ATT3000 Data
Input/Output Blocks (continued)
rule must applied whenever delay subtracted from another. However, recommended that delay compensation only used connection with input hold times. Delay compensation asynchronous circuits recommended. case, compensated delay must become negative. compensating delay greater than delay deducted from, resulting delay zero. rule defines absolute minimum value delays that might encountered from chip chip with temperature power supply variations. simply indicates relative variations that might found within specific chip over range operating conditions. Typically, delays will less than their maximum, with some delays being disproportionately faster than others. rule describes spread scaling factors: delay that decreases most will less than what would have been scaled proportion delay that decreased least. particular, worst-case design where assumed that delay might have scaled remains maximum value, other delays will less than their maximum.
VOLTS
5-4063(F)
Figure Output Current/Voltage Characteristics -70, -100, -125, -150 Speed Grades
Outputs
ATT3000 outputs true CMOS, with n-channel transistors pulling down p-channel transistors pulling Unloaded, these outputs pull rail-to-rail. Some additional characteristics output listed Table Figures show output current/voltage curves typical ATT3000 devices. Output short-circuit current values given only indicate capability charge discharge capacitive loads. accordance with common industry practice other logic devices, only output time short-circuited, duration this short circuit ground exceed second. continuous output clamp current excess output recommended. data sheet guarantees outputs more than avoid problems when many outputs sinking current simultaneously.
VOLTS
5-4064(F)
Figure Output Current/Voltage Characteristics Speed Grades active-high 3-state control same active-low output enable (OE). other words, high T-pin OBUFZ places output highimpedance state, enables output. same naming convention used TBUFs within FPGA device.
Lucent Technologies Inc.
Additional ATT3000 Data
Input/Output Blocks (continued)
Clocks
Internally, eight distinct clocks used- each four edges die. While does provide programmable clock polarity, clock lines serving used true inverted clock. appropriate polarity then connected IOB. This does, however, limit lOBs that edge using only edges clock. latches have active-low latch enables; they transparent when clock input low, they closed when high. latch captures data what would otherwise active clock edge, transparent half-clock period before active clock edge. Table Additional Output Characteristics Parameters
Unloaded Output Slew Rate Unloaded Transition Time Additional Rise Time Normalized Additional Fall Time Normalized
Table Number Horizontal Long Lines Part Name ATT3020 ATT3030 ATT3042 ATT3064 ATT3090 Rows Columns CLBs HLLs TBUFs
Optionally, HLLs pulled either both ends. value each pull-up resistor addition, HLLs permanently driven lowpowered latches (bus hold circuits) that easily overridden active outputs pull-up resistors. These latches maintain logic levels HLLs that pulled that temporarily driven. logic level maintained last level actively driven onto line. When using 3-state HLLs multiplexing, fewer than four TBUFs waste resources. Multiplexers with four fewer inputs implemented more efficiently using CLBs.
Fast*
Slow*
V/ns V/ns 1.45 0.12 ns/pF 0.12 ns/pF 0.06 ns/pF 0.08 ns/pF
Vertical Long Lines
There four vertical long lines routing channel: general purpose, global clock net, alternate clock net.
Fast slow refer output programming option.
Routing
Horizontal Long Lines
shown Table there horizontal long lines (HLLs) CLBs. Each driven TBUF each column CLBs, plus additional TBUF left long line. This additional TBUF convenient driving data onto long line. general, routing resources pins TBUFs somewhat limited.
Lucent Technologies Inc.
Additional ATT3000 Data
Routing (continued)
Clock Buffers
ATT3000 devices contain high fan-out, low-skew, clock distribution networks. global clock originates from GCLK buffer upper-left corner die, while alternate clock originates from ACLK buffer lower-right corner die. global alternate clock networks each have optional fast CMOS inputs called TCLKIN BCLKIN, respectively. Using these inputs provides fastest path from board internal flip-flops latches. Since signal bypasses input buffer, well-defined CMOS levels must guaranteed these clock pins. specify TCLKIN BCLKIN schematic, connect IPAD symbol directly GCLK ACLK symbol. Placing IBUF between IPAD clock buffer will prevent TCLKIN BCLKIN from being used. clock buffer output nets only drive clock pins. They drive other inputs. rare cases where clock needs connected logic input device output, signal should tapped clock buffer input routed logic input. This possible with clocks using TCLKIN BCLKIN. clock skew created routing clocks through local interconnect makes safe designs very difficult achieve, this practice recommended. general, fewer clocks used, safer design. High fan-out clocks should always GCLK ACLK. more than clocks required, ACLK segmented into individual vertical lines that driven PlPs bottom each column. Clock signals routed through local interconnect should only considered individual flip-flops.
General Information
Recovery from Reset
Recovery from reset specified ATT3000 data sheet because very difficult measure production environment. following values assumed ATT3000 devices speed grades:
clocked immediately (<0.2 after internal reset direct signal (RD). clocked earlier than (worstcase) after release externally applied global reset signal, i.e., after rising edge activelow signal.
Configuration Start-Up
Until chip goes active after configuration, pins involved configuration process remain high-impedance state with weak pull-up resistors, internal flip-flops latches held reset. Multiple FPGA devices hooked daisy chain will active simultaneously same CCLK edge. This documented ATT3000 data sheet. documented, however, internal combinatorial logic comes alive during configuration: configuration data shifted reaches destination, activates logic also "looks inputs. Even crystal oscillator starts operating soon receives configuration data. Since flip-flops latches being held reset outputs being held their high-impedance state, there danger this staggered awakening internal logic. operation logic prior configuration even useful-it ensures that clock enables output enables correctly defined before elements they control become active.
Lucent Technologies Inc.
Additional ATT3000 Data
internal reset, RESET kept high internal external pull-up resistors. configuration, unasserted, remains high since function generator acts latch; stays low, RESET still pulled high external resistor. first system clock after configuration ends, clocked high, resetting latch enabling output driver, which forces RESET low. This resets whole chip until permits RESET pulled high again. whole chip thus been reset short pulse instigated system clock. further pulses generated, since high prevents latch from becoming set.
General Information (continued)
Once configuration complete, device activated. This occurs rising edge CCLK, when outputs clocks that enabled become active simultaneously. Since activation triggered CCLK, asynchronous event with respect system clock. avoid start-up problems caused this asynchronism, some designs might require reset pulse that synchronized system clock. circuit shown Figure generates short global reset pulse response first system clock after configuration. uses IOB, also precludes I/O. During configuration, asserted holds D-input flip-flop high, while held
HIGH SYSTEM CLOCK RESET
HIGH
5-4065(F)
Figure Synchronous Reset
Lucent Technologies Inc.
Additional ATT3000 Data
General Information (continued)
Power Dissipation
most CMOS ICs, almost FPGA power dissipation dynamic caused charging discharging internal capacitances. Each node device dissipates power according capacitance node (which fixed each type node) frequency which particular node switching (which different from clock frequency). total dynamic power power dissipated individual nodes. While clock line frequency easy specify, usually more difficult estimate average frequency other nodes. extreme cases binary counters, where half total power dissipated first flipflop, shift registers with alternating zeros ones, where whole circuit exercised clocking speed. popular assumption that, average, each node exercised clock rate; major EPLD vendor uses 16-bit counter model, where effective percentage only 12%. Undoubtedly, there extreme cases where ratio much lower much higher, valid approximation most normal designs. Note that global clock lines must always entered with their real, wellknown, frequency. Consequently, most power consumption estimates only serve guidelines based gross approximations. Table shows dynamic power dissipation, MHz, different types ATT3000 nodes. While precise, these numbers sufficiently accurate calculations which they used, used ATT3000 device. Table shows sample power calculation.
Table Dynamic Power Dissipation Example driving three local interconnects device output with load global clock buffer line long line without driver ATT3020 ATT3090 (mW/MHz) (mW/MHz) 0.25 1.25 2.00 0.10 0.25 1.25 3.50 0.15
Table Sample Power Calculation ATT3020 Node Clock Buffer CLBs CLBs CLBs Long Lines Outputs Total Power Quantity 2.00 0.25 0.25 0.25 0.10 1.25 ~800
Lucent Technologies Inc.
Additional ATT3000 Data
frequencies, width which oscillating frequency. exact frequency oscillation within this band depends components surrounding crystal. Series-resonant crystals specified their manufacturers according lower edge frequency band; parallel-resonant crystals specified according upper edge. resistor controls loop gain, value must established experimentation. small, oscillation will distorted; large, oscillation will fail start will only start slowly. most cases, value noncritical, typically Once component values have been chosen, good practice test oscillator with resistor series with crystal. oscillator still starts reliably, independent whether power supply turns quickly slowly, will always work without resistor.
General Information (continued)
Crystal Oscillator
ATT3000 devices contain on-chip crystal oscillator circuit that connects ACLK buffer. This circuit (see Figure comprises high-speed, high-gain, inverting amplifier, with input connected dedicated XTL2 pin, output connected XTL1 pin. external biasing resistor, with value required. crystal, additional phase-shifting components, complete circuit. capacitors, parallel, form load crystal. This load specified crystal manufacturer typically capacitors should approximately equal each crystal. Either series- parallel-resonant crystals used, since they differ only their specification. Crystals constrain oscillation narrow band
INTERNAL
EXTERNAL
XTAL1
ALTERNATE CLOCK BUFFER
XTAL2 (IN) OVERTONE ONLY
5-3109(F)
Figure Crystal Oscillator Inverter
Lucent Technologies Inc.
Additional ATT3000 Data
General Information (continued)
operation above MHz, crystal must operate third harmonic. capacitor replaced parallel-resonant tank circuit tuned ~2/3 desired frequency; i.e., twice fundamental frequency crystal. Table shows typical component values tank circuit. Table Third Harmonic Crystal Oscillator Tank Circuit
Tank Frequency (MHz) (µH) (pF) Freq. (MHz) 20.6 24.0 28.6 37.5 (pF)
Table CCLK Frequency Variation Temperature (°C) +130 Frequency (kHz)
Metastable Recovery
Whenever clocked flip-flop synchronizes asynchronous input, there small probability that flipflop output will exhibit unpredictable delay. This happens when input transition only violates setup hold-time specifications, actually occurs within tiny timing window where flip-flop accepts input. Under these circumstances, flip-flop enter symmetrically balanced transitory state, called metastable (meta between). While slightest deviation from perfect balance will cause output revert stable states, delay doing depends only gain bandwidth product circuit, also perfect balance noise level within circuit; delay can, therefore, only described statistical terms. problem system designer illegal logic level balanced state (it's easy enough translate either unpredictable timing final change valid logic state. metastable flip-flop drives destinations with differing path delays, destination might reflect final data state, while other does not. With help mostly self-contained circuit demonstration board, ATT3020-70 flip-flop evaluated. result this evaluation shows ATT3000 flip-flop superior metastable performance many popular devices. Statistically, when asynchronous event with frequency approximately being synchronized clock, flip-flop suffers additional delay once hour once 1000 years.
CCLK Frequency Variation
on-chip oscillator that brought CCLK also performs several other internal functions. generates power-on delay: 65,536 periods master and/or 16,384 periods slave peripheral device. generates shift pulses clearing configuration array, using clock period frame, clock source several small shift registers acting low-pass filters variety input signals. nominal frequency this oscillator with maximum deviation +25% -50%. clock frequency, therefore, between 1.25 MHz. Lucent Technologies Microelectronics Group's circuit designers make sure that internal clock frequency does faster devices migrated smaller geometries faster processes. Even newest fastest Lucent FPGA compatible with oldest slowest device ever manufactured. CCLK frequency fairly insensitive changes VCC, varying only 0.6% change VCC. however, very temperature dependent, increasing temperature drops from (see Table
Lucent Technologies Inc.
Additional ATT3000 Data
Deliberate skew input data eight metastable circuits ensured that, most, metastable event could occur each clock. This permitted eight detectors ORed into single metastable event counter. expected, metastable events were observed clock rates below MHz, since one-half clock period adequate almost metastability resolution delay, plus flip-flop setup time. Increasing clock rate around brought sudden burst metastable events. Careful adjustment clock frequency gave repeatable, reliable measurements, showing that decrease half clock period increased frequency metastable occurrences factor conservative, compensate favorable conditions room temperature, avoid possibility overstating good case, measurements were interpreted follows: when capturing asynchronous data, error rate decreases factor every additional nanosecond metastability resolution delay that system tolerate.
General Information (continued)
frequency occurrence these metastable delays proportional product asynchronous event frequency clock frequency. example, event synchronized clock, above delays (besides being more tolerable) will occur times less often. Since metastability only measured statistically, this data obtained configuring ATT3020 with eight concurrent detectors. Eight D-type flip-flops were clocked from common high-speed source, their inputs driven from common, lower frequency asynchronous signal, Figure output each flip-flop inputs more flip-flops, clocked onehalf clock period later second full clock period later. metastable event first flip-flop increased output settling time more than one-half clock period, second flip-flops would capture differing data. Therefore, occurrence long metastable delay could detected using simple comparator.
CLOCK
COUNTER DISPLAY
NONMETASTABLE METASTABLE
CLOCK COUNT PULSE METASTABLE
REPEATED EIGHT TIMES
5-4066(F)
Figure Metastable Measuring Circuit
Lucent Technologies Inc.
Additional ATT3000 Data
General Information (continued)
Metastability Calculations
mean time between failures (MTBF) only defined statistically. inversely proportional product frequencies involved: clock frequency (F1) average frequency data changes (F2), provided that these frequencies independent have correlation. factor that dimension time, describes likelihood going metastable. exponent that describes speed with which metastable condition being resolved. 1/MTBF MTBF seconds 1010 seconds (measured ATT3020-70) ln(40) 3.69 second (ATT3020-70) clock approximately data rate, table below gives expected MTBF function acceptable extra delay output metastable going flip-flop.
1011 1010 MTBF (ns)
5-4067(F)
1000 YEARS
YEAR MONTH HOUR FDATA FCLOCK
Extra Delay (ns) 10.0 11.0 12.0
MTBF days 225,000 million million
Figure Metastable MTBF Function Additional Acceptable Delay
Lucent Technologies Inc.
Additional ATT3000 Data
Figure shows powerdown circuit developed Shel Epstein Epstein Associates, Wilmette, Schottky diodes power FPGA from either primary supply Lithium battery. Seiko S8054 three-terminal power monitor circuit monitors pulls PWRDWN whenever falls below
SEIKO S8054 SPECIFICATIONS DETECT VOLTAGE HYSTERESIS TEMP. COEFF. 3.995 4.305 0.52
General Information (continued)
Battery Backup
Since logic cell arrays manufactured using highperformance, low-power CMOS process, they preserve configuration data stored internal static memory cells, even during loss primary power. This accomplished forcing device into low-power, nonoperational state, while supplying minimal current requirement from battery. There primary considerations battery backup which must accomplished external circuits:
Control powerdown (PWRDWN) Switching between primary supply battery
IN5817
IN5817
Important considerations include following:
Ensure that PWRDWN asserted logic prior falling, that held while primary absent, that returned high after returned normal level. PWRDWN edges must rise fall slowly. Ensure glitch-free switching power connections FPGA device from primary battery back. Ensure that during normal operation FPGA maintained acceptable level, (+10% industrial).
SEIKO PWRDWN 8054 ATT3000
LITHIUM BATTERY
5-4068(F)
Figure Battery Backup Circuit
Lucent Technologies Inc.
Additional ATT3000 Data
Notes
Lucent Technologies Inc.
Additional ATT3000 Data
FPGA technical applications support, please call 1-800-327-9374. Outside U.S.A., please call 1-610-712-4331. additional information, contact your Microelectronics Group Account Manager following: INTERNET: U.S.A.: Microelectronics Group, Lucent Technologies Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18103 1-800-372-2447, 1-610-712-4106 CANADA: 1-800-553-2448, 1-610-712-4106), e-mail docmaster@micro.lucent.com ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 8833, (65) 7495 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 5421 1600, (81) 5421 1700 data requests Europe: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1734 299, (44) 1734 technical inquiries Europe: CENTRAL EUROPE: (49) 95086 (Munich), NORTHERN EUROPE: (44) 1344 (Bracknell UK), FRANCE: (33) (Paris), SOUTHERN EUROPE: (39) 6601 1800 (Milan) (34) 1700 (Madrid)
Lucent Technologies Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. rights under patent accompany sale such product(s) information. ORCA trademark Lucent Technologies Inc.
Copyright 1996 Lucent Technologies Inc. Rights Reserved Printed U.S.A.
October 1996 AP96-057FPGA (Replaces AP95-003FPGA)
Printed Recycled Paper

This application note designed serve supplement ATT3000 Series Data Sh

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