µPD78F4225, 78F4225Y 16/8-BIT SINGLE-CHIP MICROCONTROLLERS D

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µPD78F4225, 78F4225Y 16/8-BIT SINGLE-CHIP MICROCONTROLLERS D

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INTEGRATED CIRCUIT
µPD78F4225, 78F4225Y
16/8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
µPD78F4225 78F4225Y products µPD784225, 784225Y Subseries 78K/IV Series. µPD78F4225 78F4225Y have flash memory place internal µPD784225 784225Y. Data written erased from flash memory µPD78F4225 78F4225Y with microcontroller mounted printed wiring board. µPD78F4225Y based µPD78F4225 with interface added supporting multi masters. Detailed function descriptions provided following user's manuals. sure read them before designing.
µPD784225, 784225Y Subseries User's Manual Hardware: U12697E
78K/IV Series User's Manual Instruction: U10905E
FEATURES
Pin-compatible with mask version (except pin) Flash memory: Serial interface: channels UART/IOE (3-wire serial I/O): channels (I2C supporting 3-wire serial multi mastersNote): channel Internal RAM: 4,352 bytes Supply voltage: Note
µPD78F4225Y only
ORDERING INFORMATION
Part Number Package 80-pin plastic 80-pin plastic TQFP (fine pitch) 80-pin plastic 80-pin plastic TQFP (fine pitch)
µPD78F4225GC-8BT µPD78F4225GK-9EU µPD78F4225YGC-8BT µPD78F4225YGK-9EU
APPLICATIONS
audios, portable audios, telephones, etc. Unless otherwise specified, descriptions this document made using
PD78F4225Y typical product.
information this document subject change without notice. Before using this document, please confirm that this latest version.
devices/types available every country. Please check with local representative availability additional information.
Document U12377EJ1V0DS00 (1st edition) Date Published February 2001 CP(K) Printed Japan
mark
shows major revised points.
1997, 2001
µPD78F4225, 78F4225Y
78K/IV SERIES LINEUP
mass production Under development Supports Supports multi-master
PD784038Y PD784038
PD784225Y PD784225
80-pin, correction added Supports multi-master
Standard models
PD784026
Enhanced converter, 16-bit timer, power management
Enhanced internal memory capacity Pin-compatible with PD784026 Supports multi-master
µPD784216AY PD784216A
100-pin, enhanced internal memory capacity
µPD784218AY PD784218A
Enhanced internal memory capacity, correction added
µPD784054 µPD784046
ASSP models
PD784956A
inverter control
On-chip 10-bit converter
PD784938A
Enhanced functions PD784908, enhanced internal memory capacity, correction added Supports multi-master
µPD784967
Enhanced functions PD784938A, enhanced internal memory capacity, expanded peripheral functions
PD784908
On-chip IEBuscontroller
PD784928Y µPD784915
Software servo control On-chip analog circuit VCRs Enhanced timer
PD784928
Enhanced functions PD784915
PD784976
On-chip controller/driver
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
OVERVIEW FUNCTIONS
Item Number basic instructions (mnemonics) General-purpose registers Minimum instruction execution time Internal memory Memory space ports Total CMOS input CMOS Pins with ancillary functionsNote Pins with pull-up resistor LEDs direct drive output Flash memory bits registers banks, bits registers banks (memory mapping) ns/320 ns/640 ns/1280 ns/2560 (main system clock: 12.5 MHz) (subsystem clock: 32.768 kHz) 4,352 bytes with program data spaces combined bits bits Timer/event counter: bits) timer counter Capture/compare register Pulse output PWM/PPG output Square wave output One-shot pulse output Pulse output output Square wave output Pulse output output Square wave output Function
Real-time output port Timer/counter
Timer/event counter timer counter bits) Compare register Timer/event counter timer counter bits) Compare register Timer bits) Timer bits) Serial interface converter converter Clock output Buzzer output Watch timer Watchdog timer Standby Interrupts Hardware Software Non-maskable Maskable timer counter Compare register timer counter Compare register
UART/IOE (3-wire serial I/O): channels (on-chip baud rate generator) (3-wire serial I/O, supporting multi mastersNote channel 8-bit resolution channels 8-bit resolution channels Selectable from fXX, /22, /23, /24, fXX/26 fXX/27, Selectable from /210 /211, fXX/212, fXX/213 channel channel HALT/STOP/IDLE mode power-saving mode (CPU operation with subsystem clock): HALT/IDLE mode (internal: external: instruction, BRKCS instruction, operand error Internal: external: Internal: external: programmable priority levels servicing modes: vectored interrupt/macro service/context switching
Supply voltage Package
80-pin plastic 80-pin plastic TQFP (fine pitch)
Notes pins with ancillary functions included pins. µPD78F4225Y only
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
CONTENTS
DIFFERENCES AMONG PRODUCTS µPD784225, 784225Y SUBSERIES CONFIGURATION (TOP VIEW) BLOCK DIAGRAM FUNCTION
Port Pins Non-Port Pins Circuits Recommended Connection Unused Pins
INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) PROGRAMMING FLASH MEMORY
Selecting Communication Mode Flash Memory Programming Function Connecting Flashpro
ELECTRICAL SPECIFICATIONS PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS
APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
DIFFERENCES AMONG PRODUCTS µPD784225, 784225Y SUBSERIES
difference between µPD784224, 784225, 784224Y, 784225Y lies internal memory capacity. µPD784224Y 784225Y versions with control added. µPD78F4225 78F4225Y provided with flash memory instead mask above versions. These differences summarized Table 1-1. Table 1-1. Differences Among Products µPD784225, 784225Y Subseries
Part Number Item Internal
µPD784224, µPD784224Y
(mask ROM) 3,584 bytes None
µPD784225, µPD784225Y
(mask ROM) 4,352 bytes
µPD78F4225, µPD78F4225Y
(flash memory)
Internal Internal memory size switching register (IMS) Note Supply voltage Electrical specifications Recommended soldering conditions TEST pins
Provided
Refer relevant data sheet.
Provided None
None Provided
Note Internal flash memory capacity internal capacity changed with internal memory size switching register (IMS). Caution There differences noise immunity noise radiation between flash memory mask versions. When pre-producing application with flash memory version then mass-producing with mask version, sure conduct sufficient evaluations commercial samples (not engineering samples) mask version.
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
CONFIGURATION (TOP VIEW)
80-pin plastic
µPD78F4225GC-8BT, 78F4225YGC-8BT
80-pin plastic TQFP (fine pitch)
µPD78F4225GK-9EU, 78F4225YGK-9EU
P02/INTP2/NMI
P05/INTP5
P04/INTP4
P03/INTP3
P01/INTP1
P15/ANI5 P16/ANI6 P17/ANI7 AVSS P130/ANO0 P131/ANO1 AVREF1 P70/SI2/RxD2 P71/SO2/TxD2 P72/SCK2/ASCK2 P20/SI1/RxD1 P21/SO1/TxD1 P22/SCK1/ASCK1 P23/PCL P24/BUZ P25/SI0/SDA0
Note
P00/INTP0
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
VPPNote
AVDD
VDD0
VDD1
VSS0
RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RTP2 P121/RTP1 P120/RTP0 P37/EXA P36/TI01 P35/TI00 P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR
P26/SO0 P27/SCK0/SCL0Note P40/AD0 P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P50/A8
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
P60/A16
P61/A17
P62/A18
P63/A19
Notes µPD78F4225Y only normal operation mode, connect directly pin, pull down. system where internal flash memory rewritten while mounted board, pull down. When pulling down, connection higher lower resistor recommended. Cautions Connect AVDD pin. Connect AVSS pin. Remark When using applications where noise from inside microcontroller reduced, recommended take countermeasures against noise such supplying power VDD0 VDD1 independently, connecting VSS0 VSS1 different ground lines.
Data Sheet U12377EJ1V0DS
P64/RD
VSS1
µPD78F4225, 78F4225Y
A19: AD7: ANI0 ANI7: ANO0, ANO1: ASCK1, ASCK2: ASTB: AVDD: AVREF1: AVSS: BUZ: EXA: INTP0 INTP5: NMI: P05: P17: P27: P37: P47: P57: P67: P72: P120 P127: Address Address/data Analog input Analog output Asynchronous serial clock Address strobe Analog power supply Analog reference voltage Analog ground Buzzer clock External access status output Interrupt from peripherals Non-maskable interrupt Port Port Port Port Port Port Port Port Port P130, P131: PCL: RESET: RTP0 RTP7: RxD1, RxD2: SCK0 SCK2: SCL0Note: SDA0Note: SI2: SO2: TI00, TI01, TI1, TI2: TO2: TxD1, TxD2: VDD0, DD1: VPP: VSS0, VSS1: WAIT: XT1, XT2: Port Programmable clock Read strobe Reset Real-time output port Receive data Serial clock Serial clock Serial data Serial input Serial output Timer input Timer output Transmit data Power supply Programming power supply Ground Wait Write strobe Crystal (main system clock) Crystal (subsystem clock)
Note µPD78F4225Y only
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
BLOCK DIAGRAM
RxD1/SI1 TxD1/SO1 ASCK1/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 SI0/SDA0Note SCK0/SCL0Note Timer/counter bits) Timer/counter bits) 78K/IV core Flash memory Port Watch timer Port Port Watchdog timer Port Port Port Port converter Port Port Port converter WAIT ASTB P120 P127 P130, P131 RESET Clock output control Buzzer output System control VDD0, VDD1 VSS0, VSS1
INTP2/NMI INTP0, INTP1, INTP3 INTP5 TI00 TI01
Programmable interrupt controller Timer/event counter bits) Timer/event counter bits) Timer/event counter bits)
UART/IOE1 Baud-rate generator UART/IOE2 Baud-rate generator Clocked serial interface
RTP0 RTP7 NMI/INTP2 ANO0 ANO1 AVREF1 AVSS ANI0 ANI7 AVDD AVSS P03/INTP3
Real-time output port
Note µPD78F4225Y only. Supports interface.
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
FUNCTION Port Pins (1/2)
Name Input Alternate Function INTP0 INTP1 INTP2/NMI INTP3 INTP4 INTP5 ANI0 ANI7 Port (P1): 8-bit input port Port (P2): 8-bit port Input/output specified 1-bit units. Pins input mode connected internal pull-up resistors software 1-bit units. Function Port (P0): 6-bit port Input/output specified 1-bit units. Pins input mode connected internal pull-up resistors software 1-bit units.
RxD1/SI1 TxD1/SO1 ASCK1/SCK1 SI0/SDA0Note SCK0/SCL0Note
TI00 TI01
Port (P3): 8-bit port Input/output specified 1-bit units. Pins input mode connected internal pull-up resistors software 1-bit units.
Port (P4): 8-bit port Input/output specified 1-bit units. pins input mode connected internal pull-up resistors software. drive LEDs. Port (P5): 8-bit port Input/output specified 1-bit units. pins input mode connected internal pull-up resistors software. drive LEDs.
Note µPD78F4225Y only
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Port Pins (2/2)
Name Alternate Function WAIT ASTB RxD2/SI2 Port (P7): 3-bit port Input/output specified 1-bit units. Pins input mode connected internal pull-up resistor software 1-bit units. Function Port (P6): 8-bit port Input/output specified 1-bit units. pins input mode connected internal pull-up resistors software.
TxD2/SO2
ASCK2/SCK2
P120 P127
RTP0 RTP7
Port (P12): 8-bit port Input/output specified 1-bit units. Pins input mode connected internal pull-up resistor software 1-bit units. Port (P13): 2-bit port Input/output specified 1-bit units.
P130, P131
ANO0, ANO1
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Non-Port Pins (1/2)
Name TI00 TI01 RxD1 RxD2 TxD1 TxD2 ASCK1 ASCK2 SDA0 SCK0 SCK1 SCK2 SCL0 INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 RTP0 RTP7 Output Output Output Input Output Input Input Output Input Output Input Alternate Function P20/SI1 P70/SI2 P21/SO1 P71/SO2 P22/SCK1 P72/SCK2 P25/SDA0Note P20/RxD1 P70/RxD2 P21/TxD1 P71/TxD2 P25/SI0 P27/SCL0Note P22/ASCK1 P72/ASCK2 P27/SCK0 P02/INTP2 P02/NMI P120 P127 Clock output (for trimming main system clock subsystem clock) Buzzer output Real-time output port that outputs data synchronization with trigger Low-order address/data when external memory connected Middle-order address when external memory connected High-order address when external memory connected Strobe signal output read operation external memory Strobe signal output write operation external memory Serial data input (UART1) Serial data input (UART2) Serial data output (UART1) Serial data output (UART2) Baud rate clock input (UART1) Baud rate clock input (UART2) Serial data input (3-wire serial clock I/O0) Serial data input (3-wire serial clock I/O1) Serial data input (3-wire serial clock I/O2) Serial data output (3-wire serial I/O0) Serial data output (3-wire serial I/O1) Serial data output (3-wire serial I/O2) Serial data input/output (I2C bus) Serial clock input/output (3-wire serial I/O0) Serial clock input/output (3-wire serial I/O1) Serial clock input/output (3-wire serial I/O2) Serial clock input/output (I2C bus) Non-maskable interrupt request input External interrupt request input Function External count clock input 16-bit timer register Capture trigger signal input capture/compare register External count clock input 8-bit timer register External count clock input 8-bit timer register 16-bit timer output (shared 14-bit output) 8-bit timer output (shared 8-bit output)
Output
Output
Note µPD78F4225Y only
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Non-Port Pins (2/2)
Name WAIT ASTB Input Output Alternate Function Function insert wait state(s) when external memory accessed Strobe output externally latch address information output ports through access external memory External access status output System reset input Connecting crystal resonator main system clock oscillation
RESET ANI0 ANI7 ANO0, ANO1 AVREF1 AVDD AVSS VDD0 VSS0 VDD1 VSS1
Output Input Input Input Input Output
Connecting crystal resonator subsystem clock oscillation
P130, P131
Analog voltage input converter Analog voltage output converter apply reference voltage converter Positive power supply converter. Connected VDD0. converter converter. Connected VSS0. Positive power supply port block potential port block Positive power supply (except port block) potential (except port block)
Sets flash memory programming mode. high voltage application when program written verified. normal operation mode, connect directly pin, pull down. system where internal flash memory rewritten while mounted board, pull down. When pulling down, connection higher lower resistor recommended.
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Circuits Recommended Connection Unused Pins
circuit types each recommended connection unused pins shown Table 4-1. circuit configuration each type, refer Figure 4-1. Table 4-1. Circuits Recommended Connection Unused Pins (1/2)
Name P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 P05/INTP5 P10/ANI0 P17/ANI7 P20/RxD1/SI1 P21/TxD1/SO1 P22/ASCK1/SCK1 P23/PCL P24/BUZ P25/SDA0Note/SI0 P26/SO0 P27/SCL0Note/SCK0 P30/TO0 P32/TO2 P33/TI1, P34/TI2 P35/TI00, P36/TI01 P37/EXA P40/AD0 P47/AD7 P50/A8 P57/A15 P60/A16 P63/A19 P64/RD P65/WR P66/WAIT P67/ASTB P70/RxD2/SI2 P71/TxD2/SO2 P72/ASCK2/SCK2 P120/RTP0 P127/RTP7 P130/ANO0, P131/ANO1 12-D 10-I 10-J 10-I 10-I 10-J 10-I 10-J Input Connect VSS0 VDD0 Input Independently connect VSS0 resistor Output: Leave open Circuit Type Recommended Connection Unused Pins Input Independently connect VSS0 resistor Output: Leave open
Note µPD78F4225Y only
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Table 4-1. Circuits Recommended Connection Unused Pins (2/2)
Name RESET AVREF1 AVDD AVSS Connect VSS0 Directly connect VSS0 Circuit Type Input Connect VSS0 Leave open Connect VDD0 Recommended Connection Unused Pins
Remark Because circuit type numbers standardized among Series products, they sequential some models (i.e., some circuits provided).
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Figure 4-1. Types Circuits (1/2)
Type Type VDD0
Pullup enable VDD0 Data P-ch
P-ch
IN/OUT Schmitt-triggered input with hysteresis characteristics Output disable VSS0 Input enable Type Pullup enable VDD0 Data P-ch IN/OUT Output disable VSS0 Input enable Type VDD0 Type 10-I VDD0 N-ch Input enable VDD0 Type N-ch
P-ch P-ch N-ch Comparator
VREF (threshold voltage)
Pullup enable VDD0 Data P-ch
P-ch
Pullup enable VDD0 Data IN/OUT P-ch
P-ch
IN/OUT Open drain Output disable VSS0 N-ch
Output disable VSS0
N-ch
Type
VDD0
Type 10-J
VDD0
Pullup enable VDD0 Data P-ch
P-ch
Pullup enable VDD0 Data IN/OUT P-ch
P-ch
IN/OUT Open drain Output disable VSS0 N-ch
Open drain Output disable VSS0
N-ch
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Figure 4-1. Types Circuits (2/2)
Type 12-D
VDD0 Data P-ch IN/OUT Output disable Input enable N-ch VSS0 P-ch Analog output voltage
N-ch
VSS0
Type Feedback cut-off P-ch
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
register that prevents software part internal memory from being used. using this register, memory µPD78F4225Y mapped same manner mask version with different internal memory (ROM RAM) capacity. This register using 8-bit memory manipulation instruction. RESET input sets FFH. Figure 5-1. Format Internal Memory Size Switching Register (IMS)
Address: 0FFFCH After reset: ROM1 ROM0 RAM1 RAM0
ROM1
ROM0
Internal capacity selection
RAM1
RAM0
Peripheral capacity selection 1,536 bytes 2,304 bytes 3,072 bytes 3,840 bytes
Caution
provided mask versions (µPD784224, 784225, 784224Y, 784225Y).
value memory µPD78F4225Y same manner mask version shown Table 5-1. Table 5-1. Setting Value Internal Memory Size Switching Register (IMS)
Mask Version Setting Value
µPD784224, 784224Y µPD784225, 784225Y
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
PROGRAMMING FLASH MEMORY
flash memory written with µPD78F4225Y mounted target board (on-board). connect dedicated flash programmer (Flashpro (Part No.: FL-PR3, PG-FR3)) host machine target system. Writing flash memory performed flash memory writing adapter connected Flashpro III. Remark FL-PR3 product Naito Densei Machida Mfg. Co., Ltd.
Selecting Communication Mode
write flash memory, Flashpro serial communication. Select serial communication mode from those listed Table format shown Figure 6-1. Each communication mode selected number pulses shown Table 6-1. Table 6-1. Communication Modes
Communication Mode 3-wire serial Number Channels Pins UsedNote SCK0/P27/SCL0Note SO0/P26 SI0/P25/SDA0Note SCK1/ASCK1/P22 SO1/TxD1/P21 SI1/RxD1/P20 SCK2/ASCK2/P72 SO2/TxD2/P71 SI2/RxD2/P70 3-wire serial (handshakeNote SCK0/P27/SCL0Note SO0/P26 SI0/P25/SDA0Note P24/BUZ TxD1/SO1/P21 RxD1/SI1/P20 TxD2/SO2/P71 RxD2/SI2/P70 Number Pulses
UART
Notes Shifting flash memory programming mode sets pins used flash memory programming same state immediately after reset. Therefore, external devices acknowledge port state immediately after reset, handling such connecting resistor connecting resistor required. µPD78F4225Y only Other than standards Caution sure select communication mode with number pulses shown Table 6-1.
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Figure 6-1. Communication Mode Selection Format
pulse Flash writing mode
RESET
Flash Memory Programming Function
flash memory written transferring receiving commands data selected communication mode. major functions flash memory programming listed Table 6-2. Table 6-2. Major Functions Flash Memory Programming
Function Area erasure Area blank check Data write Description Erases contents specified memory area. Checks erased status specified area. Writes flash memory based write start address number data written bytes). Compares contents specified memory area with input data.
Area verify
Connecting Flashpro
Flashpro µPD78F4225Y connected differently depending selected communication mode. Figures show connections respective communication modes. Figure 6-2. Connection Flashpro 3-Wire Serial Mode (When Using 3-Wire Serial
µPD78F4225Y
VDD0, VDD1, AVDD RESET SCK0 VSS0, VSS1, AVSS
Flashpro RESET
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Figure 6-3. Connection Flashpro 3-Wire Serial Mode (When Using Handshake)
PD78F4225Y
VDD0, VDD1, AVDD RESET SCK0 VSS0, VSS1, AVSS
Flashpro RESET HS/VPP2
Figure 6-4. Connection Flashpro UART Mode (When Using UART1)
µPD78F4225Y
VDD0, VDD1, AVDD RESET RxD1 TxD1 VSS0, VSS1, AVSS
Flashpro RESET
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings 25°C)
Parameter Supply voltage Symbol VDD0 VDD1 AVDD AVSS AVREF1 Input voltage Analog input voltage Output voltage Output current, Total pins Output current, high Total pins Operating ambient temperature Storage temperature During normal operation During flash memory programming Tstg during programming Analog input converter reference voltage input Conditions Ratings -0.3 +6.5 -0.3 +6.5 -0.3 +10.5 -0.3 VDD0 -0.3 VSS0 -0.3 VDD0 -0.3 VDD0 -0.3 +10.5 AVSS AVREF1 -0.3 +125 Unit
Caution
Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded.
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Operating Conditions Operating ambient temperature (TA): +85°C Power supply voltage clock cycle time: Figure Operating voltage during subsystem clock operation: Figure 7-1. Power Supply Voltage Clock Cycle Time (CPU Clock Frequency: fCPU)
10000
8000
Clock cycle time tCYK [ns]
Guaranteed operation range
Supply voltage
Capacitance 25°C, VDD1
Parameter Input capacitance Output capacitance capacitance Symbol Unmeasured pins returned Conditions MIN. TYP. MAX. Unit
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Main System Clock Oscillator Characteristics +85°C, VDD0 DD1)
Resonator Recommended Circuit Ceramic resonator crystal resonator Parameter Oscillation frequency (fX) Conditions MIN. TYP. MAX. 12.5 6.25 3.125 Unit
External clock
input frequency (fX)
12.5 6.25 3.125
input high-/lowlevel width (tWXH, tWXL)
PD74HCU04
input rise/fall time (tXR, tXF)
Cautions When using main system clock oscillator, wire follows area enclosed broken lines above figures avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential VSS. ground capacitor ground pattern through which high current flows. fetch signals from oscillator. When main system clock stopped device operating subsystem clock, wait until oscillation stabilization time been secured program before switching back main system clock. Remark resonator selection oscillator constant, customers required either evaluate oscillation themselves apply resonator manufacturer evaluation.
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Subsystem Clock Oscillator Characteristics +85°C, VDD0 DD1)
Resonator Recommended Circuit Crystal resonator Parameter Oscillation frequency (fXT) Conditions MIN. TYP. 32.768 MAX. Unit
Oscillation stabilization timeNote
External clock
input frequency (fXT) input high-/low-level width (tXTH, tXTL)
14.3
15.6
PD74HCU04
Note Time required stabilize oscillation after applying supply voltage (VDD). Cautions When using subsystem clock oscillator, wire follows area enclosed broken lines above figures avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential VSS. ground capacitor ground pattern through which high current flows. fetch signals from oscillator. When main system clock stopped device operating subsystem clock, wait until oscillation stabilization time been secured program before switching back main system clock. Remark resonator selection oscillator constant, customers required either evaluate oscillation themselves apply resonator manufacturer evaluation.
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Recommended Oscillator Constant Main system clock resonator +85°C)
Manufacturer Part Number Oscillation Frequency (MHz) Murata Mfg. Co., Ltd. CSTLS2M00G56-B0 CSTCC2.00MG0H6 CSTCR4M00G55-R0 CSTS0400MG06 CSTCC4.00MG0H6 CSTCR6M00G53-R0 CSTS0600MG03 CSTCC6.00MG CSTS0800MG03 CSTCC8.00MG CSTS1000MG03 CSTCC10.0MG CSA12.5MTZ CST12.5MTW CSTCV12.5MTJ0C4 Kyocera Corporation PBRC4.00HR PBRC4.00GR KBR-4.0MKC KBR-4.0MSB PBRC8.00HR PBRC8.00GR KBR-8.0MKC KBR-8.0MSB PBRC10.00BR-A PBRC12.50BR-A FCR4.0MC5 FCR6.0MC5 FCR8.0MC5 FCR10.0MC5 10.0 10.0 12.5 12.5 12.5 10.0 12.5 10.0 Recommended Circuit Constant (pf) On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip (pf) On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip On-chip Oscillation Voltage Range MIN. MAX. Oscillation Stabilization Time (MAX.) Tost (ms) 0.44 0.40 0.38 0.40 0.38 0.28 0.24 0.23 0.22 0.22 0.23 0.22 0.24 0.24 0.22 0.15 0.15 0.12 0.12
Caution
oscillator constant oscillation voltage range indicate conditions stable oscillation. Oscillation frequency precision guaranteed. applications requiring oscillation frequency precision, oscillation frequency must adjusted implementation circuit. details, please contact directly manufacturer resonator will use.
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Characteristics +85°C, VDD0 VDD1 AVDD VSS0 VSS1 AVSS (1/2)
Parameter supply voltage Input voltage, Symbol VPP1 VIL1 normal operation Note VIL2 P05, P20, P22, P33, P34, P70, P72, RESET VIL4 P17, P130, P131 VIL5 XT1, VIL6 P25, Input voltage, high VIH1 Note VIH2 P05, P20, P22, P33, P34, P70, P72, RESET VIH4 P17, P130, P131 VIH5 XT1, VIH6 P25, Output voltage, VOL1 pins other than P47, P57, mANote P47, mANote VOL2 Output voltage, high VOH1 µANote mANote Except XT1, XT1, VDD0 Except XT1, XT1, Conditions MIN. 0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD TYP. MAX. 0.2VDD 0.3VDD 0.2VDD 0.2VDD 0.15VDD 0.3VDD 0.2VDD 0.2VDD 0.1VDD 0.3VDD 0.2VDD Unit
-100 Input leakage current, ILIL1
µANote
ILIL2 Input leakage current, high ILIH1
ILIH2
Notes P21, P23, P24, P26, P32, P37, P47, P57, P67, P71, P87, P120 P127
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Characteristics +85°C, VDD0 VDD1 AVDD VSS0 VSS1 AVSS (2/2)
Parameter Output leakage current, Output leakage current, high Supply voltage ILOH1 VOUT 12.5 MHz, ±10% MHz, ±10% MHz, IDD2 HALT mode 12.5 MHz, ±10% MHz, ±10% MHz, IDD3 IDLE mode 12.5 MHz, ±10% MHz, ±10% MHz, IDD4 Operating modeNote kHz, ±10% kHz, ±10% kHz, kHz, IDD5 HALT modeNote kHz, ±10% kHz, ±10% kHz, kHz, IDD6 IDLE modeNote kHz, ±10% kHz, ±10% kHz, kHz, Data retention voltage Data retention current VDDDR IDDDR HALT, IDLE modes STOP mode ±10% ±10% Pull-up resistor Symbol ILOL1 VOUT Conditions MIN. TYP. MAX. Unit
IDD1
Operating mode
Note When main system clock stopped. Remark Unless otherwise specified, characteristics alternate-function pins same those port pins.
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Characteristics +85°C, VDD0 VDD1 AVDD VSS0 VSS1 AVSS Read/write operation (1/3)
Parameter Cycle time Symbol tCYK Conditions Address setup time ASTB) tSAST ±10% ±10% Address hold time (from ASTB) tHSTLA ±10% ±10% ASTB high-level width tWSTH ±10% ±10% Address hold time (from tHRA ±10% ±10% Delay time from address tDAR ±10% ±10% Address float time (from tFAR ±10% ±10% Data input time from address tDAID ±10% ±10% Data input time from ASTB tDSTID ±10% ±10% Data input time from tDRID ±10% ±10% MIN. (0.5 (0.5 (0.5 0.5T 0.5T 0.5T (0.5 (0.5 (0.5 0.5T 0.5T 0.5T (2.5 (2.5 (2.5 (1.5 (1.5 (1.5 TYP. MAX. Unit
Remark tCYK 1/fXX (fXX: Main system clock frequency) (during address wait), otherwise, Number wait states
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Characteristics +85°C, VDD0 VDD1 AVDD VSS0 VSS1 AVSS Read/write operation (2/3)
Parameter Delay time from ASTB Symbol tDSTR Conditions ±10% ±10% Data hold time (from tHRID ±10% ±10% Address active time from tDRA ±10% ±10% Delay time from ASTB tDRST ±10% ±10% low-level width tWRL ±10% ±10% Delay time from address tDAW ±10% ±10% Address hold time (from tHRD ±10% ±10% Delay time from ASTB data output tDSTOD ±10% ±10% Delay time from data output tDWOD ±10% ±10% Delay time from ASTB tDSTW ±10% ±10% Data setup time tSODWR ±10% ±10% 0.5T 0.5T 0.5T (1.5 (1.5 (1.5 MIN. 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T (1.5 (1.5 (1.5 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T TYP. MAX. Unit
Remark tCYK 1/fXX (fXX: Main system clock frequency) (during address wait), otherwise, Number wait states
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Characteristics +85°C, VDD0 VDD1 AVDD VSS0 VSS1 AVSS Read/write operation (3/3)
Parameter Data hold time (from Symbol tHWOD Conditions ±10% ±10% Delay time from ASTB tDWST ±10% ±10% low-level width tWWL ±10% ±10% Delay time from address tADEXD ±10% ±10% Delay time from ASTB tEXTAH ±10% ±10% Delay time from tEXRDS ±10% ±10% Delay time from tEXWDS ±10% ±10% Delay time from ASTB tEXADR ±10% ±10% MIN. 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T (1.5 (1.5 (1.5 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T TYP. MAX. Unit
Remark tCYK 1/fXX (fXX: Main system clock frequency) Number wait states
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Characteristics +85°C, VDD0 VDD1 AVDD VSS0 VSS1 AVSS External wait timing (1/2)
Parameter Input time from address WAIT Symbol tDAWT Conditions ±10% ±10% Input time from ASTB WAIT tDSTWT ±10% ±10% Hold time from ASTB WAIT tHSTWT ±10% ±10% Delay time from ASTB WAIT tDSTWTH ±10% ±10% Input time from WAIT tDRWTL ±10% ±10% Hold time from WAIT tHRWT ±10% ±10% Delay time from WAIT tDRWTH ±10% ±10% Data input time from WAIT tDWTID ±10% ±10% Delay time from WAIT tDWTR ±10% ±10% Delay time from WAIT tDWTW ±10% ±10% Input time from WAIT tDWWTL ±10% ±10% 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T (0.5 (0.5 (0.5 (1.5 (1.5 (1.5 MIN. TYP. MAX. 1.5T 1.5T 1.5T Unit
Remark tCYK 1/fXX (fXX: Main system clock frequency) (during address wait), otherwise, Number wait states
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
External wait timing (2/2)
Parameter Hold time from WAIT Symbol tHWWT Conditions ±10% ±10% Delay time from WAIT tDWWTH ±10% ±10% MIN. TYP. MAX. Unit
Remark tCYK 1/fXX (fXX: Main system clock frequency) Number wait states
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Serial Operation +85°C, VDD1 AVDD VSS0 VSS1 AVSS 3-wire serial mode (SCK: Internal clock output)
Parameter cycle time Symbol tKCY1 high-/low-level width tKH1, tKL1 setup time SCK) tSIK1 Conditions MIN. 1,280 2,560 4,000 1,180 1,900 hold time (from SCK) output delay time (from SCK) tKSI1 tKSO1 TYP. MAX. Unit
3-wire serial mode (SCK: External clock input)
Parameter cycle time Symbol tKCY2 high-/low-level width tKH2 tKL2 setup time SCK) tSIK2 Conditions MIN. 1,280 2,560 4,000 1,280 2,000 hold time (from SCK) output delay time (from SCK) tKSI2 tKSO2 TYP. MAX. Unit
UART mode
Parameter ASCK cycle time Symbol tKCY3 Conditions MIN. 1,667 ASCK high-/low-level width tKH3 tKL3 TYP. MAX. Unit
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
mode (µPD78F4225Y only)
Parameter Symbol MIN. SCL0 clock frequency free time (between stop start conditions) Hold timeNote1 Low-level width SCL0 clock High-level width SCL0 clock Setup time start/restart conditions Data hold When using time CBUS-compatible master When using Data setup time Rise time SDA0 SCL0 signals Fall time SDA0 SCL0 signals Setup time stop condition Pulse width spike restricted input filter Load capacitance each line fCLK tBUF Standard Mode MAX. High-Speed Mode MIN. MAX. Unit
tLOW
tHIGH
0Note
1,000
0Note 100Note 0.1CbNote 0.1CbNote
0.9Note
Notes start condition, first clock pulse generated after hold time. fill undefined area SCL0 falling edge, necessary device provide internal SDA0 signal VIHmin.) with least hold time. device does extend SCL0 signal low-level hold time LOW), only maximum data hold time needs satisfied. high-speed mode used standard mode system. this case, conditions described below must satisfied. device does extend SCL0 signal low-level hold time device extends SCL0 signal low-level hold time sure transmit data SDA0 line before SCL0 line released (tRmax. 1,000 1,250 standard mode specification) Total capacitance line (unit:
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Other Operations +85°C, VDD0 AVDD VSS0 VSS1 AVSS
Parameter high-/low-level width Interrupt input high-/ low-level width RESET high-/low-level width Symbol tWNIL tWNIH tWITL tWITH tWRSL tWRSH INTP0 INTP5 Conditions MIN. TYP. MAX. Unit
Clock Output Operation +85°C, VDD0 VDD1 AVDD VSS0 VSS1 AVSS
Parameter cycle time high-/low-level width rise/fall time Symbol tCYCL tCLL tCLH tCLR tCLF Conditions 0.5T MIN. TYP. MAX. 31,250 15,615 Unit
Remark tCYK 1/fXX (fXX: Main system clock frequency) Division ratio software When using main system clock: When using subsystem clock:
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Converter Characteristics +85°C, VDD0 VDD1 AVDD VSS0 VSS1 AVSS
Parameter Resolution Overall errorNote 6.25 12.5 MHz, AVDD VDD0 3.125 6.25 MHz, AVDD VDD0 3.125 MHz, AVDD VDD0 MHz, AVDD VDD0 Conversion time Sampling time Analog input voltage Reference voltage Resistance between AVDD AVSS tCONV tSAMP VIAN AVDD RAVREF0 conversion performed 24/fXX AVSS AVDD Symbol Conditions MIN. TYP. MAX. Unit
±1.2 %FSR ±1.2 %FSR ±1.6 %FSR ±1.6 %FSR
Note Excludes quantization error (±0.2%FSR). Remark FSR: Full-scale range Converter Characteristics +85°C, VDD0 VDD1 AVDD VSS0 VSS1 AVSS
Parameter Resolution Overall errorNote AVDD VDD0 AVREF1 AVDD AVDD VDD0 AVREF1 AVDD Settling time Load conditions: AVREF1 AVREF1 AVREF1 Output resistance Reference voltage AVREF1 current AVREF1 AIREF1 only channel DACS0, VDD0 Symbol Conditions MIN. TYP. MAX. Unit
±0.6 %FSR ±1.2 %FSR
Note Excludes quantization error (±0.2%FSR). Remark FSR: Full-scale range
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Flash Memory Programming Characteristics 40°C, AVDD AVSS 10.3 Basic characteristics
Parameter Operating frequency Symbol Oscillation frequencyNote Supply voltage VPPL VPPH Write time Operating temperature Storage temperature Programming temperature CWRT Tstg TPRG When detecting level When detecting high level When detecting high voltage Conditions MIN. 0.9VDD 20Note TYP. MAX. 12.5 6.25 3.125 12.5 6.25 0.2VDD 1.1VDD 10.3 Unit times
Notes When rewriting without using handshake mode Operation cannot guaranteed when number rewrites exceeds case standard products, operation cannot guaranteed when number rewrites exceeds Cautions writing successful initial write operation, execute program command again, then execute verify command confirm that write operation been completed normally standard). Handshake mode supported products other than those with standard. Remarks fifth letter from left number indicates standard product. After executing program command, execute verify command confirm that write operation been completed normally. Handshake mode write mode that uses P24. Handshake mode used with PGFR3 FL-PR3. standard only applies (engineering sample) products. Because these products engineering samples, their operation cannot guaranteed.
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Flash Memory Programming Characteristics 40°C, AVDD AVSS 10.3 Write erase characteristics
Parameter supply voltage supply current supply current Step erase time Overall erase time area Write-back time Number write-backs write-back command Symbol VPP2 Tera Conditions During flash memory programming When VPP2, 12.5 When VPP2 Note When step erase time sNote MIN. TYP. 10.0 MAX. 10.3 Unit s/area
Note When write-back time msNote
times/ writeback command
Number erase/ write-backs Step write time Overall write time word Number rewrites area
Cerwb
times
Twrw
Note When step write time word byte)Note erase write after erase rewriteNote
word
times/ area
Cerwr
Notes recommended setting value step erase time prewrite time before erasure erase verify time (write-back time) included. recommended setting value write-back time Write-back executed once issuance write-back command. Therefore, retry times must maximum value minus number commands issued. actual write time word longer. internal verify time during after write included. When product first written after shipment, "erase write" "write only" both taken rewrite. Example: Write, Erase Shipped product rewrites Shipped product rewrites Remarks range operating clock during flash memory programming same range during normal operation. When using PG-FP3, time parameters that need downloaded from parameter files write/erase automatically set. Unless otherwise directed, change values.
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Data Retention Characteristics +85°C, VDD0 VDD1 AVDD VSS0 VSS1 AVSS
Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR STOP mode VDDDR ±10% VDDDR rise time fall time hold time (from STOP mode setting) STOP release signal input time Oscillation stabilization wait time Input voltage, Input voltage, high tRVD tFVD tHVD Conditions MIN. TYP. MAX. Unit
tDREL
tWAIT
Crystal resonator Ceramic resonator RESET, P00/INTP0 P05/INTP5
0.9VDDDR 0.1VDDDR VDDDR
Timing Measurement Points
0.8VDD
Points measurement
0.8VDD
0.45
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Timing Waveform Read operation
(CLK) tCYK (output) tDAID tDSTID (I/O) Hi-Z Lower address (output) tSAST ASTB (output) tHSTLA tFAR tWSTH tDSTR tDAR (output) tDRWTL tDAWT WAIT (input) tADEXD tDSTWT tDSTWTH tHSTWT tEXADR tDRWTH tHRWT tDRID tWRL tDWTR tDWTID tDRST Hi-Z Data (input) tHRID
Higher address tHRA tDRA Hi-Z
Higher address
Lower address (output)
tEXTAH tEXRDS
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Write operation
(CLK) tCYK (output) tDAID tDSTOD (output) Hi-Z Lower address (output) tSAST ASTB (output) tHSTLA tFAR tWSTH tDSTW tDAW (output) tDWWTL tDAWT WAIT (input) tADEXD tDSTWT tDSTWTH tHSTWT tEXADR tDWWTH tHWWT tDWOD tWWL tDWTW tDWTID tDWST Hi-Z Data (output) tHWOD tSODWR
Higher address tHWA tDAW Hi-Z
Higher address
Lower address (output)
tEXTAH tEXWDS
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Serial Operation 3-wire serial mode
tKCY1, tKH1, tKL1, tKSO1, tKSI1, tSIK1, SI/SO
UART mode
tKCY3 tKH3 ASCK tKL3
mode (µPD78F4255Y only)
tLOW SCL0
tHIGH
SDA0 tBUF Stop condition Start condition Restart condition Stop condition
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Clock Output Timing
tCLH
tCLL
CLKOUT tCLR tCYCL tCLF
Interrupt Input Timing
tWNIH
tWNIL
tWITH
tWITL
INTP0 INTP5
Reset Input Timing
tWRSH
tWRSL
RESET
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Clock Timing
tWXH
tWXL
1/fX
tXTH
tXTL
1/fXT
Data Retention Characteristics
STOP mode setting
tHVD tFVD
VDDDR tRVD tDREL tWAIT
RESET
(Cleared falling edge)
(Cleared rising edge)
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
PACKAGE DRAWINGS
80-PIN PLASTIC (14x14)
detail lead
ITEM MILLIMETERS 17.20±0.20 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06 0.13 0.65 (T.P.) 1.60±0.20 0.80±0.20 0.17 +0.03 -0.07 0.10 1.40±0.10 0.125±0.075 1.70 MAX. P80GC-65-8BT-1
NOTE Each lead centerline located within 0.13 true position (T.P.) maximum material condition.
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
80-PIN PLASTIC TQFP (FINE PITCH) (12x12)
detail lead
NOTE
Each lead centerline located within 0.08 true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 14.0±0.2 12.0±0.2 12.0±0.2 14.0±0.2 1.25 1.25 0.22±0.05 0.08 (T.P.) 1.0±0.2 0.145±0.05 0.08 0.1±0.05 1.1±0.1 0.25 0.6±0.15 P80GK-50-9EU-1
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
RECOMMENDED SOLDERING CONDITIONS
µPD78F4225Y should soldered mounted under following recommended conditions. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact sales representative. Table 9-1. Soldering Conditions Surface Mount Type µPD78F4225GC-8BT: 80-pin plastic
µPD78F4225YGC-8BT: 80-pin plastic
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-107-2
Infrared reflow
Package peak temperature: 235°C, Time: seconds max. 210°C higher), Count: times less, Exposure limit: daysNote (after that, prebake 125°C hours) Package peak temperature: 215°C, Time: seconds max. 200°C higher), Count: times less, Exposure limit: daysNote (after that, prebake 125°C hours) Solder bath temperature: 260°C max., Time: seconds max., Count: Once, Preheating temperature: 120°C max. (package surface temperature) Exposure limit: daysNote (after that, prebake 125°C hours) temperature: 300°C max., Time: seconds max. (per row)
VP15-107-2
Wave soldering
WS60-107-1
Partial heating
Note After opening pack, store 25°C less less allowable storage period. Caution different soldering methods together (except partial heating). 80-pin plastic TQFP (fine pitch)
µPD78F4225GK-9EU:
µPD78F4225YGK-9EU: 80-pin plastic TQFP (fine pitch)
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-103-2
Infrared reflow
Package peak temperature: 235°C, Time: seconds max. 210°C higher), Count: times less, Exposure limit: daysNote (after that, prebake 125°C hours) Package peak temperature: 215°C, Time: seconds max. 200°C higher), Count: times less, Exposure limit: daysNote (after that, prebake 125°C hours) temperature: 300°C max., Time: seconds max. (per row)
VP15-103-2
Partial heating
Note After opening pack, store 25°C less less allowable storage period. Caution different soldering methods together (except partial heating).
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using µPD78F4225Y. Also Cautions Using Development Tools. Language Processing Software
RA78K4 CC78K4 DF784225 CC78K4-L Assembler package common 78K/IV Series compiler package common 78K/IV Series Device file common µPD784225, 784225Y Subseries compiler library source file common 78K/IV Series
Flash Memory Writing Tools
Flashpro (Part No.: FL-PR3, PG-FP3) FA-80GC FA-80GK Dedicated flash programmer microcontroller incorporating flash memory
Adapter writing 80-pin plastic (GC-8BT type) flash memory Adapter writing 80-pin plastic TQFP (GK-9EU type) flash memory
Debugging Tools When IE-78K4-NS in-circuit emulator used
IE-78K4-NS IE-70000-MC-PS-B IE-70000-98-IF-C In-circuit emulator common 78K/IV Series Power supply unit IE-78K4-NS Interface adapter used when PC-9800 series (except notebook type) used host machine supported) IE-70000-CD-IF-A IE-70000-PC-IF-C card cable when notebook used host machine (PCMCIA socket supported) Interface adapter when using PC/ATor compatible host machine (ISA supported) Interface adapter when using that incorporates host machine Emulation board emulate µPD784225, 784225Y Subseries Emulation probe 80-pin plastic (GC-8BT type) Emulation probe 80-pin plastic TQFP (GK-9EU type) Socket mounted target system board made 80-pin plastic (GC-8BT type) Conversion adapter connect NP-80GK target system board which 80pin plastic TQFP (GK-9EU type) mounted Integrated debugger IE-78K4-NS System simulator common 78K/IV Series Device file common µPD784225, 784225Y Subseries
IE-70000-PCI-IF-A IE-784225-NS-EM1 NP-80GC NP-80GK EV-9200GC-80 TGK-080-SDW
ID78K4-NS SM78K4 DF784225
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
When IE-784000-R in-circuit emulator used
IE-784000-R IE-70000-98-IF-C In-circuit emulator common 78K/IV Series Interface adapter used when PC-9800 series (except notebook type) used host machine supported) Interface adapter when using PC/AT compatible host machine (ISA supported) Interface adapter when using that incorporates host machine Interface adapter cable used when used host machine Emulation board emulate µPD784225, 784225Y Subseries Emulation board common 78K/IV Series Emulation probe conversion board necessary when using IE-784225-NS-EM1 IE784000-R Emulation probe 80-pin plastic (GC-8BT type) Emulation probe 80-pin plastic LQFP (GK-9EU type) Socket mounted target system board made 80-pin plastic (GC-8BT type) Conversion adapter connect EP-78054GK-R target system board which 80-pin plastic TQFP (GK-9EU type) mounted Integrated debugger IE-784000-R System simulator common 78K/IV Series Device file common µPD784225, 784225Y Subseries
IE-70000-PC-IF-C
IE-70000-PCI-IF-A IE-78000-R-SV3 IE-784225-NS-EM1 IE-784000-R-EM IE-78K4-R-EX2
EP-78230GC-R EP-78054GK-R EV-9200GC-80 TGK-080SDW
ID78K4 SM78K4 DF784225
Real-time
RX78K/IV MX78K4 Real-time 78K/IV Series 78K/IV Series
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Cautions Using Development Tools ID78K4-NS, ID78K4, SM78K4 used combination with DF784225. CC78K4 RX78K/IV used combination with RA78K4 DF784225. FL-PR3, FA-80GC, FA-80GK, NP-80GC, NP-80GK products made Naito Densei Machida Mfg. Co., Ltd. (TEL: +81-44-822-3813). TGK-080-SDW product made TOKYO ELETECH CORPORATION. further information, contact Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL: +81-3-3820-7112) Osaka Electronics Department (TEL: +81-6-6244-6672) third-party development tools, Single-Chip Microcontroller Development Tools Selection Guide (U11069E). host machine suitable each software follows:
Host Machine [OS] Software RA78K4 CC78K4 ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4
Note Note
PC-9800 series [Windows] PC/AT compatibles [Japanese/English Windows]
Note Note
HP9000 series 700[HP-UXTM] SPARCstation[SunOSTM, SolarisTM] NEWS(RISC) [NEWS-OSTM]
Note DOS-based software
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
APPENDIX RELATED DOCUMENTS
Documents Related Device
Document Name Document U12376E This document prepared U10905E
µPD784224, 784225, 784224Y, 784225Y Data Sheet µPD78F4225, 78F4225Y Data Sheet µPD784225, 784225Y Subseries User's Manual Hardware
78K/IV Series User's Manual Instruction
Documents Related Development Tools (User's Manuals)
Document Name RA78K4 Assembler Package Operation Language Structured Assembler Preprocessor CC78K4 Series Operation Language IE-78K4-NS IE-784000-R IE-784225-NS-EM1 EP-78230 EP-78054 SM78K4 System Simulator Windows Base SM78K Series System Simulator Reference External component user open interface specification ID78K4-NS Integrated Debugger based ID78K4 Integrated Debugger Windows based ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS based Reference Reference Reference U12796E U10440E U11960E Document U11334E U11162E U11743E U11572E U11571E U13356E U12903E U13742E EEU-1515 U13630E U10093E U10092E
Caution
related documents listed above subject change without notice. sure latest version each document designing.
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Documents Related Embedded Software (User's Manual)
Document Name 78K/IV Series Real-Time Fundamentals Installation Document U10603E U10604E
Other Documents
Document Name SEMICONDUCTOR SELECTION GUIDE Products Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability/Quality Control System Guide Prevent Damage Semiconductor Devices Electrostatic Discharge (ESD) Document X13769X C10535E C11531E C10983E C11892E
Caution
related documents listed above subject change without notice. sure latest version each document designing.
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829
J00.7
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
Caution
Purchase components conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
IEBus trademark Corporation. Windows either registered trademark trademark Microsoft Corporation United States and/or other countries. PC/AT trademark International Business Machines Corporation. HP9000 series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. Solaris SunOS trademarks Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation.
Data Sheet U12377EJ1V0DS
µPD78F4225, 78F4225Y
related documents indicated this publication include preliminary versions. However, preliminary versions marked such.
information this document current November, 2000. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

µPD78F4225, 78F4225Y 16/8-BIT SINGLE-CHIP MICROCONTROLLERS D

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