complete Acompatible single chip Transmitter Receiver Seamless operati
|
|
|
Top Searches for this datasheet
OC-3/STS-3 CLOCK RECOVERING TRANSCEIVER
complete Acompatible single chip Transmitter Receiver Seamless operation with PMC-Sierra PM5345, VLSI VNS67200, WAC-013-B/WAC-413-A µPD98402 Processors Supports clock data recovery from 51.84 Mbit/s 155.52 Mbit/s NRZI data stream 155.52MHz clock multiplication from 19.44MHz source 51.84MHz clock multiplication from 6.48MHz source Line Receiver Inputs: external buffering needed Differential output buffering Link Status Indication Loop-back testing 100K compatible Single volt power supply Replacement Cypress CY7B952 SY69952 complies with Bellcore, ITU/CCITT ANSI specifications Available 28-pin SOIC package
SY69952 FINAL
DESCRIPTION
Micrel-Synergy's SY69952 contains fully integrated transmitter receiver functions designed provide clock recovery generation either 51.84Mbit/s STS-1 155.52Mbit/s OC/STS-3 SONET/SDH (SY69952) Aapplications. On-chip clock generation performed low-jitter phase-locked loop (PLL) allowing 19.44MHz reference 155.52MHz generation 6.48MHz reference 51.84MHz generation. Clock recovery performed synchronizing on-chip directly incoming data stream. SY69952 meets jitter compliance criteria Bellcore, ITU/CCITT ANSI standards. jitter ensured Micrel-Synergy's advanced technology positive (PECL) I/O. Micrel-Synergy's circuit design techniques coupled with ASSETbipolar technology result ultra-fast performance with noise power dissipation.
FUNCTIONAL BLOCK DIAGRAM
PLL2+ PLL2-
CONFIGURATION
LOOP
MODE
ROUT+ ROUT-
ROUT+ ROUTRIN+ RINRCLK+ RCLKPLL RSER+ RSER-
VIEW SOIC
RCLKRCLK+ RSERRSER+ TCLKTCLK+ TSER+ TSERPLL2+ PLL2-
RIN+ RIN-
MODE LOOP REFCLKREFCLK+ TOUTTOUT+ PLL1+
RECEIVE TRANSMIT
TOUT+ TOUTPLL TSER+ TSERTCLK+ TCLK-
PLL1-
REFCLK+ REFCLK-
PLL1+ PLL1-
Rev.:
Amendment:
Issue Date: October, 1998
Micrel
SY69952
DESCRIPTIONS
INPUTS RIN± Differential PECL Input Receive Input. These built-in line receiver inputs connected differential Receive serial input data stream. internal Receive recovers embedded clock (RCLK±) data (RSER±) information. incoming data rate within frequency ranges depending state MODE pin. PECL/TTL Input Carrier Detect. This input controls recovery function Receive driven carrier detect output from optical modules from external transition detection circuitry. When this input HIGH, input data stream (RIN±) recovered normally Receive PLL. When this input LOW, Receive longer aligns RIN±, instead aligns with REFCLKx8 frequency. Also, Link Fault Indicator (LFI) will transition LOW, recovered data outputs (RSER) will remain regardless signal level Receive data stream inputs (RIN). When input (0.8V), internal transition detection circuitry disabled. TSER± Differential PECL Input Transmit Serial Data. These built-in line receiver inputs connected differential Transmit serial input data stream. These inputs receive very amplitude signals compatible with PECL signal levels. REFCLK± Differential PECL/TTL Input Reference Clock. This input clock frequency reference clock data recovery Receive PLL. REFCLK multiplied internally eight sets approximate center frequency internal Receive track incoming stream. This input also multiplied eight frequency multiplier Transmit produce rate Transmit Clock (TCLK±). REFCLK connected either differential PECL single-ended frequency source. When either REFCLK+ REFCLK- LOW, opposite REFCLK signal becomes level input. OUTPUTS ROUT± Differential PECL Output Receive Output. These Positive 100K outputs (+5V referenced) represent buffered version input data stream (RIN±). This output pair used Receiver input data equalization copper based systems, reducing system impact data dependent jitter. PECL outputs powered down connecting both outputs leaving them both unconnected. LOOP Input Loop Back Select. This input used select input data stream source that Receive used clock data recovery. When LOOP input HIGH, Receive input data stream (RIN±) used clock data recovery. When LOOP LOW, Transmit input data stream (TSER±) used Receive clock data recovery. RSER± Differential PECL Output Recovered Serial Data. These Positive 100K outputs (+5V referenced) represent recovered data from input data stream (RIN±). This recovered data aligned with recovered clock (RCLK±) with sampling window compatible with most data processing devices. RCLK± Differential PECL Output Recovered Clock. These Positive 100K outputs (+5V referenced) represent recovered clock from input data stream (RIN±). This recovered clock used sample recovered data (RSER±) timing compatible with most data processing devices. Output Link Fault Indicator. This input indicates status input data stream (RIN±). controlled three functions; Carrier Detect (CD) input, internal Transition Detector, Lock (OOL) detector. Transition Detector determines RIN± contains enough transitions accurately recovered Receive PLL. Lock detector determines RIN± within frequency range Receive PLL. When HIGH RIN± sufficient transitions within frequency range Receive PLL, input will high. RIN± does contain sufficient transitions RIN± outside frequency range Receive then output will LOW. then output will only transition when frequency RIN± outside range Receive PLL. TOUT± Differential PECL Output Transmit Output. These Positive 100K outputs (+5V referenced) represent buffered version Transmit data stream (TSER±). This Transmit path used take weak input signals rebuffer them drive impedance copper media. TCLK± Differential PECL Output Transmit Clock. These Positive 100K outputs (+5V referenced) provide rate frequency source external Transmit data processing devices. This output synthesized Transmit derived multiplying REFCLK frequency eight.
Micrel
SY69952
DESCRIPTIONS
MODE Level Input Frequency Mode Select. This three-level input selects frequency range clock data recovery receive frequency multiplier transmit PLL. When input held PECL HIGH (VCC -0.9 typ.), PLLs operate SONET (SDH) STS-3 (STM-1) line rate 155.52MHz. When this input held (connected GND), PLLs operate SONET STS-1 line rate 51.84MHz. REFCLK± frequency both operating modes operating frequency. When MODE input (VCC typ), device enters into test mode, TSER± inputs substitue internal factory testing. PLL1±, PLL2± Loop Filter Inputs These pins used connect external loop filters on-board PLLs. below:
VIEW
0.1µf
0.1µf
Transmit Filter
PLL1+ PLL1-
PLL2+ PLL2-
Receiver Filter
Figure Suggested Loop Filter Values
DESCRIPTION
General SY69952 Serial SONET/SDH Transceiver used SONET/SDH Aapplications recover clock data information from 155.52MHz 51.84MHz (Non Return Zero) NRZI (Non Return Zero Invert ones) serial data stream. This device also provides bitrate Transmit clock, from byte rate source through frequency multiplier PLL, differential data buffering Transmit side system. This device compliant with relevant SONET/SDH specifications including ANSI T1X1.6/91-022, ANSI T1X1.3/93-006R1 Draft ITU/CCITT G958. Operating Frequency SY69952 operates either frequency ranges. MODE input selects which frequency ranges Transmit frequency multiplier Receive clock data recovery will operate. When MODE connected VCC, highest operating range device selected. 19.44MHz source must drive REFCLK input PLLs will multiply this rate provide output clocks that operate 155.52MHz When MODE input connected ground (GND), lowest operating range device selected. 6.48MHz source must drive REFCLK inputs PLLs will multiply this rate provide output clocks that operate 51.84MHz Transmit Functions transmit section SY69952 contains that takes REFCLK input multiplies (REFCLKx8) produce PECL (Positive ECL) differential output clock (TCLK±). transmitter operating ranges that selectable with three-level MODE explained above. SY69952 Transmit frequency multiplier allows low-cost byte rate clock sources used time upstream serial data transmitter. REFCLK± input configured three ways. When both REFCLK+ REFCLK- connected differential 100K-compatible PECL source, REFCLK input will behave differential PECL input. When either REFCLK+ REFCLK- input LOW, other REFCLK input becomes TTL-level input allowing connected low-cost crystal oscillator. REFCLK input structure, therefore, used differential PECL input, single input, dual clock multiplexing input.
Micrel
SY69952
DESCRIPTION
Transmit PECL differential input pair (TSER±) buffered SY69952 yielding differential data outputs (TOUT±). These outputs used directly drive transmission media such Printed Circuit Board (PCB) traces, optical drivers, twisted pair, coaxial cable. Receive Functions primary function receiver recover clock (RCLK±) data (RSER±) from incoming differential PECL data stream (RIN±) without need external buffering. These built-in line receiver inputs, well TSER± inputs mentioned above, have wide commonmode range (2.5V) ability receive signals with little 50mV differential voltage. They compatible with PECL signals copper media. clock recovery function performed using embedded PLL. recovered clock only passed RCLK± outputs, also used internally sample input serial stream order recover data pattern. Receive uses REFCLK input byte-rate reference. This input multiplied (REFCLKx8) used improve lock time provide center frequency operation absence input data stream transitions. receiver recover clock data different frequency ranges depending state MODE explained earlier. insure accurate data clock recovery, REFCLKx8 must within 1000 transmit rate. standards, however, specify that REFCLKx8 frequency accuracy within 20-100 ppm. differential input serial data (RIN±) only used recover clock data, also buffered presented PECL differential output pair ROUT±. This output pair used part transmission line interface circuit base line wander compensation, improving system performance providing reduced input jitter increased data opening. Carrier Detect Link Fault Indicator Functions Link Fault Indicator (LFI) output TTL-level output that indicates status receiver. This output used external controller Loss Signal (LOS), Loss Frame (LOF), Frame (OOF) indications. controlled Carrier Detect input, internal Transitions Detector, Lock (OOL) circuitry. input driven external circuitry that monitoring incoming data stream. Optical modules have outputs that indicate presence light optical fiber some copper based systems external threshold detection circuitry monitor incoming data stream. input 100K PECL compatible signal that should held HIGH when incoming data stream valid. When pulled PECL (2.5V max.), output will transition Receiver will align itself
with REFCLKx8 frequency recovered data outputs (RSER) will remain regardless signal level Receive data-stream inputs (RIN). addition, SY69952 built-in transitions detector that also checks quality incoming data stream. absence data transitions caused broken transmission media, broken transmitter, problem with transmit receive media coupling. SY69952 will detect quiet link counting number times that have passed without data transition. time defined period RCLK±. When times have passed without data transition RIN±, will transition LOW. receiver will assume that serial data stream invalid and, instead allowing RCLK± frequency wander absence data, will lock REFCLKx8 frequency. This will insure that RCLK± close correct link operating frequency REFCLK accuracy. will driven HIGH again receiver will recover clock data from incoming data stream when transition detection circuitry determines that adequate transitions ensure reliable clock data recovery have been detected within bit-times. Transition Detector turned pulling input (0.8V). When pulled will only driven recovered clock locked incoming data stream. this will only indicate that Receiver Lock (OOL). should left unconnected. Loop Back Testing level LOOP used perform loop-back testing. When LOOP asserted (held LOW) Transmitter serial input (TSER±) used Receiver clock data recovery. This allows in-system testing performed entire device except differential Transmit drivers (TOUT±) differential Receiver inputs (RIN±). example, Acontroller present Acells input Acell processor check that these same cells received. When LOOP input deasserted (held HIGH) Receive once again connected Receiver serial inputs (RIN±). LOOP feature also used applications where clock data recovery performed from either data streams. these systems LOOP used select whether TSER± RIN± inputs used Receive clock data recovery. Loop back testing mode, regardless presence data input (RIN±), transmit serial data stream from (TSER±) will flow through Receive Recovered serial data output (RSER±).
Micrel
SY69952
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC, TVCC, AVCC IOUT Tstore Parameter Power Supply (GND, TGND, AGND Input Voltage (GND, TGND, AGND Output Current Ambient Temperature Range Storage Temperature Range Continuous Surge Rating +150 Unit
NOTE: Permanent device damage occur ABSOLUTE MAXIMUM RATINGS exceeded. This stress rating only functional operation implied conditions other than those detailed operational sections this data sheet. Exposure ABSOLUTE MAXIMUM RATING conditions extended periods affect device reliability.
PECL ELECTRICAL CHARACTERISTICS
TVCC AVCC 4.75V 5.25V; GND, TGND, AGND +85°C(1)
85°C Symbol Parameter Output HIGH Voltage Output Voltage Input HIGH Voltage(2) Input Voltage(2) Input Current Min. -1.075 -1.860 -1.165 -1.810 Typ. -.955 -1.705 Max. -.830 -1.570 -.880 -1.475 Unit
NOTES: Equilibrium temperature Forcing input time. Apply (max) (min) other inputs.
ELECTRICAL CHARACTERISTICS
TVCC AVCC 4.75V 5.25V; GND, TGND, AGND +85°C
Symbol Parameter Output HIGH Voltage Output Voltage Output Short Circuit Current Input HIGH Voltage Input Voltage Min. -150 Max. 0.45 Unit Condition -2mA VOUT
ELECTRICAL CHARACTERISTICS (2), ELECTRICAL CHARACTERISTICS(1),
±5%; +85°C
Symbol IOUT Parameter Internal Operating Current Termination Output Current Min. Typ. Max. Unit duty cycle Condition
NOTES: calculate total power supply current into pins: IOUT); where number output pins used (ie, terminated). calculate total device power dissipation; [IEE (VCC VEE)] IOUT 1.33](3). Average output voltage calculated VOAVG (VOH(max) VOH(min) VOL(max) VOL(min)) 1.33V.
Micrel
SY69952
ELECTRICAL CHARACTERISTICS
±5%; +85°C
Symbol fREF tODC tLOCK tRPWH tRPWL Parameter Reference Frequency Time(1) Output Duty Cycle(2) (TCLK±, RCLK±) Output Rise/Fall Tiime(2) Lock Time(2) REFCLK Pulse Width High REFCLK Pulse Width Data Valid Data Hold Propagation Delay(3) (RIN ROUT, TSER TOUT) Min. 6.41 19.24 19.5 6.50 Typ. 6.48 19.44 19.3 6.43 Max. 6.55 19.64 19.1 6.36 Units load, (20% 80%) transition density MODE MODE MODE MODE Prior RCLK+ rising edge After RCLK+ rising edge MODE MODE MODE MODE Condition
NOTES: calculated 1/(fREF Tested initially after design process changes that affect these parameters. switching threshold differential zero crossing (ie, point where signals cross).
TIMING WAVEFORMS
tODC RCLKP
tODC
RSERP/RSERN
TSERP/TSERN RINP/RINN
ROUTP/ROUTN
PRODUCT ORDERING CODE
Ordering Code SY69952ZC Package Type Z28-1 Operating Range Commercial
Micrel
SY69952
LEAD SOIC .300" WIDE (Z28-1)
Rev.
MICREL-SYNERGY
3250 SCOTT BOULEVARD SANTA CLARA 95054
(408) 980-9191
(408) 914-7878
http://www.micrel.com
This information believed accurate reliable, however responsibility assumed Micrel infringement patents other rights third parties resulting from use. license granted implication otherwise under patent patent right Micrel Inc. 2000 Micrel Incorporated
Other recent searches
WP4060VH - WP4060VH WP4060VH Datasheet
PI5V330 - PI5V330 PI5V330 Datasheet
PG-3000---THE - PG-3000---THE PG-3000---THE Datasheet
MC68HC908MR32 - MC68HC908MR32 MC68HC908MR32 Datasheet
DSP56007P - DSP56007P DSP56007P Datasheet
DSP56007ROM - DSP56007ROM DSP56007ROM Datasheet
BH8S - BH8S BH8S Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
