µPD78P048A 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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µPD78P048A 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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INTEGRATED CIRCUIT
µPD78P048A
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD78P048A product µPD78044F subseries within 78K/0 series, which internal µPD78042F, 78043F, 78044F, 78045F replaced with one-time PROM EPROM. µPD78P048A user-programmable, ideal evaluation system development, short-run multipledevice production, early start-up. Caution µPD78P048AKL-S does provide reliability intended mass production user systems. this model only experiments evaluation functions. Details functions described User's Manuals shown below. sure read design. µPD78044F subseries User's Manual: U10908E 78K/0 series User's Manual -Instruction: U12326E
FEATURES
compatible with mask products (except pin) Internal PROM: bytesNote µPD78P048AKL-S: Reprogrammable. (ideal system evaluation) µPD78P048AGF-3B9: Programmable only once (ideal limited production) Internal high-speed RAM: 1024 bytesNote Internal expansion RAM: 1024 bytesNote Buffer RAM: bytes FIPdisplay RAM: bytes Operable same supply voltage mask products: (except converter) converter supply voltage: AVDD Notes Internal PROM internal high-speed capacities changed memory size switching register (IMS). Internal expansion capacity changed internal expansion size switching register (IXS).
Remark difference between products mask products, refer DIFFERENCES BETWEEN µPD78P048A MASK PRODUCTS. this document, "PROM" used parts common one-time PROM products EPROM products.
information this document subject change without notice. Document U10611EJ2V0DS00 (2nd edition) Date Published June 1997 Printed Japan
mark
shows major revised points.
1995
µPD78P048A
ORDERING INFORMATION
Part Number Package 80-pin plastic 80-pin ceramic WQFN Internal One-time PROM EPROM Quality Grade Standard applicable
µPD78P048AGF-3B9 µPD78P048AKL-S
Please refer "Quality Grades Semiconductor Devices" (Document C11531E) published Corporation know specification quality grade devices recommended applications.
µPD78P048A
78K/0 SERIES PRODUCT DEVELOPMENT following shows 78K/0 Series products development. Subseries name shown inside frames.
Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
Products mass production Products under development subseries products compatible with bus. EMI-noise reduced version PD78078 timer added µPD78054 external interface enhanced ROM-less version µPD78078 Serial PD78078 enhanched function limited Serial PD78054 enhanced EMI-noise reduced EMI-noise reduced version PD78054 UART converter were added PD78014 enchanced converter µPD780024 enchanced Serial µPD78018F added EMI-noise reduced EMI-noise reduced version PD78018F Low-voltage (1.8 operation version µPD78014, with larger selection capacities converter 16-bit timer were added µPD78002 converter added µPD78002 Basic subseries control On-chip UART, capable operating voltage (1.8
µPD78075B µPD78075BY µPD78078 µPD78078Y PD78070A µPD78070AY µPD780018Note PD780018YNote PD780058 PD780058YNote PD78058F PD78058FY PD78054 PD78054Y PD780034 PD780034Y PD780024 µPD780024Y PD78014H µPD78018F PD78018FY µPD78014 PD78014Y µPD780001 µPD78002 µPD78002Y µPD78083
Inverter control
64-pin 64-pin 78K/0 Series
PD780964 PD780924
drive
converter µPD780924 enhanced On-chip inverter control circuit UART. EMI-noise reduced. PD78044F were enhanced, Display output total: PD78044H were enhanced, Display output total: N-ch open drain added µPD78044F, Display output total: Basic subseries driving FIP, Display output total:
100-pin 100-pin 80-pin 80-pin
µPD780208 PD780228 µPD78044H µPD78044F
drive
100-pin 100-pin 100-pin
PD780308 PD78064B µPD78064
µPD780308Y PD78064Y
µPD78064 enhanced ROM, capacity increased EMI-noise reduced version µPD78064 Basic subseries driving LCDs, On-chip UART
IEBussupported 80-pin 80-pin
PD78098B µPD78098
Meter control
EMI-noise reduced version µPD78098 IEBus controller added PD78054
80-pin 100-pin
PD780973 PD780805
General-purpose version PD780805 controller/driver driving automobile meters On-chip controller/driver automobile meters
64-pin
PD78P0914
On-chip output, digital code decoder, Hsync counter
Note Under planning
µPD78P048A
following lists main functional differences between subseries products.
Function Subseries Name Control Capacity K-40 K-60 K-60 (time division 3-wire: 1ch) (time division UART: 1ch) (UART: Timer 8-bit 16-bit Watch 8-bit 10-bit 8-bit Serial Interface (UART MIN. External Value Expansion
µPD78075B µPD78078 µPD78070A µPD780018 µPD780058 µPD78058F µPD78054 µPD780034 µPD780024 µPD78014H µPD78018F µPD78014 µPD780001 µPD78002 µPD78083
K-60
K-60 K-60 K-32
(UART: time division 3-wire:
K-60 K-32 K-16 K-32 Note K-60 K-60 K-48 K-40 K-60 (time division UART: 1ch) (UART (UART: (UART:
Inverter control drive
µPD780964 µPD780924 µPD780208 µPD780228 µPD78044H µPD78044F
drive
µPD780308 µPD78064B µPD78064
K-32 K-60 K-60 K-32 K-60
IEBus supported Meter control
µPD78098B µPD78098 µPD780973 µPD780805 µPD78P0914
(UART
(UART
Note 10-bit timer: channel
µPD78P048A
FUNCTION DESCRIPTION
Item PROM Internal memory High-speed Expansion Buffer display General-purpose register Minimum instruction execution time When main system clock selected When subsystem clock selected Instruction bytesNote Function
1024 bytesNote 1024 bytesNote bytes bytes bits registers bits registers banks) Instruction execution time variable function built µs/0.8 µs/1.6 µs/3.2 µs/6.4 (when operating MHz) (when operating 32.768 kHz) Multiplication/division bits bits, bits bits) manipulation (set, reset, test, boolean operation) Total CMOS input CMOS input/output N-ch open-drain input/output P-ch open-drain input/output P-ch open-drain output Display output total segments digits
ports (including dual-function pin)
controller/driver
converter
8-bit resolution Supply voltage: AVDD 3-wire serial I/O/SBI/2-wire serial mode selectable 3-wire serial mode (on-chip max. bytes automatic data transmit/receive function): 16-bit timer/event counter 8-bit timer/event counter Clock timer Watchdog timer 6-bit up/down counter channel channels channel channel channel
Serial interface
Timer
Timer output Clock output
(14-bit output capability 19.5 kHz, 39.1 kHz, 78.1 kHz, kHz, kHz, (When operating main system clock MHz) 32.768 (when operating subsystem clock 32.768 kHz) kHz, kHz, (when operating main system clock MHz) Internal: External: Internal: Internal: 80-pin plastic 80-pin ceramic WQFN
Buzzer output Vectored interrupt sources Test input Supply voltage Package Maskable Non-maskable Software
Notes Internal PROM/internal high-speed capacity changed memory size switching register (IMS). Internal expansion capacity changed internal expansion size switching register (IXS).
µPD78P048A
CONFIGURATION (Top View) Normal operating mode 80-pin plastic
µPD78P048AGF-3B9 80-pin ceramic WQFN µPD78P048AKL-S
P100/FIP10 P101/FIP11 P102/FIP12 P103/FIP13 P104/FIP14 P105/FIP15 P106/FIP16 P107/FIP17 P110/FIP18 P111/FIP19 P112/FIP20 P113/FIP21 P95/FIP7 P96/FIP8 P97/FIP9
P94/FIP6 P93/FIP5 P92/FIP4 P91/FIP3 P90/FIP2 P81/FIP1 P80/FIP0 P27/SCK0 P26/SO0/SB1 P25/SI0/SB0 P24/BUSY P23/STB P22/SCK1 P21/SO1 P20/SI1 RESET AVSS P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4
VLOAD
P114/FIP22 P115/FIP23 P116/FIP24 P117/FIP25 P120/FIP26 P121/FIP27 P122/FIP28 P123/FIP29 P124/FIP30 P125/FIP31 P126/FIP32 P127/FIP33 P00/INTP0/TI0 P01/INTP1 P02/INTP2 P03/INTP3/CI0 P30/TO0 P31/TO1 P32/TO2
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
P04/XT1
AVREF
AVDD
P36/BUZ
P35/PCL
P34/TI2
Cautions Connect directly VSS. Connect AVDD VDD. Connect AVSS VSS.
P33/TI1
µPD78P048A
P80, P100 P107 P110 P117 P120 INTP0 INTP3 SB0, SI0, SO0, Port Port Port Port Port Port Port Port Port Port Interrupt from Peripherals Timer Input Timer Output Clock Input Serial Serial Input Serial Output SCK0, SCK2 BUSY FIP0 FIP33 VLOAD XT1, RESET ANI0 ANI7 AVDD AVSS AVREF Serial Clock Programmable Clock Buzzer Clock Strobe Busy Fluorescent Indicator Panel Negative Power Supply Crystal (Main System Clock) Crystal (Subsystem Clock) Reset Analog Input Analog Power Supply Analog Ground Analog Reference Voltage Power Supply Programming Power Supply Ground
µPD78P048A
PROM programming mode 80-pin plastic
µPD78P048AGF-3B9 80-pin ceramic WQFN µPD78P048AKL-S
RESET
Open
Open
Cautions
Individually connect pull-down resistor. Connect ground.
RESET level. Open connection. Address Data Chip Enable Output Enable Program RESET: Reset Power Supply Programming Power Supply Ground
µPD78P048A
BLOCK DIAGRAM
TO0/P30 TI0/INTP0/P00
16-bit TIMER/ EVENT COUNTER
PORT0
P01-P03 P10-P17
TO1/P31 TI1/P33
8-bit TIMER/ EVENT COUNTER1
PORT1
PORT2 TO2/P32 TI2/P34 8-bit TIMER/ EVENT COUNTER2 PORT3 WATCHDOG TIMER PORT7 WATCH TIMER 78K/0 CORE PROM PORT8 CI0/INTP3/P03 6-bit UP/DOWN COUNTER PORT9 SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 ANI0/P10ANI7/P17 AVDD AVSS AVREF INTP0/TI0/P00INTP3/CI0/P03 SERIAL INTERFACE0 PORT10
P20-P27
P30-P37
P70-P74
P80,
P90-P97
P100-P107
SERIAL INTERFACE1
PORT11
P110-P117
PORT12
P120-P127
CONVERTER CONTROLLER/ DRIVER FIP0-FIP33 VLOAD
INTERRUPT CONTROL
BUZ/P36
BUZZER OUTPUT SYSTEM CONTROL
RESET XT1/P04
PCL/P35
CLOCK OUTPUT CONTROL
µPD78P048A
CONTENTS
DIFFERENCES BETWEEN µPD78P048A MASK PRODUCTS FUNCTION
Pins Normal Operating Mode Pins PROM Programming Mode Input/Output Circuits Recommended Connection Unused Pins
MEMORY SIZE SWITCHING REGISTER (IMS) INTERNAL EXPANSION SIZE SWITCHING REGISTER (IXS) PROM PROGRAMMING
Operating Modes PROM Write Procedure PROM Read Procedure
ERASURE METHOD (µPD78P048AKL-S ONLY) ERASURE WINDOW SEAL (µPD78P048AKL-S ONLY) ONE-TIME PROM PRODUCTS SCREENING ELECTRICAL SPECIFICATIONS CHARACTERISTIC CURVE (REFERENCE VALUE) PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
µPD78P048A
DIFFERENCES BETWEEN µPD78P048A MASK PRODUCTS
µPD78P048A single-chip microcontroller with on-chip one-time writable PROM with on-chip EPROM which program write, erasure rewrite capability. possible make functions except PROM specification, mask option, same those mask products setting memory size switching register (IMS) internal expansion size switching register (IXS). Differences between µPD78P048A mask products (µPD78042F, 78043F, 78044F, 78045F) shown Table 1-1. Table 1-1. Differences between µPD78P048A Mask Products
Item Internal structure Internal capacity
µPD78P048A
One-time PROM/EPROM bytes
Mask Products Mask
µPD78042F: µPD78043F: µPD78044F: µPD78045F: µPD78042F: µPD78043F: µPD78044F: µPD78045F:
available
bytes bytes bytes bytes bytes bytes 1024 bytes 1024 bytes
Internal high-speed capacity
1024K bytes
Changes internal internal high-speed capacities memory size switching register (IMS) Change internal expansion capacity internal expansion size switching register (IXS)
AvailableNotes
AvailableNotes
available
Mask option with internal pull-down resistor pins P30-P37, P106, P107, P110-P117, P120-P127. Mask option with internal pull-up resistor pins P70-P74. Electrical characteristics
Refer Data Sheet each product.
Notes internal PROM becomes bytes internal high-speed becomes 1024 bytes RESET input. internal expansion becomes 1024 bytes RESET input. Caution Noise resistance noise radiation different PROM version mask versions. using mask version instead PROM version processes between prototype development full production, sure fully evaluate mask version (not ES).
µPD78P048A
FUNCTION
Pins Normal Operating Mode Port pins (1/2)
Name P04Note Input Input/output Input/Output Input Input/output Port 5-bit input/ output port Function Input only Input Input/Output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software. Input only Port 8-bit input/output port Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software.Note Port 8-bit input/output port Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software. Reset Input Dual-Function INTP0/TI0 INTP1 Input INTP2 INTP3/CI0 Input
Input
ANI0 ANI7
Input/output
Input
SCK1 BUSY SI0/SB0 SO0/SB1 SCK0
Input/output
Port 8-bit input/output port Input/output specifiable bit-wise. Direct drive capability. When used input port, possible on-chip pull-up resistor software.
Input
Notes When P04/XT1 pins used input ports, processor clock control register (PCC) (FRC) should (the subsystem clock oscillator incorporated feedback resistor should used). When P10/ANI0 P17/ANI7 pins used converter analog input, port should input mode. on-chip pull-up resistor automatically used.
µPD78P048A
Port pins (2/2)
Name Input/Output Input/output Function Port N-ch open-drain 5-bit input/output port. Direct drive capability. Input/output specifiable bit-wise. Port P-ch open-drain 2-bit high-voltage output port. Direct drive capability. Pull-down resistor (connected VLOAD) chip. Port P-ch open-drain 8-bit high-voltage output port. Direct drive capability. Pull-down resistor (connected VLOAD) chip. Port P-ch open-drain 8-bit high-voltage output port. Direct drive capability. Pull-down resistor (connected VLOAD) chip P100 P105. Port P-ch open-drain 8-bit high-voltage output port. Input/output specifiable bit-wise. Port P-ch open-drain 8-bit high-voltage output port. Direct drive capability. Input/output specifiable bit-wise. Reset Input Dual-Function
P80,
Output
Output
FIP0, FIP1
Output
Output
FIP2 FIP9
P100 P107
Output
Output
FIP10 FIP17
P110 P117
Input/output
Input
FIP18 FIP25
P120 P127
Input/output
Input
FIP26 FIP33
µPD78P048A
Non-port pins (1/2)
Name INTP0 INTP1 INTP2 INTP3 SCK0 SCK1 BUSY Input Output Output Output Input Input Serial interface automatic transmit/receive strobe output Serial interface automatic transmit/receive busy input External count clock input 16-bit timer (TM0) External count clock input 8-bit timer (TM1) External count clock input 8-bit timer (TM2) 16-bit timer (TM0) output (shared with 14-bit output) 8-bit timer (TM1) output 8-bit timer (TM2) output Clock input 6-bit up/down counter Clock output (for main system clock, subsystem clock trimming) Buzzer output controller/driver digit output high-voltage highcurrent output controller/driver digit/segment output highvoltage high-current output controller/driver segment output high-voltage output Input Input Iutput Input Input Input Input/output Serial clock input/output serial interface Input Input/output Serial data input/output serial interface Input Output Serial data output serial interface Input Input Falling edge detection external interrupt request input Serial data input serial interface Input Input Input/Output Input Function Specifiable valid edges (rising edge, falling edge, both rising falling edges). External interrupt request input Reset Input Dual-Function P00/TI0 P03/CI0 P25/SB0 P26/SB1 P25/SI0 P26/SO0 P00/INTP0 P03/INTP3
FIP0, FIP1 FIP2 FIP9 FIP10 FIP15
Output Output
Input Output
P80,
Output
Output
P100 P105
FIP16, FIP17 FIP18 FIP25 FIP26 FIP33 VLOAD ANI0 ANI7 AVREF AVSS AVDD
Output
Output Input
P106, P107 P110 P117 P120 P127
Input Input
controller/driver pull-down resistor connection converter analog input converter reference voltage input converter ground potential. Connected converter analog power supply. Connected
Input
µPD78P048A
Non-port pins (2/2)
Name RESET Input/Output Input Input Input Positive power supply Directly connected Ground potential Subsystem clock oscillation crystal connection System reset input Main system clock oscillation crystal connection Function Reset Input Dual-Function
Pins PROM Programming Mode
Name RESET Input/Output Input Function PROM programming mode setting When +12.5 applied level signal applied RESET pin, this chip PROM programming mode. PROM programming mode setting high-voltage applied during program write/ verification Address Data PROM enable input/program pulse input Read strobe input PROM Program/program inhibit input PROM programing mode. Positive power supply Ground potential
Input
Input Input/output Input Input Input
µPD78P048A
Input/Output Circuits Recommended Connection Unused Pins Types input/output circuits pins recommeded connection unused pins shown Table 2-1. configuration each type input/output circuit, refer Figure 2-1. Table 2-1. Type Input/Output Circuit Each
Name Input/Output Circuit Type Input/Output Recommended Connecting Method when Unused Connect VSS. Individually connect resistor
P00/TI0/INTP0 P01/INTP1 P02/INTP2 P03/INTP3/CI0 P04/XT1 P10A/ANI0 P17/AN7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P80/FIP0, P81/FIP1 P90/FIP2 P97/FIP9 P100/FIP10 P105/FIP15 P106/FIP16, P107/FIP17 P110/FIP18 P117/FIP25 P120/FIP26 P127/FIP33 RESET AVREF AVDD AVSS VLOAD
Input Input/output
Input Input/output
Connect VSS. Individually connect resistor
10-A
13-D Output Leave open.
14-B 15-B Input/output Individually connect resistor
Input Leave open Connect Connect Connect
Directly connect
µPD78P048A
Figure 2-1. List Input/Output Circuits (1/2)
Type
Type 10-A
pull-up enable data P-ch
P-ch
IN/OUT Schmitt-triggered input with hysteresis characteristics open drain output disable N-ch
Type
Type pull-up enable data P-ch
P-ch
pull-up enable data P-ch
P-ch
IN/OUT IN/OUT output disable Comparator N-ch P-ch N-ch VREF (Threshold voltage)
output disable input enable Type
N-ch
input enable Type 13-D IN/OUT
pull-up enable data P-ch
P-ch
data output disable IN/OUT
N-ch
output disable
N-ch
P-ch
Middle-high voltage input buffer
µPD78P048A
Figure 2-1. List Input/Output Circuits (2/2)
Type
Type 15-B
data
P-ch
P-ch IN/OUT
P-ch data N-ch
P-ch N-ch
LOAD
N-ch
Type 14-B
Type feed back cut-off P-ch P-ch P-ch N-ch
data
µPD78P048A
MEMORY SIZE SWITCHING REGISTER (IMS)
This register disable part internal memories software. setting this memory size switching register (IMS), possible same memory mapping that mask product having different internal memories. 8-bit memory manipulation instruction. will result RESET input. Figure 3-1. Memory Size Switching Register Format
Symbol Address FFF0H Reset
RAM2 RAM1 RAM0
ROM3 ROM2 ROM1 ROM0
ROM3 ROM2 ROM1 ROM0
Selection Internal Capacity bytes bytes bytes bytes bytes Setting prohibited
Other than above
RAM2 RAM1 RAM0
Selection Internal High-Speed Capacity bytes 1024 bytes Setting prohibited
Other than above
Table shows setting values which makes memory mapping same that various mask model. Table 3-1. Memory Size Switching Register Setting Values
Target Mask Product Setting Value
µPD78042F µPD78043F µPD78044F µPD78045F
µPD78P048A
INTERNAL EXPANSION SIZE SWITCHING REGISTER (IXS)
using this register, internal expansion µPD78P048A mapped same manner mask model. 8-bit memory manipulation instruction. contents this register RESET. Figure 4-1. Format Internal Expansion Size Switching Register
Symbol Address FFF4H reset
IXRAM3 IXRAM2 IXRAM1 IXRAM0
Selects internal expansion IXRAM3 IXRAM2 IXRAM1 IXRAM0 capacity 1024 bytes internal expansion Setting prohibited
Other than above
Table shows value settings internal expansion µPD78P048A same manner respective mask models. Table 4-1. Memory Size Switching Register Setting Values
Mask Model Value Setting
µPD78042F µPD78043F µPD78044F µPD78045F
µPD78P048A
PROM PROGRAMMING
µPD78P048A on-chip 60K-byte PROM program memory. programming, PROM programming mode RESET pins. connecting unused pins, refer CONFIGURATION PROM programming mode. Caution Program writing should performed address range 0000H EFFFH (the last address, EFFFH, should specified). Writing cannot performed with PROM programmer that cannot specify write addresses. Operating Modes When +12.5 applied level signal applied RESET pin, PROM programming mode set. This mode will become operating mode shown Table when pins shown. Further, when read mode set, possible read contents PROM. Table 5-1. Operating Modes PROM Programming
Operating Mode Page data latch Page write Byte write Program verify Program inhibit +12.5 +6.5 Read Output disable Standby Data output High-impedance High-impedance Data input High-impedance Data input Data output High-impedance RESET
µPD78P048A
Read mode Read mode set. Output disable mode Data output becomes high-impedance, output disable mode, set. Therefore, allows data read from device controlling pin, multiple µPD78P048As connected data bus. Standby mode Standby mode set. this mode, data outputs become high-impedance irrespective status. Page data latch mode Page data latch mode beginning page write mode. this mode, page 4-byte data latched internal address/data latch circuit. Page write mode After page bytes addresses data latched page data latch mode, page write executed applying program pulse (active low) with Then, program verification performed, set. programming performed one-time program pulse, write verification operations should executed repeatedly. Byte write mode Byte write executed when program pulse (active low) applied with Then, program verification performed set. programming performed one-time program pulse, write verification operations should executed repeatedly. Program verify mode Program verify mode set. this mode, check write operation performed correctly, after write. Program inhibit mode Program inhibit mode used when pin, pins multiple µPD78P048As connected parallel write performed those devices. When write operation performed, page write mode byte write mode described above used. this time, write performed device which driven high.
µPD78P048A
PROM Write Procedure Figure 5-1. Page Program Mode Flow Chart
Start Address 12.5
Latch Address address Latch Address address Latch Address address Address address Latch
X=X+1 program pulse
Verify bytes Pass Address Pass
Fail
Verify bytes Pass Write
Fail
Faulty product
Start address Program last address
µPD78P048A
Figure 5-2. Page Program Mode Timing
Page Data Latch
Page Program
Program Verify
Data Input Data Output
µPD78P048A
Figure 5-3. Byte Program Mode Flow Chart
Start Address 12.5
X=X+1 program pulse Address address Fail Verify Pass Address Pass Fail
Verify bytes Pass Write
Faulty product
Start address Program last address
µPD78P048A
Figure 5-4. Byte Program Mode Timing
Program
Program Verify
Data Input
Data Output
Cautions should applied before after VPP. must exceed +13.5 including overshoot. Reliability adversely affected removal/reinsertion performed while +12.5 being applied VPP.
µPD78P048A
PROM Read Procedure contents PROM readable external data according read procedure shown below. RESET level, supply pin, connect other unused pins shown CONFIGURATION PROM programming mode. Supply pins. Input address read data into pins. Read mode Output data pins. timings above steps shown Figure 5-5.
Figure 5-5. PROM Read Timings
Address Input
(Input)
(Input)
Hi-Z
Data Output
Hi-Z
µPD78P048A
ERASURE METHOD (µPD78P048AKL-S ONLY)
µPD78P048AKL-S capable erasing (FFH) contents data written program memory rewriting. When erasing contents data, irradiate light having wavelength less than about erasing window. Normally, irradiate ultraviolet rays wavelength. Volume irradiation required completely erase contents data follows: intensity erasing time: more Erasing time: minutes (MIN.) (When lamp 12,000 µW/cm2 used. However, longer time needed because deterioration performance lamp, contamination erasing window, etc.) When erasing contents data, lamp within from erasing window. Further, filter provided lamp, irradiate ultraviolet rays after removing filter.
ERASURE WINDOW SEAL (µPD78P048AKL-S ONLY)
protect from miserasure rays other than that lamp erasing EPROM contents, protect internal circuit other than EPROM from misoperating rays, stick protection seal erasure window when EPROM contents erasure performed.
ONE-TIME PROM PRODUCTS SCREENING
one-time PROM product (µPD78P048AGF-3B9) tested completely before shipped, because structure. recommended perform screening verify PROM after writing necessary data performing high-temperature storage under condition below.
Storage Temperature
Storage Time hours
µPD78P048A
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Symbol VLOAD AVDD AVREF AVSS Input voltage P04, P17, P27, P37, XT2, RESET P70-P74 P110 P117, P120 P127 N-ch open drain P-ch open drain Conditions Rating -0.3 +7.0 +0.3 -0.3 13.5 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 Unit
Output voltage Analog input voltage High-level output current
-0.3 +0.3 -0.3 +0.3 -0.3 +0.3 AVSS -0.3 AVREF0 +0.3 -120 +150
P03, P17, P27, P80, P81, P97, P100 P107, P110 P117, P120 P127 ANI0 ANI7 Analog input pins
P03, P17, P27, Total P03, P17, P27,
P80, P81, P97, P100 P107, P110 P117, P120 P127 Total P80, P81, P97, P100 P107, P110 P117, P120 P127
Low-level output current
Note
P03, P17, P27, P37, Total P03, P17, P27, Total P56, P57,
Peak value Peak value Peak value
Total
Peak value
Total power dissipation Operating ambient temperature Storage temperature
Note
Tstg
Caution Product quality suffer absolute maximum rating exceeded even single parameter, even momentarily. other words, absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions which ensure that absolute maximum ratings exceeded. Remark Unless specified otherwise, dual-function characteristics same port characteristics. Notes should calculated follows: [rms value] [Peak value] Duty
µPD78P048A
Notes Total power dissipation differs depending temperature (refer following figure).
Total power dissipation [mW]
Temperature [°C]
calculate total power dissipation following three power dissipation available µPD78P048A. three power dissipation should less than total power dissipation less ratings recommended). power dissipation: calculate (MAX.) (MAX.). Output power dissipation: Power dissipation when maximum current flows into display output pin. Pull-down resistor power dissipation: Power dissipation pull-down resistor incorporated display output mask option. following calculate total power dissipation example Figure 9-1. Example Assume following conditions: oscillator Supply current (IDD) 21.6 Display output: grids segments (Cut width 1/16) Maximum current grid Maximum current segment scan timing, display output OFF. Display output voltage: grid (voltage drop segments (voltage drop Fluorescent display control voltage (VLOAD) Mask option pull-down resistor placing above conditions calculation <3>, total dissipation worked out. power dissipation: 21.6 118.8
µPD78P048A
Output power dissipation: Digit width width) number grids Grids 25.8 Grids Total segment current value illuminated dots Segment (VDD VOD) number grids Dots Grids Grid Pull-down resistor power dissipation: number grids (VOD VLOAD)2 Digit width Pull-down resistor value number grids Grids (5.5 (-30 V))2 38.6 Grids (VOD VLOAD)2 Pull-down resistor value (5.5 (-30 V))2 number illuminated dots (VDD VOD) Total current value each grid
Grid
Segment
number grids dots 127.3 Grids
Total power dissipation 118.8 25.8 38.6 127.3 313.6 this example, total power dissipation exceed rating total power dissipation shown figure above, there problem power dissipation. However, when total power dissipation exceeds rating total power dissipation, necessary lower power dissipation. reduce power dissipation, reduce number pull-down resistor.
Figure 9-1. Display Example Segments-11 Digits
Display Data Memory
FA7AH FA79H FA6AH FA69H FA78H FA77H FA76H FA68H FA67H FA66H FA75H FA74H FA73H FA65H FA64H FA63H FA72H FA71H FA70H FA62H FA61H FA60H
µPD78P048A
µPD78P048A
Main System Clock Oscillation Circuit Characteristics
Resonator Ceramic resonator Recommended Circuit
Parameter Oscillator frequency (fX)Note Oscillator stabilization timeNote Oscillator frequency (fX)Note Oscillator stabilization timeNote input frequency (fX)Note input high-/low-level width (tXH/tXL)
Conditions
MIN. TYP. MAX. Unit
Crystal resonator
4.19
External clock
PD74HCU04
Notes Only oscillator characteristics shown. Refer characteristics instruction execution times. This time required oscillation stabilize after addition VDD, STOP mode release. Cautions When main system clock oscillator used, following should noted concerning wiring area figure enclosed broken line prevent influence wiring capacitance, etc. wiring should kept short possible. other signal lines should crossed. Keep away from lines carrying high fluctuating current. oscillator capacitor grounding point should always same potential VSS. connect ground pattern carrying high current. signal should taken from oscillator. When main system clock stopped device operating subsystem clock, wait until oscillation stabilization time been secured program before switching back main system clock.
µPD78P048A
Subsystem Clock Osillator Characteristics
Resonator Crystal resonator
Recommended Circuit
Parameter Oscillator frequency (fXT)Note1 Oscillator stabilization timeNote2 input frequency (fXT)Note1 input high-/low-level width (tXTH/tXTL)
Conditions
MIN. TYP. MAX. Unit 32.768
External clock
Notes Only oscillator characteristics shown. Refer characteristics instruction execution times. This time required oscillation stabilize after power (VDD) turned Cautions When subsystem clock oscillator used, following should noted concerning wiring area figure enclosed broken line prevent influence wiring capacitance, etc. wiring should kept short possible. other signal lines should crossed. Keep away from lines carrying high fluctuating current. oscillator capacitor grounding point should always same potential VSS. connect ground pattern carrying high current. signal should taken from oscillator. subsystem clock oscillator low-amplitude circuit order achieve consumption current, more prone misoperation noise than main system clock oscillator. Particular care therefore required with wiring method when subsystem clock used.
µPD78P048A
Recommended Oscillator Constant Main system clock: ceramic resonator
Manufacturer Product Name Frequency (MHz) Murata Mfg. Co., Ltd. CSB1000J CSA2.00MG CST2.00MG Matsushita Electronics Components Co., Lltd. EFOGC2004A4 EFOEC3004A4 EFOEC4004A4 EFOEC4194A4 EFOGC5004A4 Corp. FCR2.0MC3 FCR4.0MC5 OCR4.0MC3Note CCR5.0MC5Note 1.00 2.00 2.00 3.00 5.00 3.00 5.00 2.00 3.00 4.00 4.19 5.00 2.00 4.00 4.00 5.00 Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Circuit Constant Oscillator Voltage Range Remark
(pF) (pF) MIN. MAX. Built-in capacitor
Note Surface-mount type Remark indicates frequencies. Subsystem clock: crystal resonator
Manufacturer Product Name Frequency (kHz) Kyocera Corp. KF-38GNote (Load capacitance 32.768 Circuit Constant Oscillator Voltage Range
(pF) (pF) MIN. MAX.
Note Maintained product. Caution oscillation circuit constants oscillation voltage range indicate conditions stable oscillation. However, they guarantee accuracy oscillation frequency. application circuit requires accuracy oscillation frequency, necessary oscillation frequency application circuit. this, necessary directly contact manufacturer resonator that being used.
µPD78P048A
Capacitance
Parameter Input capacitance Output capacitance Input/output capacitance Symbol COUT Conditions Unmeasured pins returned Unmeasured pins returned MIN. TYP. MAX. Unit
Unmeasured pins returned
P03, P17, P27, P110 P117, P120 P127
Remark Unless otherwise specified, characteristics shared same characteristics port pin. Operating power supply voltage
Parameter CPUNote Display controller mode 16-bit time/event counter (TM0) converter Other hardware Conditions MIN. 2.7Note TYP. MAX. Unit
Notes Except system clock oscillator, display controller/driver, PWM. Operating power supply voltage differs depending cycle time. Refer Characteristics.
µPD78P048A
Characteristics
Parameter High-level input voltage Symbol VIH1 VIH2 VIH3 VIH4 VIH5 P21, P03, P20, P22, P27, P33, P34, RESET XT1/P04, N-ch open-drain Conditions MIN. VIH6 P17, P32, VIH7 P110 P117, P120 P127 0.65 Low-level input voltage VIL1 VIL2 VIL3 P21, P03, P20, P22, P27, P33, P34, RESET VIL4 VIL5 XT1/P04, VIL6 VIL7 High-level output voltage P17, P32, P110 P117, P120 P127 P03, P17, P27, P37, P80, P81, P97, P100 P107, P110 -100 P117, P120 P127 P37, P03, P17, VOL2 SB0, SB1, SCK0 With open-drain pull-up TYP. MAX. Unit
Low-level output voltage
VOL1
VOL3 High-level input leakage current ILIH1
P03, P17, P27, P37, P03, P17, P27, P37, RESET XT1/P04, P110 P117, P120 P127
ILIH2 ILIH3 ILIH4
3Note 3Note
Notes P110 P117 P120 P127, high-level input leak current (MAX.) flows only during clocks after instruction been executed read ports (P11, port mode registers (PM11, 12). Outside period clocks following executing read-out instruction, current (MAX.). P110 P117 P120 P127, high-level input leak current (MAX.) flows only during clocks after instruction been executed read P11, P12, PM11, PM12. Outside period clocks following executing read-out instruction, current (MAX.). Remark Unless otherwise specified, characteristics shared same those port pin.
µPD78P048A
Characteristics
Parameter Low-level input leakage current Symbol ILIL1 ILIL2 ILIL3 ILIL4 High-level output leakage current ILOH1 VOUT Conditions P03, P17, P27, P37, RESET XT1/P04 P110 P117, P120 P127 P03, P17, P27, P37, P80, P81, P97, P100 P107, P110 P117, P120 P127 P03, P17, P27, P37, P80, P81, P97, P100 107, P110 P117, P120 P127 MIN. TYP. MAX. -3Note Unit
ILOH2 Low-level output leakage current ILOL1
VOUT VOUT
ILOL2
VOUT VLOAD
Display output current Software pull-up resistor
P03, P17, P27,
On-chip pull-down resistor Power supply currentNote
IDD1
P80, P81, P97, P100 P105 crystal oscillation operation mode
VLOAD %Note %Note
9.75Note 0.05
28.5 29Note
IDD2
crystal oscillation HALT mode
IDD3
32.768 crystal oscillation operation mode 32.768 crystal oscillation HALT mode STOP mode when connecting feedback resistor STOP mode when connecting feedback resistor
IDD4
IDD5
IDD6
Notes This current excludes AVREF current, port current, current which flows built-in pull-down resistor. When operating high-speed mode (when processor clock control register (PCC) 00H) When operating low-speed mode (when 04H) P74, low-level input leak current -150 (MAX.) flows only during clocks after instruction been executed read port (P7) port mode register (PM7). Outside period clocks following executing read-out instruction, current (MAX.). This current includes AVDD current converter operation. Remark Unless otherwise specified, characteritics shared same those port pin.
µPD78P048A
Characteristics Basic operation
Parameter Cycle time (minimum) instruction execution time) TI1, input frequency TI1, input high, low-level width Interrupt input high, low-level width RESET low-level width Symbol Conditions Operated with main system clock Operated with subsystem clock MIN. 40Note fTIH fTIL fINTH fINTL tRSL INTP0 INTP1 INTP3 8/fsamNote TYP. MAX. Unit
Notes Value when external clock input used subsystem clock. When crystal used, value becomes Selection fsam fx/2N+1, fx/64, fx/128 available bits (SCS0, SCS1) sampling clock select register (SCS).
(with main system clock operated)
Operation guarantee range
Cycle time [µs]
Power supply voltage
µPD78P048A
Serial interface Serial interface channel 3-wire serial mode (SCK0: Internal clock output)
Symbol tKCY1 Conditions MIN. 3200 SCK0 high, low-level width setup time SCK0 tKH1 tKL1 tSIK1 tKCY1/2 tKCY1/2 pFNote 1000 TYP. MAX. Unit
Parameter SCK0 cycle time
hold time from SCK0 tKSI1 SCK0 output delay time tKSO1
Note load capacitance SCK0 output line. (ii) 3-wire serial mode (SCK0: External clock input)
Parameter SCK0 cycle time Symbol tKCY2 Conditions MIN. 3200 SCK0 high, low-level width setup time SCK0 tKH2 tKL2 tSIK2 1600 pFNote 1000 TYP. MAX. Unit
hold time from SCK0 tKSI2 SCK0 output delay time SCK0 rise, fall time tKSO2
Note load capacitance output line.
µPD78P048A
(iii) mode (SCK0: Internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 Conditions MIN. 3200 SCK0 high, low-level width SB0, setup time SB0, hold time from SCK0 SCK0 SB0, output delay time SCK0SB0, SB0, SB1SCK0 SB0, high-level width SB0, low-level width tKH3 tKL3 tSIK3 tKCY3/2 tKCY3/2 tKSI3 pFNote tKCY3/2 TYP. MAX. Unit
tKSO3
1000
tKSB tSBK tSBH
tKCY3 tKCY3 tKCY3
tSBL
tKCY3
Note load resistance SCK0, SB0, output line, load capacitance. (iv) mode (SCK0: External clock input)
Parameter SCK0 cycle time Symbol tKCY4 Conditions MIN. 3200 SCK0 high, low-level width SB0, setup time SCK0 SB0, hold time from SCK0 SCK0 SB0, output delay time SCK0SB0, SB0, SB1SCK0 SB0, high-level width SB0, low-level width SCK0 rise, fall time tKH4 tKL4 tSIK4 1600 tKSI4 pFNote tKCY4/2 TYP. MAX. Unit
tKSO4
1000
tKSB tSBK tSBH
tKCY4 tKCY4 tKCY4
tSBL
tKCY4
Note load resistance output line, load capacitance.
µPD78P048A
2-wire serial mode (SCK0: Internal clock output)
Parameter SCK0 cycle time Symbol tKCY5 Conditions pFNote MIN. 1600 3800 SCK0 high-level width SCK0 low-level width SB0, setup time SCK0 SB0, hold time from SCK0 SCK0SB0, output delay time tKH5 tKL5 tSIK5 tCKY5/2 tCKY5/2 TYP. MAX. Unit
tKSI5
tKSO5
1000
Note load resistance SCK0, SB0, output line, load capacitance. (vi) 2-wire serial mode (SCK0: External clock input)
Parameter SCK0 cycle time Symbol tKCY6 Conditions pFNote MIN. 1600 3800 SCK0 high-level width SCK0 low-level width SB0, setup time SCK0 SB0, hold time from SCK0 SCK0SB0, output delay time SCK0 rise, fall time tKH6 tKL6 tSIK6 TYP. MAX. Unit
tKSI6
tKCY6/2
tKSO6
1000
Note load resistance output line, load capacitance.
µPD78P048A
Serial interface channel 3-wire serial mode (SCK1: Internal clock output)
Symbol tKCY7 Conditions MIN. 3200 SCK1 high, low-level width setup time SCK1 hold time from SCK1 SCK1 output delay time tKH7 tKL7 tSIK7 tKSI7 tKSO7 pFNote tKCY7/2 tKCY7/2 1000 TYP. MAX. Unit
Parameter SCK1 cycle time
Note load capacitance SCK1 output line. (ii) 3-wire serial mode (SCK1: External clock input)
Parameter SCK1 cycle time Symbol tKCY8 Conditions MIN. 3200 SCK1 high, low-level width setup time SCK1 tKH8 tKL8 tSIK8 1600 pFNote 1000 TYP. MAX. Unit
hold time from SCK1 tKSI8 SCK1 output delay time SCK1 rise, fall time tKSO8
Note load capacitance output line.
µPD78P048A
(iii) 3-wire serial mode with automatic transmit/receive function (SCK1: Internal clock output)
Parameter SCK1 cycle time Symbol tKCY9 Conditions MIN. 3200 SCK1 high, low-level width setup time SCK1) hold time (from SCK1) output delay time from SCK1 from SCK1 Strobe signal high-level width signal setup time busy signal detection timing) Busy signal hold time (from busy signal detection timing SCK1 from busy inactibe tKH9 tKL9 tSIK9 tKSI9 tKSO9 pFNote tKCY9/2 tKCY9/2 1000 tSBD tSBW tKCY9/2 tKCY9 tKCY9/2 tKCY9 TYP. MAX. Unit
tBYS
tBYH
tSPS
2tKCY9
Note load resistance SCK1 output line, load capacitance. (iv) 3-wire serial mode with automatic transmit/receive function (SCK1: External clock input)
Parameter SCK1 cycle time Symbol tKCY10 Conditions MIN. 3200 SCK1 high, low-level width setup time SCK1) hold time (from SCK1) output delay time from SCK1 SCK1 rise, fall time tKH10 tKL10 tSIK10 tKSI10 tKSO10 pFNote 1600 1000 tR10 tF10 TYP. MAX. Unit
Note load capacitance output line.
µPD78P048A
Timing Test Point (Excluding Input)
Test Points
Clock timing
1/fX
Input
VIH4 (MIN.) VIL4 (MAX.)
1/fXT tXTL tXTH
Input
VIH5 (MIN.) VIL5 (MAX.)
timing
1/fTI tTIL tTIH
TI1,
µPD78P048A
Serial Transfer Timing 3-wire serial mode:
MHz,
tKCY1,
tKL1, tR2, SCK0, SCK1
tKH1, tF2,
tSIK1, tKSI1,
SI0, tKSO1,
Input Data
SO0,
Output Data
mode (bus release signal transfer):
tKCY3, tKL3, SCK0 tKSB tSBL tSBH tSBK tSIK3, tKSI3, tKH3,
SB0, tKSO3,
mode (command signal transfer):
tKCY3, tKH3,
tKL3,
SCK0 tKSB tSBK tSIK3, tKSI3,
SB0, tKSO3,
µPD78P048A
2-wire serail mode:
tKCY5, tKL5, SCK0 tSIK5, tKH5,
tKSO5,
tKSI5,
SB0,
3-wire serial mode with automatic transmit/receive function:
tSIK9, tKSO9,
tKSI9, tKH9,
tF10 SCK1 tR10 tKL9, tKCY9, tSBD tSBW
3-wire serial mode with automatic transmit/receive function (Busy processing):
SCK1
Note
Note
10+n tBYH
Note
tSPS
tBYS BUSY (Active high)
Note Though does become level actually, heve described does timing rule.
µPD78P048A
Converter Characteristics AVDD AVSS
Parameter Resolution Total errorNote timeNote tCONV tSAMP VIAN AVREF RAIREF 19.1 2.86 AVSS Symbol Conditions MIN. TYP. MAX. AVREF AVDD Unit
Conversion Sampling
timeNote
Analog signal input voltage Reference voltage AVREF resistor
Notes Quantization error (+1/2LSB) included. This parameter indicated ratio full-scale value. conversion time 19.1 more. Sampling time depends conversion time. Data Memory STOP Mode Supply Voltage Data Retention Characteristics
Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR VDDDR Subsystem clock stopped, Feedback resistor non-connected Release RESET Release interrupt 217/fx Note Conditions MIN. TYP. MAX. Unit
Release signal time Oscillation stabilization wait time
tSREL tWAIT
Note Selection 212/fx, 214/fx 217/fx available bits (OSTS0 OSTS2) oscillation stabilization time select register (OSTS). Data retention timing (STOP mode release RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operating mode
STOP instruction execution
VDDDR
tSREL
RESET
tWAIT
µPD78P048A
Data retention timing (standby release signal: STOP mode release interrupt signal)
HALT mode STOP mode Data retention mode Operating mode
STOP instruction execution
VDDDR
tSREL
Standby release signal (interrupt request) tWAIT
Interrupt input timing
tINTL tINTH
INTP0 INTP2
tINTL
INTP3
RESET input timing
tRSL
RESET
µPD78P048A
PROM Programming Characteristics characteristics PROM write mode ±0.25 12.5 ±0.3
Parameter Input voltage high Input voltage Output voltage high Output voltage Input leakage current supply voltage supply voltage supply current supply current Symbol SymbolNote 12.2 6.25 12.5 Conditions MIN. -1.0 12.8 6.75 TYP. MAX. Unit
PROM read mode ±0.5 ±0.6
Parameter Input voltage high Input voltage Output voltage high Symbol VOH1 VOH2 Output voltage Input leakage current Output leakage current supply voltage supply voltage supply current supply current SymbolNote VOH1 VOH2 ICCA1 VIL, -100 VOUT VDD, -0.6 Conditions MIN. -1.0 -0.5 +0.6 TYP. MAX. Unit
Note Corresponding µPD27C1001A symbol.
µPD78P048A
characteristics PROM write mode Page program mode ±0.25 12.5 ±0.3
Parameter Address setup time setup time setup time Input data setup time Address hold time (from Symbol tOES tCES tAHL tAHV Input data hold time (from Data output float delay time from setup time setup time Program pulse width Valid data delay time from pulse width during data latching setup time hold time hold time tVPS tVDS tPGMS tCEH tOEH SymbolNote tOES tCES tAHL tAHV tVPS tVCS tPGMS tCEH tOEH Conditions MIN. 0.095 0.105 TYP. MAX. Unit
Byte program mode ±0.25 12.5 ±0.3
Parameter Address setup time PGM) setup time setup time PGM) Input data setup time PGM) Address hold time (from Input data hold time (from PGM) Data output float delay time from setup time PGM) setup time PGM) Program pulse width Valid data delay time from hold time Symbol tOES tCES tAHL tVPS tVDS tOEH SymbolNote tOES tCES tAHL tVPS tVCS Conditions MIN. 0.095 0.105 TYP. MAX. Unit
Note Corresponding µPD27C1001A symbol
µPD78P048A
PROM read mode ±0.5 ±0.6
Parameter Data output delay time from address Data output delay time from Data output delay time from Data output float delay time from Data hold time from address Symbol tACC SymbolNote tACC Conditions MIN. TYP. MAX. Unit
Note Corresponding µPD27C1001A symbol PROM programming mode setting
Parameter PROM programming mode setup time Symbol tSMA Conditions MIN. TYP. MAX. Unit
µPD78P048A
PROM write mode timing (page program mode)
Page Data Latch
Page Program
Program Verify
Hi-Z Hi-Z tPGMS Data Output Hi-Z tAHL tAHV
tVPS tVDS
Data Input
tCES tOES tCEH
tOEH
µPD78P048A
PROM write mode timing (byte program mode)
Program Program Verify
Hi-Z tVDS tOES tCES tOEH tVPS Data Input Hi-Z Data Output Hi-Z
Cautions shonld applied before VPP, after VPP. shonld exceed +13.5 including overshoot. Disconnection during application ±12.5 have adverse effect reliability. PROM read mode timing
Effective Address
tACC
Note
Note
Note
Data Output Hi-Z
Hi-Z
Notes want read within tACC range, make input delay time from fall maximum tACC tOE. time from when either first reaches VIH.
µPD78P048A
PROM programming mode setting timing
RESET
tSMA
Effective Address
µPD78P048A
CHARACTERISTIC CURVE (REFERENCE VALUE)
(Main system clock MHz)
100.0
50.0
10.0
HALT oscillates, oscillates)
Supply Current [mA]
0.05
HALT stops, oscillates) STOP stops, oscillates)
0.01
0.005
0.001 Supply voltage
µPD78P048A
(VDD
Supply Current [mA]
HALT oscillates)
Clock oscillation frequency [MHz]
(VDD
Supply current [mA]
HALT oscillates)
Clock oscillation frequency fX[MHz]
µPD78P048A
(Port
Low-level output current [mA]
Low-level output voltage
(Ports
Low-level output current [mA]
Low-level output voltage
µPD78P048A
(Port
Low-level output current [mA]
Low-level output voltage
VDD-VOH (Port 0-Port
High-level output current [mA]
High-level output voltage VDD-VOH
µPD78P048A
VDD-VOH (Port 8-Port
High-level output current [mA]
High-level output voltage VDD-VOH
µPD78P048A
PACKAGE DRAWINGS
PLASTIC
detail lead
ITEM MILLIMETERS 23.6±0.4 20.0±0.2 14.0±0.2 17.6±0.4 0.35±0.10 0.15 (T.P.) 1.8±0.2 0.8±0.2 0.15 +0.10 -0.05 0.10 0.1±0.1 5°±5° MAX. INCHES 0.929±0.016 0.795 +0.009 -0.008 0.551 +0.009 -0.008 0.693±0.016 0.039 0.031 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.004±0.004 5°±5° 0.119 MAX. P80GF-80-3B9-3
NOTE Each lead centerline located within 0.15 (0.006 inch) true position (T.P.) maximum material condition.
Remark Dimensions materials products same those mass-production products.
µPD78P048A
CERAMIC WQFN
X80KW-80A-1 NOTE Each lead centerline located within 0.08 (0.003 inch) true position (T.P.) maximum material condition. ITEM MILLIMETERS 20.0 19.0 13.2 14.2 1.64 2.14 4.064 MAX. 0.51 0.10 0.08 (T.P.) 12.0 0.75 INCHES 0.787+0.017 -0.016 0.748 0.520 0.559 0.016 0.065 0.084 0.160 MAX. 0.020 0.004 0.003 0.031 (T.P.) 0.039 -0.008 0.020 0.031 0.043 0.118 0.472 0.030 -0.009
+0.008 +0.009
Remark Dimensions materials products same those mass-production products.
µPD78P048A
RECOMMENDED SOLDERING CONDITIONS
conditions listed below shall when soldering µPD78P048A. details recommended soldering conditions, refer information document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with sales offices case other soldering process used, case soldering done under different conditions. Table 12-1. Soldering Conditions Surface-Mount Type
µPD78P048AGF-3B9: 80-pin plastic
Soldering Method Soldering Conditions Recommended Condition Symbol
Infrared reflow
Package peak temperature: Duration: sec. max. above), IR35-00-3 Number times: Thrice max. Package peak temperature: Duration: sec. max. above), VP15-00-3 Number times: Thrice max. Solder bath temperature: max. Duration: sec. max. Number times: Once Preliminary heat temperature: max. (Package surface temperature) temperature: max., Duration: sec. max. (per device side) WS60-00-1
Wave soldering
Partial heating
Caution Using more than soldering method should avoided (except case partial heating).
µPD78P048A
APPENDIX DEVELOPMENT TOOLS
following tools available development systems using µPD78P048A: Language Processing Software
RA78K/0Note CC78K/0Note DF78044Note CC78K/0-LNote Assembler package common 78K/0 series compiler package common 78K/0 series Device file µPD78044F subseries compiler library source file common 78K/0 series
PROM Writing Tools
PG-1500 PA-78P048GF PA-78P048KL-S PG-1500 ControllerNote PROM programmer Programmer adapter connected PG-1500
Control program PG-1500
Debugging Tools
IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78044-R-EM EP-78130GF-R EV-9200G-80 SM78K0Note ID78K0Note SD78K/0Note DF78044Note In-circuit emulator common 78K/0 series In-circuit emulator common 78K/0 series (for integrated debugger) Break board common 78K/0 series Emulation board evaluating µPD78044F subseries Emulation probe common µPD78134 Socket mounted target system created 80-pin plastic (GF-3B9 type) System simulator common 78K/0 series Integrated debugger IE-78000-R-A Screen debugger IE-78000-R Device file µPD78044F subseries
Real-time
RX78K/0Note MX78K0Note Real-time 78K/0 series 78K/0 series
Notes PC-9800 series (MS-DOSTM) based PC/ATand compatible DOSTM/IBM DOSTM/MS-DOS) based HP9000 series 300(HP-UXTM) based HP9000 series 700(HP-UX) based, SPARCstation(Sun OSTM) based, EWS4800 series (EWS-UX/ based PC-9800 series (MS-DOS WindowsTM) based PC/AT compatible DOS/IBM DOS/MS-DOS Windows) based NEWS(NEWS-OSTM) based
µPD78P048A
Fuzzy Inference Development Support System
FE9000Note 1/FE9200Note FT9080Note 1/FT9085Note FI78K0Note FD78K0Note Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
Notes PC-9800 series (MS-DOS) based PC/AT compatible DOS/IBM DOS/MS-DOS) based PC/AT compatible DOS/IBM DOS/MS-DOS Windows) based Remarks Please refer 78K/0 Series Selection Guide (U11126E) information third party development tools. RA78K/0, CC78K/0, SM78K0, ID78K0, RX78K/0, SD78K/0 used combination with DF78044.
µPD78P048A
DIMENSIONS RECOMMENDED MOUNTING PATTERN CONVERSION SOCKET Figure A-1. Dimensions EV-9200G-80 (Reference)
EV-9200G-80-G0E INCHES 0.984 0.799 0.157 0.569 0.748 0.11 0.031 0.433 0.866 0.972 0.197 0.638 0.744 0.315 0.307 0.098 0.079 0.053 0.014+0.004 -0.005
EV-9200G-80
No.1 index
ITEM MILLIMETERS 25.0 20.30 14.45 19.0 11.0 22.0 24.7 16.2 18.9 1.35 0.35
0.091 0.059
µPD78P048A
Figure A-2. Recommended Mounting Pattern V-9200G-80
EV-9200G-80-P1E INCHES 1.012 0.827 0.598 0.783 0.433+0.004 -0.003 0.217+0.001 -0.002 0.197+0.003 -0.004 0.098 +0.002 -0.001 0.02+0.001 -0.002
ITEM Caution
MILLIMETERS 25.7 21.0
0.8±0.02 23=18.4±0.05 0.031+0.002 0.906=0.724 +0.003 -0.001 -0.002 0.8±0.02 15=12.0±0.05 0.031+0.002 0.591=0.472 +0.003 -0.001 -0.002 15.2 19.9 11.00 0.08 5.50 0.03 5.00 0.08 2.50 0.03 0.02
2.36 0.03 1.57 0.03
0.093+0.001 -0.002 0.062+0.001 -0.002
Dimensions mount EV-9200 that target device (QFP) different some parts. recommended mount dimensions QFP, refer "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
µPD78P048A
APPENDIX RELATED DOCUMENTS
Device Related Documents
Document Name Document Japanese English U10908E U10700E This document U12326E U10121E
µPD78044F Subseries User's Manual µPD78042F, 78043F, 78044F, 78045F Data Sheet µPD78P048A Data Sheet µPD78044A, 78044F Subseries Special Function Register Table
78K/0 Series User's Manual-Instruction 78K/0 Series Instruction 78K/0 Series Instruction Table 78K/0 Series Application Note-Basics (II)
U10908J U10700J U10611J U10701J U12326J U10904J U10903J U10121J
Development Tool Related Documents (User's Manual) (1/2)
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µPD78P048A
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µPD78P048A
[MEMO]
µPD78P048A
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD78P048A
documents referred this publication include preliminary versions. However preliminary versions marked such. export these products from Japan regulated Japanese government. export some these products prohibited without governmental license. export re-export some these products from country other than Japan also prohibited without license from that country. Please call sales representative. License needed: µPD78P048AKL-S customer must judge need license: µPD78P048AGF-3B9
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
96.5
registered trademark Corporation. IEBus trademark Corporation. MS-DOS Windows either registered trademarks trademarks Microsoft Corporation United States and/or other countries. DOS, PC/AT, trademarks Corporation. HP9000 series 300, HP9000 series HP-UX trademarks Hewlett Packard Inc. SPARCstation trademark SPARC International, Inc. SunOS trademark MicroSystems Inc. NEWS NEWS-OS trademarks Sony Corporation.

µPD78P048A 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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