µPD78P083 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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µPD78P083 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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INTEGRATED CIRCUIT
µPD78P083
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD78P083 member µPD78083 subseries 78K/0 series products. includes on-chip, 24-Kbyte, one-time PROM EPROM. Because this device programmed users, ideally suited applications involving evaluation systems development stages, small-scale production many different products, rapid development time-to-market product. Caution µPD78P083DU does maintain planned reliability when used your systems' mass-produced products. Please only experimentally evaluation purposes during trial manufacture.
details functions described user's manuals. sure read following manuals before designing. µPD78083 Subseries User's Manual 78K/0 Series User's Manual Instructions IEU-1407 IEU-1372
FEATURES
Pin-compatible with mask version (except pin) Internal PROM: Kbytes Note µPD78P083DU: Reprogrammable (ideally suited system evaluation) µPD78P083CU, µPD78P083GB: One-time programmable (ideally suited small-scale production) Internal high-speed RAM: bytes Note operated same supply voltage mask version (VDD Corresponding QTOPMicrocontrollers Note internal PROM internal high-speed capacities changed setting internal memory size switching register (IMS). Remark QTOP microcontroller general term microcontrollers which incorporate one-time PROM totally supported NEC's programming service (from programming marking, screening verification).
Differs from mask version following points same memory mapping mask version enabled setting internal memory size switching register (IMS).
this document, term PROM used parts common one-time PROM versions EPROM versions.
information this document subject change without notice.
Document U11006EJ1V0DS00 (1st edition) (Previous IP-3556) Date Published June 1996 Printed Japan
mark
shows major revised points.
1995
µPD78P083
ORDERING INFORMATION
Part Number µPD78P083CU µPD78P083GB-3B4 µPD78P083GB-3BS-MTX µPD78P083DU 42-pin 44-pin 44-pin 42-pin Package plastic shrink (600 mil) plastic plastic ceramic shrink Internal One-Time PROM One-Time PROM One-Time PROM EPROM
(with window) (600 mil) Caution
µPD78P083GB kinds package. (Refer PACKAGE DRAWINGS). Please refer
NEC's sales representative available package.
QUALITY GRADE
Part Number µPD78P083CU µPD78P083GB-3B4 µPD78P083GB-3BS-MTX µPD78P083DU Package 42-pin plastic shrink (600 mil) 44-pin plastic 44-pin plastic 42-pin ceramic shrink (with window) (600 mil) Quality Grades Standard Standard Standard applicable
Please refer "Quality grades Semiconductor Devices" (Document number IEI-1209) published Corporation know specification quality grade devices recommended applications.
µPD78P083
78K/0 SERIES DEVELOPMENT
following shows 78K/0 series products development. Subseries names shown inside frames.
Products mass production Products under development subseries products compatible with bus. Control 100-pin 100-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin µPD78078 µPD78070A µPD78058F µPD78054 µPD78018F µPD78014 µPD780001 µPD78002 µPD78083 µPD78002Y µPD78078Y µPD78070AY µPD78058FY µPD78054Y µPD78018FY µPD78014Y timer added µPD78054 external interface function enhanced ROM-less versions µPD78078 noise reduced product µPD78054 UART converter were added µPD78014 enhanced Low-voltage (1.8 operation versions µPD78014 with several capacities available. converter 16-bit timer were added µPD78002 converter added µPD78002 Basic subseries control On-chip UART, capable operating voltage (1.8
FIPdrive 100-pin 78K/0 Series 80-pin 64-pin µPD780208 µPD78044A µPD78024 µPD78044A were enhanced. Display output total: 6-bit counter added µPD78024. Display output total: Basic subseries driving FIP. Display output total:
drive 100-pin 100-pin 100-pin µPD780308 µPD78064B µPD78064 µPD78064Y µPD780308Y enhanced µPD78064 increased capacities noise reduced product µPD78064 Subseries driving LCDs, On-chip UART
IEBussupported 80-pin µPD78098 IEBus controller added µPD78054
control 64-pin µPD78P0914 On-chip PWM, digital code decoder, Hsync counter
µPD78P083
following table shows differences among subseries functions.
Function Part Number Control µPD78078 µPD78070A Capacity Timer 8-bit 8-bit (UART: 1ch) (UART: 1ch) (UART: 1ch) (UART: 1ch) Available Serial Interface MIN. External Value Expansion Available
8-bit 16-bit Watch
µPD78058F µPD78054
µPD78018F µPD78014
µPD780001 µPD78002 µPD78083 drive µPD780208 µPD78044A µPD78024 drive
µPD780308 µPD78064B µPD78064
IEBus supported control
µPD78098
(UART: 1ch)
Available
µPD78P0914
Available
µPD78P083
FUNCTION DESCRIPTION
Item Internal memory Function PROM: Kbytes Internal high-speed RAM: bytes Memory space General register Instruction cycles Instruction Kbytes bits registers bits registers banks) Instruction execution time variable function integrated. µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 (@5.0-MHz operation with main system clock) 16-bit operation Multiply/divide bits bits, bits bits) manipulation (set, reset, test, Boolean operation) adjust, etc. ports Total CMOS input CMOS input/output converter Serial interface Timer Timer output Clock output Buzzer output Vectored interrupts Maskable interrupts Non-maskable interrupt Software interrupt Power supply voltage Operating ambient temperature Packages
Note Note
8-bit resolution channels 3-wire serial I/O/UART mode selectable: channel 8-bit timer/event counter: channels Watchdog timer: channel pins (8-bit output enable) 19.5 kHz, 39.1 kHz, 78.1 kHz, kHz, kHz, kHz, 1.25 MHz, MHz, 5.0-MHz operation with main system clock) kHz, kHz, kHz, 5.0-MHz operation with main system clock) Internal Internal Internal external
+85°C 42-pin plastic shrink (600 mil) 44-pin plastic 42-pin ceramic shrink (with window) (600 mil)
Note
Internal PROM high-speed capacities changed setting internal memory size switching register (IMS).
µPD78P083
CONFIGURATIONS (Top View) Normal operating mode 42-pin plastic shrink (600 mil) µPD78P083CU 42-pin ceramic shrink (with window) (600 mil) µPD78P083DU
P35/PCL P36/BUZ P01/INTP1 P02/INTP2 P03/INTP3 RESET AVDD
P100/TI5/TO5 P101/TI6/TO6 P70/RXD/SI2 P71/TXD/SO2 P72/ASCK/SCK2 P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVSS AVREF
Cautions
Connect directly Connect AVDD VDD. Connect AVSS VSS.
µPD78P083
44-pin plastic µPD78P083GB-3B4, µPD78P083GB-3BS-MTX
P11/ANI1
P10/ANI0
AVSS
RESET
AVREF
AVDD
P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 P72/ASCK/SCK2 P71/TXD/SO2 P70/RXD/SI2 P101/TI6/TO6 P100/TI5/TO5
P03/INTP3 P02/INTP2 P01/INTP1 P36/BUZ P35/PCL
Cautions
Connect Connect Connect Connect
directly AVDD VDD. AVSS VSS. noise protection left open).
µPD78P083
P100, P101 INTP1 INTP3 TI5, TO5, SCK2 ASCK
Port Port Port Port Port Port
RESET ANI0-ANI7
Programmable Clock Buzzer Clock Crystal (Main System Clock) Reset Analog Input Analog Power Supply Analog Ground Analog Reference Voltage Power Supply Programming Power Supply
Interrupt from Peripherals Timer Input Timer Output Serial Input Serial Output Serial Clock Receive Data Transmit Data
Ground Non-connection
Asynchronous Serial Clock
µPD78P083
PROM programming mode 42-pin plastic shrink (600 mil) µPD78P083CU 42-pin ceramic shrink (with window) (600 mil) µPD78P083DU
RESET Open
Cautions
(L):
Individually connect pull-down resistor.
VSS: Connect GND. RESET: level. Open: Leave open.
µPD78P083
44-pin plastic µPD78P083GB-3B4, µPD78P083GB-3BS-MTX
RESET
Open
Cautions
(L): Individually connect pull-down resistor. VSS: Connect GND. RESET: level. Open: Leave open. RESET Reset Power Supply Programming Power Supply Ground
Address Data Chip Enable Output Enable Program
µPD78P083
BLOCK DIAGRAM
P100/TI5/TO5 8-bit TIMER/ EVENT COUNTER PORT P01-P03
P101/TI6/TO6
8-bit TIMER/ EVENT COUNTER WATCHDOG TIMER 78K/0 CORE
PORT
P10-P17
PROM KBytes)
PORT
P30-P37
SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVDD AVSS AVREF INTP1/P01INTP3/P03
SERIAL INTERFACE
PORT
P50-P57
CONVERTER DATA MEMORY (512 Bytes)
PORT
P70-P72
INTERRUPT CONTROL BUZZER OUTPUT
PORT
P100, P101
BUZ/P36
RESET SYSTEM CONTROL
PCL/P35
CLOCK OUTPUT CONTROL
µPD78P083
CONTENTS
DIFFERENCES BETWEEN µPD78P083 MASK VERSIONS FUNCTIONS
Pins Normal Operating Mode Pins PROM Programming Mode Input/Output Circuits Recommended Connection Unused Pins
INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) PROM PROGRAMMING
Operating Modes PROM Write Procedure PROM Read Procedure
PROGRAM ERASURE (µPD78P083DU ONLY) OPAQUE FILM ERASURE WINDOW (µPD78P083DU ONLY) ONE-TIME PROM VERSION SCREENING ELECTRICAL SPECIFICATIONS PACKAGE DRAWINGS
RECOMMENDED SOLDERING CONDITIONS APPENDIX APPENDIX DEVELOPMENT TOOLS RELATED DOCUMENTS
µPD78P083
DIFFERENCES BETWEEN µPD78P083 MASK VERSIONS
µPD78P083 single-chip microcontroller with on-chip one-time PROM with on-chip EPROM which program write, erasure rewrite capability. Setting internal memory size switching register (IMS) makes functions except PROM specification identical mask versions, that µPD78081 µPD78082. Differences between µPD78P083 mask versions shown Table 1-1.
Table 1-1. Differences between µPD78P083 Mask Versions
Parameter type capacity Internal high-speed capacity Internal internal high-speed capacity change internal memory size switching register Electrical specifications Refer data sheet each product Kbytes bytes changed
Note
µPD78P083 One-time PROM/EPROM
Mask Versions Mask µPD78081 µPD78082 µPD78081 µPD78082 Kbytes Kbytes bytes bytes
changed
Note
internal PROM becomes Kbytes internal expansion becomes bytes RESET input.
µPD78P083
FUNCTIONS
Pins Normal Operating Mode
Port pins
Name Input/Output Input Input/output Port 4-bit input/output port Function Input only Input/output specifiable bit-wise. When used input port, possible connect pull-up resistor software. P10-P17 Input/output Port 8-bit input/output port Input/output specifiable bit-wise. When used input port, possible connect pull-up resistor software. P30-P34 P50-P57 Input/output Input/output Port 8-bit input/output port Input/output specifiable bit-wise. When used input port, possible connect pull-up resistor software. Port 8-bit input/output port drive seven LEDs directly. Input/output specifiable bit-wise. When used input port, possible connect pull-up resistor software. Input/output Port 3-bit input/output port Input/output specifiable bit-wise. When used input port, possible connect pull-up resistor software. P100 P101 Input/output Port 2-bit input/output port Input/output specifiable bit-wise. When used input port, possible connect pull-up resistor software. Input TI5/TO5 TI6/TO6 Input SI2/RxD SO2/TxD SCK2/ASCK Input
Note
After Reset Input Input
Alternate Function INTP1 INTP2 INTP3
Input
ANI0-ANI7
Input
Note
When P10/ANI0-P17/ANI7 pins used analog inputs converter, port input mode. on-chip pull-up resistor automatically disabled.
µPD78P083
Non-port pins
Name INTP1 INTP2 INTP3 SCK2 ASCK ANI0-ANI7 RESET Input Input Positive power supply. High-voltage applied during program write/verification. Connected directly normal operating mode. Ground potential. Does internally connected. Connect VSS. left open) Output Output Input Input Clock output. (for main system clock trimming) Buzzer output. converter analog input. converter reference voltage input. converter analog power supply. Connected VDD. converter ground potential. Connected VSS. System reset input. Main system clock oscillation crystal connection. Input Input Input Output Input Output Input/Output Input Output Input Input Serial interface serial data input. Serial interface serial data output. Serial interface serial clock input/output. Asynchronous serial interface serial data input. Asynchronous serial interface serial data output. Asynchronous serial interface serial clock input. External count clock input 8-bit timer (TM5). External count clock input 8-bit timer (TM6). 8-bit timer output. Input Input Input Input Input Input Input Input Input/Output Input Function External interrupt input which active edge (rising edge, falling edge, both rising falling edges) specified. After Reset Input Alternate Function P70/RxD P71/TxD P72/ASCK P70/SI2 P71/SO2 P72/SCK2 P100/TO5 P101/TO6 P100/TI5 P101/TI6 P10-P17
µPD78P083
Pins PROM Programming Mode
Input/Output Input Function PROM programming mode setting When +12.5 applied low-level signal applied RESET pin, this chip PROM programming mode.
Name RESET
A0-A14 D0-D7
Input Input Input/output Input Input Input
PROM programming mode setting high-voltage applied during program write/verification. Address Data PROM enable input/program pulse input Read strobe input PROM Program/program inhibit input PROM programming mode. Positive power supply Ground potential
Input/Output Circuits Recommended Connection Unused Pins Types input/output circuits pins recommeded connection unused pins shown Table 2-1. configuration each type input/output circuit, Figure 2-1.
Table 2-1. Type Input/Output Circuit Each
Name P01/INTP1 P02/INTP2 P03/INTP3 P10/ANI0-P17/ANI7 P30-P32 P33, P35/PCL P36/BUZ P50-P57 P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P100/TI5/TO5 P101/TI6/TO6 RESET AVREF AVDD AVSS Input Connect VSS. Connect VDD. Connect VSS. Connect directly VSS. Connect (can leave open) Input/Output Independently connect resistor. Input/Output Circuit Type Input Input/Output Connect VSS. Independently connect resistor. Input/Output Recommended Connection Unused Pins
µPD78P083
Figure 2-1. Types Input/Output Circuits
Type Type
pull-up enable data P-ch
P-ch
IN/OUT Schmitt-triggered input with hysteresis characteristics output disable N-ch
Type pull-up enable data
Type pull-up enable
P-ch
P-ch P-ch IN/OUT
data
P-ch IN/OUT output disable P-ch N-ch Comparator N-ch VREF (threshold voltage) input enable N-ch
output disable
input enable
µPD78P083
INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
This register disable part internal memories software. setting this internal memory size switching register (IMS), possible same memory mapping that mask versions with different internal memory (ROM, RAM). with 8-bit memory manipulation instruction. RESET input sets 46H.
Figure 3-1. Internal Memory Size Switching Register Format
Symbol RAM2 RAM1 RAM0 ROM3 ROM2 ROM1 ROM0 Address FFF0H After Reset
ROM3 ROM2 ROM1 ROM0
Selection Internal Capacity Kbytes Kbytes Kbytes Setting prohibited
Other than above
RAM2 RAM1 RAM0
Selection Internal High-Speed Capacity bytes bytes bytes Setting prohibited
Other than above
Table shows setting values which make memory mapping same that mask version.
Table 3-1. Internal Memory Size Switching Register Setting Values
Target Mask Versions µPD78081 µPD78082 Setting Value
µPD78P083
PROM PROGRAMMING
µPD78P083 internal 24-Kbyte PROM program memory. programming, PROM programming mode with RESET pins. connection unused pins, refer "PIN CONFIGURATIONS (TOP VIEW) PROM programming mode." Caution Programs must written addresses 0000H 5FFFH (The last address 5FFFH must specified). They cannot written PROM programmer which cannot specify write address. Operating Modes When +12.5 applied low-level signal applied RESET pin, PROM programming mode set. This mode will become operating mode shown Table when pins shown. Further, when read mode set, possible read contents PROM.
Table 4-1. Operating Modes PROM Programming
Operating Mode Page data latch Page write Byte write Program verify Program inhibit +12.5 +6.5 Read Output disable Standby Data output High-impedance High-impedance Data input High-impedance Data input Data output High-impedance RESET
µPD78P083
Read mode Read mode set. Output disable mode Data output becomes high-impedance, output disable mode, set. Therefore, allows data read from device controlling pin, multiple µPD78P083s connected data bus. Standby mode Standby mode set. this mode, data outputs become high-impedance irrespective status. Page data latch mode Page data latch mode beginning page write mode. this mode, page 4-byte data latched internal address/data latch circuit. Page write mode After page bytes addresses data latched page data latch mode, page write executed applying 0.1-ms program pulse (active low) with Then, program verification performed, set. programming performed one-time program pulse, times write verification operations should executed repeatedly. Byte write mode Byte write executed when 0.1-ms program pulse (active low) applied with Then, program verification performed set. programming performed one-time program pulse, times write verification operations should executed repeatedly. Program verify mode Program verify mode set. this mode, check write operation performed correctly after write. Program inhibit mode Program inhibit mode used when pin, pin, D0-D7 pins multiple µPD78P083s connected parallel write performed those devices. When write operation performed, page write mode byte write mode described above used. this time, write performed device which driven high.
µPD78P083
PROM Write Procedure
Figure 4-1. Page Program Mode Flow Chart
Start Address +6.5 +12.5
Latch Address Address Latch Address Address Latch Address Address Address Address Latch
X=X+1 0.1-ms program pulse
Verify bytes Pass Address
Fail
Pass
Verify bytes Pass Write
Fail
Defective product
Start address Program last address
µPD78P083
Figure 4-2. Page Program Mode Timing
Page Data Latch Page Program Program Verify
A2-A14
D0-D7 Data Input Data Output
µPD78P083
Figure 4-3. Byte Program Mode Flow Chart
Start Address +6.5 +12.5
X=X+1 0.1-ms program pulse Address Address Fail Verify Pass Address
Pass
Verify bytes Pass Write
Fail
Defective product
Start address Program last address
µPD78P083
Figure 4-4. Byte Program Mode Timing
Program
Program Verify
A0-A14
D0-D7
Data Input
Data Output
Cautions
should applied before removed after VPP. must exceed +13.5 including overshoot. Reliability adversely affected removal/reinsertion performed while +12.5 being applied VPP.
µPD78P083
PROM Read Procedure contents PROM readable external data (D0-D7) according read procedure shown below. RESET level, supply pin, connect other unused pins shown "PIN CONFIGURATIONS (TOP VIEW) PROM programming mode". Supply pins. Input address read data into A0-A16 pins. Read mode Output data D0-D7 pins. timings above steps shown Figure 4-5.
Figure 4-5. PROM Read Timings
A0-A14
Address Input
(Input)
(Input)
D0-D7
Hi-Z
Data Output
Hi-Z
µPD78P083
PROGRAM ERASURE (µPD78P083DU ONLY)
µPD78P083DU capable erasing (FFH) data written program memory rewriting. erase programmed data, expose erasure window light having wavelength shorter than about Normally, irradiate ultraviolet rays 254-nm wavelength. amount exposure required completely erase programmed data follows: intensity erasing time more
Erasure time: min. more (When lamp 12,000 µW/cm2 used. However, longer time needed because deterioration performance lamp, soiled erasure window, etc.) When erasing contents data, lamp within from erasure window. Further, filter provided lamp, irradiate ultraviolet rays after removing filter.
OPAQUE FILM ERASURE WINDOW (µPD78P083DU ONLY)
protect from unintentional erasure rays other than that lamp erasing EPROM contents, protect internal circuit other than EPROM from misoperating rays, cover erasure window with opaque film when EPROM contents erasure performed.
ONE-TIME PROM VERSION SCREENING
one-time PROM version (µPD78P083CU, 78P083GB-3B4, 78P083GB-3BS-MTX) cannot tested completely before shipped, because structure. recommended perform screening verify PROM after writing necessary data performing high-temperature storage under condition below.
Storage Temperature 125°C Storage Time hours
offers additional one-time PROM writing marking, screening, verify products designated "QTOP Microcontroller". Please contact sales representative details.
µPD78P083
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings 25°C)
Parameter Supply voltage Symbol AVDD AVREF AVSS Input voltage Output voltage Analog input voltage Output current, high P10-P17 Total P10-P17, P50-P54, P70-P72, P100, P101 Total P01-P03, P30-P37, P55-P57 Output current,
Note
Ratings -0.3 +7.0 -0.3 +13.5 -0.3 -0.3 -0.3 +0.3 -0.3 Unit
Test Conditions
PROM programming mode -0.3 +13.5
-0.3 Analog input pins AVSS AVREF +150
Total P50-P54 Total P55-P57 Total P10-P17, P70-P72, P100, P101 Total P01-P03, P30-P37
Peak value
r.m.s. value
Peak value
r.m.s. value
Peak value
r.m.s. value
Peak value
r.m.s. value
Peak value
r.m.s. value
Operating ambient temperature Storage temperature
Tstg
Note r.m.s. value should calculated follows: [r.m.s. value] [Peak value] Duty Caution absolute maximum rating even above parameters exceeded, quality product degraded. absolute maximum ratings therefore rated values that may, exceeded, physically damage product. sure product with absolute maximum ratings observed. Unless otherwise specified, dual-function characteristics same port characteristics.
Remark
µPD78P083
Capacitance 25°C,
Parameter Input capacitance capacitance Symbol Test Conditions MHz, Unmeasured pins returned MHz, Unmeasured pins returned P01-P03, P10-P17, P30-P37, P50-P57, P70-P72, P100, P101 MIN. TYP. MAX. Unit
Remark
Unless otherwise specified, dual-function characteristics same port characteristics.
Main System Clock Oscillator Characteristics +85°C,
Resonator Recommended Circuit Ceramic resonator
Parameter
Test Conditions
MIN.
TYP.
MAX.
Unit
Oscillation frequency (fX) Note Oscillation stabilization time
Note
Oscillation voltage range After came MIN. oscillation voltage range
Crystal resonator
Oscillation frequency (fX)
Note
Oscillation stabilization time
Note
External clock
input frequency (fX) Note
PD74HCU04
input high- low-level widths (tXH, tXL)
Notes Only oscillator characteristics shown. instruction execution time, refer Characteristics. Time required oscillation stabilize after reset STOP mode been released. Caution When using oscillation circuit main system clock, wire portion enclosed broken lines figures follows avoid adverse influences wiring capacitance: Keep wiring length short possible. cross wiring over other signal lines. route wiring vicinity lines through which high fluctuating current flows. Always keep ground point capacitor oscillation circuit same potential VSS. connect power source pattern through which high current flows. extract signals from oscillation circuit.
µPD78P083
Characteristics +85°C,
Parameter Input voltage, high Symbol VIH1 Test Conditions P10-P17, P30-P32, P35-P37, P50-P57, VIH2 P00-P03, P33, P34, P70, P72, P100, P101, RESET VIH3 Input voltage, VIL1 P10-P17, P30-P32, P35-P37, P50-P57, VIL2 P00-P03, P33, P34, P70, P72, P100, P101, RESET VIL3 Output voltage, high Output voltage, -100 P50-P57 P01-P03, P10-P17, P30-P37, P70-P72, P100, P101 Input-leak current, high ILIH1 P00-P03, P10-P17, P30-P37, P50-P57, P70-P72, P100, P101, RESET ILIH2 Input-leak current, ILIL1 P00-P03, P10-P17, P30-P37, P50-P57, P70-P72, P100, P101, RESET ILIL2 Output leak current, high Output leak current, Software pull-up resistor ILOH ILOL P01-P03, P10-P17, P30-P37, P50-P57, P70-P72, P100, P101 VDD-1.0 VDD-0.5 0.15VDD 0.2V 0.2V 0.85VDD VDD-0.5 VDD-0.2 0.3V 0.8VDD 0.8VDD MIN. 0.7VDD TYP. MAX. Unit
Remark Unless otherwise specified, dual-function characteristics same port characteristics.
µPD78P083
Characteristics +85°C,
Parameter Supply current
Note
Symbol IDD1
Test Conditions 5.0-MHz crystal oscillation operating mode (fXX MHz) Note 5.0-MHz crystal oscillation operating mode (fXX MHz)
Note
MIN.
Note Note Note Note Note
TYP. 0.45 0.65 0.05 0.05
MAX. 16.2 1.35 28.5 1.95
Unit
IDD2
5.0-MHz crystal oscillation HALT mode (fXX MHz)
Note
5.0-MHz crystal oscillation HALT mode (fXX MHz) IDD3 STOP mode
Note
Notes including AVREF, AVDD currents port currents (including current flowing into internal pull-up resistors). fX/2 operation (when oscillation mode selection register (OSMS) 00H). operation (when oscillation mode selection register (OSMS) 01H). High-speed mode operation (when processor clock control register (PCC) 00H). Low-speed mode operation (when processor clock control register (PCC) 04H). Remark fxx: Main system clock frequency x/2) Main system clock oscillation frequency
µPD78P083
Characteristics
Basic Operation +85°C,
Parameter Cycle time (minimum instruction execution time) TI5, input frequency TI5, input high-/ low-level widths Interrupt input high-/ low-level widths RESET low-level width tTIH, tTIL tINTH, tINTL tRSL Note2 Symbol
Note1
Test Conditions
MIN.
TYP.
MAX.
Unit
Notes When oscillation mode selection register (OSMS) 00H. When OSMS 01H. Remark fxx: Main system clock frequency x/2) Main system clock oscillation frequency
(Main System Clock fx/2 Operation)
(Main System Clock Operation)
Cycle Time
Operation Guaranteed Range
Cycle Time
Operation Guaranteed Range
Power Supply Voltage
Power Supply Voltage
µPD78P083
Serial Interface +85°C, 3-wire serial mode (SCK2 internal clock output)
Parameter SCK2 cycle time Symbol tKCY1 Test Conditions SCK2 high-/low-level width setup time SCK2 tKH1, tKL1 tSIK1 hold time (from SCK2 SCK2 output delay time tKSO1 pFNote tKSI1 MIN. 1600 3200 4800 tKCY1/2-50 tKCY1/2-100 TYP. MAX. Unit
Note SCK2, output line load capacitance. 3-wire serial mode (SCK2 external clock input)
Parameter SCK2 cycle time Symbol tKCY2 Test Conditions SCK2 high-/low-level width tKH2, tKL2 setup time SCK2 hold time (from SCK2 SCK2 output delay time SCK2 rise, fall time tR2, tKSO2 pFNote 1000 tKSI2 tSIK2 MIN. 1600 3200 4800 1600 2400 TYP. MAX. Unit
Note output line load capacitance.
µPD78P083
UART mode (Dedicated baud rate generator output)
Parameter Symbol Test Conditions MIN. TYP. MAX. 78125 39063 19531 9766 Unit
Transfer rate
UART mode (External clock input)
Parameter Symbol tKCY3 Test Conditions MIN. 1600 3200 4800 1600 2400 39063 19531 9766 6510 1000 TYP. MAX. Unit
ASCK cycle time
ASCK high-/low-level width
tKH3 tKL3
Transfer rate
ASCK rise, fall time
tR3,
µPD78P083
Timing Test Point (Excluding Input)
Test Points
Clock Timing
1/fx
Input
Timing
1/fTI tTIL tTIH
TI5,
µPD78P083
Serial Transfer Timing 3-wire serial mode:
tKCY1, tKL1, SCK2 tKH1,
tSIK1,
tKSI1,
tKSO1,
Input Data
Output Data
UART mode (external clock input):
tKCY3 tKL3 ASCK tKH3
µPD78P083
Converter Characteristics +85°C, AVDD AVSS
Parameter Resolution Total error
Note
Symbol
Test Conditions AVREF AVDD
MIN.
TYP.
MAX. AVREF AVDD
Unit
Conversion time Sampling time Analog input voltage Reference voltage AVREF-AVSS resistance
tCONV tSAMP VIAN AVREF RAIREF
19.1 12/fxx AVSS
Note Excluding quantization error (±1/2 LSB). Shown percentage full scale value. Remark fxx: Main system clock frequency x/2) Main system clock oscillation frequency
µPD78P083
Data Memory STOP Mode Supply Voltage Data Retention Characteristics +85°C)
Parameter Data retention supply voltage Data retention supply current Release signal time Oscillation stabilization wait time Symbol VDDDR IDDDR tSREL tWAIT Release RESET Release interrupt DDDR 17/f
Note
Test Conditions
MIN.
TYP.
MAX.
Unit
Note 212/fxx 214/fxx-217/fxx selected 0-bit (OSTS0-OSTS2) oscillation stabilization time selection register (OSTS). Remark fxx: Main system clock frequency x/2) Main system clock oscillation frequency
Data Retention Timing (STOP mode released RESET)
Internal reset operation HALT mode STOP mode Data retention mode VDDDR STOP instruction execution RESET tSREL Operating mode
tWAIT
Data Retention Timing (Standby release signal: STOP mode released interrupt signal)
HALT mode STOP mode Data retention mode VDDDR STOP instruction execution Standby release signal (interrupt request) tWAIT tSREL Operating mode
µPD78P083
Interrupt Input Timing
tINTL INTP1-INTP3 tINTH
RESET Input Timing
tRSL
RESET
µPD78P083
PROM Programming Characteristics Characteristics
PROM Write Mode ±5°C, ±0.25 12.5 ±0.3
Parameter Input voltage, high Input voltage, Output voltage, high Output voltage, Input leakage current supply voltage supply voltage supply current supply current Symbol SymbolNote 12.2 6.25 12.5 Test Conditions MIN. 0.7VDD 12.8 6.75 TYP. MAX. 0.3V Unit
PROM Read Mode ±5°C, ±0.5 ±0.6
Parameter Input voltage, high Input voltage, Output voltage, high Output voltage, Input leakage current Output leakage current supply voltage supply voltage supply current supply current Symbol SymbolNote VOH1 VOH2 VOH1 VOH2 ICCA1 VIL, -100 VOUT VDD, Test Conditions MIN. 0.7VDD TYP. MAX. 0.3V Unit
Note Corresponding µPD27C1001A symbol.
µPD78P083
Characteristics
PROM Write Mode Page program mode ±5°C, ±0.25 12.5 ±0.3
Parameter Address setup time setup time setup time Address hold time (from Symbol Symbol Note tOES tCES tAHL tAHV Input data hold time (from Data output float delay time setup time setup time Program pulse width pulse width during data latching setup time hold time hold time tPGMS tCEH tOEH tPGMS tCEH tOEH tVPS tVDS tVPS tVCS 0.095 0.105 tOES tCES tAHL tAHV Test Conditions MIN. TYP. MAX. Unit
Input data setup time
Valid data delay time
Byte program mode ±5°C, ±0.25 12.5 ±0.3
Parameter time setup time Address hold time (from Input data hold time (from Data output float delay time setup time setup time Program pulse width hold time tVPS tVDS tOEH tVPS tVCS 0.095 0.105 Symbol Symbol Note tOES tCES tOES tCES Test Conditions MIN. TYP. MAX. Unit Address setup time
Input data setup time
Valid data delay time
Note
Corresponding µPD27C1001A symbol.
µPD78P083
PROM Read Mode ±5°C, ±0.5 ±0.6
Parameter Address Data output delay time Data output delay time Data output delay time Data output float delay time Address Data hold time Symbol Symbol Note tACC tACC Test Conditions MIN. TYP. MAX. Unit
Note Corresponding µPD27C1001A symbol. PROM Programming Mode 25°C,
Parameter PROM programming mode setup time Symbol tSMA Test Conditions MIN. TYP. MAX. Unit
µPD78P083
PROM Write Mode Timing (page program mode)
Page Data Latch A2-A14 D0-D7 Hi-Z tVPS tVDS VDD+1.5 tCES tOES tCEH tOEH Data Input Hi-Z tPGMS Output
Data
Page Program
Program Verify
tAHL
tAHV
Hi-Z
µPD78P083
PROM Write Mode Timing (byte program mode)
Program A0-A14 D0-D7 VDD+1.5 tOES tCES tVPS Hi-Z Data Input Hi-Z Data Output Hi-Z Program Verify
tVDS
tOEH
Cautions
should applied before VPP, removed after VPP. must exceed +13.5 including overshoot. Reliability adversely affected removal/reinsertion performed while 12.5 being applied VPP.
PROM Read Mode Timing
A0-A14
Effective Address
tACCNote D0-D7 Hi-Z tOENote Data Output Hi-Z tDFNote
Notes want read within range tACC, make input delay time from fall maximum tACC- tOE. time from when either first reaches VIH.
µPD78P083
PROM Programming Mode Setting Timing
RESET
tSMA Effective Address
A0-A14
µPD78P083
PACKAGE DRAWINGS
42PIN PLASTIC SHRINK (600 mil)
NOTES Each lead centerline located within 0.17 (0.007 inch) true position (T.P.) maximum material condition. Item center leads when formed parallel.
ITEM
MILLIMETERS 39.13 MAX. 1.78 MAX. 1.778 (T.P.) 0.50±0.10 MIN. 3.2±0.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 15.24 (T.P.) 13.2 0.25 +0.10 -0.05 0.17 0~15°
INCHES 1.541 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.126±0.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.600 (T.P.) 0.520 0.010 +0.004 -0.003 0.007 0~15° P42C-70-600A-1
Remark shape material versions same those mass-produced versions.
µPD78P083
µPD78P083GB-3B4
PLASTIC
detail lead
NOTE Each lead centerline located within 0.15 (0.006 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 13.6±0.4 10.0±0.2 10.0±0.2 13.6±0.4 0.35±0.10 0.15 (T.P.) 1.8±0.2 0.8±0.2 0.15 +0.10 -0.05 0.10 0.1±0.1 5°±5° MAX. INCHES 0.535 +0.017 -0.016 0.394 +0.008 -0.009 0.394 +0.008 -0.009 0.535 +0.017 -0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.004±0.004 5°±5° 0.119 MAX. P44GB-80-3B4-3
Remark shape material versions same those mass-produced versions.
µPD78P083
µPD78P083GB-3BS-MTX
PLASTIC
detail lead
NOTE Each lead centerline located within 0.16 (0.007 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 13.2±0.2 10.0±0.2 10.0±0.2 13.2±0.2 0.37 +0.08 -0.07 0.16 (T.P.) 1.6±0.2 0.8±0.2 0.17 +0.06 -0.05 0.10 0.125±0.075 MAX. INCHES 0.520 +0.008 -0.009 0.394 +0.008 -0.009 0.394 +0.008 -0.009 0.520 +0.008 -0.009 0.039 0.039 0.015 +0.003 -0.004 0.007 0.031 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.007 +0.002 -0.003 0.004 0.106 0.005±0.003 0.119 MAX. S44GB-80-3BS
Remark shape material versions same those mass-produced versions.
µPD78P083
42PIN CERAMIC SHRINK (WINDOW) (600 mil)
0°~15° P42DW-70-600A
NOTES Each lead centerline located within 0.25 (0.01 inch) true position (T.P.) maximum material condition. Item center leads when formed parallel.
ITEM
MILLIMETERS 38.25 MAX. 1.345 MAX. 1.778 (T.P.) 0.46 0.05 0.85 MIN. 1.02 MIN. 3.026 5.282 MAX. 15.24 (T.P.) 14.99 0.25 0.05 0.25 12.0 4-R3.0
INCHES 1.506 MAX. 0.053 MAX. 0.07 (T.P.) 0.018 0.002 0.033 MIN. 0.138 0.012 0.040 MIN. 0.119 0.208 MAX. 0.600 (T.P.) 0.590 0.010 -0.003 0.01 0.472 0.236 4-R0.118
+0.002
µPD78P083
RECOMMENDED SOLDERING CONDITIONS
recommended that µPD78P083 soldered under following conditions. details recommended soldering conditions, refer information document "Semiconductor Device Mounting Technology Manual" (C10535E). soldering methods conditions other than those recommended, please contact your sales representative.
Table 10-1. Soldering Conditions Surface Mount Types µPD78P083GB-3B4 44-pin plastic µPD78P083GB-3BS-MTX 44-pin plastic
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Reflow time: seconds less 210°C higher), Number reflow processes: less Cautions Wait device temperature return normal after first reflow before starting second reflow. perform flux cleaning with water after first reflow. Package peak temperature: 215°C, Reflow time: seconds less 200°C higher), Number reflow processes: less Cautions Wait device temperature return normal after first reflow before starting second reflow. perform flux cleaning with water after first reflow. Solder temperature: 260°C below, Flow time: seconds less, Number flow processes: Preheating temperature: 120°C max. (package surface temperature) temperature: 300°C below, Flow time: seconds less (per row) IR35-00-2 Symbol
VP15-00-2
Wave soldering
WS60-00-1
Partial heating
Caution
different soldering methods together (except partial heating method).
Table 10-2. Soldering Condition Hole-Through Types µPD78P083CU 42-pin plastic shrink (600 mil) µPD78P083DU 42-pin ceramic shrink (with window) (600 mil)
Soldering Method Wave Soldering (only pins) Partial heating Soldering Conditions Solder temperature: 260°C below, Flow time: seconds less temperature: 300°C below, Flow time: seconds less (per pin)
Caution
Apply wave soldering only pins careful bring solder into direct contact with package.
µPD78P083
APPENDIX DEVELOPMENT TOOLS
following development tools available support development systems using µPD78P083. Language Processing Software
RA78K/0 CC78K/0 DF78083
Notes Notes Notes Notes
Assembler package common 78K/0 series compiler package common 78K/0 series Device file used µPD78083 subseries compiler library source file common 78K/0 series
CC78K/0-L
PROM Writing Tools
PG-1500 PA-78P083CU PA-78P083GB PG-1500 Controller
Notes
PROM programmer Programmer adapter connected PG-1500 Control program PG-1500
Debugging Tools
IE-78000-R IE-78000-R-A
Note
In-circuit emulator common 78K/0 series In-circuit emulator common 78K/0 series (for integrated debugger) Break board common 78K/0 series Emulation board common µPD78078 subseries Emulation probe µPD78083 subseries Socket mounted target system board prepared 44-pin plastic System simulator common 78K/0 series Integrated debugger IE-78000-R-A Screen debugger IE-78000-R Device file used µPD78083 subseries
IE-78000-R-BK IE-78078-R-EM EP-78083CU-R EP-78083GB-R EV-9200G-44 SM78K0 ID78K0 SD78K/0 DF78083
Notes Notes Notes Notes
Notes Based PC-9800 series (MS-DOSTM) Based PC/ATand compatibles DOSTM/IBM DOSTM/MS-DOS) Based HP9000 series 300(HP-UXTM) Based HP9000 series 700(HP-UX), SPARCstation(SunOSTM), EWS4800 series (EWS-UX/V) Based PC-9800 series (MS-DOS WindowsTM) PC/AT compatibles DOS/IBM DOS/MS-DOS Windows) Based NEWS(NEWS-OSTM)
Under development Remarks Please refer 78K/0 Series Selection Guide (U11126E) information third party development tools. RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0 combination with DF78083.
µPD78P083
Fuzzy Inference Development Support System
FE9000 FT9080 FI78K0 FD78K0
Note Note
/FE9200
Note Note
Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
/FT9085
Notes Notes
Notes Based PC-9800 series (MS-DOS) Based PC/AT compatibles DOS/IBM DOS/MS-DOS+Windows) Based PC/AT compatibles DOS/IBM DOS/MS-DOS) Remark Please refer 78K/0 Series Selection Guide (U11126E) information third party development tools.
µPD78P083
APPENDIX RELATED DOCUMENTS
Documents Related Devices
Document Name µPD78083 Subseries User's Manual 78K/0 Series User's Manual-Instructions 78K/0 Series Instruction Table 78K/0 Series Instruction µPD78083 Subseries Special Function Register Table 78K/0 Series Application Note Basic (III) IEU-886 IEU-849 U10903J U10904J IEM-5599 IEA-767 Document Japanese English IEU-1407 IEU-1372 U10182E
Documents Related Development Tools (User's Manual)
Document Name RA78K Series Assembler Package RA78K Series Structured Assembler Preprocessor CC78K Series Compiler CC78K/0 Compiler Application Note CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS) Based PG-1500 Controller Series DOS) Based IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78078-R-EM EP-78083 SM78K0 System Simulator SM78K Series System Simulator Reference Third party's user open interface specifications SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) Based SD78K/0 Screen Debugger PC/AT DOS) Based Introduction Reference Introduction Reference EEU-852 U10952J EEU-5024 EEU-993 EEU-1414 EEU-1413 Operation Language Programming know-how EEU-777 EEU-651 EEU-704 EEU-5008 EEU-810 U10057J EEU-867 U10775J EEU-5003 EEU-5002 U10092J EEU-1335 EEU-1291 U10540E EEU-1398 U10057E EEU-1427 EEU-1504 EEU-1529 U10181E U10092E Operation Language Document Japanese EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 EEA-618 English EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284 EEA-1208
Caution
contents documents listed above subject change without prior notice. Make sure latest edition when starting design.
µPD78P083
Documents Related Embedded Software (User's Manual)
Document Name 78K/0 Series MX78K0 Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System Translator 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger Basic Document Japanese EEU-5010 EEU-829 EEU-862 EEU-858 EEU-921 EEU-1438 EEU-1444 EEU-1441 EEU-1458 English
Other Documents
Document Name Semiconductor Device Package Manual Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide Quality Assurance Semicoductor Devices Microcontroller-Related Product Guide Third Party Products IEI-635 C10535J IEI-620 C10983J MEM-539 MEI-603 MEI-604 Document Japanese English IEI-1213 C10535E IEI-1209 C10983E IEI-1201 MEI-1202
Caution
contents documents listed above subject change without prior notice. sure latest edition when starting design.
µPD78P083
[MEMO]
µPD78P083
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
FIP, IEBus, QTOP trademarks Corporation. MS-DOS Windows trademarks Microsoft Corporation. DOS, PC/AT trademarks International Business Machines Corporation. HP9000 series 300, HP9000 series 700, HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation.
µPD78P083
related documents indicated this publication include preliminary versions. However, preliminary versions marked such. export these products from Japan regulated Japanese government. export some these products prohibited without governmental license. export re-export some these products from country other than Japan also prohibited without license from that country. Please call sales representive. License needed µPD78P083DU
customer must judge need license µPD78P083CU, 78P083GB-3B4, 78P083GB-3BS-MTX
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customer must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact Sales Representative advance. Anti-radioactive design implemented this product.
94.11

µPD78P083 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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