µPD78P018FY 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION
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INTEGRATED CIRCUIT
µPD78P018FY
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD78P018FY member µPD78018FY Subseries 78K/0 Series products. internal mask µPD78018FY replaced with one-time PROM EPROM. Because µPD78P018FY programmed users, ideally suited applications involving evaluation systems development stages, small-scale production many different products, rapid development timeto-market products. Caution µPD78P018FYDW 78P018FYKK-S guaranteed maintain reliability level required mass production customer's devices. Please only experimentally evaluation purposes during trial manufacture. Detailed function descriptions provided following user's manuals. sure read them before designing.
µPD78018F, 78018FY Subseries User's Manual: U10659E
78K/0 Series User's Manual Instructions: U12326E
FEATURES
compatible with mask version (except pin) Internal PROM: Kbytes Note
µPD78P018FYDW, 78P018FYKK-S: Re-programmable (suited system evaluation) µPD78P018FYCW, 78P018FYGC-AB8: Programmable only once (suited small-scale production)
Internal high-speed RAM: 1024 bytes Note Internal expansion RAM: 1024 bytes Note Internal buffer RAM: bytes Supports interface Operable over same supply voltage range mask version: (except converter) QTOPmicrocontroller supported Notes capacities internal PROM internal high-speed changed means internal memory size switching register (IMS). capacity internal expansion changed means internal expansion size switching register (IXS). Remarks QTOP Microcontroller general term microcontrollers which incorporate one-time PROM totally supported NEC's programming service (from programming marking, screening, verification). differences between PROM version mask versions, refer DIFFERENCES BETWEEN µPD78P018FY MASK VERSIONS. this document, term PROM used parts common one-time PROM versions EPROM versions.
information this document subject change without notice. Document U10989EJ3V0DS00 (3rd edition) Date Published December 1998 CP(K) Printed Japan
mark
shows major revised points.
1994
µPD78P018FY
ORDERING INFORMATION
Part Number Package 64-pin plastic shrink (750 mils) 64-pin ceramic shrink (with window) (750 mils) 64-pin plastic 64-pin ceramic WQFN Internal One-time PROM EPROM One-time PROM EPROM
µPD78P018FYCW µPD78P018FYDW µPD78P018FYGC-AB8 µPD78P018FYKK-S
QUALITY GRADE
Part Number Package 64-pin plastic shrink (750 mils) 64-pin ceramic shrink (with window) (750 mils) 64-pin plastic 64-pin ceramic WQFN Quality Grades Standard applicable (for function evaluation) Standard applicable (for function evaluation)
µPD78P018FYCW µPD78P018FYDW µPD78P018FYGC-AB8 µPD78P018FYKK-S
Please refer "Quality grade Semiconductor Devices" (Document number C11531E) published Corporation know specification quality grade devices recommended applications.
µPD78P018FY
78K/0 SERIES PRODUCT LINEUP
products 78K/0 Series listed below. names enclosed boxes subseries names.
Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
Products mass production Products under development subseries products compatible with bus. EMI-noise reduced version µPD78078
µPD78075B µPD78078 PD78070A PD780058 PD78058F PD78054 PD780065 PD780034 PD780024 PD78014H µPD78018F µPD78083
Inverter control
µPD78078Y µPD78070AY PD780018AY PD780058YNote PD78058FY PD78054Y PD780034Y µPD780024Y PD78018FY
Timer added µPD78054 external interface enhanced ROM-less version µPD78078 Serial µPD78078Y enhanced function limited Serial µPD78054 enhanced EMI-noise reduced EMI-noise reduced version µPD78054 UART converter were added µPD78018F enhanced capacity µPD780024 expanded converter µPD780024 enhanced Serial µPD78018F enhanced EMI-noise reduced version µPD78018F Basic subseries control On-chip UART, capable operating voltage (1.8
64-pin
PD780988
FIPdrive
On-chip inverter control circuit UART. EMI-noise reduced
78K/0 Series
100-pin 100-pin 80-pin 80-pin 80-pin
µPD780208 PD780228 PD780232 µPD78044H µPD78044F
drive
µPD78044F were enhanced, Display output total: µPD78044H were enhanced, Display output total: panel control. On-chip C/D. Display output total: N-ch open drain added µPD78044F, Display output total: Basic subseries driving FIP, Display output total:
100-pin 100-pin 100-pin
PD780308 PD78064B µPD78064
µPD780308Y PD78064Y
µPD78064 enhanced ROM, capacity expanded EMI-noise reduced version µPD78064 Basic subseries driving LCDs, On-chip UART
interface supported 80-pin 80-pin 80-pin 80-pin
µPD78098B PD780948 PD780701Y PD780833Y
Meter control
IEBuscontroller added µPD78054. EMI-noise reduced. On-chip DCAN controller On-chip DCAN/IEBus controller On-chip J1850 (CLASS2) controller
80-pin 80-pin 100-pin
PD780973 µPD780955 µPD780958
On-chip controller/driver automotive meter drive Ultra-low power consumption on-chip UART industrial meter control
Note Under planning
µPD78P018FY
major functional differences among subseries shown below.
Function Capacity Subseries Name Control Configuration Serial Interface 3-wire/2-wire/I2C: 3-wire with automatic transmit/receive function: 3-wire/UART: 3-wire with automatic transmit/receive function: Time-division 3-wire: (multimaster supported): 3-wire/2-wire/I2C: 3-wire with automatic transmit/receive function: 3-wire/time-division UART: 3-wire/2-wire/I2C: 3-wire with automatic transmit/receive function: 3-wire/UART: UART: 3-wire: (multimaster supported): MIN. Value
µPD78078Y µPD78070AY µPD780018AY
µPD780058Y
µPD78058FY µPD78054Y µPD780034Y µPD780024Y µPD78018FY
drive
3-wire/2-wire/I2C: 3-wire with automatic transmit/receive function: 3-wire/2-wire/I2C: 3-wire/time-division UART: 3-wire: 3-wire/2-wire/I2C: 3-wire/UART:
µPD780308Y
µPD78064Y
Remark functions other than serial interface common Subseries without
µPD78P018FY
FUNCTION OVERVIEW (1/2)
Item PROM High-speed Expansion Buffer Memory space General-purpose registers Minimum instruction execution time When main system clock selected When subsystem clock selected Instruction Kbytes Note 1024 bytes Note 1024 bytes Note bytes Kbytes bits registers bits registers banks) Minimum instruction execution time cycle modification function provided. µs/0.8 µs/1.6 µs/3.2 µs/6.4 10.0-MHz operation) 32.768-kHz operation) 16-bit operation Multiply/divide bits bits, bits bits) manipulate (set, reset, test, Boolean operation) adjust, etc. ports Total: CMOS input: CMOS I/O: N-channel open-drain (15-V withstand voltage): Function
Internal memory
converter
8-bit resolution channels Operable over wide power supply voltage range: 3-wire serial mode/2-wire serial mode/I2C mode selectable: channel 3-wire serial mode (on-chip max. bytes automatic data transmit/receive function): channel 16-bit timer/event counter: 8-bit timer/event counter: Watch timer: Watchdog timer: channel channels channel channel
Serial interface
Timer
Timer output Clock output
(14-bit output 39.1 kHz, 78.1 kHz, kHz, kHz, kHz, 1.25 10.0-MHz operation with main system clock), 32.768 32.768-kHz operation with subsystem clock) kHz, kHz, 10.0-MHz operation with main system clock) Internal: Internal: External:
Buzzer output Vectored interrupt sources Software Maskable Non-maskable
Notes internal PROM internal high-speed capacities changed with internal memory size switching register (IMS). internal expansion capacity changed with internal expansion size switching register (IXS).
µPD78P018FY
FUNCTION OVERVIEW (2/2)
Item Test input Supply voltage Operating ambient temperature Package Internal: External: Function
+85°C 64-pin 64-pin 64-pin 64-pin plastic shrink (750 mils) ceramic shrink (with window) (750 mils) plastic ceramic WQFN (750 mils)
µPD78P018FY
CONFIGURATION (Top View)
Normal operating mode 64-pin Plastic Shrink (750 mils) µPD78P018FYCW 64-pin Ceramic Shrink (with window) (750 mils) µPD78P018FYDW
P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13
P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 P04/XT1 P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 RESET P67/ASTB P66/WAIT P65/WR P64/RD P57/A15 P56/A14
Cautions Connect directly VSS. Connect AVDD VDD. Connect AVSS VSS.
µPD78P018FY
64-pin Plastic µPD78P018FYGC-AB8 64-pin Ceramic WQFN µPD78P018FYKK-S
P26/SO0/SB1/SDA1
P25/SI0/SB0/SDA0
P27/SCK0/SCL
P24/BUSY
P22/SCK1
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6
P12/ANI2
P21/SO1
P23/STB
P20/SI1
P11/ANI1 P10/ANI0 P04/XT1 P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 RESET P67/ASTB P66/WAIT
P47/AD7
P52/A10
P53/A11
P54/A12
P55/A13
P50/A8
P51/A9
P56/A14
P57/A15
P64/RD
Cautions Connect directly VSS. Connect AVDD VDD. Connect AVSS VSS.
P65/WR
µPD78P018FY
A15: AD7: ANI0 ANI7: ASTB: AVDD: AVREF: AVSS: BUSY: BUZ: INTP0 INTP3: P04: P17: P27: P37: P47: P57: P67: PCL: Address Address/Data Analog Input Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Busy Buzzer Clock Interrupt from Peripherals Port Port Port Port Port Port Port Programmable Clock RESET: Reset Read Strobe
SB0, SB1: Serial SCK0, SCK1: Serial Clock SCL: Serial Clock SDA0, SDA1: Serial Data SI0, SI1: SO0, SO1: STB: TI2: TO2: VDD: VPP: VSS: WAIT: XT1, XT2: Serial Input Serial Output Strobe Timer Input Timer Output Power Supply Programming Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock)
µPD78P018FY
PROM programming mode 64-pin Plastic Shrink (750 mils) µPD78P018FYCW 64-pin Ceramic Shrink (with window) (750 mils) µPD78P018FYDW
Open Open RESET
Cautions (L):
Independently connect pull-down resistor.
Connect GND. VSS: RESET: level. Open: Leave open.
µPD78P018FY
64-pin Plastic µPD78P018FYGC-AB8 64-pin Ceramic WQFN µPD78P018FYKK-S
Open Open RESET
Cautions (L): VSS: RESET: Open: A16: PGM:
Independently connect pull-down resistor. Connect GND. level. Leave open. RESET: VDD: VPP: VSS: Reset Power Supply Programming Power Supply Ground
Address Chip Enable Data Output Enable Program
µPD78P018FY
BLOCK DIAGRAM
TO0/P30 TI0/INTP0/P00 TO1/P31 TI1/P33 TO2/P32 TI2/P34
16-bit TIMER/ EVENT COUNTER
PORT0
8-bit TIMER/ EVENT COUNTER
PORT1
8-bit TIMER/ EVENT COUNTER
PORT2
WATCHDOG TIMER
PORT3
WATCH TIMER 78K/0 CORE SERIAL INTERFACE PROM Kbytes)
PORT4
SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 ANI0/P10ANI7/P17 AVDD AVSS AVREF SERIAL INTERFACE
PORT5
PORT6
AD0/P40 AD7/P47 A8/P50 A15/P57
(2048 bytes)
EXTERNAL ACCESS
RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET
CONVERTER
INTP0/P00INTP3/P03
INTERRUPT CONTROL
SYSTEM CONTROL XT1/P04
BUZ/P36
BUZZER OUTPUT
PCL/P35
CLOCK OUTPUT CONTROL
µPD78P018FY
CONTENTS DIFFERENCES BETWEEN µPD78P018FY MASK VERSIONS FUNCTIONS
Pins During Normal Operating Mode Pins During PROM Programming Mode Circuits Recommended Connection Unused Pins
INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) INTERNAL EXPANSION SIZE SWITCHING REGISTER (IXS) PROM PROGRAMMING
Operating Modes PROM Write Procedure PROM Read Procedure
PROGRAM ERASURE (FOR µPD78P018FYDW, 78P018FYKK-S) OPAQUE FILM ERASURE WINDOW (FOR µPD78P018FYDW, 78P018FYKK-S) ONE-TIME PROM VERSION SCREENING ELECTRICAL SPECIFICATIONS
CHARACTERISTIC CURVE (REFERENCE VALUE) PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
µPD78P018FY
DIFFERENCES BETWEEN µPD78P018FY MASK VERSIONS
µPD78P018FY single-chip microcontroller with on-chip one-time PROM EPROM that program write, erase, rewrite capability. possible make functions except PROM specification mask option pins, same those mask versions µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY) setting internal memory size switching register (IMS) internal expansion size switching register (IXS). Differences between µPD78P018FY mask versions shown Table 1-1. Table 1-1. Differences Between µPD78P018FY Mask Version
Item Internal type Internal capacity
µPD78P018FY
One-time PROM EPROM Kbytes
Mask Versions Mask µPD78011FY: µPD78012FY: µPD78013FY: µPD78014FY: µPD78015FY: µPD78016FY: µPD78018FY: µPD78011FY: µPD78012FY: µPD78013FY: µPD78014FY: µPD78015FY: µPD78016FY: µPD78018FY: µPD78011FY: µPD78012FY: µPD78013FY: µPD78014FY: µPD78015FY: µPD78016FY: µPD78018FY:
Internal high-speed capacity
1024 bytes
Internal expansion capacity
1024 byte
Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes bytes bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes bytes bytes 1024 bytes
Internal ROM, internal high-speed capacity changeable with internal memory size switching register (IMS) Internal expansion capacity changeable with internal expansion size switching register (IXS) On-chip pull-up resistor mask option pins Electrical specifications Recommended soldering conditions
Note
Note
respective data sheet individual products.
Notes internal PROM capacity becomes Kbytes internal high-speed capacity becomes 1024 bytes RESET input. internal expansion capacity becomes 1024 bytes RESET input. Caution There differences noise immunity noise radiation between PROM mask versions. When pre-producing application with PROM version then mass-producing with mask version, sure conduct sufficient evaluations commercial samples (not engineering samples) mask version.
µPD78P018FY
FUNCTIONS
Pins During Normal Operating Mode
Port Pins (1/2)
Name
Note1
Input Input/ output Port 5-bit input/ output port Input only
Function
After Reset Input Input
Alternate Function INTP0/TI0 INTP1 INTP2 INTP3
Input/output specified 1-bit units. When used input port, on-chip pullup resistor specified means software. Input only
Input Input/ output
Input Input
ANI0 ANI7
Port 8-bit input/output port. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. Note Port 8-bit input/output port. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software.
Input/ output
Input
SCK1 BUSY SI0/SB0/SDA0 SO0/SB1/SDA1 SCK0/SCL
Input/ output
Port 8-bit input/output port. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software.
Input
Input/ output
Port 8-bit input/output port. Input/output specified 8-bit units. When used input port, on-chip pull-up resistor specified means software. Test input flag (KRIF) falling edge detection.
Input
Notes When using P04/XT1 input port, (FRC) processor clock control register (PCC) on-chip feedback resistor subsystem clock oscillator). When using P10/ANI0 P17/ANI7 pins converter analog input pins, port input mode. this time, on-chip pull-up resistors automatically disconnected.
µPD78P018FY
Port Pins (2/2)
Name Input/ output Function Port 8-bit input/output port. LEDs driven directly. Input/output specified 1-bit units. When used input port, on-chip pull-up resistor specified means software. Port 8-bit input/output port. Input/output specified 1-bit units. N-ch open-drain input/ output port. LEDs driven directly. After Reset Input Alternate Function
Input/ output
Input
When used input port, on-chip pull-up resistor specified means software.
WAIT ASTB
Non-port Pins (1/2)
Name INTP0 INTP1 INTP2 INTP3 SDA0 SDA1 SCK0 SCK1 BUSY Output Input Serial interface automatic transmit/receive strobe output. Serial interface automatic transmit/receive busy input. Input Input Input/ output Serial interface serial clock input/output. Input Input/ output Serial interface serial data input/output. Input Output Serial interface serial data output. Input Input Input Function External interrupt request input which effective edge (rising edge, falling edge, both rising edge falling edge) specified. Falling edge detection external interrupt request input. Serial interface serial data input. Input After Reset Input Alternate Function P00/TI0 P25/SB0/SDA0 P26/SB1/SDA1 P25/SI0/SDA0 P26/SO0/SDA1 P25/SI0/SB0 P26/SO0/SB1 P27/SCL P27/SCK0
µPD78P018FY
Non-port Pins (2/2)
Alternate Function P00/INTP0 Input Input Input Input Input Input Input
Name WAIT ASTB
Input
Function External count clock input 16-bit timer (TM0). External count clock input 8-bit timer (TM1). External count clock input 8-bit timer (TM2).
After Reset Input
Output
16-bit timer (TM0) output (shared 14-bit output). 8-bit timer (TM1) output. 8-bit timer (TM2) output.
Output Output Input/ output Output Output
Clock output (for main system clock, subsystem clock trimming). Buzzer output. Lower address/data expanding memory externally. Higher address expanding memory externally. Strobe signal output read from external memory. Strobe signal output writing external memory.
Input Output
Wait insertion external memory access. Strobe output that externally latches address information output port port access external memory. converter analog input. converter reference voltage input. converter analog power supply. Connect VDD. converter ground potential. Connect VSS. System reset input. Connecting crystal resonator main system clock oscillation.
ANI0 ANI7 AVREF AVDD AVSS RESET
Input Input Input Input Input
Input
Connecting crystal resonator subsystem clock oscillation.
Input
Positive power supply. High voltage applied during program write/verify. normal operating mode, connect directly.
Ground potential.
µPD78P018FY
Pins During PROM Programming Mode
RESET Input Function Sets PROM programming mode. When +12.5 applied level applied RESET pin, microcontroller shifted PROM programming mode. Applies high voltage during PROM programming mode setting program write/verify. Address Data PROM enable input/program pulse input. Read strobe input PROM. Program/program inhibit input PROM programming mode. Positive power supply Ground potential
Input Input Input/ output Input Input Input
µPD78P018FY
Circuits Recommended Connection Unused Pins input/output circuit type each recommended connection unused pins shown Table 2-1. input/output circuit configuration each type, Figure 2-1. Table 2-1. Types Circuits
Name P00/INTP0/TI0 P01/INTP1 P02/INTP2 P03/INTP3 P04/XT1 P10/ANI0 P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P47/AD7 P50/A8 P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB RESET Input Leave open. Connect Connect Connect Connect directly VSS. 13-D Independently connect resistor. Independently connect resistor. Independently connect resistor. Independently connect resistor. 10-A Input Input/output Connect VDD. Independently connect resistor. Input/output Circuit Type Input Input/output Recommended Connection when Used Connect Independently connect resistor.
µPD78P018FY
Figure 2-1. Input/Output Circuits
Type
Type 10-A pullup enable data open drain output disable
P-ch
P-ch N-ch
Schmitt-Triggered Input with Hysteresis Characteristic
Type pullup enable data output disable input enable Type pullup enable data output disable
P-ch
Type pullup enable data
P-ch P-ch N-ch P-ch N-ch VREF (Threshold Voltage)
P-ch N-ch
output disable Comparator
input enable P-ch P-ch N-ch P-ch data output disable N-ch Type 13-D
Middle-Voltage Input Buffer
Type pullup enable data output disable
P-ch
Type feedback cut-off P-ch
P-ch N-ch
µPD78P018FY
INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
This register used disable part internal memory software. setting this register (IMS), possible same memory that mask versions with different internal memory (ROM, RAM). with 8-bit memory manipulate instruction. RESET input sets CFH. Figure 3-1. Internal Memory Size Switching Register Format
Symbol Address After Reset FFF0H
RAM2 RAM1 RAM0
ROM3 ROM2 ROM1 ROM0
ROM3 ROM2 ROM1 ROM0
Selection Internal Capacity Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Setting prohibited
Note
Other than above
RAM2 RAM1 RAM0
Selection Internal High-Speed Capacity bytes 1024 bytes Setting prohibited
Other than above
Note external device expansion functions employed µPD78P018FY, size internal Kbytes below using internal memory size switching register (IMS). Table shows setting values which make memory same that mask versions. Table 3-1. Internal Memory Size Switching Register Setting Values
Target Mask Versions
Setting Value
µPD78011FY µPD78012FY µPD78013FY µPD78014FY µPD78015FY µPD78016FY µPD78018FY
µPD78P018FY
INTERNAL EXPANSION SIZE SWITCHING REGISTER (IXS)
This register used disable part internal expansion capacity software. setting this register (IXS), possible same memory that mask versions with different internal expansion RAM. with 8-bit memory manipulate instruction. RESET input sets 0AH. Figure 4-1. Internal Expansion Size Switching Register Format
Address After Reset FFF4H
RAM3 RAM2 RAM1 RAM0
RAM3 RAM2 RAM1 RAM0
Selection Internal Expansion Capacity 1024 bytes (F400H F7FFH) bytes (F600H F7FFH) bytes Setting prohibited
Other than above
Table shows setting values which make memory same that mask versions. Table 4-1. Internal Expansion Size Switching Register Setting Values
Target Mask Versions
Setting Value
Note
µPD78011FY µPD78012FY µPD78013FY µPD78014FY µPD78015FY µPD78016FY µPD78018FY
Note Even program µPD78P018FY which "MOV IXS, #0CH" written executed µPD78011FY, 78012FY, 78013FY, 78014FY, operations affected.
µPD78P018FY
PROM PROGRAMMING
µPD78P018FY internal 60-Kbyte PROM program memory. programming, PROM programming mode setting RESET pins. unused connection, refer "PIN CONFIGURATION (Top View) PROM programming mode." Caution When writing program, locations 0000H-EFFFH (specify last address EFFFH). cannot write using PROM programmer that cannot specify addresses write.
Operating Modes
When +12.5 applied low-level signal applied RESET pin, PROM programming mode set. This mode will become operating mode shown Table when pins shown. Further, when read mode set, possible read contents PROM.
Table 5-1. Operating Modes PROM Programming
RESET Operating Mode Page data latch Page write Byte write Program verify Program inhibit +12.5 +6.5 Read Output disable Standby Data output High-impedance High-impedance Data input High-impedance Data input Data output High-impedance
µPD78P018FY
Read mode Read mode set. Output disable mode Data output becomes high-impedance, output disable mode, set. Therefore, allows data read from device controlling pin, multiple µPD78P018FYs connected data bus. Standby mode Standby mode set. this mode, data outputs become high-impedance irrespective status. Page data latch mode Page data latch mode beginning page write mode. this mode, page 4-byte data latched internal address/data latch circuit. Page write mode After page bytes addresses data latched page data latch mode, page write executed applying 0.1-ms program pulse (active low) with Then, program verification performed, set. programming performed one-time program pulse, write verification operations should executed repeatedly. Byte write mode Byte write executed when 0.1-ms program pulse (active low) applied with Then, program verification performed set. programming performed one-time program pulse, write verification operations should executed repeatedly. Program verify mode Program verify mode set. this mode, check write operation performed correctly, after write. Program inhibit mode Program inhibit mode used when pin, pin, pins multiple µPD78P018FYs connected parallel write performed those devices. When write operation performed, page write mode byte write mode described above used. this time, write performed device which driven high.
µPD78P018FY
PROM Write Procedure Figure 5-1. Page Program Mode Flow Chart
Start Address 12.5
Latch Address Address Latch Address Address Latch Address Address Address Address Latch
X=X+1 0.1-ms program pulse
Verify bytes Pass Address Pass
Fail
Verify bytes Pass Write
Fail
Defective product
Start address Program last address
µPD78P018FY
Figure 5-2. Page Program Mode Timing
Page Data Latch
Page Program
Program Verify
Hi-Z Data Input Data Output
µPD78P018FY
Figure 5-3. Byte Program Mode Flow Chart
Start Address 12.5
X=X+1 0.1-ms program pulse Address Address Fail Verify Pass Address Pass Fail
Verify bytes Pass Write
Defective product
Start address Program last address
µPD78P018FY
Figure 5-4. Byte Program Mode Timing
Program
Program Verify
Data Input
Hi-Z
Data Output
Cautions should applied before after VPP. must exceed +13.5 including overshoot. Removing reinserting while +12.5 applied adversely affect reliability.
µPD78P018FY
PROM Read Procedure
contents PROM readable external data according read procedure shown below. RESET level, supply pin, connect other unused pins shown "PIN CONFIGURATION (Top View) PROM programming mode". Supply pins. Input address read data into pins. Read mode Output data pins. timings above steps shown Figure 5-5. Figure 5-5. PROM Read Timings
Address Input
(Input)
(Input)
Hi-Z
Data Output
Hi-Z
µPD78P018FY
PROGRAM ERASURE (FOR µPD78P018FYDW, 78P018FYKK-S)
µPD78P018FYDW, 78P018FYKK-S capable erasing (FFH) contents data written program memory rewriting. When erasing contents data, irradiate light having wavelength less than about erasure window. Normally, irradiate ultraviolet rays wavelength. Volume irradiation required completely erase contents data follows: intensity erasing time: s/cm2 more Erasing time: min. longer (When lamp mW/cm2 used. However, longer time needed because deterioration performance lamp, contamination erasure window, etc.) When erasing contents data, lamp within from erasing window. Further, filter provided lamp, irradiate ultraviolet rays after removing filter.
OPAQUE FILM ERASURE WINDOW (FOR µPD78P018FYDW, 78P018FYKK-S)
protect from unintentional erasure rays other than that lamp erasing EPROM contents, protect internal circuit other than EPROM from misoperating rays, cover erasure window with opaque film when EPROM contents erasure performed.
ONE-TIME PROM VERSION SCREENING
one-time PROM versions (µPD78P018FYCW, 78P018FYGC-AB8) cannot tested completely before shipped, because structure. recommended perform screening verify PROM after writing necessary data performing high-temperature storage under condition below.
Storage Temperature 125°C
Storage Time hours
provides one-time PROM writing, marking, screening, verify service products designated "QTOP Microcontrollers." details, contact sales representative.
µPD78P018FY
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings 25°C)
Parameter Supply voltage Symbol AVDD AVREF AVSS Input voltage P04, P17, P27, P37, P47, P57, P67, XT2, RESET Output voltage Analog input voltage Output current, high Total P17, P27, Total P03, P47, P57, Output current, Peak value value Total P47, Peak value value Total P03, P56, P57, IOLNote Total P03, Total P17, P27, Operating ambient temperature Storage temperature Peak value value Peak value value Peak value value Analog input Open-drain PROM programming mode -0.3 AVSS -0.3 -0.3 +13.5 -0.3 Test Conditions Ratings -0.3 +7.0 -0.3 +13.5 -0.3 -0.3 -0.3 +0.3 Unit
Tstg
+150
Note value should calculated follows: [rms value] [Peak value] Duty Caution Product quality suffer absolute maximum rating exceed even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded.
µPD78P018FY
Capacitance 25°C,
Parameter Input capacitance capacitance Unmeasured pins returned Symbol Test Conditions Unmeasured pins returned P03, P17, P27, P37, P47, P57, MIN. TYP. MAX. Unit
Remark
Unless otherwise specified, characteristics alternate-function pins same those port functions.
Main System Clock Oscillator Characteristics +85°C,
Resonator Ceramic resonator Recommended Circuit
Parameter Oscillation frequency Note Oscillation stabilization time Note Oscillation frequency Note Oscillation stabilization time Note input frequency Note input high-/low-level width (tXH tXL)
Test Conditions After reaches oscillator voltage range MIN.
MIN.
TYP.
MAX.
Unit
Crystal resonator
External clock
10.0
µPD74HCU04
Notes Indicates only oscillator characteristics. Refer Characteristics instruction execution time. Time required stabilize oscillation after reset STOP mode release. Cautions When using main system clock oscillator, wire area enclosed broken line above figures follows avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always keep ground point oscillator capacitor same potential VSS. ground capacitor ground pattern which high current flows.
fetch signals from oscillator. When main system clock stopped system operated subsystem clock, subsystem clock should switched again main system clock after oscillation stabilization time secured program.
µPD78P018FY
Subsystem Clock Oscillator Characteristics +85°C,
Resonator Crystal resonator Recommended Circuit
Parameter Oscillation frequency (fXT) Note
Test Conditions
MIN.
TYP.
MAX.
Unit
32.768
Oscillation Note stabilization time input frequency (fXT) Note input high-/low-level width (tXTH tXTL)
External clock
µPD74HCU04
Notes Indicates only oscillator characteristics. Refer Characteristics instruction execution time. Time required stabilize oscillation after reaches oscillator voltage MIN. Cautions When using subsystem clock oscillator, wire area enclosed broken line above figures follows avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always keep ground point oscillator capacitor same potential VSS. ground capacitor ground pattern which high current flows. fetch signals from oscillator.
subsystem clock oscillator low-amplitude circuit order achieve consumption current, more prone malfunction noise than main system clock oscillator. Particular care therefore required with wiring method when subsystem clock used.
µPD78P018FY
RECOMMENDED OSCILLATOR CONSTANTS Main system clock: Ceramic resonator +85°C)
Recommended Frequency Oscillator Constants (pF) (pF) 4.00 4.00 4.19 4.19 5.00 5.00 8.00 8.00 8.38 8.38 10.00 10.00 4.00 4.00 4.19 4.19 5.00 5.00 8.00 8.00 8.38 8.38 10.00 10.00 On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip Oscillation Voltage Range MIN. MAX. On-chip capacitor, surface mounting type On-chip capacitor, insertion type On-chip capacitor, surface mounting type On-chip capacitor, insertion type On-chip capacitor, surface mounting type On-chip capacitor, insertion type On-chip capacitor, surface mounting type On-chip capacitor, insertion type On-chip capacitor, surface mounting type On-chip capacitor, insertion type On-chip capacitor, surface mounting type On-chip capacitor, insertion type Insertion type On-chip capacitor, insertion type Insertion type On-chip capacitor, insertion type Insertion type On-chip capacitor, insertion type Insertion type On-chip capacitor, insertion type Insertion type On-chip capacitor, insertion type Insertion type On-chip capacitor, insertion type
Manufacturer
Name
Remarks
CCR4.0MC3 FCR4.0MC5 CCR4.19MC3 FCR4.19MC5 CCR5.00MC3 FCR5.00MC5 CCR8.00MC FCR8.00MC5 CCR8.38MC FCR8.38MC5 CCR10.00MC FCR10.00MC5
Murata Mfg. Co., Ltd.
CSA4.00MG CST4.00MGW CSA4.19MG CST4.19MGW CSA5.00MG CST5.00MGW CSA8.00MTZ CST8.00MTW CSA8.38MTZ CST8.38MTW CSA10.00MTZ CST10.00MTW
Caution oscillator constants oscillation voltage range indicate conditions stable oscillation, guarantee oscillation frequency accuracy. oscillation frequency accuracy required actual circuits, necessary adjust oscillation frequency oscillator actual circuit. Please contact directly manufacturer resonator used.
µPD78P018FY
Main system clock: Ceramic resonator +80°C)
Recommended Oscillation Frequency Oscillator Constants Voltage Range (MHZ) (pF) (pF) MIN. MAX. 4.00 4.00 4.00 4.00 5.00 5.00 5.00 5.00 8.00 10.00 On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip
Manufacturer
Name
Remarks
Kyocera Corporation
PBRC4.00A PBRC4.00B KBR-4.00MSA KBR-4.00MKS PBRC5.00A PBRC5.00B KBR-5.00MSA KBR-5.00MKS KBR-8M KBR-10M
Surface mounting type On-chip capacitor, surface mounting type Insertion type On-chip capacitor, insertion type Surface mounting type On-chip capacitor, surface mounting type Insertion type On-chip capacitor, insertion type Insertion type Insertion type
Caution oscillator constants oscillation voltage range indicate conditions stable oscillation. oscillation frequency precision guaranteed. applications requiring oscillation frequency precision, oscillation frequency must adjusted implementation circuit. details, please contact directly manufacturer resonator will use.
µPD78P018FY
Characteristics +85°C,
Parameter Symbol Test Conditions P17, P21, P23, P32, P37, P47, P57, VIH2 P03, P20, P22, P27, P33, P34, RESET VIH3 (N-ch open-drain) VIH4 0.8VDD 0.8VDD 0.85V 0.7VDD 0.8VDD VIH5 XT1/P04, Note Input voltage, VIL1 P17, P21, P23, P32, P37, P47, P57, VIL2 P03, P20, P22, P27, P33, P34, RESET VIL3 VIL4 VIL5 XT1/P04, Note Output voltage, high Output voltage, P03, P17, P27, P37, P47, VOL2 SB0, SB1, SCK0 VOL1 VOH1 -100 P57, opendrain pulled-up VOL3 0.2VDD 0.2V 0.2VDD 0.15VDD 0.3VDD 0.2VDD 0.1VDD 0.2VDD 0.1VDD 0.1VDD 0.8VDD 0.9VDD 0.9VDD 0.3VDD MIN. 0.7VDD TYP. MAX. Unit
Input voltage, VIH1 high
Note
When using XT1/P04 P04, input inverse phase should input using inverter.
Remark Unless specified otherwise, characteristics alternate-function pins same those port pins.
µPD78P018FY
Characteristics +85°C,
Parameter Symbol Test Conditions P03, P17, P27, P37, P47, P57, P67, RESET ILIH2 ILIH3 Input leakage ILIL1 current, XT1/P04, P03, P17, P27, P37, P47, P57, P67, RESET ILIL2 ILIL3 Output leakage ILOH current, high Output leakage ILOL current, Software pull-up resistor P03, P17, P27, P37, P47, P57, VOUT VOUT XT1/P04, Note MIN. TYP. MAX. Unit
Input leakage ILIH1 current, high
Note pins P63, low-level input leak current -200 (MAX.) flows only during clocks (no-wait time) after instruction been executed read port (P6) port mode register (PM6). Outside period clocks following execution read-out instruction, current (MAX.). Remark Unless specified otherwise, characteristics alternate-function pins same those port pins.
µPD78P018FY
Characteristics +85°C,
Parameter Supply current
Note
Symbol IDD1 10.00-MHz crystal
Test Conditions Note
Note Note Note
MIN.
TYP. 12.0 0.05 0.05
MAX. 24.0
Unit
oscillation operation mode IDD2 10.00-MHz crystal oscillation HALT mode IDD3 32.768-kHz crystal oscillation operation mode
Note
Note
IDD4
32.768-kHz crystal oscillation HALT mode
IDD5
STOP mode when using feedback resistor IDD6 STOP mode when using feedback resistor
Notes Refers current flowing pin. current flowing on-chip pull-up resistors, ports, converter included. When operating high-speed mode (when processor clock control register (PCC) 00H) When operating low-speed mode (when 04H) When main system clock operation stopped.
µPD78P018FY
Characteristics Basic Operation +85°C,
Parameter Cycle time (Min. instruction execution time) Operating with subsystem clock input width TI1, input frequency TI1, input width Interrupt request input high-/low-level width RESET lowlevel width tRSL INTP1 INTP3, tINTH, tINTL INTP0 tTIH1, high-/low-level tTIL1 2/fsam+0.1 Note 2/fsam+0.2 2/fsam+0.5 Note
Note
Symbol
Test Conditions Operating with main system clock
MIN. Note sam+0.1
Note
TYP.
MAX.
Unit
tTIH0,
high-/low-level tTIL0 fTI1
sam+0.2 Note sam+0.5 Note
Notes Value when external clock used. This value (MIN.) when crystal resonator used. combination with bits (SCS0) (SCS1) sampling clock select register (SCS), selection fsam possible between fX/2N+1, fX/64, fX/128 (when main system clock operation)
60.0
10.0
Operation Guaranteed Range
Cycle Time
Supply Voltage
µPD78P018FY
Read/Write Operation +85°C,
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from tRDD1 tRDD2 Read data hold time low-level width tRDH tRDL1 tRDL2 WAIT input time from tRDWT1 tRDWT2 WAIT input time from WAIT low-level width Write data setup time Write data hold time low-level width delay time from ASTB delay time from ASTB ASTB delay time from external fetch Address hold time from external fetch Write data output time from tWRWT tWTL tWDS tWDH tWRL tASTRD tASTWR tRDAST tRDADH tRDWD Load resistance (0.5+2n)tCY+10 (2.5+2n)tCY 0.5tCY-30 1.5tCY-30 tCY-10 0.5tCY+5 0.5tCY+15 Write data output time from tWRWD Address hold time from tWRADH delay time from WAIT delay time from WAIT tWTRD tWTWR 0.5tCY 0.5tCY tCY+40 tCY+50 0.5tCY+30 0.5tCY+90 tCY+60 tCY+100 2.5tCY+80 2.5tCY+80 (1.5+2n)tCY-20 (2.5+2n)tCY-20 0.5tCY 1.5tCY 0.5tCY (2+2n)tCY Test Conditions MIN. 0.5tCY 0.5tCY-30 (2.5+2n)tCY-50 (3+2n)tCY-100 (1+2n)tCY-25 (2.5+2n)tCY-100 MAX. Unit
Remarks TCY/4 indicates number waits.
µPD78P018FY
Serial Interface +85°C, Serial Interface Channel 3-wire serial mode (SCK0. Internal clock output)
Parameter SCK0 cycle time Symbol tKCY1 Test Conditions MIN. 1600 3200 4800 SCK0 high-/low-level width setup time SCK0) tKH1, tKL1 tSIK1 tKCY1/2-50 tKCY1/2-100 hold time (from SCK0) output delay time from SCK0 tKSO1 Note tKSI1 TYP. MAX. Unit
Note load capacitance SCK0 output lines. (ii) 3-wire serial mode (SCK0. External clock input)
Parameter SCK0 cycle time Symbol tKCY2 Test Conditions MIN. 1600 3200 4800 SCK0 high-/low-level width tKH2, tKL2 1600 2400 setup time SCK0) hold time (from SCK0) output delay time from SCK0 SCK0 rise/fall time tR2, When external device expansion function used When external When 16-bit timer device expansion output function function used used When 16-bit timer output function used 1000 tKSO2 Note tKSI2 tSIK2 TYP. MAX. Unit
Note load capacitance output line.
µPD78P018FY
(iii) 2-wire serial mode (SCK0. Internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 Test Conditions SCK0 high-level width SCK0 low-level width SB0, setup time SCK0) tKH3 tKL3 tSIK3
Note
MIN. 1600 3200 4800 tKCY3/2-160 tKCY3/2-190 tKCY3/2-50 tKCY3/2-100
TYP.
MAX.
Unit
SB0, hold time (from SCK0)
tKSI3
SB0, output delay tKSO3 time from SCK0
Note load resistance load capacitance SCK0, SB0, output lines. (iv) 2-wire serial mode (SCK0. External clock input)
Parameter SCK0 cycle time Symbol tKCY4 Test Conditions SCK0 high-level width tKH4 SCK0 low-level width tKL4 SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output delay tKSO4 time from SCK0 SCK0 rise/fall time tR4,
Note
MIN. 1600 3200 4800 1300 2100 1600 2400 tKCY4/2
TYP.
MAX.
Unit
tSIK4 tKSI4
When external device expansion function used When external device expansion function used When 16-bit timer output function used When 16-bit timer output function used
1000
Note load resistance load capacitance output lines.
µPD78P018FY
mode (SCL. Internal clock output)
Parameter cycle time Symbol tKCY5 Test Conditions Note high-level width low-level width tKH5 tKL5 MIN. tKCY5-160 tKCY5-190 tKCY5-50 tKCY5-100 SDA0, SDA1 setup time tSIK5 SCL) SDA0, SDA1 hold time tKSI5 (from SCL) SDA0, SDA1 output delay time from SDA0, SDA1 from tKSB SDA0, SDA1 from from SDA0, SDA1 tSBK SDA0, SDA1 high-level tSBH width tKSO5 TYP. MAX. Unit
Note load resistance load capacitance SCL, SDA0, SDA1 output lines. (vi) mode (SCL. External clock input)
Parameter cycle time high-/low-level width SCL) SDA0, SDA1 hold time tKSI6 (from SCL) SDA0, SDA1 output delay time from SDA0, SDA1 from tKSB SDA0, SDA1 from from SDA0, SDA1 tSBK SDA0, SDA1 high-level tSBH width rise/fall time tR6, When external device expansion function used When external device expansion function used When 16-bit timer output function used When 16-bit timer output function used 1000 tKSO6
Note
Symbol tKCY6 tKH6, tKL6
Test Conditions
MIN. 1000
TYP.
MAX.
Unit
SDA0, SDA1 setup time tSIK6
Note load resistance load capacitance SDA0 SDA1 output lines.
µPD78P018FY
Serial Interface Channel 3-wire serial mode (SCK1. Internal clock output)
Parameter SCK1 cycle time Symbol tKCY7 Test Conditions MIN. 1600 3200 4800 SCK1 high-/low-level width setup time SCK1) tKH7, tKL7 tSIK7 tKCY7/2-50 tKCY7/2-100 hold time (from SCK1) output delay time from SCK1 tKSO7 Note tKSI7 TYP. MAX. Unit
Note load capacitance SCK1 output lines. (ii) 3-wire serial mode (SCK1. External clock input)
Parameter SCK1 cycle time Symbol tKCY8 Test Conditions MIN. 1600 3200 4800 SCK1 high-/low-level width tKH8, tKL8 1600 2400 setup time SCK1) hold time (from SCK1) output delay time from SCK1 SCK1 rise/fall time tR8, When external device expansion function used When external device expansion function used When 16-bit timer output function used When 16-bit timer output function used 1000 tKSO8 Note tKSI8 tSIK8 TYP. MAX. Unit
Note load capacitance output line.
µPD78P018FY
(iii) 3-wire serial mode with automatic transmit/receive function (SCK1. Internal clock output)
Parameter SCK1 cycle time Symbol tKCY9 Test Conditions MIN. 1600 3200 4800 SCK1 high-/low-level width setup time SCK1) tKH9, tKL9 tSIK9 tKCY9/2-50 tKCY9/2-100 hold time (from SCK1) output delay time from SCK1 from SCK1 Strobe signal high-level width tSBD tSBW tKCY9/2-100 tKCY9-30 tKCY9-60 tKCY9-90 Busy signal setup time tBYS busy signal detection timing) Busy signal hold time (from busy signal detection timing) tBYH SCK1 from busy inactive tSPS 2tKCY9 tKCY9/2+100 tKCY9+30 tKCY9+60 tKCY9+90 tKSO9 Note tKSI9 TYP. MAX. Unit
Note load capacitance SCK1 output lines.
µPD78P018FY
(iv) 3-wire serial mode with automatic transmit/receive function (SCK1. External clock input)
Parameter SCK1 cycle time Symbol tKCY10 Test Conditions MIN. 1600 3200 4800 SCK1 high-/low-level width tKH10 tKL10 1600 2400 setup time SCK1) hold time (from SCK1) output delay time from SCK1 SCK1 rise/fall time tR10, tF10 When external device expansion function used When external device expansion function used 1000 tKSO10 Note tKSI10 tSIK10 TYP. MAX. Unit
Note load capacitance output line.
µPD78P018FY
Timing Test Point (Excluding Input)
Test Points
Clock Timing
1/fX
Input
VIH4 (MIN.) VIL4 (MAX.)
1/fXT tXTL tXTH
Input
VIH5 (MIN.) VIL5 (MAX.)
Timing
tTIL0
tTIH0
1/fTI1 tTIL1 tTIH1
TI1,TI2
µPD78P018FY
Read/Write Operation External fetch wait):
Higher 8-Bit Address tADD1 Hi-Z
tADS tASTH ASTB
Lower 8-Bit Address
Operation Code tRDD1 tRDADH tRDAST
tADH
tASTRD tRDL1 tRDH
External fetch (Wait insertion):
Higher 8-Bit Address tADD1
tADS tASTH ASTB
Lower 8-Bit Address
Hi-Z tRDD1
Operation Code tRDADH tRDAST
tADH
tASTRD WAIT tRDWT1 tWTL tWTRD tRDL1 tRDH
µPD78P018FY
External data access wait):
tADD2 tADS tASTH ASTB
Lower 8-Bit Address
Higher 8-Bit Address
Hi-Z tRDD2
Read Data
Hi-Z
Write Data
Hi-Z
tADH
tRDH
tASTRD tASTWR tWRL tRDL2 tRDWD tWRWD tWDS tWDH tWRADH
External data access (Wait insertion):
tADD2 tADS tADH tASTH ASTB tASTRD tRDL2 tASTWR WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR tWRL tWRADH tRDWD tWDS tWRWD tWDH tRDD2 tRDH
Lower 8-Bit Address
Higher 8-Bit Address Hi-Z Hi-Z Hi-Z
Read Data
Write Data
µPD78P018FY
Serial Transfer Timing 3-wire serial mode:
tKCYm tKLm tKHm
SCK0,SCK1
tSIKm
tKSIm
SI0,SI1
Input Data
tKSOm
SO0,SO1
Output Data
2-wire serial mode:
tKCY3,4 tKL3,4 SCK0 tKSO3,4 SB0, tSIK3,4 tKSI3,4 tKH3,4
mode:
tKL5, SDA0, SDA1 tSBH tSBK tKH5, tKSI5, tSIK5, tKSO5, tKCY5, tKSB tSBK tKSB
µPD78P018FY
3-wire serial mode with automatic transmit/receive function:
tSIK9,10 tKSO9,10
tKSI9,10 tKH9,10 tF10
SCK1 tKL9,10 tKCY9,10 tR10 tSBD tSBW
3-wire serial mode with automatic transmit/receive function (busy processing):
SCK1
Note
tBYS
Note
tBYH
Note
tSPS
BUSY (Active High)
Note signal actually driven here; shown such indicate timing.
µPD78P018FY
Converter Characteristics +85°C, AVDD AVSS
Parameter Resolution Overall error Note AVREF AVDD AVREF Conversion time tCONV AVREF AVDD AVREF Sampling time Analog input voltage Reference voltage AVREF resistance tSAMP VIAN AVREF RAIREF 19.1 38.2 24/fX AVSS AVREF AVDD Symbol Test Conditions MIN. TYP. MAX. Unit
Note Overall error excluding quantization error (±1/2 LSB). indicated ratio full-scale value. Data Memory STOP Mode Supply Voltage Data Retention Characteristics +85°C)
Parameter Data retention supply voltage Data retention supply current IDDDR VDDDR Subsystem clock stops feedback resistor disconnected Release signal time tSREL Oscillation stabilization tWAIT wait time Release RESET Release interrupt request Note
Symbol VDDDR
Test Conditions
MIN.
TYP.
MAX.
Unit
Note combination with bits (OSTS0 OSTS2) oscillation stabilization time select register (OSTS), selection 213/fX 215/fX 218/fX possible. Data Retention Timing (STOP Mode Release RESET)
Internal Reset Operation HALT Mode STOP Mode Data Retention Mode Operating Mode
STOP Instruction Execution
VDDDR
tSREL
RESET tWAIT
µPD78P018FY
Data Retention Timing (Standby Release Signal: STOP Mode Release Interrupt Request Signal)
HALT Mode STOP Mode Data Retention Mode Operating Mode
VDDDR STOP Instruction Execution
tSREL
Standby Release Signal (Interrupt Request) tWAIT
Interrupt Input Request Timing
tINTL INTP0 INTP2
tINTH
tINTL
INTP3
RESET Input Timing
tRSL
RESET
µPD78P018FY
PROM PROGRAMMING CHARACTERISTICS Characteristics PROM Write Mode 5°C, 0.25 12.5
Parameter Input voltage, high Input voltage, Output voltage, high Output voltage, Input leakage current supply voltage supply voltage supply current supply current Symbol Symbol 12.2 6.25 12.5
Note
Test Conditions
MIN. 0.7VDD
TYP.
MAX. 0.3VDD
Unit
12.8 6.75
Note
Corresponding µPD27C1001A symbol
PROM Read Mode 5°C,
Parameter Input voltage, high Input voltage, Output voltage, high Symbol VOH1 VOH2 Output voltage, Input leakage current Output leakage current supply voltage supply voltage supply current supply current Symbol VOH1 VOH2 ICCA1 VIL, -100 VOUT VDD,
Note
Test Conditions
MIN. 0.7VDD
TYP.
MAX. 0.3VDD
Unit
Note
Corresponding µPD27C1001A symbol
µPD78P018FY
Characteristics PROM Write Mode Page program mode 5°C, 0.25 12.5
Parameter Address setup time setup time setup time Input data setup time Address hold time (from Symbol tOES tCES tAHL tAHV Input data hold time (from Data output float delay time from setup time setup time Program pulse width Valid data delay time from pulse width during data latching setup time hold time hold time tVPS tVDS tPGMS tCEH tOEH Symbol Note tOES tCES tAHL tAHV tVPS tVCS tPGMS tCEH tOEH Test Conditions MIN. 0.095 0.105 TYP. MAX. Unit
Note
Corresponding µPD27C1001A symbol Byte program mode 5°C, 0.25 12.5
Parameter Symbol tOES tCES tVPS tVDS tOEH Symbol Note tOES tCES tVPS tVCS Test Conditions MIN. 0.095 0.105 TYP. MAX. Unit
Address setup time PGM) setup time setup time PGM) Input data setup time PGM) Address hold time (from Input data hold time (from PGM) Data output float delay time from setup time PGM) setup time PGM) Program pulse width Valid data delay time from hold time
Note
Corresponding µPD27C1001A symbol
µPD78P018FY
PROM Read Mode
Parameter Data output time from address Data output delay time from Data output delay time from Data output float delay time from Data hold time from address Symbol tACC Symbol Note tACC Test Conditions MIN. TYP. MAX. Unit
Note
Corresponding µPD27C1001A symbol
PROM Programming Mode Setting 25°C,
Parameter PROM programming mode setup time Symbol tSMA Test Conditions MIN. TYP. MAX. Unit
PROM Write Mode Timing (Page program mode)
Page Data Latch Page Program Program Verify
Hi-Z Hi-Z tPGMS tVPS tVDS tCES tOES tCEH tOEH Data Input Data Output Hi-Z tAHL tAHV
µPD78P018FY
PROM Write Mode Timing (Byte program mode)
Program Program Verify
Hi-Z Data Input Hi-Z Data Output Hi-Z
Cautions must applied before after VPP. must exceed +13.5 including overshoot. Removing reinserting while +12.5 applied adversely affect reliability. PROM Read Mode Timing
Effective Address
Note Note
Data Output
Note
Hi-Z
Hi-Z
Notes When reading within tACC range, input delay time from fall time must maximum tACC time from point which either (whichever first) reaches VIH.
µPD78P018FY
PROM Programming Mode Setting Timing
RESET
Effective Address
µPD78P018FY
CHARACTERISTIC CURVE (REFERENCE VALUE)
(Main System Clock: 10.0 MHz)
10.0
HALT Oscillation, Halt)
Supply Current [mA]
0.05
HALT Halt, Oscillation)
0.01
0.005 10.0 32.768
0.001 Supply Voltage
µPD78P018FY
PACKAGE DRAWINGS
PLASTIC SHRINK (750 mils)
NOTE Each lead centerline located within 0.17 (0.007 inch) true position (T.P.) maximum material condition. Item center leads when formed parallel.
ITEM
MILLIMETERS 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.50±0.10 MIN. 3.2±0.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25+0.10 -0.05 0.17 0~15°
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020+0.004 -0.005 0.035 MIN. 0.126±0.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010+0.004 -0.003 0.007 0~15° P64C-70-750A,C-1
Remark
dimensions materials (Engineering Sample) versions same those mass-produced versions.
µPD78P018FY
CERAMIC SHRINK (750 mils)
NOTES Each lead centerline located within 0.25 (0.010 inch) true position (T.P.) maximum material condition. Item center leads when formed parallel.
ITEM
MILLIMETERS 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.46±0.05 MIN. 3.5±0.3 MIN. 5.08 MAX. 19.05 (T.P.) 18.8 0.25±0.05 0.25 0~15°
INCHES 2.310 MAX. 0.070 MAX. 0.070 (T.P.) 0.018±0.002 0.031 MIN. 0.138±0.012 0.039 MIN. 0.118 0.200 MAX. 0.750 (T.P.) 0.740 0.010 +0.002 -0.003 0.010 0~15°
8.89
0.350
P64DW-70-750A-1
µPD78P018FY
PLASTIC (14x14)
detail lead
NOTE Controlling dimension
ITEM MILLIMETERS 17.6±0.4 14.0±0.2 14.0±0.2 17.6±0.4 0.37 +0.08 -0.07 0.15 (T.P.) 1.8±0.2 0.8±0.2 0.17 +0.08 -0.07 0.10 2.55±0.1 0.1±0.1 5°±5° 2.85 MAX. INCHES 0.693±0.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.693±0.016 0.039 0.039 0.015 +0.003 -0.004 0.006 0.031 (T.P.) 0.071±0.008 0.031 +0.009 -0.008 0.007 +0.003 -0.004 0.004 0.100±0.004 0.004±0.004 5°±5° 0.113 MAX. P64GC-80-AB8-4
millimeter.
Each lead centerline located within 0.15 (0.006 inch) true position (T.P.) maximum material condition.
Remark
dimensions materials (Engineering Sample) versions same those mass-produced versions.
µPD78P018FY
CERAMIC WQFN
X64KW-80A1
NOTE Each lead centerline located within 0.08 (0.003 inch) true position (T.P.) maximum material condition. ITEM MILLIMETERS 14.0 0.18 13.4 13.4 14.0 0.18 1.84 3.56 MAX. 0.51 0.08 (T.P.) 0.15 10.8 0.75 0.15 0.10 INCHES 0.551 0.007 0.528 0.528 0.551 0.007 0.072 0.141 MAX. 0.02 0.004 0.003 0.031 (T.P.) 0.039+0.007 -0.006 0.012 0.039 0.039 0.118 0.425 0.055 0.03+0.006 -0.007 0.004
µPD78P018FY
RECOMMENDED SOLDERING CONDITIONS
µPD78P018FY should soldered mounted under following recommended conditions. recommended soldering conditions, refer document "Semiconductor Device Mounting Technology Manual" (C10535E). soldering methods conditions other than those recommended below, contact your sales representative. Table 12-1. Surface Mounting Type Soldering Conditions
µPD78P018FYGC-AB8: 64-pin Plastic
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: seconds Max. 210°C higher), Count: Three times less Package peak temperature: 215°C, Time: seconds Max. 200°C higher), Count: Three times less Solder bath temperature: 260°C, Time: seconds Max., Count: Once, Preheating temperature: 120°C Max. (package surface temperature) temperature: 300°C Max., Time: seconds Max. (per row) Symbol IR35-00-3
VP15-00-3
Wave soldering
WS60-00-1
Partial heating
Caution different soldering methods together (except partial heating). Table 12-2. Insertion Type Soldering Conditions
µPD78P018FYCW: 64-pin Plastic Shrink (750 mils) µPD78P018FYDW: 64-pin Ceramic Shrink (with window) (750 mils)
Soldering Method Wave soldering (pin only) Partial heating Soldering Conditions Solder temperature: 260°C Max., Time: seconds Max.
temperature: 300°C Max., Time: seconds Max. (per pin)
Caution
Apply wave soldering only pins careful bring solder into direct contact with package.
µPD78P018FY
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using µPD78P018FY. Read Cautions using developing tools reference. Language Processing Software
RA78K/0 CC78K/0 DF78014 CC78K/0-L Assembler package common 78K/0 Series compiler package common 78K/0 Series Device file common µPD78018F Subseries compiler library source file common 78K/0 Series
PROM Writing Tools
PG-1500 PA-78P018CW PA-78P018GC PA-78P018KK-S PG-1500 controller PROM programmer Programmer adapter connected PG-1500
PG-1500 control program
Debugging Tool When using in-circuit emulator IE-78K0-NS
IE-78K0-NS IE-70000-MC-PS-B IE-70000-98-IF-C IE-70000-CD-IF-A IE-70000-PC-IF-C IE-70000-PCI-IF IE-78018-NS-EM1 NP-64CW NP-64GC EV-9200GC-64 ID78K0-NS SM78K0 DF78014 In-circuit emulator common 78K/0 Series Power supply unit IE-78K0-NS Interface adapter required when using PC-9800 series host machine (excluding notebook PCs, supported) card interface cable required when using notebook PC-9800 series host machine (PCMCIA socket supported) Interface adapter when using PC/ATcompatible host machine (ISA supported) Adapter when using that incorporates host machine Emulation board common µPD78018F Subseries Emulation probe 64-pin plastic shrink type) Emulation probe 64-pin plastic (GC-AB8 type) Socket mounted target system board made 64-pin plastic (GC-AB8 type) Integrated debugger IE-78K0-NS System simulator common 78K/0 Series Device file common µPD78018F Subseries
µPD78P018FY
When using in-circuit emulator IE-78001-R-A
IE-78001-R-A IE-70000-98-IF-C IE-70000-PC-IF-C IE-78000-R-SV3 IE-70000-PCI-IF IE-78018-NS-EM1 IE-78K0-R-EX1 EP-78240CW-R EP-78240GC-R EV-9200GC-64 ID78K0 SM78K0 DF78014 In-circuit emulator common 78K/0 Series Interface adapter required when using PC-9800 series host machine (excluding notebook PCs, supported) Interface adapter required when using PC/AT compatible host machine (ISA supported) Interface adapter cable when using host machine Adapter when using that incorporates host machine Emulation board common µPD78018F Subseries Emulation probe conversion board necessary IE-78018-NS-EM1 IE-78001-R-A Emulation probe 64-pin plastic shrink type) Emulation probe 64-pin plastic (GC-AB8 type) Socket mounted target system board made 64-pin plastic (GC-AB8 type) Integrated debugger IE-78001-R-A System simulator common 78K/0 Series Device file common µPD78018F Subseries
Real-time
RX78K/0 MX78K0 Real-time 78K/0 Series 78K/0 Series
µPD78P018FY
Cautions using development tools ID-78K0-NS, ID78K0, SM78K0 used combination with DF78014. CC78K/0 RX78K/0 used combination with RA78K/0 DF78014. NP-64CW NP-64GC products made Naitou Densei Machidaseisakusho (TEL: +81-44-8223813). Contact distributor regarding purchase these products. third party development tools, 78K/0 Series Selection Guide (U11126E). host machine suitable each software follows:
Host Machine [OS] Software RA78K/0 CC78K/0 PG-1500 Controller ID78K0-NS ID78K0 SM78K0 RX78K/0 MX78K0 PC-9800 series [WindowsTM] PC/AT compatible [Japanese/English Windows] Note Note
Note
HP9000 series [HP-UX SPARCstation[SunOSTM, SolarisTM] NEWS(RISC) [NEWS-OSTM]
Note Note
Note
DOS-based software
µPD78P018FY
Drawing Conversion Socket (EV-9200GC-64) Recommended Footprint Figure A-1. Drawing EV-9200GC-64 (for reference only)
EV-9200GC-64-G0E ITEM MILLIMETERS 18.8 14.1 14.1 18.8 15.8 18.5 15.8 18.5 1.35 0.35 INCHES 0.74 0.555 0.555 0.74 0.118 0.031 0.236 0.622 0.728 0.236 0.622 0.728 0.315 0.307 0.098 0.079 0.053 0.014+0.004 -0.005
EV-9200GC-64
No.1 index
0.091 0.059
µPD78P018FY
Figure A-2. Recommended Footprint EV-9200GC-64 (for reference only)
EV-9200GC-64-P1E ITEM Caution MILLIMETERS 19.5 14.8 0.8±0.02 15=12.0±0.05 INCHES 0.768 0.583 0.031+0.002 -0.001 0.591=0.472 +0.003 -0.002
0.8±0.02 15=12.0±0.05 0.031+0.002 0.591=0.472 +0.003 -0.001 -0.002 14.8 19.5 6.00 0.08 6.00 0.08 0.02
2.36 0.03 1.57 0.03
0.583 0.768 0.236+0.004 -0.003 0.236+0.004 -0.003 0.197+0.001 -0.002
0.093+0.001 -0.002 0.087+0.004 -0.005 0.062+0.001 -0.002
Dimensions mount EV-9200 that target device (QFP) different some parts. recommended mount dimensions QFP, refer "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
µPD78P018FY
APPENDIX RELATED DOCUMENTS
Device Related Documents
Document Name Document Japanese U10281J U10989J U10659J U12326J U10903J U10904J U10287J U12704J U13482J English U10281E This document U10659E U12326E U12704E IEA-1289
µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Data Sheet
µPD78P018FY Data Sheet µPD78018F, 78018FY Subseries User's Manual
78K/0 Series User's Manual Instructions 78K/0 Series Instruction List 78K/0 Series Instruction
µPD78018FY Subseries Special Function Register List
78K/0 Series Application Note Basics Floating-Point Arithmetic Programs
Development Tool Documents (User's Manual) (1/2)
Document Name RA78K0 Assembler Package Operation Assembly Language Structured Assembly Language RA78K Series Structured Assembler Preprocessor CC78K0 Compiler Operation Language CC78K/0 Compiler Application Note PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS Based PG-1500 Controller Series Based IE-78K0-NS IE-78001-R-A IE-78K0-R-EX1 IE-78018-NS-EM1 EP-78240 Programming Know-How Document Japanese U11802J U11801J U11789J U12323J U11517J U11518J U13034J U11940J EEU-704 EEU-5008 prepared prepared prepared U13289J EEU-986 English U11802E U11801E U11789E EEU-1402 U11517E U11518E U13034E U11940E EEU-1291 U10540E prepared prepared prepared prepared U10332E
Caution
related documents listed above subject change without notice. sure latest version each document designing.
µPD78P018FY
Development Tool Documents (User's Manual) (2/2)
Document Japanese Reference External Part User Open Interface Specification ID78K0-NS Integrated Debugger Windows Based ID78K0 Integrated Debugger based ID78K0 Integrated Debugger based ID78K0 Integrated Debugger Windows based Reference Reference Reference Guide U12900J U11151J U11539J U11649J U12900E U11539E U11649E U10181J U10092J English U10181E U10092E
Document Name SM78K0 System Simulator Windows Based SM78K Series System Simulator
Embedded Software Documents (User's Manual)
Document Name 78K/0 Series Real-Time Basic Installation 78K/0 Series MX78K0 Basic Document Japanese U11537J U11536J U12257J English U11537E U11536E U12257E
Other Documents
Document Name Package Manual (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability/Quality Control System Guide Prevent Damages Semiconductor Devices Electrostatic Discharge (ESD) Guide Quality Assurance Semiconductor Devices Microcomputer Related Product Guide Third Parties Document Japanese C10535J C11531J C10983J C11892J U11416J English C13388E C10535E C11531E C10983E C11892E MEI-1202
Caution
related documents listed above subject change without notice. sure latest version each document designing.
µPD78P018FY
[MEMO]
µPD78P018FY
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD78P018FY
Purchase components conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
FIP, IEBus, QTOP trademarks Corporation. MS-DOS Windows either registered trademarks trademarks Microsoft Corporation United States and/or other countries. PC/AT trademarks International Business Machines Corporation. HP9000 series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. Solaris SunOS trademarks Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation.
µPD78P018FY
Regional Information
Some information contained this document vary from country country. Before using product your application, please contact office your country obtain list authorized representatives distributors. They will verify: Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J98.
µPD78P018FY
related documents indicated this publication include preliminary versions. However, preliminary versions marked such.
export these products from Japan regulated Japanese government. export some these products prohibited without governmental license. export re-export some these products from country other than Japan also prohibited without license from that country. Please call sales representative. License needed: µPD78P018FYDW, 78P018FYKK-S
customer must judge need license: µPD78P018FYCW, 78P018FYGC-AB8
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
96.5
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