Preliminary CMOS SRAM 256Kx8 Super Power Voltage Full CMOS Static

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Preliminary CMOS SRAM 256Kx8 Super Power Voltage Full CMOS Static

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K6F2008T2E Family
Preliminary CMOS SRAM
256Kx8 Super Power Voltage Full CMOS Static
Revision History
Revision History
Initial draft
Draft Date
June 2003
Remark
Preliminary
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications products. SAMSUNG Electronics will answer your questions about device. have questions, please contact SAMSUNG branch offices.
Revision June 2003
K6F2008T2E Family
256Kx8 Super Power Voltage Full CMOS Static FEATURES
Process Technology: Full CMOS Organization: 256Kx8 Power Supply Voltage: 3.6V Data Retention Voltage: 1.5V(Min) Three State Outputs Package Type: 32-TSOP1-0813.4F
Preliminary CMOS SRAM
GENERAL DESCRIPTION
K6F2008T2E families fabricated SAMSUNGs advanced Full CMOS process technology. families support industrial temperature ranges user flexibility system design. families also supports data retention voltage battery back-up operation with data retention current.
PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Range Speed(ns) Standby (ISB1, Typ) 0.5µA2) Operating (ICC1, Max) Type
K6F2008T2E-F
Industrial(-40~85°C)
2.7~3.6V
551)/70ns
32-TSOP1-0813.4F
parameter measured with 30pF test load. Typical values measured VCC=3.0V, TA=25°C 100% tested.
DESCRIPTION
I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
FUNCTIONAL BLOCK DIAGRAM
gen. Precharge circuit.
Address
32-sTSOP Type1-Forward
select
Memory array 1024 rows 256x8 columns
I/O1 I/O8
Data cont
Circuit Column select
Data cont
Name
Function
Name
Function
Address
CS1, Chip Select Input Output Enable Write Enable Input
I/O1~I/O8 Data Inputs/Outputs Power Ground
A0~A17 Address Inputs
Control logic
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision June 2003
K6F2008T2E Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C) Part Name K6F2008T2E-YF55 K6F2008T2E-YF70 Function 32-sTSOP1-F, 55ns, 3.0V/3.3V, 32-sTSOP1-F, 70ns, 3.0V/3.3V,
Preliminary CMOS SRAM
FUNCTIONAL DESCRIPTION
High-Z High-Z High-Z Dout
Mode Deselected Deselected Output Disable Read Write
Power Standby Standby Active Active Active
means dont care (Must high states)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT TSTG Ratings -0.2 VCC+0.5V -0.2 4.6V Unit K6F2008T2E-F Remark
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted recommended operating condition. Exposure absolute maximum rating conditions extended periods affect reliability.
Revision June 2003
K6F2008T2E Family
RECOMMENDED OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input voltage Symbol -0.23) Typ. 3.0/3.3
Preliminary CMOS SRAM
Vcc+0.22)
Unit
Note: Industrial Product: TA=-40 85°C, unless otherwise specified. Overshoot: Vcc+2.0V case pulse width20ns. Undershoot: -2.0V case pulse width20ns. Overshoot undershoot sampled, 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Symbol ICC1 Average operating current ICC2 Output voltage Output high voltage Standby Current(CMOS) ISB1 Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL IOL=2.1mA =-1.0mA Other inputs=Vss CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) 0VCS20.2V controlled) VIN=Vss CS1=VIH CS2=VIL OE=VIH WE=VIL, VIO=Vss Cycle time=1µs, 100% duty, IIO=0mA, CS10.2V, CS2VCC-0.2V, VIN0.2V VINVCC-0.2V Test Conditions Typ1) Unit
Typical value measured VCC=3.0V, TA=25°C, 100% tested.
Revision June 2003
K6F2008T2E Family
OPERATING CONDITIONS
TEST CONDITIONS (Test Load Test Input/Output Reference)
Input pulse level: 2.2V Input rising falling time: Input output reference voltage: 1.5V Output load (See right): CL=100pF+1TTL CL=30pF+1TTL
Preliminary CMOS SRAM
VTM3) R12)
CL1)
R23)
Including scope capacitance R1=3070, R2=3150 V=2.8V
CHARACTERISTICS(Vcc=2.7~3.6V, TA=-40 85°C)
Speed Bins Parameter List Symbol Read Cycle Time Address Access Time Chip Select Output Output Enable Valid Output Read Chip Select Low-Z Output Output Enable Low-Z Output Chip Disable High-Z Output Output Disable High-Z Output Output Hold from Address Change Write Cycle Time Chip Select Write Address Set-up Time Address Valid Write Write Write Pulse Width Write Recovery Time Write Output High-Z Data Write Time Overlap Data Hold from Write Time Write Output Low-Z
parameter measured with 30pF test load.
55ns1)
70ns
Units
tOLZ tOHZ tWHZ
DATA RETENTION CHARACTERISTICS
Item data retention Data retention current Data retention set-up time Recovery time Symbol tSDR tRDR Test Condition CS1Vcc-0.2V1) Vcc=1.5V, CS1Vcc-0.2V1) 0.22) Unit
data retention waveform
CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) CS20.2V(CS2 controlled). Typical values measured TA=25°C 100% tested.
Revision June 2003
K6F2008T2E Family
TIMING DIAGRAMS
TIMING WAVEFORM READ CYCLE(1)
Address Data Previous Data Valid
(Address Controlled, CS1=OE=VIL, WE=VIH)
Preliminary CMOS SRAM
Data Valid
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address tCO1 tHZ(1,2) tCO2
tOLZ Data Valid tOHZ
Data
NOTES (READ CYCLE)
High-Z
tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than tLZ(Min.) both given device from device device interconnection.
Revision June 2003
K6F2008T2E Family
TIMING WAVEFORM WRITE CYCLE(1) Controlled)
Address tCW(2) tWP(1) tAS(3) Data tWHZ Data Data Undefined Data Valid tWR(4)
Preliminary CMOS SRAM
TIMING WAVEFORM WRITE CYCLE(2) (CS1
Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision June 2003
K6F2008T2E Family
TIMING WAVEFORM WRITE CYCLE(3) (CS2 Controlled)
Address tAS(3) tCW(2) tWP(1) Data Data Valid tWR(4)
Preliminary CMOS SRAM
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap CS1, high write begins latest transition among goes low, going high going write earliest transition among going high, going going high, measured from begining write write. measured from going going high write. measured from address valid beginning write. measured from write address change.
DATA RETENTION WAVE FORM
controlled
2.7V tSDR Data Retention Mode tRDR
2.2V CS1VCC 0.2V
controlled
2.7V tSDR
Data Retention Mode
tRDR
0.4V CS20.2V
Revision June 2003
K6F2008T2E Family
PACKAGE DIMENSIONS
THIN SMALL OUTLINE PACKAGE TYPE (0813.4F)
Preliminary CMOS SRAM
Units: millimeters(inches)
0.20 0.008
+0.10 -0.05 +0.004 -0.002
13.40 ±0.20 0.528 ±0.008
0.10 0.004 8.40 0.331 8.00 0.315 0.25 0.010 1.00 ±0.10 0.039 ±0.004
+0.10 -0.05 0.006 +0.004 -0.002
0.50 0.0197
0.25 0.010
11.80 ±0.10 0.465 ±0.004
0.15
0.05 0.002 1.20 0.047
0~8°
0.45~0.75 0.018~0.030
0.50 0.020
Revision June 2003

Preliminary CMOS SRAM 256Kx8 Super Power Voltage Full CMOS Static

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