LC662508A, 662512A, 662516A Four-Bit Single-Chip Microcontrollers
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Ordering number EN5997
LC662508A, 662512A, 662516A
Four-Bit Single-Chip Microcontrollers with On-Chip
Overview
LC662516A, LC662512A, LC662508A 4-bit CMOS microcontrollers that integrate single chip functions required special-purpose telephone controller, including ROM, RAM, ports, serial interface, DTMF generator, timers, interrupt functions. These microcontrollers available 64-pin package.
Features Functions
On-chip capacities kilobytes, on-chip capacity bits. Fully supports LC66000 Series common instruction (128 instructions). ports: pins DTMF generator This microcontroller incorporates circuit that generate sine wave outputs, DTMF output, melody output software applications. 8-bit serial interface: Two-wire interface (16-bit data length. Supports cascade connection.) Instruction cycle time: 0.95 Powerful timer functions prescalers
Time limit timer, event counter, pulse width measurement, square wave output using 12-bit timer. Time limit timer, event counter, output, square wave output using 8-bit timer. Time base function using 12-bit prescaler. Powerful interrupt system with interrupt factors interrupt vector locations. External interrupts: factors/3 vector locations Internal interrupts: factors/5 vector locations (Waveform output internal interrupts: factors vector; shared with external expansion interrupts) Flexible functions Selectable options include 20mA drive outputs, inverter circuits, pull-up open drain circuits. Optional runaway detection function (watchdog timer) 8-bit functions Power saving functions using halt hold modes. Packages: DIP64S, QIP64E (QFP64E) Evaluation ICs: LC665099 (evaluation chip) EVA86K-ECB662500 LC66E2516(on-chip EPROM microcontroller)
SANYO products described contained herein have specifications that handle applications that require extremely high levels reliability, such life-support systems, aircraft's control systems, other applications whose failure reasonably expected result serious physical and/or material damage. Consult with your SANYO representative nearest before using SANYO products described contained herein such applications. SANYO assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO products described contained herein.
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TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O1698RM (OT) 5997-1/17
LC662508A, 662512A, 662516A
Package Dimensions
unit: 3071-DIP64S
[LC662508A,12A,16A]
unit: 3159-QFP64E
[LC662508A,12A,16A]
SANYO: DIP64S
SANYO: QFP64E
Series Organization
Type LC66304A/306A/308A LC66404A/406A/408A LC66506B/508B/512B/516B LC66354A/356A/358A LC66354S/356S/358S LC66556A/558A/562A/566A LC66354B/356B/358B LC66556B/558B/562B/566B LC66354C/356C/358C LC662104A/06A/08A LC662304A/06A/08A/12A/16A LC662508A/12A/16A LC665304A/06A/08A/12A/16A LC66E308 LC66P308 LC66E408 LC66P408 LC66E516 LC66P516 LC66E2108 LC66E2316 LC66E2516 LC66E5316 LC66P2108 LC66P2316 LC66P2516 LC66P5316 pins 52/48 capacity K/12 K/16 K/12 K/16 K/12 K/16 capacity DIP64S DIP42S DIP64S DIP42S DIP30SD DIP42S DIP64S DIP48S DIC42S with window DIP42S DIC42S with window DIP42S DIC64S with window DIP64S DIP42S DIP42S DIP64S DIP42S Package QFP48E QFP48E QFP64A QFP48E QFP44M QFP64E QFP48E QFP64E QFP48E MFP30S QFP48E QFP64E QFP48E QFC48 with window QFP48E QFC48 with window QFP48E QFC64 with window QFP64E Window evaluation versions V/0.92 Dual oscillator support V/0.95 On-chip DTMF generator versions V/0.95 Low-voltage versions V/3.92 Low-voltage high-speed versions V/0.92 V/0.92 Normal versions V/0.92 Features
K/12 K/16 K/12 K/16
K/12 K/16 EPROM OTPROM EPROM OTPROM EPROM OTPROM EPROM EPROM EPROM EPROM OTPROM OTPROM OTPROM OTPROM
DIC42S with window DIC64S with window DIC52S with window DIP30SD DIP42S DIP64S DIP48S
QFC48 with window QFC64 with window QFC48 with window MFP30S QFP48E QFP64E QFP48E
Window evaluation versions V/0.92
V/0.95
5997-2/17
LC662508A, 662512A, 662516A Assignments DIP64S
QFP64E
view
recommend reflow-soldering techniques solder-mount packages. Please consult with your Sanyo representative details process conditions package itself directly immersed dip-soldering bath (dip-soldering techniques).
5997-3/17
LC662508A, 662512A, 662516A System Block Diagram
When used, only channel used serial I/O. INT3, INT4, INT5 pins used with internal functions.
Differences between LC665XX Series LC6625XX Series
Item System differences Hardware wait time (number cycles) when hold mode cleared LC6650XB Series (Including LC66599 evaluation chip) 65536 cycles About (Tcyc LC6655XB Series 16384 cycles About (Tcyc LC6625XX Series 16384 cycles About (Tcyc
Value timer after reset (Including value after hold mode FF0. cleared) DTMF generator Inverter array Three-value inputs/comparator inputs Three-state output from Using clear halt mode External extended interrupts None (Tools handled with external devices.) None (Tools handled with external devices.) None 4-bit groups INT3, INT4, INT5. (Tools handled with external devices.) Shared with (INT2) (Tools handled with external devices.) LC66506B/08B/12B/16B V/0.92 LC66E516/P516 V/0.92 about handling Others: Normal voltage
FFC.
FFC.
None None None 4-bit groups INT3, INT4, INT5.
None specified each bit. INT3, INT4, INT5 used with internal functions.
INT2 functions
Shared with (INT2) V/0.92 LC6655XA, 56XA V/3.92 V/1.96 about handling Others: Normal voltage
Shared with (INT2)
Differences main characteristics Operating power-supply voltage operating speed (cycle time) Pull-up resistors
V/0.95
about P61, P63, voltage handling Others: normal voltage
Port voltage handling
5997-4/17
LC662508A, 662512A, 662516A Function Overview
Overview Output driver type Options State after Standby mode reset operation Hold mode: Output High (option) Halt mode: Output retained Hold mode: Output High (option) Halt mode: Output retained
ports Input output 4-bit 1-bit units support halt mode control function (This function specified units.)
Pch: Pull-up type Nch: Intermediate sink current type
Pull-up output Output level reset
ports Input output 4-bit 1-bit units
Pch: Pull-up type Nch: Intermediate sink current type
Pull-up output Output level reset
P20/SI0 P21/SO0 P22/SCK0 P23/INT0
ports Input output 4-bit 1-bit units also used serial input pin. also used serial output pin. also used serial clock SCK0 pin. also used INT0 interrupt request pin, also timer event counting pulse width measurement input. ports Input output 3-bit 1-bit units also used INT1 interrupt request. also used square wave output from timer also used square wave output from timer also support 3-state outputs.
Pch: CMOS type Nch: Intermediate sink current type Nch: +15V handling when option selected
Hold mode: Output CMOS output
Halt mode: Output retained
P30/INT1 P31/POUT0 P32/POUT1
Pch: CMOS type Nch: Intermediate sink current type Nch: +15V handling when option selected
Hold mode: Output CMOS output Halt mode: Output retained
P33/HOLD
Hold mode control input Hold mode HOLD instruction when HOLD low. hold mode, restarted setting HOLD high level. This used input port along with P32. When P33/HOLD level, will reset level pin. Therefore, applications must P33/HOLD when power first applied.
P40/INV0I P41/INV0O P42/INV1I P43/INV1O
ports Input output 4-bit 1-bit units Input output 8-bit units when used conjunction with P53. used output 8-bit data when used conjunction with P53. Dedicated inverter circuit (option)
Pch: Pull-up type CMOS type when inverter circuit option selected Nch: Intermediate sink current type
Pull-up output Output level reset Inverter circuit
High inverter (option)
Hold mode: Port output off, inverter output Halt mode: Port output retained, inverter output continues
Continued next page.
5997-5/17
LC662508A, 662512A, 662516A
Continued from preceding page.
Overview ports Input output 4-bit 1-bit units Input output 8-bit units when used conjunction with P43. used output 8-bit data when used conjunction with P43. also used INT2 interrupt request. ports Input output 4-bit 1-bit units also used serial input melody output pin. also used serial output pin. also used SCK1 serial clock dial tone output pin. also used event count input timer Output driver type Options State after Standby mode reset operation
P53/INT2
Pch: Pull-up type Nch: Intermediate sink current type
Pull-up output Output level reset
Hold mode: Output High (option) Halt mode: Output retained
P60/SI1/ML P61/S01/ P62/ SCK1/DT/ P63/PIN1
Pch: CMOS type Nch: Intermediate sink current type Nch: +15V handling when option selected (P61 only)
CMOS output (When output used, select open-drain output provide external pull-up resistor.)
Hold mode: Output Halt mode: Output retained
Output ports Output either 1-bit 4-bit units. contents output latch input input instruction.
Pch: Nch: Intermediate sink current type
Hold mode: Output Pull-up output Halt mode: Output retained Hold mode: Output High (option) Halt mode: Output retained Hold mode: Output CMOS output Halt mode: Output retained Hold mode: Output Pull-up output Halt mode: Output retained Hold mode: Output Pull-up output Halt mode: Output retained Hold mode: Port output Inverter output High inverter (option)
Output ports Output either 1-bit 4-bit units. contents output latch input input instruction.
Pch: Nch: Intermediate sink current type
CMOS output Output level reset
ports Input output either 1-bit 4-bit units.
Pch: CMOS Nch: Intermediate sink current type
Output ports Output either 1-bit 4-bit units. contents output latch input input instruction.
Pch: Nch: +15-V handling when option selected
Output ports Output either 1-bit 4-bit units. contents output latch input input instruction.
Pch: Pull-up Nch: Intermediate sink current type
PC2/INV2I PC3/INV2O
ports Output either 1-bit 4-bit units. Dedicated input ports Dedicated inverter circuits (option)
Pch: CMOS Nch: Intermediate sink current type
CMOS output Inverter circuit
Halt mode: Port output retained Inverter output retained
Continued next page.
5997-6/17
LC662508A, 662512A, 662516A
Continued from preceding page.
Overview Output driver type Options State after Standby mode reset operation Inverter Hold mode: output Halt mode: output continues Hold mode: input disabled Halt mode: input enabled Hold mode: Oscillator stops Halt mode: Oscillator continues
PD0/INV3I PD1/INV3O PD2/INV4I PD3/INV4O
Dedicated input ports Dedicated inverter circuits (option)
When inverter circuit option selected. Pch: CMOS type Nch: Intermediate sink current type
Inverter circuits
Normal input inverter (option)
Dedicated input ports
OSC1 OSC2
System clock oscillator connections When external clock used, leave OSC2 open connect clock signal OSC1. System reset input When P33/HOLD high level, level input will initialize CPU. test This must connected during normal operation. Power supply pins
Ceramic oscillator external clock selection
Option selection
TEST
Note: Pull-up type: output circuit includes transistor that pulls VDD. CMOS output: Complementary output. output: Open-drain output
User Options Ports output level reset option output levels reset ports independent 4-bit groups, selected from following options.
Option Output high reset Output reset Conditions notes four bits ports group four bits ports group
Oscillator circuit options Main clock
Option Circuit Conditions notes
External clock
OSC1
input Schmitt characteristics
Ceramic oscillator Ceramic oscillator
OSC1
OSC2
Note: There oscillator option.
5997-7/17
LC662508A, 662512A, 662516A Watchdog timer option runaway detection function (watchdog timer) selected option. Port output type options output type each (pin) ports (except P33/HOLD pin), selected individually from following options. (in1-bit units)
Option Circuit Output data Open-drain output Input data ports inputs have Schmitt characteristics. output-only ports. Conditions notes
Output data Output with built-in pull-up resistor
ports inputs have Schmitt characteristics. CMOS outputs (ports pull-up outputs (P0, distinguished drive capacity p-channel transistor.
Input data
options specified 1-bit units)
Option Circuit Conditions notes
Open-drain output
Output data
Output data Output with built-in pull-up resistor (CMOS output)
5997-8/17
LC662508A, 662512A, 662516A Inverter array circuit option following options selected each following port sets: P40/P41, P42/P43, PC2/PC3, PD0/PD1, PD2/PD3. (PDs option because they dedicated input.)
Option Circuit Output data Input data When open-drain output type selected Conditions notes
Normal port circuit Output data When built-in pull-up resistor output type selected. CMOS outputs (PC) pull-up outputs (P4) distinguished drive capacity P-channel transistor.
Input data
Input Output data high Input data
Inverter circuit Output Output data high Input data
this option selected, circuit disabled signal. Also note that open-drain port output type option high level reset option must selected.
5997-9/17
LC662508A, 662512A, 662516A LC662516 Series Option Data Area Definitions
area 3FF0H 3FF1H 3FF2H 3FF3H 3FF4H 3FF5H 3FF6H Unused Oscillator option Watchdog timer option Unused Output type Output type Output type Output type Output type Output type Output type Output type Output type Output type This must Output type Output type none, Output level reset level, high level Option specified Output level reset Option/data relationship high level, level This must external clock, ceramic oscillator
Continued next page. 5997-10/17
LC662508A, 662512A, 662516A
Continued from preceding page.
area 3FF7H 3FF8H 3FF9H 3FFAH 3FFBH 3FFCH 3FFDH Reserved. Must predefined data values. This data generated assembler. assembler used, this data Unused This must Unused This must Unused This must Unused This must Unused This must Unused This must Unused This must Unused This must disabled option Unused Unused Inverter output inverter output, none disabled, enabled This must This must Output type Unused This must Option specified Option/data relationship
Continued next page. 5997-11/17
LC662508A, 662512A, 662516A
Continued from preceding page.
area 3FFEH 3FFFH Reserved. Must predefined data values. This data generated assembler. assembler used, this data Reserved. Must predefined data values. This data generated assembler. assembler used, this data Option specified Option/data relationship
Specifications
Absolute Maximum Ratings 25°C,
Parameter Maximum supply voltage Input voltage Symbol VIN1 VIN2 Output voltage VOUT1 VOUT2 ION1 ION2 Output current -IOP1 -IOP2 -IOP3 ION1 Total current ION2 IOP1 IOP2 Allowable power dissipation Operating temperature Storage temperature Topr Tstg (except P33/HOLD pin), P61, other inputs (except P33/HOLD pin), P61, P63, other inputs (except P33/HOLD pin), PD1, P41, P43, PC3, PD1, (except P33/HOLD pin), P41, P43, PC3, PD1, (except P33/HOLD pin), (except P33/HOLD pin), +70°C: DIP64S (QFP64E) Conditions Ratings -0.3 +7.0 -0.3 +15.0 -0.3 -0.3 +15.0 -0.3 (430) +125 Unit Note
Note: Applies pins with open-drain output specifications. pins with other than open-drain output specifications, ratings column that apply. oscillator input output pins, levels free-running oscillation level allowed. Sink current (Applies when CMOS output specifications applies when inverter array specifications selected.) Source current (Applies pins except which pull-up output specifications, CMOS output specifications, inverter array specifications have been selected. Applies pins which inverter array specifications have been selected.) Contact your Sanyo representative details electrical characteristics when inverter array specifications option selected. recommend reflow soldering techniques solder mount packages. Please consult with your Sanyo representative details process conditions package itself directly immersed dip-soldering bath (dip-soldering techniques).
5997-12/17
LC662508A, 662512A, 662516A Allowable Operating Ranges +70°C, unless otherwise specified.
Parameter Operating supply voltage Memory retention supply voltage Symbol VDDH VIH1 Input high-level voltage VIH2 VIH3 VIL1 Input low-level voltage VIL2 VIL3 Operating frequency (instruction cycle time) [External clock input conditions] OSC1: Defined Figure Input clock signal OSC1 leave OSC2 open. (External clock input must selected oscillator circuit option.) OSC1: Defined Figure Input clock signal OSC1 leave OSC2 open. (External clock input must selected oscillator circuit option.) OSC1: Defined Figure Input clock signal OSC1 leave OSC2 open. (External clock input must selected oscillator circuit option.) (Tcyc) VDD: During hold mode (except P33/HOLD pin), P61, P63: N-channel output transistor P33/HOLD, P60, P62, RES, OSC1: N-channel output transistor N-channel output transistor (except P33/HOLD pin), RES, OSC1: N-channel output transistor P33/HOLD: TEST: N-channel output transistor Conditions (10) 13.5 (0.95) Unit (µs) Note
Frequency
fext
Pulse width
textH, textL
Rise fall times
textR, textF
Note: Applies pins with open-drain specifications. However, VIH2 applies P33/HOLD pin. When ports have CMOS output specifications they cannot used input pins. Applies pins with open-drain specifications. port pins with CMOS output specifications cannot used input pins. port pins with CMOS output specifications cannot used input pins. Contact Sanyo details allowable operating ranges P4,PC, pins with inverter array specifications.
5997-13/17
LC662508A, 662512A, 662516A Electrical Characteristics +70°C, unless otherwise specified.
Parameter Symbol IIH1 Conditions (except P33/HOLD pin), P61, P63: 13.5 with output transistor TEST, RES, P33/HOLD (Does apply P63.): VDD, with output transistor VDD, with output transistor Input ports other than PE3: VSS, with output transistor VSS, with output transistor (except P33/HOLD pin), (except P33/HOLD pin), -0.1 (except P33/HOLD pin): (except P33/HOLD pin): P61, P63, 13.5 Does apply P61, P63, -1.0 -1.0 -1.0 Unit Note
Input high-level current
IIH2
IIH3 IIL1 Input low-level current IIL2
Output high-level voltage
VOH1
Value output pull-up resistor
VOL1
Output low-level voltage VOL2 IOFF1 Output leakage current IOFF2 IOFF3 [Schmitt characteristics] Hysteresis voltage High-level threshold voltage Low-level threshold voltage [Ceramic oscillator] Oscillator frequency Oscillator stabilization time [Serial clock] Cycle time Input Output tCKCY tCKL tCKH tCKR, tCKF fCFS VHYS
P61, RES, OSC1 (EXT) OSC1, OSC2: Figure Figure 10.0
SCK0, SCK1: With timing Figure test load Figure
Tcyc Tcyc
Low-level high-level Input pulse widths Output Rise fall times [Serial input] Data setup time Data hold time [Serial output] Output delay time Output
tICK tCKI
SI0, SI1: With timing Figure Stipulated with respect rising edge SCK0, SCK1.
tCKO
SO0, SO1: With timing Figure test load Figure Stipulated with respect falling edge SCK0, SCK1.
Continued next page.
5997-14/17
LC662508A, 662512A, 662516A
Continued from preceding page.
Parameter [Pulse conditions] INT0 high low-level pulse widths High low-level pulse widths interrupt inputs other than INT0 PIN1 high low-level pulse widths high low-level pulse widths INT0: Figure conditions under which INT0 interrupt accepted, conditions under which timer event counter pulse width measurement input accepted INT1, INT2: Figure conditions under which corresponding interrupt accepted PIN1: Figure conditions under which timer event counter input accepted RES: Figure conditions under which reset applied. Symbol Conditions Unit Note
tIOH, tIOL
Tcyc
tIIH, tIIL tPINH, tPINL tRSH, tRSL
Tcyc Tcyc Tcyc
Operating current drain
IDDHALT IDDHOLD
VDD: 4MHz ceramic oscillator VDD: 4MHz external clock VDD: 4MHz ceramic oscillator VDD: 4MHz external clock VDD:
0.01
Halt mode current drain Hold mode current drain
Note: With output transistor shared ports with open-drain output specifications. These pins cannot used input pins CMOS output specifications selected. With output transistor shared ports with open-drain output specifications. rating pull-up output specification pins stipulated terms output pull-up current IPO. These pins cannot used input pins CMOS output specifications selected. With output transistor CMOS output specification pins. (Also applicable when p-channel open-drain option specified P8.) With output transistor pull-up output specification pins. Applies when CMOS output specifications selected. With output transistor open-drain output specification pins. With output transistor open-drain output specification pins. Reset state
Tone (DTMF) Output Characteristics Characteristics +70°C, When MLOUT enable option selected (the output function used)
Parameter Tone output voltage (p-p) Row/column tone output voltage ratio Tone distortion Symbol DBCR1 THD1 Conditions Dual tone, Dual tone, Single tone, Unit
Note: item below MLOUT disable mask option selected.
When MLOUT disable option selected (the output function cannot used)
Parameter Tone output voltage (p-p) Row/column tone output voltage ratio Tone distortion Symbol DBCR1 THD1 Conditions Dual tone, Dual tone, Single tone, Unit
Note: item above MLOUT enable mask option selected.
5997-15/17
LC662508A, 662512A, 662516A
External clock
OSC1
(OSC2) Open textF textL textR 1/fext textH
Figure External Clock Input Waveform
OSC1
OSC2
Operating lower limit
Ceramic oscillator
Stable oscillation Oscillator unstable period tCFS
Figure Ceramic Oscillator Circuit
Figure Oscillator Stabilization Period
Table Recommended Ceramic Oscillator Constants
External capacitor type (Murata Mfg. Co., Ltd.) CSA4.00MG (Kyocera Corporation) KBR4.0MSB Built-in capacitor type (Murata Mfg. Co., Ltd.) CST4.00MG (Kyocera Corporation) KBR4.0MKC
tCKCY SCK0 SCK1 (output) (intput) tCK0 tCKL tCKR tCKH tCKF 0.8V (input) (output) tICK tCKI Test point
Figure Serial Timing
Figure Timing Load
5997-16/17
LC662508A, 662512A, 662516A
tI0H tI1H tPINH tRSH tI0L tI1L tPINL tRSL
Figure Input Timing INT0, INT1, INT2, PIN1, pins
Figure Tone Output Load
Specifications SANYO products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer's products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer's products equipment. SANYO Electric Co., Ltd. strives supply high-quality high-reliability products. However, semiconductor products fail with some probability. possible that these probabilistic failures could give rise accidents events that could endanger human lives, that could give rise smoke fire, that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO products (including technical data, services) described contained herein controlled under applicable local export control laws regulations, such products must exported without obtaining export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written permission SANYO Electric Co., Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties.
This catalog provides information October, 1998. Specifications information herein subject change without notice. 5997-17/17
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