LC66556B, 66558B Four-Bit Single-Chip Microcontrollers with Bytes
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Ordering number EN5003
LC66556B, 66558B
Four-Bit Single-Chip Microcontrollers with Bytes On-Chip
Overview
LC66556B LC66558B four-bit single-chip CMOS microcontrollers that integrate single chip functions required microcontroller, including ROM, RAM, ports, serial interfaces, comparator inputs, three-value inputs, timers interrupts. These products provided 64-pin package. These products differ from earlier LC66558A Series power supply voltage range certain other electrical characteristics.
Features Functions
On-chip with byte 4-bit capacities same instruction (with instructions) LC66000 Series (except that instruction supported) ports: pins 8-bit serial interface: circuits (16-bit cascade connection supported) Instruction cycle: 0.92 Series Structure
Type LC66304A/306A/308A LC66404A/406A/408A LC66506B/508B/512B/516B LC66354A/356A/358A LC66354S/356S/358S* LC66556A/558A/562A/566A LC66354B/356B/358B LC66556B/558B LC66562B/566B LC66E308 LC66P308 LC66E408 LC66P408 LC66E516 LC66P516 Note: Under development count capacity k/12 k/16 k/12 k/16 k/16 EPROM OTPROM EPROM OTPROM EPROM OTPROM
Powerful timers prescalers 12-bit timer: time-limit timer, event counter, pulse width measurement, square wave output 8-bit timer: time-limit timer, event counter, output, square wave output 12-bit prescaler: time base functions Powerful 11-factor 8-vector interrupt system External interrupts: factors/3 vectors Internal interrupts: factors/5 vectors Flexible functions Comparator inputs, three-value inputs, drive outputs, breakdown voltage pins, pull-up/opendrain option switching possible Runaway detection function (watchdog timer) option 8-bit function Power saving functions: halt hold modes Package: DIP64S, QFP64E Evaluation LSI: LC66599 (evaluation chip) EVA850/800-TB665XX LC66E516 (On-chip EPROM microcontrollers) LC66P516 (On-chip OTPROM microcontrollers)
capacity DIP64S DIP42S DIP64S DIP64S DIC42S (window) DIC42S DIC42S (window) DIC42S DIC64S (window) DIC64S DIP42S DIP42S DIP64S DIP42S
Package QFP48E QFP48E QFP64A QFP48E QFP44M QFP64E QFP48E QFP64E QFP64E QFC48 (window) QFP48E QFC48 (window) QFP48E QFC64 (window) QFP64E
Features Normal versions V/0.92
Low-voltage versions V/3.92
Low-voltage high-speed versions V/0.92
Evaluation (window) versions versions V/0.92
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
33195TH (OT) 5003-1/22
LC66556B, 66558B
Package Dimensions
unit: 3071-DIP64S
[LC66556B, 66558B]
unit: 3159-QFP64E
[LC66556B, 66558B]
SANYO: DIP64S
SANYO: QIP64E
Assignments
view
view
recommend using reflow soldering solder mounting technique. Consult your Sanyo representative concerning temperature other conditions techniques which whole package immersed solder bath, i.e. solder techniques, used.
5003-2/22
LC66556B, 66558B System Block Diagram
Differences between LC66556B/LC66558B LC66508B Series
Item System differences Hardware wait time (number cycles) when hold mode cleared Value timer reset (including value after hold mode cleared) LC66508B series (Including EVA850/800-TB665XX tool) 65536 cycles (Tcyc µs): about value loaded. LC66556B, 66558B 16384 cycles (Tcyc µs): about value loaded.
LC66512B, 516B Differences major characteristics V/0.92 Operating power supply voltage/operating speed LC66E516, P516 V/0.92
5.5V/0.92
oscillator cannot used with LC66556B LC66558B addition, certain other output current comparator input voltage specifications differ. details, individual catalogs LC66508B, LC66E516 LC66P516. Keep these differences mind when using LC66E516 LC66P516 evaluation chips.
5003-3/22
LC66556B, 66558B Function Overview
Function ports Input output 4-bit 1-bit units have control functions HALT mode. Output drive type Option Either with pull-up N-channel output Reset output level Value reset
P-channel: pull-up type N-channel: small sink current type
High (option)
ports Input output 4-bit 1-bit units ports Input output 4-bit 1-bit units also used serial input pin. also used serial output pin. also used serial clock SCK0 pin. also used INT0 interrupt request, timer event counter pulse width measurement input. ports Input output 3-bit 1-bit units also used INT1 interrupt request. also used square wave output from timer also used square wave output from timer output. Hold mode control input Hold mode entered HOLD instruction executed when HOLD low. When hold mode, reactivated setting HOLD high level. also used input port together with P32. When P33/HOLD low, will reset level RES. Therefore, cannot used applications that P33/HOLD when power first applied. ports Input output 4-bit 1-bit units 8-bit units when used conjunction with Output 8-bit data when used conjunction with ports Input output 4-bit 1-bit units 8-bit units when used conjunction with Output 8-bit data when used conjunction with
P-channel: pull-up type N-channel: small sink current type
Either with pull-up N-channel output Reset output level
High (option)
P20/SI0 P21/SO0 P22/SCK0 P23/INT0
P-channel: CMOS type N-channel: small sink current type withstand voltage Nchannel
Either CMOS Nchannel output
High
P30/INT1 P31/POUT0 P32/POUT1
P-channel: CMOS type N-channel: small sink current type withstand voltage Nchannel
Either CMOS Nchannel output
High
P33/HOLD
P-channel: pull-up type N-channel: small sink current type
Either CMOS Nchannel output
High
P-channel: pull-up type N-channel: small sink current type
Either CMOS Nchannel output
High
Continued next page. 5003-4/22
LC66556B, 66558B
Continued from preceding page.
Function ports Input output 4-bit 1-bit units also used serial input pin. also used serial output pin. also used serial clock SCK1 pin. also used timer event counter input. Output drive type Option Value reset
P60/SI1 P61/SO1 P62/SCK1 P63/PIN1
P-channel: CMOS type N-channel: small sink current type withstand voltage Nchannel
CMOS N-channel output
High
Dedicated output ports Output 4-bit 1-bit units latched output data read with input instructions.
P-channel: pull-up type N-channel: intermediate sink current type withstand voltage Nchannel
With pull-up transistor N-channel output
High
Dedicated output ports Output 4-bit 1-bit units latched output data read with input instructions. p-channel output option available. ports Input output 4-bit 1-bit units also used INT2 interrupt request. also used INT3 interrupt request. also used INT4 interrupt request. also used INT5 interrupt request. Dedicated output ports Output 4-bit 1-bit units latched output data read with input instructions.
P-channel: CMOS type N-channel: small sink current type
CMOS P-channel output output level reset
High (option)
P90/INT2 P91/INT3 P92/INT4 P93/INT5
P-channel: CMOS type N-channel: small sink current type
CMOS N-channel output
High
P-channel: pull-up type N-channel: intermediate sink current type
With pull-up N-channel output
High
Dedicated output ports Output 4-bit 1-bit units latched output data read with input instructions. ports Input output 4-bit 1-bit units also used VREF0 comparator comparison voltage pin. also used VREF1 comparator comparison voltage pin. Dedicated input ports switched function comparator inputs under software control. comparison voltage VREF0. comparison voltage VREF1. Comparison specified units PD0, PD1, (PD2, PD3).
P-channel: CMOS type N-channel: small sink current type
With pull-up N-channel output
High
PC2/VREF0 PC3/VREF1
CMOS N-channel output
High
PD0/CMP0 PD1/CMP1 PD2/CMP2 PD3/CMP3
Normal input
Continued next page. 5003-5/22
LC66556B, 66558B
Continued from preceding page.
PE0/TRA PE1/TRB Function Dedicated input port switched under software control function threevalue input port. System clock oscillator connections When external clock used, leave OSC2 open input signal OSC1. System reset input initialized (reset) level input when P33/HOLD high level. testing This must connected during normal operation. Power supply connections Selection either ceramic oscillator external clock input Output drive type Option Value reset
Normal input
OSC1 OSC2
TEST
Note: Pull-up output: output with pull-up transistor CMOS output: complementary output output: open drain output
User Option Types Port reset time output level option output levels ports reset selected from following options 4-bit units.
Option High level output reset time level output reset time Conditions notes Ports and/or 4-bit sets Ports and/or 4-bit sets
Oscillator circuit option
Option Circuit Conditions notes
External clock
This input Schmitt specification input.
Ceramic oscillator
Note: There oscillator option.
Watchdog timer option presence absence program runaway detection function (watchdog timer) selected option.
5003-6/22
LC66556B, 66558B Port output type option following output circuit options selected each ports (except P33/HOLD pin),
Option Circuit Conditions notes
Open drain output
output only pins. Schmitt inputs.
output only pins. Schmitt inputs. Built-in pull-up resistor output CMOS outputs (P2, pull-up outputs (P0, differentiated.
circuits selected from following options units.
Option Circuit Conditions notes
Open drain output
Built-in pull-up resistor output
comparator inputs three-value inputs selected software.
5003-7/22
LC66556B, 66558B
Specifications
Absolute Maximum Ratings 25°C,
Parameter Maximum supply voltage Input voltage Symbol VOUT VOUT Output current -IOP -IOP Total current -IOP -IOP Allowable power dissipation Operating temperature Storage temperature Topr Tstg (except P33/HOLD pin) Other inputs (except P33/HOLD pin), Other outputs (except P33/HOLD pin), (except P33/HOLD pin), (except P33/HOLD pin), (except P33/HOLD pin), +70°C: DIP64S (QIP64E) Conditions Ratings -0.3 +7.0 -0.3 +15.0 -0.3 -0.3 +15.0 -0.3 (430) +125 Unit Note
Output voltage
Note: Applies open drain output specification pins. rating from "other pin" entry applies specifications other than open drain output specification. Levels free-running oscillation level allowed oscillator input output pins. Inflow current (For CMOS output specifications apply.) Outflow current (Applies pull-up output specification CMOS output specification pins except P8.) recommend using reflow soldering methods mount package version. Contact your Sanyo sales representative discuss process conditions techniques which whole package immersed solder bath (solder spray techniques) used.
Allowable Operating Ranges 70°C, unless specified otherwise
Parameter Operating supply voltage Memory retention supply voltage Symbol Input high level Voltage Intermediate level input voltage VCMM Common-mode input voltage range VCMM level input voltage Operating frequency (instruction cycle time) (TCYC) VDD: hold mode (except P33/HOLD pin), With output n-channel transistor P33/HOLD, RES, OSC1: With output n-channel transistor With output n-channel transistor When three-state input used When three-state input used PD0, PC2: When comparator input used PD1, PD2, PD3, PC3: When comparator input used (except P33/HOLD pin), RES, OSC1:N-channel output, transistor P33/HOLD: TEST: N-channel output, transistor When three-state input used Conditions 0.75 (10) 13.5 0.25 4.35 (0.92) Unit (µs) Note
Note: Applies open drain specification pins. However, rating applies P33/HOLD pin. Ports cannot used input pins when CMOS output specifications used. Applies open drain specification pins. which CMOS output specifications, used input pins. When used three-value input, (4), apply. Port cannot used input pins when CMOS output specifications used.
Continued next page. 5003-8/22
LC66556B, 66558B
Continued from preceding page.
Parameter [External clock input conditions] Frequency fext OSC1: Figure With signal input OSC1 with OSC2 open (with external clock input selected oscillator circuit option) OSC1: Figure With signal input OSC1 with OSC2 open (with external clock input selected oscillator circuit option) 4.35 Symbol Conditions Unit Note
Pulse width
textH, textL
Rise fall times
OSC1: Figure With signal input OSC1 textR, textF with OSC2 open (with external clock input selected oscillator circuit option)
Electrical Characteristics 70°C, unless otherwise specified
Parameter Symbol Input high level current Conditions (except P33/HOLD pin), 13.5 N-channel output, transistor OSC1, RES, P33/HOLD (except PC3): VDD, N-channel output, transistor PC2, PC3: VDD, N-channel output, transistor Inputs other than PC2, PC3: VSS, N-channel output, transistor PC2, PC3, VSS, N-channel output, transistor (except P33/HOLD pin), (except P33/HOLD pin), -0.1 VSS, (except P33/HOLD pin): 13.5 (except PA): PD1, PD2, PD3: PD0: -1.0 ±300 ±300 -1.0 -1.0 -1.6 Unit Note
Input level current
Output high level voltage
Output pull-up current
IOFF
Output level voltage
Output leakage current
IOFF IOFF VOFF VOFF
Comparator offset voltage [Schmitt characteristics] Hysteresis voltage High level threshold voltage level threshold voltage [Ceramic oscillator] Oscillator frequency Oscillator stabilization time
VHIS RES, OSC1, (RC, EXT) OSC1, OSC2: Figure Figure
tCFS
Note: Common input output ports with open-drain output specifications specified state with output N-channel transistor turned off. These pins cannot used input when CMOS output specification option selected. Common input output ports with open-drain output specifications specified state with output N-channel transistor turned off. Ratings pull-up output specification pins stipulated output pull-up current IPO. These pins cannot used input when CMOS output specification option selected. Stipulated CMOS output specifications with output N-channel transistor state. (This also applies when P-channel open drain selected.) Stipulated pull-up output specifications with output N-channel transistor state. Stipulated with CMOS output specifications. Stipulated open drain output specifications with output N-channel transistor state. Stipulated open drain output specifications with output P-channel transistor state.
Continued next page. 5003-9/22
LC66556B, 66558B
Continued from preceding page.
Parameter [Serial clock] Cycle time Input Output tCKCY tCKL tCKH tCKR, tCKF tICK tCKI S10, SI1, SI0, SI1: With timing Figure Stipulated with respect rising edge SCK0 SCK1. SCK0, SCK1: With timing from Figure test load from Figure TCYC TCYC Symbol Conditions Unit Note
Input level/high level pulse widths Output Rise/fall times [Serial input] Data setup time Data hold time [Serial output] Output delay time [Pulse input conditions] INT0 High level pulse widths
High level pulse widths interrupt inputs other than INT0
Output
tCKO
SO0, SO1: With timing from Figure test load from Figure Stipulated with respect falling edge SCK0 SCK1.
tI0H, tI0L
INT0, Figure Conditions such that INT0 interrupt accepted Conditions such that timer event counter pulse width measurement inputs accepted INT1, INT2, INT3, INT4, INT5, Figure Conditions such that interrupts accepted PIN1, Figure Conditions such that timer event counter inputs accepted RES, Figure Conditions such that reset occur Figure VDD: ceramic oscillator VDD: external clock VDD: ceramic oscillator VDD: external clock VDD:
TCYC
tI1H, tI1L tPINH, tPINL tRSH, tRSL IDDHALT IDDHOLD
0.01
TCYC TCYC TCYC
PIN1 High level pulse widths High level pulse widths Comparator response speed Operating mode current drain
HALT mode current drain Hold mode current drain Note: Reset state
Figure External Clock Input Waveform
Figure Ceramic Oscillator Circuit
Figure Oscillator Stabilization Period
5003-10/22
LC66556B, 66558B Table Ceramic Oscillator Guaranteed Constants
(Murata Mfg. Co., Ltd.) CSA4.00MG (Murata Mfg. Co., Ltd.) CST4.00MG (Kyocera Corporation) KBR4.0 (Kyocera Corporation) KBR4.0MES
External capacitance
Internal capacitance
Figure Serial Timing
Figure Timing Load
Figure Input Timing INT0, INT1, INT2, INT3, INT4, INT5, PIN1
Figure Comparator Response Speed Timing
5003-11/22
LC66556B, 66558B Application Development Tools Programs LC66556B LC66558B microprocessors developed IBM-PC compatible personal computer running MS-DOS operating system. cross assembler other tools available. make application development more convenient, Sanyo also provides program debugging unit (EVA850/800), evaluation board (EVA850/800-TB665XX), evaluation chip (LC66599) on-chip EPROM microprocessor (LC66E516).
Structure Application Development Tools Program debugging unit (EVA850/800) This emulator that provides functions EPROM writing serial data communications with external equipment (such host computer). supports application development machine language program modification. main debugging functions include breaking, stepping tracing. (The MPM665XX used EVA850/800 monitor ROM.) Evaluation chip board (EVA800/850-TB665XX) evaluation chip signals ports output 64-pin connector when output cable connected, evaluation chip board converts these signals same assignments those mass production chip. evaluation chip board includes jumpers setting options other states these jumper settings allow evaluation chip implement same circuit types functions mass production chip. However, there differences hold mode clear timing electrical characteristics. Jumpers
Type Jumper Jumper setting mode oscillator oscillator Jumper (J1) External oscillator (external clock) Reset method Jumper (J2:RES) Reset instruction from host computer. Power supply user application board Jumper (J3:VDD) supplied user application printed circuit board through evaluation chip board.
Reset reset circuit user application printed circuit board.
Separate power supplies user application printed circuit board evaluation chip board
Switches (SW1)
Type Switch Switch setting mode Port high Port Port output levels reset Port high Port Port high Port Watchdog timer presence absence setting Watchdog timer present Watchdog timer absent
Note: Switches must both position.
5003-12/22
LC66556B, 66558B Switches SW14: Pull-up resistor option settings corresponding switch position built-in pull-up resistors switch position open drain output. (SW10 used port pull-down resistor setting.) These settings specified individual pins. Cross assembler
Cross assembler (file name) Object microprocessors LC66562B/566B (LC66E516/P516) (LC66599) Limitations program creation instruction limitations LC66556B: SB0, SB1, cannot used LC66558B: SB0, SB1, cannot used LC66E516/P516: SB0, SB1, used LC66599: SB0, SB1, used
LC66S.
Simulation chip (See LC66E516 individual product catalog more details.) LC66E516 simulation chip on-chip EPROM microprocessor. Mounted configuration operation confirmed application product using dedicated conversion board (the W66E516DH products W66E516QH products) writing programs with commercial PROM writer. Form LC66E516 assignment functions identical those LC66556B LC66558B. However, there differences hold mode clear timing electrical characteristics. figure below shows assignment figure below shows assignment Options options (the port levels reset, watchdog timer port output circuit types) microprocessor evaluated specified EPROM data. This allows evaluation with same peripheral circuits those that will used mass production product. Assignments
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5003-13/22
LC66556B, 66558B LC665XX Series Instruction Table function) Abbreviations: Accumulator register Carry flag Zero flag Data pointer DPH, Data pointer DPX, Data memory (HL): Data memory pointed DPH, data pointer (XY): Data memory pointed DPX, auxiliary data pointer (HL): words data memory (starting even address) pointed DPH, data pointer Stack pointer (SP): words data memory pointed stack pointer (SP): Four words data memory pointed stack pointer bits immediate data specification
PCh: PCm: PCl: TIMER0: TIMER1: SIO: (i4): INT:
Bits Bits Bits User flag, Timer Timer Serial register Port Port indicated bits immediate data Interrupt enable flag Indicates contents location Transfer direction, result Exclusive Logical Logical Addition Subtraction Taking one's complement
5003-14/22
LC66556B, 66558B
Instruction code Mnemonic [Accumulator manipulation instructions] Clear Decimal adjust addition Decimal adjust subtraction Clear Complement Increment Decrement Rotate right through Rotate left through Transfer Transfer Exchange with Clear (Equivalent (AC) (Equivalent (AC) (Equivalent 0AH.) (AC) (AC) (AC) (CF), (ACn (AC0) (CF), (ACn), (AC3) (AC) (AC) Clear Take one's complement Increment Decrement Shift (including right. vertical skip function.
Number bytes Number cycles
Operation
Description
Affected status bits
Note
Shift (including left. Move contents
Move contents Exchange contents
[Memory manipulation instructions] IMDR Increment Decrement Increment direct (HL) (HL)] (HL) (HL)] (i8) (i8)] (i8) (i8)] (HL), (HL), Increment (HL). Decrement (HL). Increment (i8). Decrement (i8). (HL) specified Clear (HL) specified
DMDR Decrement direct data Reset data
[Arithmetic, logic comparison instructions] (AC) (HL)] contents (HL) two's complement values store result
ADDR direct
contents (i8) two's complement (AC) (i8)] values store result (AC) (HL)] (CF) contents (HL) two's complement values store result contents immediate data two's complement values store result Subtract contents from (HL) two's complement values store result Take logical (HL) store result Take logical (HL) store result
with
immediate data
(AC)
SUBC
Subtract from with
(HL)] (AC) (CF) (AC) (HL)] (AC) (HL)]
will zero there borrow otherwise.
ANDA
with then store with then store
Continued next page. 5003-15/22
LC66556B, 66558B
Continued from preceding page.
Instruction code Mnemonic [Arithmetic, logic comparison instructions] Exclusive with then store with then store with then store (AC) (HL)] (HL) (AC) (HL)] (HL) (AC) (HL)] Take logical exclusive (HL) store result Take logical (HL) store result (HL). Take logical (HL) store result (HL). Compare contents (HL) clear according result. Compare with (HL)] (AC) Magnitude comparison (HL)] (AC) (HL)] (AC) (HL)] (AC)
Number bytes Number cycles
Operation
Description
Affected status bits
Note
ANDM
Compare contents immediate data clear according result. Compare with immediate data (AC) Magnitude comparison (DPL) (DPL) (AC, (HL), (AC, (HL), (HL), (i8)] (HL) (AC) (HL) (AC)
Compare with immediate data
Compare contents with immediate data. identical clear not. Compare corresponding bits specified (HL). identical clear not.
Compare with data
[Load store instructions] LADR Load from (HL) Load with immediate data Load from direct Store Store (HL) Load contents (HL) into Load immediate data into Load contents (i8) into Store contents into (HL). Store contents into (HL). Load contents (reg) into either depending vertical skip function
Load from (reg)
(reg)]
Continued next page. 5003-16/22
LC66556B, 66558B
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Instruction code Mnemonic [Load store instructions] Load contents (reg) into (The either XY.) Then increment contents either DPY. relationship between same that instruction. Load contents (reg) into (The either XY.) Then decrement contents either DPY. relationship between same that instruction. Exchange contents (reg) either depending according result incrementing DPY.
Number bytes Number cycles
Operation
Description
Affected status bits
Note
reg,
Load from (reg) then increment
(reg)] (DPL) (DPY)
Load from (reg) reg, then decrement
(reg)] (DPL) (DPY)
according result decrementing DPY.
Exchange with (reg)
(AC) (reg)]
Exchange with reg, (reg) then increment
(AC) (reg)] (DPL) (DPY)
Exchange contents (reg) (The either XY.) Then increment contents either DPY. relationship between that instruction. Exchange contents (reg) (The either XY.) Then decrement contents either DPY. relationship between that instruction. Exchange contents (i8). Load immediate data into Load into data location determined replacing lower bits with Output from ports data location determined replacing lower bits with
according result incrementing DPY.
Exchange with reg, (reg) then decrement
(AC) (reg)] (DPL) (DPY)
according result decrementing DPY.
XADR LEAI
Exchange with direct Load with immediate data
(AC) (i8)] [ROM (PCh, AC)]
RTBL
Read table data from program
RTBLP
Read table data from program then output
Port [ROM (PCh, AC)]
[Data pointer manipulation instructions] Load with zero with immediate data respectively Load with immediate data Load with immediate data Load DPH, with immediate data Load DPX, with immediate data Load zero into immediate data into DPL. Load immediate data into DPH. Load immediate data into DPL. Load immediate data into DLH, DPL. Load immediate data into DLX, DPY.
LHLI LXYI
Continued next page. 5003-17/22
LC66556B, 66558B
Continued from preceding page.
Instruction code Mnemonic [Data pointer manipulation instructions] Increment Decrement Increment Decrement Transfer Transfer Exchange with Transfer Transfer Exchange with Transfer Transfer Exchange with Transfer Transfer Exchange with (DPL) (DPL) (DPY) (DPY) (AC) (DPH) (AC) (DPH) (AC) (DPL) (AC) (DPL) (AC) (DPX) (AC) (DPX) (AC) (DPY) (AC) (DPY) Increment contents DPL. Decrement contents DPL. Increment contents DPY. Decrement contents DPY. Transfer contents DPH. Transfer contents Exchange contents DPH. Transfer contents DPL. Transfer contents Exchange contents DPL. Transfer contents DPX. Transfer contents Exchange contents DPX. Transfer contents DPY. Transfer contents Exchange contents DPY. flag specified Reset flag specified
Number bytes Number cycles
Operation
Description
Affected status bits
Note
[Flag manipulation instructions] flag Reset flag
[Jump subroutine instructions] PC13, PC13, PC11 PC13 PC13 (E), (AC) PC13 PC10 (SP) (CF, PC13 (SP)-4 Jump location same bank specified immediate data P12. Jump location determined replacing lower bits This becomes PC12 (PC12) immediately following BANK instruction.
addr
Jump current bank
P11P10P9
JPEA
Jump address stored current page
addr
Call subroutine
Call subroutine.
addr
Call subroutine zero page
PC13 PC10 Call subroutine page (SP) bank (CF, PC12 SP-4 Change memory bank register bank.
BANK
Change bank
Continued next page. 5003-18/22
LC66556B, 66558B
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Instruction code Mnemonic [Jump subroutine instructions] Store contents (SP). Subtract from after store. PUSH Push (SP) (SP) (reg) (SP)-2 Illegal
Number bytes Number cycles
Operation
Description
Affected status bits
Note
(SP)
(SP) (SP)]
then load contents M2(SP) into reg. relation between i1i0 same that PUSH instruction. Return from subroutine interrupt handling routine. restored. Return from subroutine interrupt handling routine. restored.
Return from subroutine Return from interrupt routine
(SP) (SP)] (SP) (SP)] (SP)] (AC, (AC, (HL),t2] (HL),t2]
[Branch instructions] BAt2 addr Branch location same page specified specified immediate data Branch location same page specified specified immediate data Branch location same page specified (HL) specified immediate data Branch location same page specified (HL) specified immediate data Internal control registers also tested executing this instruction immediately after BANK instruction. However, this limited registers that read out. Internal control registers also tested executing this instruction immediately after BANK instruction. However, this limited registers that read out.
Branch
BNAt2 addr
Branch
BMt2 addr
Branch
BNMt2 addr
Branch
BPt2 addr
Branch Port
(DPL),
Branch location same page specified port (DPL) specified immediate data
BNPt2 addr
Branch Port
(DPL),
Branch location same page specified port (DPL) specified immediate data
Continued next page. 5003-19/22
LC66556B, 66558B
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Instruction code Mnemonic [Branch instructions] (CF) (CF) (ZF) (ZF) (Fn) (Fn) Branch location same page specified Branch location same page specified Branch location same page specified Branch location same page specified Branch location same page specified flag user flags) specified Branch location same page specified flag user flags) specified
Number bytes Number cycles
Operation
Description
Affected status bits
Note
addr
Branch
addr
Branch
addr
Branch
addr
Branch
BFn4 addr
Branch flag
BNFn4 addr
Branch flag
[I/O instructions] IPDR Input port Input port Input port Input port direct Input port respectively Output port Output port Output port direct Output port respectively (P0) (DPL)] (HL) (DPL)] (i4)] (4)] (5)] (DPL) (AC) (DPL) (HL)] (i4) (AC) (AC) (DPL), Input contents port Input contents port (DPL) Input contents port (DPL) (HL). Input contents (i4) Input contents ports respectively. Output contents port (DPL). Output contents (HL) port (DPL). Output contents (i4). Output contents ports respectively. port (DPL) specified immediate data Clear zero port (DPL) specified immediate data
IP45
OPDR
OP45
port
Reset port
(DPL), P0)] P0)]
port with ANDPDR immediate data then output port with immediate data then output
Take logical immediate data output result P0). Take logical immediate data output result P0).
ORPDR
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LC66556B, 66558B
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Instruction code Mnemonic [Timer control instructions] WTTM0 Write timer Write contents (HL), TIMER0 (HL)], into timer reload (AC) register. TIMER1 (E), (AC) Write contents into timer reload register Read contents timer counter into (HL), Read contents timer counter into Start timer counter. Start timer counter. Stop timer counter. Stop timer counter.
Number bytes Number cycles
Operation
Description
Affected status bits
Note
WTTM1
Write timer
RTIM0
Read timer
(HL), (TIMER0) (TIMER1) Start timer counter Start timer counter Stop timer counter Stop timer counter
RTIM1
Read timer
START0 Start timer START1 Start timer STOP0 STOP1 Stop timer Stop timer
[Interrupt control instructions] MSET MRESET WTSP interrupt master enable flag Reset interrupt master enable flag Enable interrupt high Enable interrupt Disable interrupt high Disable interrupt Write Read EDIH (EDIH) EDIL (EDIL) EDIH (EDIH) EDIL (EDIL) (E), (AC) (SP) interrupt master enable flag Clear interrupt master enable flag interrupt enable flag interrupt enable flag Clear interrupt enable flag Clear interrupt enable flag Transfer contents Transfer contents
[Standby control instructions] HALT HOLD HALT HOLD HALT HOLD Enter halt mode. Enter hold mode.
[Serial control instructions] STARTS Start serial WTSIO RSIO Write serial Read serial START (E), (AC) (SIO) Start operation. Write contents SIO. Read contents into
[Other instructions] operation Select bank operation Consume machine cycle without performing operation. Specify memory bank. Illegal instruction
PC13, PC12
5003-21/22
LC66556B, 66558B
products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information March, 1995. Specifications information herein subject change without notice. 5003-22/22
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